MC908AS32AMFNR2 [MOTOROLA]
Microcontroller, 8-Bit, FLASH, 8.4MHz, HCMOS, PQCC52, PLASTIC, LCC-52;
| 型号： | MC908AS32AMFNR2 |
| 厂家： | 
MOTOROLA |
| 描述： | Microcontroller, 8-Bit, FLASH, 8.4MHz, HCMOS, PQCC52, PLASTIC, LCC-52 微控制器 外围集成电路 |
| 文件： | 总448页 (文件大小：2247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908AS32A
Advance Information
M68HC08
Microcontrollers
MC68HC908AS32A/D
Rev. 0, 5/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC908AS32A
Advance Information — Rev 0.0
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2001
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List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Section 1. General Description . . . . . . . . . . . . . . . . . . . .25
Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 3. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 4. FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . .51
Section 5. EEPROM Memory . . . . . . . . . . . . . . . . . . . . . .63
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .83
Section 7. System Integration Module (SIM) . . . . . . . .101
Section 8. Clock Generator Module (CGM). . . . . . . . . .123
Section 9. Configuration Register (CONFIG-1). . . . . . .151
Section 10. Configuration Register (CONFIG-2). . . . . .155
Section 11. Break Module (BRK) . . . . . . . . . . . . . . . . . .157
Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . .163
Section 13. Computer Operating Properly (COP) . . . .175
Section 14. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . .181
Section 15. External Interrupt Module (IRQ). . . . . . . . .187
Section 16. Serial Communications Interface (SCI). . .195
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Section 17. Serial Peripheral Interface (SPI). . . . . . . . .235
Section 18. Timer Interface Module B (TIMB). . . . . . . .267
Section 19. Programmable Interrupt Timer (PIT) . . . . .293
Section 20. Input/Output Ports . . . . . . . . . . . . . . . . . . .303
Section 21. Keyboard Module (KBD). . . . . . . . . . . . . . .323
Section 22. Timer Interface Module A (TIMA). . . . . . . .331
Section 23. Analog-to-Digital Converter (ADC) . . . . . .361
Section 24. Byte Data Link Controller (BDLC) . . . . . . .373
Section 25. Electrical Specification. . . . . . . . . . . . . . . .419
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435
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Table of Contents
List of Paragraphs
Table of Contents
List of Figures
List of Tables
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Section 2. Memory Map
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Additional Status and Control Registers. . . . . . . . . . . . . . . . . .45
Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . .46
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Section 3. RAM
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 4. FLASH Memory
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
FLASH Control and Block Protect Registers . . . . . . . . . . . . . .52
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .57
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .58
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Section 5. EEPROM Memory
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .65
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
EEPROM Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . .73
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
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Section 6. Central Processor Unit (CPU)
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 7. System Integration Module (SIM)
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . .104
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . .106
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . .111
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Section 8. Clock Generator Module (CGM)
8.1
8.2
8.3
8.4
8.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
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8.6
8.7
8.8
8.9
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .144
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .144
Section 9. Configuration Register (CONFIG-1)
9.1
9.2
9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Section 10. Configuration Register (CONFIG-2)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Section 11. Break Module (BRK)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
11.6 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Section 12. Monitor ROM (MON)
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
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12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Section 13. Computer Operating Properly (COP)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . . . .180
Section 14. Low Voltage Inhibit (LVI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Section 15. External Interrupt Module (IRQ)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
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15.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .192
15.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .192
Section 16. Serial Communications Interface (SCI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . .216
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Section 17. Serial Peripheral Interface (SPI)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
17.4 Pin Name and Register Name Conventions. . . . . . . . . . . . . .237
17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
17.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
17.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
17.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . .252
17.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
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17.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .255
17.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
17.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
Section 18. Timer Interface Module B (TIMB)
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
18.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
18.7 TIMB During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .279
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
18.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Section 19. Programmable Interrupt Timer (PIT)
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
19.5 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.7 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .297
19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
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Section 20. Input/Output Ports
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
20.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
20.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
20.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
20.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
20.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
20.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
Section 21. Keyboard Module (KBD)
21.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
21.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .328
21.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
Section 22. Timer Interface Module A (TIMA)
22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
22.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
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22.7 TIMA During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .345
22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
22.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
Section 23. Analog-to-Digital Converter (ADC)
23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
23.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
Section 24. Byte Data Link Controller (BDLC)
24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
24.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
24.5 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
24.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
24.7 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
24.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
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Section 25. Electrical Specification
25.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
25.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
25.3 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .434
Glossary
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List of Figures
Figure
Title
Page
1-1
MCU Block Diagram for the MC68HC908AS32A (52-pin PLCC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MC68HC908AS32A (52-Pin PLCC) . . . . . . . . . . . . . . . . . . . . .29
Power supply bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Memory Map (Continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . .41
Additional Status and Control Registers. . . . . . . . . . . . . . . . . .45
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .53
FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .54
FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .54
FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .61
EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .65
EEPROM Control Register (EECR) . . . . . . . . . . . . . . . . . . . . .73
EEPROM Array Configuration Register (EEACR) . . . . . . . . . .75
EEPROM Nonvolatile Register (EENVR) . . . . . . . . . . . . . . . . .77
EEDIV Divider High Register (EEDIVH) . . . . . . . . . . . . . . . . . .78
EEDIV Divider Low Register (EEDIVL). . . . . . . . . . . . . . . . . . .78
EEPROM Divider Non-Volatile Register High (EEDIVHNVR)).80
EEPROM Divider Non-Volatile Register Low (EEDIVLNVR) . .80
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . .87
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .103
CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
1-2
1-3
2-1
2-2
2-3
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6-3
6-4
6-5
6-6
7-1
7-2
7-3
7-4
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7-5
7-6
7-7
7-8
7-9
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .115
7-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
7-13 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .117
7-14 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .118
7-15 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7-16 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . .119
7-17 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .120
7-18 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .121
7-19 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .122
8-1
8-2
8-3
8-4
8-5
8-6
9-1
CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .135
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .137
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .139
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . .141
Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . . . . . .152
10-1 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . . . . . .155
11-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .158
11-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11-3 Break Status and Control Register (BSCR) . . . . . . . . . . . . . .161
11-4 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .162
12-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
12-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .167
12-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12-6 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .173
13-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .179
14-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .184
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15-1 IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .192
16-1 SCI Module Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . .198
16-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .199
16-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16-4 SCI Transmitter
16-5 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . .203
16-6 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . .206
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
16-7 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .207
16-8 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16-9 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
16-11 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .218
16-12 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .221
16-13 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .224
16-14 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .226
16-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
16-16 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . .230
16-17 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .231
16-18 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . .231
17-1 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .239
17-2 Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . .240
17-3 Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . .243
17-4 Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . .244
17-5 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . .246
17-6 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . .248
17-7 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . .249
17-8 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . .252
17-9 SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . . .253
17-10 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17-11 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . .260
17-12 SPI Status and Control Register (SPSCR). . . . . . . . . . . . . . .263
17-13 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .266
18-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
18-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .270
18-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .275
18-4 TIMB Status and Control Register (TBSC). . . . . . . . . . . . . . .281
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List of Figures
18-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . .284
18-6 TIMB Counter Modulo Registers (TBMODH and TBMODL) .285
18-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
18-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290
18-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) . . . . . . . .291
19-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
19-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .295
19-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . .298
19-4 PIT Counter Registers (PCNTH–PCNTL). . . . . . . . . . . . . . . .300
19-5 PIT Counter Modulo Registers (PMODH–PMODL) . . . . . . . .301
20-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .304
20-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .305
20-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .305
20-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
20-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .307
20-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .308
20-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
20-8 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .310
20-9 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . .311
20-10 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
20-11 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .313
20-12 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . .314
20-13 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
20-14 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .316
20-15 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .318
20-16 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
20-17 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .320
20-18 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .321
20-19 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
21-1 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . .325
21-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
21-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .329
21-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .330
22-1 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
22-2 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . .334
22-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .340
22-4 TIMA Status and Control Register (TASC). . . . . . . . . . . . . . .347
Advance Information
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22-5 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . .350
22-6 TIMA Counter Modulo Registers (TAMODH and TAMODL) .351
22-7 TIMA Channel Status and Control Registers (TASC0–TASC5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
22-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
22-9 TIMA Channel Registers (TACH0H/L–TACH5H/L) . . . . . . . .358
23-1 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23-2 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .367
23-3 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .370
23-4 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .370
24-1 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
24-2 BDLC Operating Modes State Diagram . . . . . . . . . . . . . . . . .377
24-3 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
24-4 BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . . . .381
24-5 J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . . . .383
24-6 J1850 VPW Symbols with Nominal Symbol Times. . . . . . . . .388
24-7 J1850 VPW Received Passive Symbol Times . . . . . . . . . . . .391
24-8 J1850 VPW Received Passive EOF and IFS Symbol Times .392
24-9 J1850 VPW Received Active Symbol Times . . . . . . . . . . . . .393
24-10 J1850 VPW Received BREAK Symbol Times . . . . . . . . . . . .394
24-11 J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . . . .395
24-12 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
24-13 BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . . . .397
24-14 BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
24-15 BDLC Analog and Roundtrip Delay Register (BARD) . . . . . .403
24-16 BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . . . .404
24-17 BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . . . .407
24-18 Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . . . .410
24-19 BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . . . .414
24-20 BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . . . .416
25-1 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .426
25-2 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .427
25-3 BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
MC68HC908AS32A — Rev 0.0
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List of Figures
List of Figures
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MC68HC908AS32A — Rev 0.0
List of Figures
MOTOROLA
Technical Data — MC68HC908AS32A
List of Tables
Table
Title
Page
1-1
1-3
1-2
1-4
2-1
5-1
5-2
5-3
5-4
6-1
6-2
7-1
7-2
7-3
8-1
8-2
8-3
External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Clock Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . .35
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
EEPROM Array Address Blocks. . . . . . . . . . . . . . . . . . . . . . . .68
Example Selective Bit Programming Description . . . . . . . . . . .69
EEPROM Program/Erase Mode Select . . . . . . . . . . . . . . . . . .73
EEPROM Block Protect and Security Summary. . . . . . . . . . . .76
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .104
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . .104
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .127
Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . .142
11-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .159
12-1 Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
12-2 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12-3 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .169
12-4 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .170
12-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .170
12-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .171
12-7 READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .171
12-8 RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .172
12-9 MC68HC908AS60A Monitor Baud Rate Selection. . . . . . . . .172
14-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
15-1 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .189
16-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
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List of Tables
List of Tables
16-2 SCI I/O Register Address Summary. . . . . . . . . . . . . . . . . . . .199
16-3 SCI Transmitter I/O Address Summary . . . . . . . . . . . . . . . . .203
16-4 SCI Receiver I/O Address Summary . . . . . . . . . . . . . . . . . . .207
16-5 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
16-6 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
16-7 Stop Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
16-8 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .220
16-9 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . .232
16-10 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
16-11 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . .233
17-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
17-2 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
17-3 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .238
17-4 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
17-5 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
17-6 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . .265
18-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
18-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .289
19-1 PIT I/O Register Address Summary . . . . . . . . . . . . . . . . . . . .295
19-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
20-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306
20-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
20-3 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
20-4 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
20-5 Port E Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
20-6 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
21-1 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . .325
22-1 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349
22-2 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .356
23-1 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368
23-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371
24-1 BDLC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .376
24-2 BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . . .401
24-3 BDLC Transceiver Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
24-4 BDLC Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
24-5 BDLC Transmit In-Frame Response Control Bit Priority Encoding
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
24-6 BDLC Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
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MOTOROLA
Technical Data — MC68HC908AS32A
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.226
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . .30
Oscillator Pins (OSC1 and OSC2). . . . . . . . . . . . . . . . . . .31
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .31
External Interrupt Pin (IRQ). . . . . . . . . . . . . . . . . . . . . . . .31
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .31
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .31
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .31
ADC Reference High Voltage Pin (VREFH) . . . . . . . . . . .32
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . .32
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . .32
1.5.11 Port C I/O Pins (PTC4–PTC0) . . . . . . . . . . . . . . . . . . . . . .32
1.5.12 Port D I/O Pins (PTD6–PTD0/ATD8) . . . . . . . . . . . . . . . . .32
1.5.13 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) . . . . . . . . . . . .32
1.5.14 Port F I/O Pins (PTF3–PTF0/TACH2). . . . . . . . . . . . . . . . .33
1.5.15 BDLC Transmit Pin (BDTxD) . . . . . . . . . . . . . . . . . . . . . . .33
1.5.16 BDLC Receive Pin (BDRxD) . . . . . . . . . . . . . . . . . . . . . . .33
1.6
1.6.1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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General Description
25
General Description
1.2 Introduction
The MC68HC908AS60A is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the enhanced M68HC08
central processor unit (CPU08) and are available with a variety of
modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC908AS60A include:
•
•
High-Performance M68HC08 Architecture
Fully Upward-Compatible Object Code with M6805, M146805,
and M68HC05 Families
•
•
8.4 MHz Internal Bus Frequency
32,256 bytes of FLASH Electrically Erasable Read-Only Memory
(FLASH)
•
•
FLASH Data Security
512 bytes of On-Chip Electrically Erasable Programmable Read-
Only Memory with Security Option (EEPROM)
•
•
•
•
•
•
•
•
1 Kbyte of On-Chip RAM
Clock Generator Module (CGM)
Serial Peripheral Interface Module (SPI)
Serial Communications Interface Module (SCI)
8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15)
16-Bit, 6-Channel Timer Interface Module (TIMA-6)
Programmable Interrupt Timer (PIT)
System Protection Features
– Computer Operating Properly (COP) with Optional Reset
– Low-Voltage Detection with Optional Reset
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26
MC68HC908AS32A — Rev 0.0
General Description
MOTOROLA
General Description
MCU Block Diagram
– Illegal Opcode Detection with Optional Reset
– Illegal Address Detection with Optional Reset
•
•
•
Low-Power Design (Fully Static with Stop and Wait Modes)
Master Reset Pin and Power-On Reset
SAE J1850 Byte Data Link Controller Digital Module
Features of the CPU08 include:
•
•
•
•
•
•
•
•
•
•
Enhanced HC05 Programming Model
Extensive Loop Control Functions
16 Addressing Modes (Eight More Than the HC05)
16-Bit Index Register and Stack Pointer
Memory-to-Memory Data Transfers
Fast 8 × 8 Multiply Instruction
Fast 16/8 Divide Instruction
Binary-Coded Decimal (BCD) Instructions
Optimization for Controller Applications
C Language Support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908AS60A.
MC68HC908AS32A — Rev 0.0
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General Description
General Description
F P T
D D R F
A P T
D D R A
B P T
D D R B
C P T
D D R C
E P T
D D R E
D P T
D D R D
D x T B D
D
D B R x
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General Description
MOTOROLA
General Description
Pin Assignments
1.5 Pin Assignments
Figure 1-2 shows MC68HC908AS60A 52-pin PLCC pin assignments.
PTC4
IRQ
PTD3/ATD11
PTD2/ATD10
PTD1/ATD9
PTD0/ATD8
PTB7/ATD7
PTB6/ATD6
8
46
9
45
44
43
42
41
40
39
38
37
RST
10
11
12
13
14
15
16
17
18
19
PTF0/TACH2
PTF1/TACH3
PTF2/TACH4
PTF3/TACH5
BDRxD
PTB5/ATD5
PTB4/ATD4
BDTxD
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTA7
PTE0/TxD
PTE1/RxD
PTE2/TACH0
PTE3/TACH1
36
35
20
34
Figure 1-2. MC68HC908AS32A (52-Pin PLCC)
MC68HC908AS32A — Rev 0.0
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29
MOTOROLA
General Description
General Description
NOTE: The following pin descriptions are just a quick reference. For a more
detailed representation, see Input/Output Ports on page 303.
1.5.1 Power Supply Pins (VDD and VSS)
VDD and VSS are the power supply and ground pins. The MCU operates
from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as shown in Figure
1-3. Place the C1 bypass capacitor as close to the MCU as possible. Use
a high-frequency response ceramic capacitor for C1. C2 is an optional
bulk current bypass capacitor for use in applications that require the port
pins to source high current levels.
MCU
V
V
SS
DD
C1
0.1 µF
+
C2
V
DD
NOTE: Component values shown represent typical applications.
Figure 1-3. Power supply bypassing
VSS is also the ground for the port output buffers and the ground return
for the serial clock in the Serial Peripheral Interface module (SPI). See
Serial Peripheral Interface (SPI) on page 235.
NOTE: VSS must be grounded for proper MCU operation.
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MC68HC908AS32A — Rev 0.0
General Description
MOTOROLA
General Description
Pin Assignments
1.5.2 Oscillator Pins (OSC1 and OSC2)
The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See Clock Generator Module (CGM) on page 123.
1.5.3 External Reset Pin (RST)
A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. See System Integration Module
(SIM) on page 101 for more information.
1.5.4 External Interrupt Pin (IRQ)
IRQ is an asynchronous external interrupt pin. See External Interrupt
Module (IRQ) on page 187.
1.5.5 External Filter Capacitor Pin (CGMXFC)
CGMXFC is an external filter capacitor connection for the Clock
Generator Module (CGM). See Clock Generator Module (CGM) on
page 123.
1.5.6 Analog Power Supply Pin (VDDA/ DDAREF)
V
VDDA/ VDDAREF is the power supply pin for the analog portion of the
Analog-to-Digital Converter (ADC) and the Clock Generator Module
(CGM). See Analog-to-Digital Converter (ADC) on page 361. See
Clock Generator Module (CGM) on page 123.
1.5.7 Analog Ground Pin (VSSA/VREFL
)
The VSSA/VREFL pin provides both the analog ground connection and
the reference low voltage for the Analog-to-Digital Converter (ADC) as
well as the ground connection for the Clock Generator Module (CGM).
See Analog-to-Digital Converter (ADC) on page 361. See Clock
Generator Module (CGM) on page 123.
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General Description
General Description
1.5.8 ADC Reference High Voltage Pin (VREFH
)
VREFH provides the reference high voltage for the Analog-to-Digital
Converter (ADC). See Analog-to-Digital Converter (ADC) on page
361.
1.5.9 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional I/O port pins. See
Input/Output Ports on page 303.
1.5.10 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the
Analog-to-Digital Converter (ADC). See Analog-to-Digital Converter
(ADC) on page 361 and Input/Output Ports on page 303.
1.5.11 Port C I/O Pins (PTC4–PTC0)
PTC4–PTC3 and PTC1–PTC0 are general-purpose bidirectional I/O
port pins. PTC2/MCLK is a special function port that shares its pin with
the system clock which has a frequency equivalent to the system clock.
See Input/Output Ports on page 303.
1.5.12 Port D I/O Pins (PTD6–PTD0/ATD8)
Port D is an 7-bit special-function port that shares seven of its pins with
the Analog-to-Digital Converter module (ADC-15), one of its pins with
the Timer Interface Module A (TIMA). See Timer Interface Module A
(TIMA) on page 331, Analog-to-Digital Converter (ADC) on page 361
and Input/Output Ports on page 303.
1.5.13 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD)
Port E is an 8-bit special function port that shares two of its pins with the
Timer Interface Module A (TIMA), four of its pins with the Serial
Peripheral Interface module (SPI), and two of its pins with the Serial
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MC68HC908AS32A — Rev 0.0
General Description
MOTOROLA
General Description
Pin Assignments
Communication Interface module (SCI). See Serial Communications
Interface (SCI) on page 195, Serial Peripheral Interface (SPI) on page
235, Timer Interface Module A (TIMA) on page 331, and Input/Output
Ports on page 303.
1.5.14 Port F I/O Pins (PTF3–PTF0/TACH2)
Port F is a 4-bit special function port that shares four of its pins with the
Timer Interface Module A (TIMA-6). See Timer Interface Module A
(TIMA) on page 331, and Input/Output Ports on page 303.
1.5.15 BDLC Transmit Pin (BDTxD)
This pin is the digital output from the BDLC module (BDTxD). See
Electrical Specification on page 419.
1.5.16 BDLC Receive Pin (BDRxD)
This pin is the digital input to the CAN module (BDRxD). See Electrical
Specification on page 419.
Table 1-1. External Pins Summary
Hysteresis(1)
Pin Name
Function
Driver Type
Reset State
PTA7–PTA0
General-Purpose I/O
Dual State
No
Input Hi-Z
General-Purpose I/O
ADC Channel
PTB7/ATD7–PTB0/ATD0
PTC4–PTC0
Dual State
Dual State
No
No
Input Hi-Z
Input Hi-Z
General-Purpose I/O
General-Purpose I/O
ADC Channel/Timer
External Input Clock
PTD6/ATD14/TACLK ADC Channel
PTD5/ATD13 ADC Channel
Dual State
Dual State
Dual State
Dual State
No
No
No
Input Hi-Z
Input Hi-Z
Input Hi-Z
General-Purpose I/O
ADC Channel
General-Purpose I/O
ADC Channel/Timer
External Input Clock
PTD4/ATD12/TBCLK ADC Channel
PTD3/ATD11–PTD0/ATD8 ADC
General-Purpose I/O
ADC Channel
No
Input Hi-Z
Input Hi-Z
Channels
General-Purpose I/O
SPI Clock
Dual State
Open Drain
PTE7/SPSCK
Yes
MC68HC908AS32A — Rev 0.0
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MOTOROLA
General Description
General Description
Table 1-1. External Pins Summary (Continued)
Hysteresis(1)
Pin Name
Function
Driver Type
Reset State
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
PTE6/MOSI
Yes
Input Hi-Z
General-Purpose I/O
SPI Data Path
Dual State
Open Drain
PTE5/MISO
PTE4/SS
Yes
Yes
Yes
Yes
Yes
No
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
Input Hi-Z
General-Purpose I/O
SPI Slave Select
Dual State
Dual State
Dual State
Dual State
Dual State
Dual State
Dual State
Dual State
Dual State
General-Purpose I/O
Timer A Channel 1
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
General-Purpose I/O
Timer A Channel 0
General-Purpose I/O
SCI Receive Data
General-Purpose I/O
SCI Transmit Data
PTE0/TxD
General-Purpose I/O
Timer A Channel 5
PTF3/TACH5
PTF2/TACH4
PTF1/TACH3
PTF0/TACH2
Yes
Yes
Yes
Yes
General-Purpose I/O
Timer A Channel 4
General-Purpose I/O
Timer A Channel 3
General-Purpose I/O
Timer A Channel 2
VDD
VSS
Chip Power Supply
Chip Ground
N/A
N/A
N/A
N/A
N/A
N/A
ADC Analog Power Supply
CGM Analog Power Supply
V
DDA/VDDAREF
N/A
N/A
N/A
N/A
N/A
N/A
ADC Ground/ADC
Reference Low Voltage
CGM Analog Ground
VSSA/VREFL
VREFH
A/D Reference High Voltage
External Clock In
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
No
N/A
Input Hi-Z
Output
OSC1
OSC2
CGMXFC
IRQ
External Clock Out
PLL Loop Filter Cap
External Interrupt Request
Reset
N/A
N/A
N/A
N/A
Input Hi-Z
Output Low
Input Hi-Z
Output
RST
N/A
BDRxD
BDTxD
BDLC Serial Input
BDLC Serial Output
N/A
Output
1. Hysteresis is not 100% tested but is typically a minimum of 300mV.
Advance Information
MC68HC908AS32A — Rev 0.0
34
General Description
MOTOROLA
General Description
Pin Assignments
Table 1-2. Clock Signal Naming Conventions
Clock Signal Name
Description
Buffered version of OSC1 from
Clock Generation Module (CGM)
CGMXCLK
PLL-based or OSC1-based clock output from
Clock Generator Module (CGM)
CGMOUT
Bus Clock
SPSCK
TACLK
CGMOUT divided by two
SPI serial clock
External clock input for TIMA
Table 1-3. Clock Source Summary
Module
ADC
CAN
COP
CPU
FLASH
EEPROM
RAM
SPI
Clock Source
CGMXCLK or Bus Clock
CGMXCLK or CGMOUT
CGMXCLK
Bus Clock
Bus Clock
CGMXCLK or Bus Clock
Bus Clock
Bus Clock/SPSCK
CGMXCLK
SCI
TIMA
PIT
Bus Clock or PTD6/ATD14/TACLK
Bus Clock
SIM
CGMOUT and CGMXCLK
Bus Clock
IRQ
BRK
Bus Clock
LVI
Bus Clock
CGM
OSC1 and OSC2
MC68HC908AS32A — Rev 0.0
Advance Information
35
MOTOROLA
General Description
General Description
1.6 Ordering Information
This section contains instructions for ordering the MC68HC908AS32A.
1.6.1 MC Order Numbers
Table 1-4. MC Order Numbers
Operating
Temperature Range
MC Order Number
MC68HC908AS32ACFN (52-Pin PLCC)
MC68HC908AS32AVFN (52-Pin PLCC)
MC68HC908AS32AMFN (52-Pin PLCC)
–40C to + 85C
–40C to + 105C
–40C to + 125C
Advance Information
36
MC68HC908AS32A — Rev 0.0
General Description
MOTOROLA
Technical Data — MC68HC908AS32A
Section 2. Memory Map
2.1 Contents
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I/O Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Additional Status and Control Registers . . . . . . . . . . . . . . .45
Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . .46
2.2 Introduction
The CPU08 can address 64K bytes of memory space. The memory
map, shown in Figure 2-1, includes:
•
•
•
•
•
32,256 Bytes of FLASH EEPROM
1024 Bytes of RAM
512 Bytes of EEPROM with Protect Option
52 Bytes of User-Defined Vectors
256 Bytes of Monitor ROM
The following definitions apply to the memory map representation of
reserved and unimplemented locations.
• Reserved — Accessing a reserved location can have
unpredictable effects on MCU operation.
• Unused — These locations are reserved in the memory map for
future use, accessing an unused location can have unpredictable
effects on MCU operation.
• Unimplemented — Accessing an unimplemented location can
cause an illegal address reset (within the constraints as outlined
in the Memory Map).
MC68HC908AS32A — Rev 0.0
Advance Information
37
MOTOROLA
Memory Map
Memory Map
MC68HC908AS32A
$0000
↓
$0000
↓
I/O REGISTERS (80 BYTES)
$004F
$0050
↓
$004F
$0050
↓
RAM (1024 BYTES)
UNIMPLEMENTED (944 BYTES)
EEPROM (512 BYTES)
$044F
$0450
↓
$044F
$0450
↓
$07FF
$0800
↓
$07FF
$0800
↓
$09FF
$0A00
↓
$09FF
$0A00
↓
UNIMPLEMENTED (1536 BYTES)
UNIMPLEMENTED (28,672 BYTES)
FLASH (32,256 BYTES)
$0FFF
$1000
↓
$0FFF
$1000
↓
$7FFF
$8000
↓
$7FFF
$8000
↓
$FDFF
$FE00
$FE01
$FE02
$FE03
$FDFF
$FE00
$FE01
$FE02
$FE03
SIM BREAK STATUS REGISTER (SBSR)
SIM RESET STATUS REGISTER (SRSR)
RESERVED
SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04
↓
$FE04
↓
RESERVED
$FE08
$FE08
$FE09
CONFIGURATION WRITE-ONCE REGISER 2 (CONFIG-2)
$FE09
Advance Information
38
MC68HC908AS32A — Rev 0.0
Memory Map
MOTOROLA
Memory Map
Introduction
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
$FE11
RESERVED
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
$FE11
RESERVED
BREAK ADDRESS REGISTER HIGH (BRKH)
BREAK ADDRESS REGISTER LOW (BRKL)
BREAK STATUS AND CONTROL REGISTER (BSCR)
LVI STATUS REGISTER (LVISR)
EEPROM EEDIVH NON-VOLATILE REGISTER (EEDIVHNVR)
EEPROM EEDIVL NON-VOLATILE REGISTER (EEDIVLNVR)
$FE12
↓
$FE12
↓
RESERVED
$FE19
$FE19
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
EEPROM EE DIVIDER HIGH REGISTER (EEDIVH)
EEPROM EE DIVIDER LOW REGISTER (EEDIVL)
EEPROM NON-VOLATILE REGISTER (EENVR)
EEPROM CONTROL REGISTER (EECR)
RESERVED
$FE1A
$FE1B
$FE1C
$FE1D
$FE1E
$FE1F
$FE20
↓
EEPROM ARRAY CONFIGURATION REGISTER (EEACR)
MONITOR ROM (256 BYTES)
$FF1F
$FF1F
$FF20
↓
$FF20
↓
UNIMPLEMENTED (80 BYTES)
$FF7F
$FF7F
$FF80
$FF81
↓
FLASH BLOCK PROTECT REGISTER (FLBPR)
$FF80
$FF82
↓
RESERVED (7 BYTES)
$FF87
$FF88
$FF89
$FF8A
$FF87
$FF88
$FF89
$FF8A
FLASH CONTROL REGISTER (FLCR)
RESERVED
RESERVED
MC68HC908AS32A — Rev 0.0
Advance Information
39
MOTOROLA
Memory Map
Memory Map
$FF8B
↓
$FF8B
↓
RESERVED (4 BYTES)
UNIMPLEMENTED (48 BYTES)
RESERVED (26 BYTES)
$FF8F
$FF90
↓
$FF8F
$FF90
↓
$FFBF
$FFC0
↓
$FFBF
$FFC0
↓
$FFD9
$FFDA
$FFD9
$FFDA
VECTORS (38 BYTES)
See Memory Map on page 37
↓
↓
$FFFF
$FFFF
Figure 2-1. Memory Map (Continued)
Advance Information
40
MC68HC908AS32A — Rev 0.0
Memory Map
MOTOROLA
Memory Map
I/O Section
2.3 I/O Section
Addresses $0000–$004F, shown in Figure 2-2, contain the I/O Data,
Status and Control Registers.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
$0000
Port A Data Register (PTA)
Port B Data Register (PTB)
Port C Data Register (PTC)
Port D Data Register (PTD)
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000C
$000D
$0010
$0011
$0012
$0013
PTB7
0
PTB6
0
PTB5
0
PTB4
PTC4
PTD4
PTB3
PTC3
PTD3
PTB2
PTC2
PTD2
PTB1
PTC1
PTD1
PTB0
PTC0
PTD0
0
PTD6
PTD5
Data Direction Register A
(DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register B
(DDRB)
0
0
Data Direction Register C
(DDRC)
MCLKEN
0
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Data Direction Register D
(DDRD)
DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0
Port E Data Register (PTE)
Port F Data Register (PTF)
PTE7
0
PTE6
0
PTE5
0
PTE4
0
PTE3
PTF3
PTE2
PTF2
PTE1
PTF1
PTE0
PTF0
Data Direction Register E
(DDRE)
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
Data Direction Register F
(DDRF)
DDRF3 DDRF2 DDRF1 DDRF0
SPI Control Register (SPCR)
SPRIE
R
0
SPMSTR CPOL
CPHA SPWOM SPE
SPTIE
SPR0
Read: SPRF
Write:
OVRF
MODF
SPTE
0
SPI Status and Control
Register (SPSCR)
SPR1
Read:
Write:
Read:
Write:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register (SPDR)
SCI Control Register 1 (SCC1)
LOOPS ENSCI TXINV
M
WAKE
ILTY
PEN
PTY
Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 4)
MC68HC908AS32A — Rev 0.0
Advance Information
41
MOTOROLA
Memory Map
Memory Map
Addr.
Register Name
Bit 7
SCTIE
R8
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
$0014
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
$0015
$0016
$0017
$0018
$0019
$001A
$001C
$001D
$001E
$001F
$0020
$0022
$0023
$0024
$0025
$0026
$0027
T8
R
R
ORIE
OR
NEIE
NF
FEIE
FE
PEIE
PE
Read: SCTE
Write:
TC
SCRF
IDLE
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
0
0
BKF
RPF
R7
T7
0
R6
T6
0
R5
T5
R4
T4
R3
T3
0
R2
T2
R1
T1
R0
T0
SCI Baud Rate Register (SCBR)
SCP1
0
SCP0
0
SCR2
SCR1
SCR0
0
0
IRQF
0
ACK
1
IRQ Status and Control
Register (ISCR)
IMASK MODE
PLLF
LOCK
1
0
1
0
1
0
PLL Control Register (PCTL)
PLLIE
AUTO
PLLON
ACQ
BCS
XLD
0
PLL Bandwidth Control
Register (PBWC)
PLL Programming Register
(PPG)
MUL7
MUL6
R
MUL5
MUL4
VRS7
VRS6
VRS5
STOP
VRS4
Configuration Write-Once
Register (CONFIG-1)
LVISTOP
LVIRST LVIPWR SSREC COPL
COPD
Read: TOF
0
0
11
3
Timer A Status and Control
Register (TASC)
TOIE
14
TSTOP
13
PS2
10
PS1
9
PS0
Bit 8
Write:
0
TRST
12
Read: Bit 15
Write:
Timer A Counter Register
High (TACNTH)
Read: Bit 7
Write:
6
5
4
2
1
Bit 0
Timer A Counter Register
Low (TACNTL)
Read:
Bit 15
Write:
Timer A Modulo Register
High (TAMODH)
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Read:
Bit 7
Timer A Modulo Register
Low (TAMODL)
Write:
Read: CH0F
Timer A Channel 0 Status and
Control Register (TASC0)
CH0IE
14
MS0B
13
MS0A ELS0B ELS0A TOV0 CH0MAX
Write:
Read:
Write:
0
Timer A Channel 0 Register
High (TACH0H)
Bit 15
12
11
10
9
Bit 8
Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 4)
Advance Information
42
MC68HC908AS32A — Rev 0.0
Memory Map
MOTOROLA
Memory Map
I/O Section
Addr.
Register Name
Bit 7
6
5
5
0
4
3
2
1
Bit 0
Read:
Write:
Timer A Channel 0 Register
Low (TACH0L)
$0028
Bit 7
6
4
3
2
1
Bit 0
Read: CH1F
Timer A Channel 1 Status and
Control Register (TASC1)
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
CH1IE
14
MS1A ELS1B ELS1A TOV1 CH1MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 1 Register
High (TACH1H)
Bit 15
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 1 Register
Low (TACH1L)
Bit 7
6
Read: CH2F
Timer A Channel 2 Status and
Control Register (TASC2)
CH2IE
14
MS2B
13
MS2A ELS2B ELS2A TOV2 CH2MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 2 Register
High (TACH2H)
Bit 15
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 2 Register
Low (TACH2L)
Bit 7
6
5
0
Read: CH3F
Timer A Channel 3 Status and
Control Register (TASC3)
CH3IE
14
MS3A ELS3B ELS3A TOV3 CH3MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 3 Register
High (TACH3H)
Bit 15
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 3 Register
Low (TACH3L)
Bit 7
6
Read: CH4F
Timer A Channel 4 Status and
Control Register (TASC4)
CH4IE
14
MS4B
13
MS4A ELS4B ELS4A TOV4 CH4MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 4 Register High
(TACH4H)
Bit 15
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 4 Register Low
(TACH4L)
Bit 7
6
5
0
Read: CH5F
Timer A Channel 5 Status and
Control Register (TASC5)
CH5IE
14
MS5A ELS5B ELS5A TOV5 CH5MAX
Write:
Read:
Write:
Read:
Write:
0
Timer A Channel 5 Register
High (TACH5H)
Bit 15
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
Timer A Channel 5 Register
Low (TACH5L)
Bit 7
6
Read: COCO
Analog-to-Digital Status and
Control Register (ADSCR)
AIEN
AD6
ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
AD5 AD4 AD3 AD2 AD1 AD0
Write:
R
Read: AD7
Write:
Analog-to-Digital Data Register
(ADR)
Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 4)
MC68HC908AS32A — Rev 0.0
Advance Information
43
MOTOROLA
Memory Map
Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
0
0
0
0
Analog-to-Digital Input Clock
Register (ADICLK)
$003A
ADIV2
ADIV1
ADIV0 ADICLK
0
0
BDLC Analog and Roundtrip Delay
Register (BARD)
$003B
ATE
RXPOL
CLKS
BO3
BO2
BO1
IE
BO0
R
R
0
0
$003C BDLC Control Register 1 (BCR1)
$003D BDLC Control Register 2 (BCR2)
IMSG
R1
R0
WCM
R
R
ALOOP DLOOP RX4XE NBFS
TEOD
TSIFR TMIFR1 TMIFR0
0
0
I3
R
I2
R
I1
R
I0
R
0
0
BDLC State Vector Register
$003E
(BSVR)
R
R
R
R
$003F
$004B
$004C
$004D
$004E
$004F
BDLC Data Register (BDR)
BD7
BD6
BD5
BD4
BD3
0
BD2
BD1
BD0
Read: POF
0
PIT Status and Control Register
(PSC)
PIE
14
PSTOP
13
PPS2
10
PPS1
9
PPS0
Bit 8
Write:
0
PRST
12
Read: Bit 15
Write:
11
3
PIT Counter Register High
(PCNTH)
Read: Bit 7
Write:
6
5
4
2
1
Bit 0
PIT Counter Register Low
(PCNTL)
Read:
Bit 15
Write:
PIT Modulo Register High
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
(PMODH)
Read:
Bit 7
PIT Modulo Register Low
(PMODL)
Write:
= Unimplemented
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 4)
Advance Information
44
MC68HC908AS32A — Rev 0.0
Memory Map
MOTOROLA
Memory Map
Additional Status and Control Registers
2.4 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FF88 contain additional
Status and Control registers as shown in Figure 2-3. A noted exception
is the COP Control Register (COPCTL at address $FFFF.
Addr.
Register Name
Bit 7
R
6
R
5
R
4
R
3
R
2
R
0
1
Bit 0
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
SIM Break Status Register
(SBSR)
$FE00
BW
LVI
R
0
POR
PIN
COP
ILOP
ILAD
$FE01 SIM Reset Status Register (SRSR)
SIM Break Flag Control Register
$FE03
BCFE
EEDIVCLK
Bit 15
R
R
R
R
R
R
R
AS32A
11
R
R
R
R
9
R
R
(SBFCR)
Configuration Write-Once Register
$FE09
(CONFIG-2)
Break Address Register High
$FE0C
(BRKH)
14
6
13
12
10
Bit 8
Break Address Register Low
$FE0D
(BRKL)
Bit 7
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Break Status and Control
$FE0E
BRKE
BRKA
0
Register (BRKSCR)
Read: LVIOUT
Write:
0
0
0
0
0
0
$FE0F
$FE10
LVI Status Register (LVISR)
EEDIV Hi Non-volatile Register Read:
(EEDIVHNVR) Write:
EEDIVSECD
EEDIV10 EEDIV9 EEDIV8
$FE11
$FE1A
$FE1B
EEDIV Lo Non-volatile Register
(EEDIVLNVR)
Read:
Write:
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
EEDIV Divider High Register
(EEDIVH)
Read:
Write:
EEDIVSECD
EEDIV10 EEDIV9 EEDIV8
EEDIV Divider Low Register
(EEDIVL)
Read:
Write:
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
Read:
Write:
Read:
Write:
Read:
Write:
EEPROM Nonvolatile Register
(EENVR)
$FE1C
$FE1D
$FE1F
0
EEPROM Control Register
(EECR)
EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM
EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0
EEPROM Array Configuration
Register (EEACR)
Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2)
MC68HC908AS32A — Rev 0.0
MOTOROLA
Advance Information
45
Memory Map
Memory Map
Addr.
Register Name
Bit 7
BPR7
0
6
BPR6
0
5
BPR5
0
4
BPR4
0
3
2
1
Bit 0
Read:
Write:
Read:
Write:
FLASH Block Protect Register
(FLBPR)
$FF80
BPR3
BPR2
BPR1
BPR0
FLASH Control Register
(FLCR)
$FF88
HVEN
VERF ERASE
PGM
Read:
Write:
LOW BYTE OF RESET VECTOR
WRITING TO $FFFF CLEARS COP COUNTER
$FFFF COP Control Register (COPCTL)
= Unimplemented
R
= Reserved
Figure 2-3. Additional Status and Control Registers (Sheet 2 of 2)
2.5 Vector Addresses and Priority
Addresses in the range $FFDA to $FFFF contain the user-specified
vector locations. The vector addresses are shown in Table 2-1. It is
recommended that all vector addresses are defined.
Table 2-1. Vector Addresses
Vector
Address
MC68HC908AS32A
$FFDA
$FFDB
$FFDC
$FFDD
$FFDE
$FFDF
$FFE0
$FFE1
$FFE2
$FFE3
$FFE4
$FFE5
$FFE6
PIT Vector (High)
PIT Vector (Low)
Lowest Priority
BDLC Vector (High)
BDLC Vector (Low)
ADC Vector (High)
ADC Vector (Low)
SCI Transmit Vector (High)
SCI Transmit Vector (Low)
SCI Receive Vector (High)
SCI Receive Vector (Low)
SCI Error Vector (High)
SCI Error Vector (Low)
SPI Transmit Vector (High)
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46
MC68HC908AS32A — Rev 0.0
MOTOROLA
Memory Map
Memory Map
Vector Addresses and Priority
Table 2-1. Vector Addresses
Vector
Address
$FFE7
$FFE8
$FFE9
$FFEA
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
MC68HC908AS32A
SPI Transmit Vector (Low)
SPI Receive Vector (High)
SPI Receive Vector (Low)
TIMA Overflow Vector (High)
TIMA Overflow Vector (Low)
TIMA Channel 5 Vector (High)
TIMA Channel 5 Vector (Low)
TIMA Channel 4 Vector (High)
TIMA Channel 4 Vector (Low)
TIMA Channel 3 Vector (High)
TIMA Channel 3 Vector (Low)
TIMA Channel 2 Vector (High)
TIMA Channel 2 Vector (Low)
TIMA Channel 1 Vector (High)
TIMA Channel 1 Vector (Low)
TIMA Channel 0 Vector (High)
TIMA Channel 0 Vector (Low)
PLL Vector (High)
PLL Vector (Low)
IRQ1 Vector (High)
IRQ1 Vector (Low)
SWI Vector (High)
SWI Vector (Low)
Reset Vector (High)
Reset Vector (Low)
Highest Priority
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Memory Map
Memory Map
Advance Information
48
MC68HC908AS32A — Rev 0.0
Memory Map
MOTOROLA
Technical Data — MC68HC908AS32A
Section 3. RAM
3.1 Contents
3.2
3.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2 Introduction
This section describes the 1024 bytes of random-access memory
(RAM).
3.3 Functional Description
Address $0050 through $044F is the RAM location. The 16-bit stack
pointer allows the stack RAM to be anywhere in the 64K-byte memory
space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 176 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access all page zero RAM locations efficiently.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.
MC68HC908AS32A — Rev 0.0
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49
RAM
RAM
NOTE: For M68HC05, M6805, and M146805 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU could overwrite
data in the RAM during a subroutine or during the interrupt stacking
operation.
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MC68HC908AS32A — Rev 0.0
RAM
MOTOROLA
Technical Data — MC68HC908AS32A
Section 4. FLASH Memory
4.1 Contents
4.2
4.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.4
4.4.1
4.4.2
FLASH Control and Block Protect Registers. . . . . . . . . . . .52
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .53
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . .54
4.5
4.6
4.7
4.8
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . .57
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . .58
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . .59
4.9
4.9.1
4.9.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed and erased from a single
external supply. The program and erase operations are enabled through
the use of an internal charge pump.
MC68HC908AS32A — Rev 0.0
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51
MOTOROLA
FLASH Memory
FLASH Memory
4.3 Functional Description
The FLASH memory is an array of 32,256 bytes with one byte of block
protection and an additional 38 bytes of user vectors. An erased bit
reads as a logic 1 and a programmed bit reads as a logic 0.
Memory in the FLASH array is organized into rows within pages. There
are two rows of memory per page with 64 bytes per row. The minimum
erase block size is a single page,128 bytes. Programming is performed
on a per-row basis, 64 bytes at a time. Program and erase operations
are facilitated through control bits in the FLASH Control Register
(FLCR). Details for these operations appear later in this section.
The FLASH memory map consists of:
•
•
•
•
$8000–$FDFF: User Memory (32,256 bytes)
$FF80: FLASH Block Protect Register (FLBPR)
$FF88: FLASH Control Register (FLCR)
$FFCC–$FFFF: these locations are reserved for user-defined
interrupt and reset vectors (Please see Vector Addresses and
Priority on page 46 for details)
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.(1)
4.4 FLASH Control and Block Protect Registers
The FLASH array has two registers that control its operation, the FLASH
Control Register (FLCR) and the FLASH Block Protect Register
(FLBPR).
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
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MC68HC908AS32A — Rev 0.0
FLASH Memory
MOTOROLA
FLASH Memory
FLASH Control and Block Protect Registers
4.4.1 FLASH Control Register
The FLASH Control Register (FLCR) controls FLASH program and
erase operations.
Address: $FF88
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
Figure 4-1. FLASH Control Register (FLCR)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the FLASH array for mass or
page erase operation.
1 = Mass erase operation selected
0 = Page erase operation selected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.
1 = Erase operation selected
0 = Erase operation unselected
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53
FLASH Memory
FLASH Memory
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
4.4.2 FLASH Block Protect Register
The FLASH Block Protect Register (FLBPR) is implemented as a byte
within the FLASH memory and therefore can only be written during a
FLASH programming sequence. The value in this register determines
the starting location of the protected range within the FLASH memory.
Address: $FF80
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Figure 4-2. FLASH Block Protect Register (FLBPR)
FLBPR[7:0] — Block Protect Register Bit7 to Bit0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit-
15 is logic 1 and bits [6:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. FLASH is protected from
this start address to the end of FLASH memory at $FFFF. With this
mechanism, the protect start address can be $XX00 and $XX80 (128
byte page boundaries) within the FLASH array.
16-bit memory address
Start address of FLASH block protect
0
0 0 0 0 0 0
FLBPR value
1
Figure 4-3. FLASH Block Protect Start Address
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MC68HC908AS32A — Rev 0.0
FLASH Memory
MOTOROLA
FLASH Memory
FLASH Control and Block Protect Registers
FLASH Protected Ranges:
FLBPR[7:0]
Protected Range
No Protection
$FF
$FE
$FD
$FF00 – $FFFF
$FE80 – $FFFF
$0B
$0A
$09
$08
$8580 – $FFFF
$8500 – $FFFF
$8480 – $FFFF
$8400 – $FFFF
$04
$03
$02
$01
$00
$8200 – $FFFF
$8180 – $FFFF
$8100 – $FFFF
$8080 – $FFFF
$8000 – $FFFF
Decreasing the value in FLBPR by one increases the protected range by
one page (128 bytes). However, programming the block protect register
with $FE protects a range twice that size, 256 bytes, in the
corresponding array. $FE means that locations $FF00–$FFFF are
protected in FLASH.
The FLASH memory does not exist at some locations. The block
protection range configuration is unaffected if FLASH memory does not
exist in that range. Refer to the memory map and make sure that the
desired locations are protected.
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55
FLASH Memory
FLASH Memory
4.5 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by using the FLASH Block
Protection Register (FLBPR). FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends at the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit can not be set in either ERASE or PROGRAM operations.
NOTE: In performing a program or erase operation, the FLASH Block Protect
Register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLASH Block Protect Register is programmed with all 0’s, the
entire memory is protected from being programmed and erased. When
all the bits are erased (all 1’s), the entire memory is accessible for
program and erase.
When bits within FLBPR are programmed (logic 0), they lock a block of
memory address ranges as shown in FLASH Block Protect Register
on page 54. If FLBPR is programmed with any value other than $FF, the
protected block of FLASH memory can not be erased or programmed.
NOTE: The vector locations and the FLASH Block Protect Registers are located
in the same page. FLBPR is not protected with special hardware or
software; therefore, if this page is not protected by FLBPR and the vector
locations are erased by either a page or a mass erase operation, FLBPR
will also be erased.
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FLASH Memory
MOTOROLA
FLASH Memory
FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use this step-by-step procedure to erase the entire FLASH memory to
read as logic 1:
1. Set both the ERASE bit and the MASS bit in the FLASH Control
Register (FLCR).
2. Read the FLASH Block Protect Register (FLBPR).
3. Write to any FLASH address within the FLASH array with any
data.
NOTE: If the address written to in Step 3 is within address space protected by
the FLASH Block Protect Register (FLBPR), no erase will occur.
4. Wait for a time, tNVS
.
5. Set the HVEN bit.
6. Wait for a time, tMERASE
.
7. Clear the ERASE bit.
8. Wait for a time, t NVHL
.
9. Clear the HVEN bit.
10. Wait for a time, tRCV, after which the memory can be accessed in
normal read mode.
NOTE: A. Programming and erasing of FLASH locations can not be performed
by code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
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FLASH Memory
FLASH Memory
4.7 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (128 bytes) of FLASH
memory to read as logic 1:
1. Set the ERASE bit and clear the MASS bit in the FLASH Control
Register (FLCR).
2. Read the FLASH Block Protect Register (FLBPR).
3. Write any data to any FLASH address within the address range of
the page (128 byte block) to be erased.
4. Wait for time, tNVS
5. Set the HVEN bit.
.
6. Wait for time, tERASE
7. Clear the ERASE bit.
8. Wait for time, t NVH
.
.
9. Clear the HVEN bit.
10. Wait for a time, tRCV, after which the memory can be accessed in
normal read mode.
NOTE: A. Programming and erasing of FLASH locations can not be performed
by code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
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FLASH Memory
MOTOROLA
FLASH Memory
FLASH Program Operation
4.8 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 64 consecutive bytes with address ranges as follows:
•
•
•
•
$XX00 to $XX3F
$XX40 to $XX7F
$XX80 to $XXBF
$XXC0 to $XXFF
During the programming cycle, make sure that all addresses being
written to fit within one of the ranges specified above. Attempts to
program addresses in different row ranges in one programming cycle will
fail. Use this step-by-step procedure to program a row of FLASH
memory.
NOTE: In order to avoid program disturbs, the row must be erased before any
byte on that row is programmed.
1. Set the PGM bit in the FLASH Control Register (FLCR). This
configures the memory for program operation and enables the
latching of address and data programming.
2. Read the FLASH Block Protect Register (FLBPR).
3. Write to any FLASH address within the row address range desired
with any data.
4. Wait for time, tNVS
5. Set the HVEN bit.
.
6. Wait for time, tPGS
7. Write data byte to the FLASH address to be programmed.
8. Wait for time, t PROG
.
.
9. Repeat step 7 and 8 until all the bytes within the row are
programmed.
10. Clear the PGM bit.
11. Wait for time, tNVH
.
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MOTOROLA
FLASH Memory
FLASH Memory
12. Clear the HVEN bit.
13. Wait for a time, tRCV, after which the memory can be accessed in
normal read mode.
The FLASH Programming Algorithm Flowchart is shown in Figure 4-4.
NOTE: A. Programming and erasing of FLASH locations can not be performed
by code being executed from the same FLASH array.
B. While these operations must be performed in the order shown, other
unrelated operations may occur between the steps. Care must be taken
however to ensure that these operations do not access any address
within the FLASH array memory space such as the COP Control
Register (COPCTL) at $FFFF.
C. It is highly recommended that interrupts be disabled during
program/erase operations.
D. Do not exceed t PROG maximum or tHV maximum. tHV is defined as the
cumulative high voltage programming time to the same row before next
erase. tHV must satisfy this condition: tNVS+ tNVH + tPGS + (tPROGX 64) ð tHV
max. Please also see FLASH Memory Characteristics on page 431.
E. The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed to clearing the
PGM bit (step 7 to step 10) must not exceed the maximum programming
time, tPROG max.
F. Be cautious when programming the FLASH array to ensure that non-
FLASH locations are not used as the address that is written to when
selecting either the desired row address range in step 3 of the algorithm
or the byte to be programmed in step 7 of the algorithm. This applies
particularly to:
•
$FFDA-$FFFF (38 bytes)
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MC68HC908AS32A — Rev 0.0
FLASH Memory
MOTOROLA
FLASH Memory
FLASH Program Operation
1
2
3
Set PGM bit
Algorithm for programming
a row (64 bytes) of FLASH memory
Read the FLASH block protect register
Write any data to any FLASH address
within the row address range desired
4
5
6
Wait for a time, t
Set HVEN bit
nvs
Wait for a time, t
pgs
7
8
Write data to the FLASH address
to be programmed
Wait for a time, t
PROG
Completed
programming
this row?
Y
N
10
11
12
13
Clear PGM bit
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
Wait for a time, t
nvh
Clear HVEN bit
This row program algorithm assumes the row/s
to be programmed are initially erased.
Wait for a time, t
rcv
End of programming
Figure 4-4. FLASH Programming Algorithm Flowchart
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61
FLASH Memory
FLASH Memory
4.9 Low-Power Modes
The WAIT and STOP instructions will place the MCU in low power
consumption standby modes.
4.9.1 WAIT Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. Wait mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.
4.9.2 STOP Mode
Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly; however, no
memory activity will take place since the CPU is inactive.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH. Stop mode will suspend any
FLASH program/erase operations and leave the memory in a Standby
Mode.
NOTE: Standby Mode is the power saving mode of the FLASH module, in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is minimum.
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MOTOROLA
Technical Data — MC68HC908AS32A
Section 5. EEPROM Memory
5.1 Contents
5.2
5.3
5.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EEPROM Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .65
5.5
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .66
EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . .67
EEPROM Program/Erase Protection . . . . . . . . . . . . . . . .67
EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . .68
EEPROM Programming and Erasing . . . . . . . . . . . . . . . .69
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.6
EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Control Register. . . . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Array Configuration Register . . . . . . . . . . . . . .75
EEPROM Nonvolatile Register . . . . . . . . . . . . . . . . . . . . .77
EEPROM Timebase Divider Register . . . . . . . . . . . . . . . .78
EEPROM Timebase Divider Non-Volatile Register . . . . .80
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.7
5.7.1
5.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
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EEPROM Memory
63
EEPROM Memory
5.2 Introduction
This section describes the 512 bytes of electrically erasable
programmable read-only memory (EEPROM) residing at address range
$0800 to $09FF.
5.3 Features
Features of the EEPROM include the following:
•
•
512 bytes Non-Volatile Memory
Byte, Block, or Bulk Erasable
•
Non-Volatile EEPROM Configuration and Block Protection
Options
•
•
•
On-chip Charge Pump for Programming/Erasing
Security Option
AUTO Bit Driven Programming/Erasing Time Feature
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EEPROM Memory
EEPROM Memory
EEPROM Register Summary
5.4 EEPROM Register Summary
The EEPROM Register Summary is shown in Figure 5-1.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIV Non-volatile
EEDIVSECD
R
R
R
R
EEDIV10 EEDIV9 EEDIV8
$FE10
Register High Write:
(EEDIVHNVR)*
Reset:
Unaffected by reset; $FF when blank
Read:
EEDIV Non-volatile
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
$FE11
$FE1A
$FE1B
$FE1C
$FE1D
$FE1F
Register Low Write:
(EEDIVLNVR)*
Reset:
Unaffected by reset; $FF when blank
Read:
0
0
0
0
EEDIVSECD
EEDIV10 EEDIV9 EEDIV8
EE Divider Register High
Write:
(EEDIVH)
Reset:
Read:
Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
Contents of EEDIVLNVR ($FE11)
EE Divider Register Low
Write:
(EEDIVL)
Reset:
Read:
EEPROM Non-volatile
UNUSED UNUSED UNUSED EEPRTCT EEBP3
EEBP2
EEBP1
EEBP0
Register Write:
(EENVR)*
Reset:
Unaffected by reset; $FF when blank; factory programmed $F0
0
Read:
EEPROM Control
UNUSED
0
EEOFF EERAS1 EERAS0 EELAT
AUTO
EEPGM
Register Write:
(EECR)
Reset:
0
0
0
0
0
0
0
Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3
EEBP2
EEBP1
EEBP0
EEPROM Array
Configuration Register Write:
(EEACR)
Reset:
Contents of EENVR ($FE1C)
* Non-volatile EEPROM register; write by programming.
= Unimplemented
R
= Reserved
UNUSED = Unused
Figure 5-1. EEPROM Register Summary
MC68HC908AS32A — Rev 0.0
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MOTOROLA
EEPROM Memory
EEPROM Memory
5.5 Functional Description
The 512 bytes of EEPROM are located at $0800-$09FF and can be
programmed or erased without an additional external high voltage
supply. The program and erase operations are enabled through the use
of an internal charge pump. For each byte of EEPROM, the write/erase
endurance is 10,000 cycles.
5.5.1 EEPROM Configuration
The 8-bit EEPROM Non-Volatile Register (EENVR) and the 16-bit
EEPROM Timebase Divider Non-Volatile Register (EEDIVNVR) contain
the default settings for the following EEPROM configurations:
•
•
•
EEPROM Timebase Reference
EEPROM Security Option
EEPROM Block Protection
EENVR and EEDIVNVR are non-volatile EEPROM registers. They are
programmed and erased in the same way as EEPROM bytes. The
contents of these registers are loaded into their respective volatile
registers during a MCU reset. The values in these read/write volatile
registers define the EEPROM configurations.
For EENVR, the corresponding volatile register is the EEPROM Array
Configuration Register (EEACR). For the EEDIVNCR (two 8-bit
registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile
register is the EEPROM Divider Register (EEDIV: EEDIVH and EE
DIVL).
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EEPROM Memory
Functional Description
5.5.2 EEPROM Timebase Requirements
A 35µs timebase is required by the EEPROM control circuit for program
and erase of EEPROM content. This timebase is derived from dividing
the CGMXCLK or bus clock (selected by EEDIVCLK bit in CONFIG-2
Register) using a timebase divider circuit controlled by the 16-bit
EEPROM Timebase Divider EEDIV Register (EEDIVH and EEDIVL).
As the CGMXCLK or bus clock is user selected, the EEPROM Timebase
Divider Register must be configured with the appropriate value to obtain
the 35 µs. The timebase divider value is calculated by using the following
formula:
EEDIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5]
This value is written to the EEPROM Timebase Divider Register
(EEDIVH and EEDIVL) or programmed into the EEPROM Timebase
Divider Non-Volatile Register prior to any EEPROM program or erase
operations(see EEPROM Configuration on page 66 and EEPROM
Timebase Requirements on page 67).
5.5.3 EEPROM Program/Erase Protection
The EEPROM has a special feature that designates the 16 bytes of
addresses from $08F0 to $08FF to be permanently secured. This
program/erase protect option is enabled by programming the EEPRTCT
bit in the EEPROM Non-Volatile Register (EENVR) to a logic zero.
Once the EEPRTCT bit is programmed to 0 for the first time:
•
Programming and erasing of secured locations $08F0 to $08FF is
permanently disabled.
•
•
•
Secured locations $08F0 to $08FF can be read as normal.
Programming and erasing of EENVR is permanently disabled.
Bulk and Block Erase operations are disabled for the unprotected
locations $0800-$08EF, $0900-$09FF.
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EEPROM Memory
•
Single byte program and erase operations are still available for
locations $0800-$08EF and $0900-$09FF for all bytes that are not
protected by the EEPROM Block Protect EEBPx bits (see
EEPROM Block Protection on page 68 and EEPROM Array
Configuration Register on page 75)
NOTE: Once armed, the protect option is permanently enabled. As a
consequence, all functions in the EENVR will remain in the state they
were in immediately before the security was enabled.
5.5.4 EEPROM Block Protection
The 512 bytes of EEPROM are divided into four 128-byte blocks. Each
of these blocks can be protected from erase/program operations by
setting the EEBPx bit in the EENVR. Table 5-1 shows the address
ranges for the blocks.
Table 5-1. EEPROM Array Address Blocks
Block Number (EEBPx)
Address Range
$0800–$087F
$0880–$08FF
$0900–$097F
$0980–$09FF
EEBP0
EEBP1
EEBP2
EEBP3
These bits are effective after a reset or a upon read of the EENVR
register. The block protect configuration can be modified by
erasing/programming the corresponding bits in the EENVR register and
then reading the EENVR register. Please see EEPROM Array
Configuration Register on page 75 for more information.
NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a
system reset, the EEDIV security feature is permanently enabled
because the EEDIVSECD bit in the EEDIVH is always loaded with 0
thereafter. Once this security feature is armed, erase and program mode
are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the
EEDIVH and EEDIVL registers are also disabled. Therefore, be cautious
on programming a value into the EEDIVHNVR.
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EEPROM Memory
Functional Description
5.5.5 EEPROM Programming and Erasing
The unprogrammed or erase state of an EEPROM bit is a logic 1. The
factory default for all bytes within the EEPROM array is $FF.
The programming operation changes an EEPROM bit from logic 1 to
logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a
single programming operation, the minimum EEPROM programming
size is one bit; the maximum is eight bits (one byte).
The erase operation changes an EEPROM bit from logic 0 to logic 1. In
a single erase operation, the minimum EEPROM erase size is one byte;
the maximum is the entire EEPROM array.
The EEPROM can be programmed such that one or multiple bits are
programmed (written to a logic 0) at a time. However, the user may never
program the same bit location more than once before erasing the entire
byte. In other words, the user is not allowed to program a logic 0 to a bit
that is already programmed (bit state is already logic 0).
For some applications it might be advantageous to track more than 10K
events with a single byte of EEPROM by programming one bit at a time.
For that purpose, a special selective bit programming technique is
available. An example of this technique is illustrated in Table 5-2.
Table 5-2. Example Selective Bit Programming Description
Program Data
in Binary
Result
in Binary
Description
Original state of byte (erased)
n/a
1111:1111
1111:1110
1111:1100
1111:1000
1111:0000
First event is recorded by programming bit position 0
Second event is recorded by programming bit position 1
Third event is recorded by programming bit position 2
Fourth event is recorded by programming bit position 3
Events five through eight are recorded in a similar fashion
1111:1110
1111:1101
1111:1011
1111:0111
Note that none of the bit locations are actually programmed more than
once although the byte was programmed eight times.
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EEPROM Memory
When this technique is utilized, a program/erase cycle is defined as
multiple program sequences (up to eight) to a unique location followed
by a single erase operation.
Pro g ra m / Era se
Using AUTO Bit
An additional feature available for EEPROM program and erase
operations is the AUTO mode. When enabled, AUTO mode will activate
an internal timer that will automatically terminate the program/erase
cycle and clear the EEPGM bit. Please see EEPROM Programming on
page 70, EEPROM Erasing on page 71 and EEPROM Control
Register on page 73 for more information.
EEPROM
Pro g ra m m ing
The unprogrammed or erase state of an EEPROM bit is a logic 1.
Programming changes the state to a logic 0. Only EEPROM bytes in the
non-protected blocks and the EENVR register can be programmed.
Use the following procedure to program a byte of EEPROM:
1. Clear EERAS1 and EERAS0 and set EELAT in the EECR.(A)
NOTE: If using the AUTO mode, also set the AUTO bit during Step 1.
2. Write the desired data to the desired EEPROM address.(B)
3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set.
4. Wait for time, tEEPGM, to program the byte.
5. Clear EEPGM bit.
6. Wait for time, tEEFPV, for the programming voltage to fall. Go to
Step 8.
7. Poll the EEPGM bit until it is cleared by the internal timer.(D)
8. Clear EELAT bits.(E)
NOTE: A. EERAS1 and EERAS0 must be cleared for programming. Setting the
EELAT bit configures the address and data buses to latch data for
programming the array. Only data with a valid EEPROM address will be
latched. If EELAT is set, other writes to the EECR will be allowed after a
valid EEPROM write.
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Functional Description
B. If more than one valid EEPROM write occurs, the last address and
data will be latched overriding the previous address and data. Once data
is written to the desired address, do not read EEPROM locations other
than the written location. (Reading an EEPROM location returns the
latched data and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-
valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any EEPROM
locations; otherwise, the current program cycle will be unsuccessful.
When EEPGM is set, the on-board programming sequence will be
activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than tEEPGM. However, on other MCUs, this delay time may be different.
For forward compatibility, software should not make any dependency on
this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM array.
EEPROM Era sing
The programmed state of an EEPROM bit is logic 0. Erasing changes
the state to a logic 1. Only EEPROM bytes in the non-protected blocks
and the EENVR register can be erased.
Use the following procedure to erase a byte, block or the entire
EEPROM array:
1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set
EELAT in EECR.(A)
NOTE: If using the AUTO mode, also set the AUTO bit in Step 1.
2. Byte erase: write any data to the desired address.(B)
Block erase: write any data to an address within the desired
block.(B)
Bulk erase: write any data to an address within the array.(B)
3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set.
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4. Wait for a time: tEEBYTE for byte erase; tEEBLOCK for block erase;
tEEBULK. for bulk erase.
5. Clear EEPGM bit.
6. Wait for a time, tEEFPV, for the erasing voltage to fall. Go to Step 8.
7. Poll the EEPGM bit until it is cleared by the internal timer.(D)
8. Clear EELAT bits.(E)
NOTE: A. Setting the EELAT bit configures the address and data buses to latch
data for erasing the array. Only valid EEPROM addresses will be
latched. If EELAT is set, other writes to the EECR will be allowed after a
valid EEPROM write.
B. If more than one valid EEPROM write occurs, the last address and
data will be latched overriding the previous address and data. Once data
is written to the desired address, do not read EEPROM locations other
than the written location. (Reading an EEPROM location returns the
latched data and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-
valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any EEPROM
locations; otherwise, the current program cycle will be unsuccessful.
When EEPGM is set, the on-board programming sequence will be
activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than tEEBYTE /tEEBLOCK EEBULK. However, on other MCUs, this delay
/t
time may be different. For forward compatibility, software should not
make any dependency on this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM array.
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EEPROM Register Descriptions
5.6 EEPROM Register Descriptions
Four I/O registers and three non-volatile registers control program, erase
and options of the EEPROM array.
5.6.1 EEPROM Control Register
This read/write register controls programming/erasing of the array.
Address: $FE1D
Bit 7
UNUSED
0
6
0
5
4
3
2
1
AUTO
0
Bit 0
EEPGM
0
Read:
Write:
Reset:
EEOFF EERAS1 EERAS0 EELAT
0
0
0
0
0
= Unimplemented
Figure 5-2. EEPROM Control Register (EECR)
Bit 7— Unused bit
This read/write bit is software programmable but has no functionality.
EEOFF — EEPROM power down
This read/write bit disables the EEPROM module for lower power
consumption. Any attempts to access the array will give unpredictable
results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
EERAS1 and EERAS0 — Erase/Program Mode Select Bits
These read/write bits set the erase modes. Reset clears these bits.
Table 5-3. EEPROM Program/Erase Mode Select
EEBPx
EERAS1
EERAS0
MODE
Byte Program
Byte Erase
0
0
0
1
1
X
0
1
0
1
X
0
0
Block Erase
Bulk Erase
0
1
No Erase/Program
X = don’t care
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EEPROM Memory
EEPROM Memory
EELAT — EEPROM Latch Control
This read/write bit latches the address and data buses for
programming the EEPROM array. EELAT cannot be cleared if
EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming or erase
operation
0 = Buses configured for normal operation
AUTO — Automatic termination of program/erase cycle
When AUTO is set, EEPGM is cleared automatically after the
program/erase cycle is terminated by the internal timer.
(See note D for EEPROM Programming on page 70, EEPROM
Erasing on page 71 and EEPROM Memory Characteristics on
page 430)
1 = Automatic clear of EEPGM is enabled
0 = Automatic clear of EEPGM is disabled
EEPGM — EEPROM Program/Erase Enable
This read/write bit enables the internal charge pump and applies the
programming/erasing voltage to the EEPROM array if the EELAT bit
is set and a write to a valid EEPROM location has occurred. Reset
clears the EEPGM bit.
1 = EEPROM programming/erasing power switched on
0 = EEPROM programming/erasing power switched off
NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single
instruction will clear EEPGM only to allow time for the removal of high
voltage.
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EEPROM Register Descriptions
5.6.2 EEPROM Array Configuration Register
The EEPROM array configuration register configures EEPROM security
and EEPROM block protection.
This read-only register is loaded with the contents of the EEPROM non-
volatile register (EENVR) after a reset.
Address: $FE1F
Bit 7
6
5
4
3
2
1
Bit 0
Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3
Write:
EEBP2
EEBP1
EEBP0
Reset:
Contents of EENVR ($FE1C)
Figure 5-3. EEPROM Array Configuration Register (EEACR)
Bit 7:5 — Unused Bits
These read/write bits are software programmable but have no
functionality.
EEPRTCT — EEPROM Protection Bit
The EEPRTCT bit is used to enable the security feature in the
EEPROM (see EEPROM Program/Erase Protection).
1 = EEPROM security disabled
0 = EEPROM security enabled
This feature is a write-once feature. Once the protection is enabled it
may not be disabled.
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EEPROM Memory
EEBP[3:0] — EEPROM Block Protection Bits
These bits prevent blocks of EEPROM array from being programmed
or erased.
1 = EEPROM array block is protected
0 = EEPROM array block is unprotected
Block Number (EEBPx)
Address Range
$0800–$087F
$0880–$08FF
$0900–$097F
$0980–$09FF
EEBP0
EEBP1
EEBP2
EEBP3
Table 5-4. EEPROM Block Protect and Security Summary
Address Range
EEBPx
EEPRTCT = 1
EEPRTCT = 0
Byte Programming
Available
Bulk, Block and Byte Only Byte Erasing
Byte Programming
Available
EEBP0 = 0
EEBP0 = 1
EEBP1 = 0
EEBP1 = 1
EEBP1 = 0
EEBP1 = 1
EEBP2 = 0
EEBP2 = 1
EEBP3 = 0
EEBP3 = 1
$0800 - $087F
Erasing Available
Available
Protected
Protected
Byte Programming
Available
Bulk, Block and Byte Only Byte Erasing
Byte Programming
Available
$0880 - $08EF
$08F0 - $08FF
$0900 - $097F
$0980 - $09FF
Erasing Available
Available
Protected
Protected
Byte Programming
Available
Bulk, Block and Byte
Erasing Available
Secured
(No Programming
or Erasing)
Protected
Byte Programming
Available
Bulk, Block and Byte Only Byte Erasing
Byte Programming
Available
Erasing Available
Available
Protected
Protected
Byte Programming
Available
Bulk, Block and Byte Only Byte Erasing
Byte Programming
Available
Available
Available
Protected
Protected
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EEPROM Register Descriptions
5.6.3 EEPROM Nonvolatile Register
The contents of this register is loaded into the EEPROM array
configuration register (EEACR) after a reset.
This register is erased and programmed in the same way as an
EEPROM byte. (See EEPROM Control Register on page 73 for
individual bit descriptions).
Address: $FE1C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
UNUSED UNUSED UNUSED EEPRTCT EEBP3
EEBP2
EEBP1
EEBP0
PV
= Unimplemented
PV = Programmed value or 1 in the erased state.
Figure 5-4. EEPROM Nonvolatile Register (EENVR)
NOTE: The EENVR will leave the factory programmed with $F0 such that the full
array is available and unprotected.
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EEPROM Memory
5.6.4 EEPROM Timebase Divider Register
The 16-bit EEPROM timebase divider register consists of two 8-bit
registers: EEDIVH and EEDIVL. The 11-bit value in this register is used
to configure the timebase divider circuit to obtain the 35 µs timebase for
EEPROM control.
These two read/write registers are respectively loaded with the contents
of the EEPROM timebase divider on-volatile registers (EEDIVHNVR and
EEDIVLNVR) after a reset.
Address: $FE1A
Bit 7
6
0
5
0
4
0
3
0
2
1
Bit 0
Read:
Write:
Reset:
EEDIVSECD
EEDIV10 EEDIV9 EEDIV8
Contents of EEDIVHNVR ($FE10), Bits [6:3] = 0
= Unimplemented
Figure 5-5. EEDIV Divider High Register (EEDIVH)
Address: $FE1B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIV7 EEDIV6 EEDIV5
EEDIV4
EEDIV3 EEDIV2 EEDIV1 EEDIV0
Write:
Reset:
Contents of EEDIVLNVR ($FE11)
Figure 5-6. EEDIV Divider Low Register (EEDIVL)
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EEPROM Memory
EEPROM Register Descriptions
EEDIVSECD — EEPROM Divider Security Disable
This bit enables/disables the security feature of the EEDIV registers.
When EEDIV security feature is enabled, the state of the registers
EEDIVH and EEDIVL are locked (including EEDIVSECD bit). The
EEDIVHNVR and EEDIVLNVR non-volatile memory registers are
also protected from being erased/programmed.
1 = EEDIV security feature disabled
0 = EEDIV security feature enabled
EEDIV[10:0] — EEPROM timebase prescaler
These prescaler bits store the value of EEDIV which is used as the
divisor to derive a timebase of 35µs from the selected reference clock
source (CGMXCLK or bus block in the CONFIG-2 register) for the
EEPROM related internal timer and circuits. EEDIV[10:0] bits are
readable at any time. They are writable when EELAT = 0 and
EEDIVSECD = 1.
The EEDIV value is calculated by the following formula:
EEDIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5]
Where the result inside the bracket is rounded down to the nearest
integer value
For example, if the reference frequency is 4.9152MHz, the EEDIV value
is 172
NOTE: Programming/erasing the EEPROM with an improper EEDIV value may
result in data lost and reduce endurance of the EEPROM device.
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EEPROM Memory
EEPROM Memory
5.6.5 EEPROM Timebase Divider Non-Volatile Register
The 16-bit EEPROM timebase divider non-volatile register consists of
two 8-bit registers: EEDIVHNVR and EEDIVLNVR. The contents of
these two registers are respectively loaded into the EEPROM timebase
divider registers, EEDIVH and EEDIVL, after a reset.
These two registers are erased and programmed in the same way as an
EEPROM byte.
Address: $FE10
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
EEDIVSECD
R
R
R
R
EEDIV10 EEDIV9 EEDIV8
Unaffected by reset; $FF when blank
=Reserved
R
Figure 5-7. EEPROM Divider Non-Volatile Register High
(EEDIVHNVR))
Address: $FE11
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
EEDIV7 EEDIV6 EEDIV5
EEDIV4
EEDIV3 EEDIV2 EEDIV1 EEDIV0
Unaffected by reset; $FF when blank
Figure 5-8. EEPROM Divider Non-Volatile Register Low (EEDIVLNVR)
These two registers are protected from erase and program operations if
the EEDIVSECD is set to logic 1 in the EEDIVH (see EEPROM
Timebase Divider Register) or programmed to a logic 1 in the
EEDIVHNVR.
NOTE: Once EEDIVSECD in the EEDIVHNVR is programmed to 0 and after a
system reset, the EEDIV security feature is permanently enabled
because the EEDIVSECD bit in the EEDIVH is always loaded with 0
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Low-Power Modes
thereafter. Once this security feature is armed, erase and program mode
are disabled for EEDIVHNVR and EEDIVLNVR. Modifications to the
EEDIVH and EEDIVL registers are also disabled. Therefore, care should
be taken before programming a value into the EEDIVHNVR.
5.7 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low power-
consumption standby modes.
5.7.1 Wait Mode
5.7.2 Stop Mode
The WAIT instruction does not affect the EEPROM. It is possible to start
the program or erase sequence on the EEPROM and put the MCU in
wait mode.
The STOP instruction reduces the EEPROM power consumption to a
minimum. The STOP instruction should not be executed while a
programming or erasing sequence is in progress.
If stop mode is entered while EELAT and EEPGM are set, the
programming sequence will be stopped and the programming voltage to
the EEPROM array removed. The programming sequence will be
restarted after leaving stop mode; access to the EEPROM is only
possible after the programming sequence has completed.
If stop mode is entered while EELAT and EEPGM is cleared, the
programming sequence will be terminated abruptly.
In either case, the data integrity of the EEPROM is not guaranteed.
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Technical Data — MC68HC908AS32A
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
6.4
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Index register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . .87
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.6
6.6.1
6.6.2
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
STOP mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.7
6.8
6.9
CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . .90
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
6.2 Introduction
This section describes the central processor unit (CPU8). The M68HC08
CPU is an enhanced and fully object-code-compatible version of the
M68HC05 CPU. The CPU08 Reference Manual (Motorola document
number CPU08RM/AD) contains a description of the CPU instruction
set, addressing modes, and architecture.
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
6.3 Features
Features of the CPU include the following:
•
•
•
•
•
•
•
•
•
•
Full upward, object-code compatibility with M68HC05 family
16-bit stack pointer with stack manipulation instructions
16-bit index register with X-register manipulation instructions
8.4MHz CPU internal bus frequency
64K byte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Low-power STOP and WAIT Modes
6.4 CPU registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
0
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
7
V 1 1 H
I
N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU registers
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Central Processor Unit (CPU)
CPU registers
6.4.1 Accumulator (A)
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
A
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
6.4.2 Index register (H:X)
The 16-bit index register allows indexed addressing of a 64K byte
memory space. H is the upper byte of the index register and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
Bit
Bit
0
15 14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
1
Read:
Write:
Reset:
H:X
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index register (H:X)
The index register can also be used as a temporary data storage
location.
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
6.4.3 Stack pointer (SP)
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
Bit
0
15 14 13 12 11 10
9
0
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
1
Read:
Write:
Reset:
SP
0
0
0
0
0
0
1
Figure 6-4. Stack pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.
6.4.4 Program counter (PC)
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
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MOTOROLA
Central Processor Unit (CPU)
CPU registers
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
Bit
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
PC
Loaded with vector from $FFFE and $FFFF
Figure 6-5. Program counter (PC)
6.4.5 Condition code register (CCR)
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to ‘1’. The following paragraphs describe the
functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
3
I
2
1
Z
X
Bit 0
C
Read:
Write:
Reset:
CCR
H
X
N
X
X
1
X
X = Indeterminate
Figure 6-6. Condition code register (CCR)
V — Overflow flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
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Central Processor Unit (CPU)
87
Central Processor Unit (CPU)
H — Half-carry flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The half-
carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return from interrupt (RTI) instruction pulls the CPU registers from the
stack and restores the interrupt mask from the stack. After any reset, the
interrupt mask is set and can only be cleared by the clear interrupt mask
software instruction (CLI).
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Central Processor Unit (CPU)
Arithmetic/logic unit (ALU)
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/borrow flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions - such as bit test and
branch, shift, and rotate - also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/logic unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.
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Central Processor Unit (CPU)
Central Processor Unit (CPU)
6.6 Low-power modes
The WAIT and STOP instructions put the MCU in low--power
consumption standby modes.
6.6.1 WAIT mode
The WAIT instruction:
•
•
clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
6.6.2 STOP mode
The STOP instruction:
•
clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
•
Disables the CPU clock
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
6.7 CPU during break interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Break Module (BRK). The program
counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
Table 6-1. Instruction Set Summary
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ii
A9
B9
C9
D9
E9
F9
9E
E9
9E
D9
dd
hh
ll
ADC #opr
ADC opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
ADC opr
ee
ff
ff
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Add with Carry
A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
ff
ee
ff
ii
AB
BB
CB
DB
EB
FB
9E
EB
9E
DB
dd
hh
ll
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
ADD opr
ee
ff
ff
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕
IX1
IX
SP1
SP2
ff
ee
ff
Add Immediate Value (Signed) to
SP
AIS #opr
AIX #opr
–
–
–
–
–
–
–
–
–
–
–
–
IMM
IMM
A7
AF
ii
ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
Add Immediate Value (Signed) to
H:X
ii
A4
B4
C4
D4
E4
F4
9E
E4
9E
D4
dd
hh
ll
AND #opr
AND opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
AND opr
ee
ff
ff
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Logical AND
A ← (A) & (M)
0
–
–
↕ ↕ –
IX1
IX
SP1
SP2
ff
ee
ff
38
48
58
68
78
9E
68
ASL opr
ASLA
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
ASLX
Arithmetic Shift Left
(Same as LSL)
C
0
↕ –
–
–
↕ ↕ ↕
ASL opr,X
ASL ,X
ASL opr,SP
ff
ff
b7
b7
b0
b0
SP1
37
47
57
67
77
9E
67
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
C
Arithmetic Shift Right
↕ –
↕ ↕ ↕
ff
ff
SP1
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
REL
24
rr
3
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
Branch if Carry Bit Set (Same as
BLO)
BCS rel
BEQ rel
BGE opr
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
PC ← (PC) + 2 + rel ? (N V) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
25
27
90
rr
rr
rr
3
3
3
Branch if Equal
Branch if Greater Than or Equal
To (Signed Operands)
Branch if Greater Than (Signed
Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BGT opr
–
–
–
–
–
–
REL
92
rr
3
0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
28
29
22
rr
rr
rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
REL
24
rr
3
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
2F
2E
rr
rr
3
3
ii
A5
B5
C5
D5
E5
F5
9E
E5
9E
D5
dd
hh
ll
BIT #opr
BIT opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
BIT opr
ee
ff
ff
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
(A) & (M)
0
–
–
–
–
↕ ↕ –
IX1
IX
SP1
SP2
ff
ee
ff
Branch if Less Than or Equal To
(Signed Operands)
PC ← (PC) + 2 + rel ? (Z) | (N V) =
BLE opr
–
–
–
–
REL
93
rr
3
1
BLO rel
BLS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
25
23
rr
rr
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
Branch if Less Than (Signed
Operands)
BLT opr
–
–
–
–
–
–
REL
91
rr
3
PC ← (PC) + 2 + rel ? (N
V) =1
Advance Information
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Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
BMC rel
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
REL
REL
REL
REL
REL
REL
2C
2B
2D
26
2A
20
rr
rr
rr
rr
rr
rr
3
3
3
3
3
3
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
01
03
05
07
09
0B
0D
0F
5
5
5
5
5
5
5
5
BRCLR
Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
↕
n,opr,rel
dd
rr
dd
rr
BRN rel
Branch Never
PC ← (PC) + 2
–
REL
21
rr
3
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
00
02
04
06
08
0A
0C
0E
5
5
5
5
5
5
5
5
BRSET
n,opr,rel
Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
↕
dd
rr
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSET n,opr
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
MC68HC908AS32A — Rev 0.0
Advance Information
93
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
–
–
–
–
–
–
REL
AD
rr
4
PC ← (PC) + rel
CBEQ opr,rel
CBEQA
31
41
51
61
71
9E
61
dd
rr
#opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
IMM
IMM
IX1+
IX+
5
4
4
5
4
6
CBEQX
ii rr
ii rr
ff rr
rr
#opr,rel
Compare and Branch if Equal
–
–
–
–
–
–
CBEQ
opr,X+,rel
CBEQ X+,rel
CBEQ
SP1
ff rr
opr,SP,rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
–
–
–
–
0
INH
INH
98
9A
1
2
Clear Interrupt Mask
0
–
3F
4F
5F
8C
6F
7F
9E
6F
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
INH
IX1
IX
dd
3
1
1
1
3
2
4
CLRX
CLRH
Clear
0
–
–
0
1
–
CLR opr,X
CLR ,X
ff
ff
CLR opr,SP
SP1
ii
A1
B1
C1
D1
E1
F1
9E
E1
9E
D1
dd
hh
ll
CMP #opr
CMP opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
CMP opr
ee
ff
ff
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Compare A with M
(A) – (M)
↕ –
–
↕ ↕ ↕
IX1
IX
SP1
SP2
ff
ee
ff
33
43
53
63
73
9E
63
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
COMX
Complement (One’s
0
–
–
–
↕ ↕ 1
COM opr,X
COM ,X
COM opr,SP
Complement)
ff
ff
SP1
ii
ii+1
dd
CPHX #opr
CPHX opr
IMM
DIR
65
75
3
4
Compare H:X with M
Compare X with M
(H:X) – (M:M + 1)
↕ –
↕ ↕ ↕
ii
A3
B3
C3
D3
E3
F3
9E
E3
9E
D3
dd
hh
ll
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
2
3
4
4
3
2
4
5
ee
ff
ff
(X) – (M)
↕ –
–
↕ ↕ ↕
SP1
SP2
ff
ee
ff
Advance Information
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MC68HC908AS32A — Rev 0.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
(A)
DAA
Decimal Adjust A
U –
–
↕ ↕ ↕ INH
72
2
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) –
1
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ
3B
4B
5B
6B
7B
9E
6B
dd
rr
5
3
3
5
4
6
DIR
INH
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
Decrement and Branch if Not
Zero
rr
–
–
–
–
–
–
INH
IX1
IX
rr
opr,X,rel
ff rr
rr
DBNZ X,rel
DBNZ
opr,SP,rel
SP1
ff rr
3A
4A
5A
6A
7A
9E
6A
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
DECX
Decrement
Divide
↕ –
–
–
↕ ↕ –
DEC opr,X
DEC ,X
DEC opr,SP
ff
ff
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
–
–
↕ ↕ INH
52
7
ii
A8
B8
C8
D8
E8
F8
9E
E8
9E
D8
dd
hh
ll
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IMM
DIR
EXT
IX2
IX1
IX
2
3
4
4
3
2
4
5
ee
ff
ff
Exclusive OR M with A
0
–
↕ ↕ –
A ← (A
M)
SP1
SP2
ff
ee
ff
3C
4C
5C
6C
7C
9E
6C
INC opr
INCA
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
INCX
Increment
↕ –
–
–
–
↕ ↕ –
INC opr,X
INC ,X
INC opr,SP
ff
ff
SP1
dd
hh
ll
ee
ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
2
3
4
3
2
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
dd
hh
ll
ee
ff
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
MC68HC908AS32A — Rev 0.0
Advance Information
95
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ii
A6
B6
C6
D6
E6
F6
9E
E6
9E
D6
dd
hh
ll
LDA #opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
LDA opr
LDA opr
ee
ff
ff
LDA opr,X
LDA opr,X
LDA ,X
Load A from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
↕ ↕ –
↕ ↕ –
↕ ↕ –
IX1
IX
SP1
SP2
LDA opr,SP
LDA opr,SP
ff
ee
ff
LDHX #opr
LDHX opr
IMM
DIR
45
55
ii jj
dd
3
4
Load H:X from M
Load X from M
ii
AE
BE
CE
DE
EE
FE
9E
EE
9E
DE
dd
hh
ll
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
2
3
4
4
3
2
4
5
ee
ff
ff
SP1
SP2
ff
ee
ff
38
48
58
68
78
9E
68
LSL opr
LSLA
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
C
0
↕ –
–
–
↕ ↕ ↕
LSL opr,X
LSL ,X
LSL opr,SP
ff
ff
b7
b0
SP1
34
44
54
64
74
9E
64
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
0
C
Logical Shift Right
↕ –
0 ↕ ↕
ff
ff
b7
b0
SP1
dd
dd
dd
ii
dd
dd
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E
5E
6E
7E
5
4
4
4
(M)
← (M)
Source
Destination
DIX+
IMD
IX+D
Move
0
–
–
–
↕ ↕ –
H:X ← (H:X) + 1 (IX+D, DIX+)
MUL
Unsigned multiply
X:A ← (X) × (A)
–
0
–
–
0
INH
42
5
30
40
50
60
70
9E
60
NEG opr
NEGA
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
Negate (Two’s Complement)
↕ –
–
↕ ↕ ↕
NEG opr,X
NEG ,X
NEG opr,SP
ff
ff
SP1
NOP
NSA
No Operation
None
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
9D
62
1
3
Nibble Swap A
A ← (A[3:0]:A[7:4])
Advance Information
96
MC68HC908AS32A — Rev 0.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
ii
AA
BA
CA
DA
EA
FA
9E
EA
9E
DA
dd
hh
ll
ORA #opr
ORA opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
ORA opr
ee
ff
ff
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
A ← (A) | (M)
0
–
–
↕ ↕ –
IX1
IX
SP1
SP2
ff
ee
ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
INH
INH
INH
INH
87
8B
89
86
8A
88
2
2
2
2
2
2
39
49
59
69
79
9E
69
ROL opr
ROLA
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
ROLX
C
Rotate Left through Carry
Rotate Right through Carry
↕ –
–
↕ ↕ ↕
ROL opr,X
ROL ,X
ROL opr,SP
ff
ff
b7
b0
SP1
36
46
56
66
76
9E
66
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
DIR
INH
INH
IX1
IX
dd
4
1
1
4
3
5
C
↕ –
–
–
↕ ↕ ↕
ff
ff
b7
b0
SP1
RSP
RTI
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕ ↕ ↕ ↕ ↕ ↕ INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
–
–
–
–
–
–
INH
81
4
ii
A2
B2
C2
D2
E2
F2
9E
E2
9E
D2
dd
hh
ll
SBC #opr
SBC opr
IMM
DIR
EXT
IX2
2
3
4
4
3
2
4
5
SBC opr
ee
ff
ff
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
Set Carry Bit
A ← (A) – (M) – (C)
↕ –
–
–
↕ ↕ ↕
IX1
IX
SP1
SP2
ff
ee
ff
SEC
C ← 1
–
–
–
–
1
INH
99
1
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97
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
SEI
Set Interrupt Mask
I ← 1
–
–
1
–
–
–
INH
9B
2
dd
hh
ll
ee
ff
ff
B7
C7
D7
E7
F7
9E
E7
9E
D7
STA opr
DIR
EXT
IX2
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
ff
ee
ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
↕ ↕ – DIR
35
8E
dd
4
1
STOP
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
0
–
–
–
INH
dd
hh
ll
ee
ff
ff
BF
CF
DF
EF
FF
9E
EF
9E
DF
STX opr
DIR
EXT
IX2
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
↕ ↕ – IX1
IX
SP1
SP2
ff
ee
ff
ii
A0
B0
C0
D0
E0
F0
9E
E0
9E
D0
dd
hh
ll
SUB #opr
SUB opr
IMM
DIR
EXT
2
3
4
4
3
2
4
5
SUB opr
ee
ff
ff
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IX2
↕ ↕ ↕
IX1
Subtract
A ← (A) – (M)
↕ –
–
IX
SP1
SP2
ff
ee
ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
–
INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
↕ ↕ ↕ ↕ ↕ ↕ INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
Transfer CCR to A
A ← (CCR)
3D
4D
5D
6D
7D
9E
6D
TST opr
TSTA
DIR
INH
INH
IX1
IX
dd
3
1
1
3
2
4
TSTX
Test for Negative or Zero
Transfer SP to H:X
(A) – $00 or (X) – $00 or (M) – $00
H:X ← (SP) + 1
0
–
–
–
–
↕ ↕ –
TST opr,X
TST ,X
TST opr,SP
ff
ff
SP1
TSX
–
–
–
–
INH
95
2
Advance Information
98
MC68HC908AS32A — Rev 0.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
V H I N Z C
TXA
TXS
A Accumulatorn
Transfer X to A
Transfer H:X to SP
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
INH
INH
9F
94
1
2
(SP) ← (H:X) – 1
Any bit
C Carry/borrow bitopr
CCRCondition code registerPC
ddDirect address of operandPCH
dd rrDirect address of operand and relative offset of branch instructionPCL
DDDirect to direct addressing modeREL
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
DIRDirect addressing moderel
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
DIX+Direct to indexed with post increment addressing moderr
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1
EXTExtended addressing modeSP2
Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressingSP
H Half-carry bitU
Stack pointer
Undefined
H Index register high byteV
hh llHigh and low bytes of operand address in extended addressingX
I Interrupt maskZ
Overflow bit
Index register low byte
Zero bit
ii Immediate operand byte&
IMDImmediate source to direct destination addressing mode|
Logical AND
Logical OR
IMMImmediate addressing mode
INHInherent addressing mode( )
Logical EXCLUSIVE OR
Contents of
IXIndexed, no offset addressing mode–( )
IX+Indexed, no offset, post increment addressing mode#
Negation (two’s complement)
Immediate value
IX+DIndexed with post increment to direct addressing mode«
IX1Indexed, 8-bit offset addressing mode←
IX1+Indexed, 8-bit offset, post increment addressing mode?
IX2Indexed, 16-bit offset addressing mode:
MMemory location↕
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
N Negative bit—
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC908AS32A — Rev 0.0
Advance Information
99
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Advance Information
MC68HC908AS32A — Rev 0.0
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Central Processor Unit (CPU)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 7. System Integration Module (SIM)
7.1 Contents
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.3
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . .104
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Clock Startup from POR or LVI Reset . . . . . . . . . . . . . .105
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . .105
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . .106
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Active Resets from Internal Sources . . . . . . . . . . . . . . .107
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Computer Operating Properly (COP) Reset. . . . . . . .109
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . .109
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . .109
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . .110
7.5
SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
SIM Counter During Power-On Reset. . . . . . . . . . . . . . .110
SIM Counter During Stop Mode Recovery. . . . . . . . . . .111
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . .111
7.5.1
7.5.2
7.5.3
7.6
Program Exception Control. . . . . . . . . . . . . . . . . . . . . . . . .111
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Status Flag Protection in Break Mode . . . . . . . . . . . . . .116
7.6.1
7.6.2
7.6.3
7.6.4
7.7
7.7.1
7.7.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.8
7.8.1
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . .120
MC68HC908AS32A — Rev 0.0
Advance Information
MOTOROLA
System Integration Module (SIM)
101
System Integration Module (SIM)
7.8.2
7.8.3
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . .121
SIM Break Flag Control Register . . . . . . . . . . . . . . . . . .122
7.2 Introduction
This section describes the system integration module (SIM), which
supports up to 32 external and/or internal interrupts. Together with the
central processor unit (CPU), the SIM controls all MCU activities. A block
diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of
the SIM input/output (I/O) registers. The SIM is a system state controller
that coordinates CPU and exception timing. The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
•
•
Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
CPU enable/disable timing
•
Advance Information
102
MC68HC908AS32A — Rev 0.0
MOTOROLA
System Integration Module (SIM)
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO CGM)
SIM
COUNTER
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
÷ 2
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
SIM RESET STATUS REGISTER
COP (FROM COP MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
Register Name
Bit 7
6
R
5
R
4
R
3
R
2
R
0
1
Bit 0
SIM Break Status Register (SBSR)
R
BW
LVI
R
R
0
SIM Reset Status Register (SRSR) POR
PIN
R
COP
R
ILOP
R
ILAD
R
SIM Break Flag Control Register (SBFCR) BCFE
R
R
R
=Reserved
Figure 7-2. SIM I/O Register Summary
MC68HC908AS32A — Rev 0.0
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103
MOTOROLA
System Integration Module (SIM)
System Integration Module (SIM)
Table 7-1. I/O Register Address Summary
Register
Address
SBSR
$FE00
SRSR
$FE01
SBFCR
$FE03
Table 7-2 shows the internal signal names used in this section.
Table 7-2. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
Description
Buffered Version of OSC1 from Clock Generator Module
(CGM)
PLL Output
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
IAB
IDB
Internal Address Bus
Internal Data Bus
PORRST
IRST
Signal from the Power-On Reset Module to the SIM
Internal Reset Signal
R/W
Read/Write Signal
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 7-3. This clock can come
from either an external oscillator or from the on-chip PLL. (See Clock
Generator Module (CGM) on page 123).
7.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Clock Generator Module (CGM) on page 123).
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System Integration Module (SIM)
SIM Bus Clock Control and Generation
7.3.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after 4096 CGMXCLK cycles. The
RST pin is driven low by the SIM during this entire period. The bus clocks
start upon completion of the timeout.
CGMXCLK
OSC1
SIM COUNTER
CLOCK
SELECT
CIRCUIT
A
B
CGMOUT
BUS CLOCK
GENERATORS
÷ 2
÷ 2
CGMVCLK
PLL
S*
*When S = 1,
CGMOUT = B
BCS
SIM
PTC3
MONITOR MODE
USER MODE
CGM
Figure 7-3. CGM Clock Signals
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page
118.
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
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System Integration Module (SIM)
System Integration Module (SIM)
7.4 Reset and System Initialization
The MCU has these reset sources:
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see SIM Counter on page
110), but an external reset does not. Each of the resets sets a
corresponding bit in the SIM reset status register (SRSR) (see SIM
Registers on page 119).
7.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 7-3 for details. Figure
7-4 shows the relative timing.
Table 7-3. PIN Bit Set Timing
Reset Type
POR/LVI
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
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System Integration Module (SIM)
Reset and System Initialization
CGMOUT
RST
VECT H VECT L
IAB
PC
Figure 7-4. External Reset Timing
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see Figure 7-
5). An internal reset can be caused by an illegal address, illegal opcode,
COP timeout, LVI, or POR (see Figure 7-6). Note that for LVI or POR
resets, the SIM cycles through 4096 CGMXCLK cycles during which the
SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 7-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
IRST
RSTPULLED LOW BY MCU
32 CYCLES
RST
CGMXCLK
IAB
32 CYCLES
VECTOR HIGH
Figure 7-5. Internal Reset Timing
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System Integration Module (SIM)
System Integration Module (SIM)
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
Figure 7-6. Sources of Internal Reset
7.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Another sixty-four CGMXCLK cycles later, the
CPU and memories are released from reset to allow the reset vector
sequence to occur.
At power-on, the following events occur:
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.
•
•
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
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System Integration Module (SIM)
Reset and System Initialization
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
CGMXCLK
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 7-7. POR Recovery
7.4.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the
COP bit in the SIM reset status register (SRSR) if the COPD bit in the
CONFIG-1 register is at logic zero.
See Computer Operating Properly (COP) on page 175.
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG-1 register is logic zero, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset.
7.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register SRSR) and
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System Integration Module (SIM)
System Integration Module (SIM)
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
NOTE: Extra care should be exercised if code in this part has been
migrated from older HC08 devices since the illegal address reset
specification may be different. Also, extra care should be exercised
when using this emulation part for development of code to be run
in ROM AZ, AB or AS family parts with a smaller memory size since
some legal addresses will become illegal addresses on the smaller
ROM memory map device and may as a result generate unwanted
resets.
7.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the VDD voltage falls to the VLVII voltage. The LVI bit in the SIM reset
status register (SRSR) is set and a chip reset is asserted if the LVIPWRD
and LVIRSTD bits in the CONFIG-1 register are at logic zero. The RST
pin will be held low until the SIM counts 4096 CGMXCLK cycles after
V
DD rises above VLVIR. Another sixty-four CGMXCLK cycles later, the
CPU is released from reset to allow the reset vector sequence to occur.
See Low Voltage Inhibit (LVI) on page 181.
7.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 12 bits long and is clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
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Program Exception Control
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
7.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt or reset, the SIM
senses the state of the short stop recovery bit, SSREC, in the CONFIG-
1 register. If the SSREC bit is a logic one, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.
7.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See Stop Mode on
page 118 for details. The SIM counter is free-running after all reset
states. See Active Resets from Internal Sources on page 107 for
counter control and internal reset recovery sequences.
7.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
•
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
•
•
Reset
Break interrupts
MC68HC908AS32A — Rev 0.0
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System Integration Module (SIM)
System Integration Module (SIM)
7.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-8 shows interrupt entry timing. Figure
7-10 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared), see Figure
7-9.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
IDB
R/W
DUMMY
PC – 1[7:0] PC–1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
Figure 7-8. Interrupt Entry
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System Integration Module (SIM)
System Integration Module (SIM)
Program Exception Control
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
IRQ1
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(AS MANY INTERRUPTS
AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION.
YES
YES
SWI
INSTRUCTION?
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 7-9. Interrupt Processing
MC68HC908AS32A — Rev 0.0
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System Integration Module (SIM)
System Integration Module (SIM)
MODULE
INTERRUPT
I BIT
IAB
IDB
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC –1 [7:0] PC–1[15:8] OPCODE OPERAND
R/W
Figure 7-10. Interrupt Recovery
Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing
of a hardware interrupt begins after completion of the current
instruction. When the current instruction is complete, the SIM checks
all pending hardware interrupts. If interrupts are not masked (I bit
clear in the condition code register), and if the corresponding interrupt
enable bit is set, the SIM proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service
routine, the pending interrupt is serviced before the LDA instruction is
executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE: To maintain compatibility with the M68HC05, M6805 and M146805
Families the H register is not pushed on the stack during interrupt entry.
If the interrupt service routine modifies the H register or uses the indexed
addressing mode, software should save the H register and then restore
it prior to exiting the routine.
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Program Exception Control
CLI
BACKGROUND
ROUTINE
LDA #$FF
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-11. Interrupt Recognition Example
SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
7.6.2 Reset
All reset sources always have higher priority than interrupts and cannot
be arbitrated.
MC68HC908AS32A — Rev 0.0
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System Integration Module (SIM)
System Integration Module (SIM)
7.6.3 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. See
Break Module (BRK) on page 157. The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt
subsection of each module to see how each module is affected by the
break state.
7.6.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
7.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described
below. Both STOP and WAIT clear the interrupt mask (I) in the condition
code register, allowing interrupts to occur.
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Low-Power Modes
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continue to run. Figure 7-12 shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break wait bit, BW, in the SIM break
status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly
module (COP) is enabled and remains active in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 7-12. Wait Mode Entry Timing
IAB
IDB
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-13. Wait Recovery from Interrupt or Break
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MOTOROLA
System Integration Module (SIM)
System Integration Module (SIM)
32
Cycles
32
Cycles
IAB
$6E0B
RSTVCTH RSTVCTL
IDB $A6
RST
$A6
$A6
CGMXCLK
Figure 7-14. Wait Recovery from Internal Reset
7.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the configuration
register (CONFIG-1). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The break module is inactive in Stop mode. The STOP instruction does
not affect break module register states.
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 7-15 shows stop mode entry timing.
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System Integration Module (SIM)
SIM Registers
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-15. Stop Mode Entry Timing
STOP RECOVERY PERIOD
CGMXCLK
INT/BREAK
IAB
STOP + 2
STOP + 2
SP
SP –1
SP –2
SP –3
STOP +1
Figure 7-16. Stop Mode Recovery from Interrupt or Break
7.8 SIM Registers
The SIM has three memory mapped registers.
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System Integration Module (SIM)
7.8.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break
caused an exit from wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
BW
Bit 0
R
Read:
Write:
Reset:
R
R
R
R
R
R
See Note
0
R
= Reserved
NOTE: Writing a logic 0 clears BW
Figure 7-17. SIM Break Status Register (SBSR)
BW — SIM Break Wait
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear BW by writing a logic 0 to it.
Reset clears BW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
BW can be read within the break state SWI routine. The user can modify
the return address on the stack by subtracting one from it. The following
code is an example of this. Writing zero to the BW bit clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE EQU
LOBYTE EQU
5
6
;
If not BW, do RTI
BRCLR BW,SBSR, RETURN
; See if wait mode was exited by break.
;
TST
BNE
DEC
DEC
LOBYTE,SP
DOLO
; If RETURNLO is not zero,
; then just decrement low byte.
; Else deal with high byte, too.
; Point to WAIT/STOP opcode.
; Restore H register.
HIBYTE,SP
LOBYTE,SP
DOLO
RETURN PULH
RTI
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System Integration Module (SIM)
SIM Registers
7.8.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset. The
status register will automatically clear after reading it. A power-on reset
sets the POR bit and clears all other bits in the register.
Address: $FE01
Bit 7
POR
6
5
4
3
2
0
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-18. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
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System Integration Module (SIM)
System Integration Module (SIM)
7.8.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
R
0
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
0
R
=Reserved
Figure 7-19. SIM Break Flag Control Register (SBFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Technical Data — MC68HC908AS32A
Section 8. Clock Generator Module (CGM)
8.1 Contents
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
8.4
8.4.1
8.4.2
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .125
Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . .127
8.4.2.1
8.4.2.2
8.4.2.3
8.4.2.4
8.4.2.5
8.4.3
Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Acquisition and Tracking Modes . . . . . . . . . . . . . . . .129
Manual and Automatic PLL Bandwidth Modes . . . . .129
Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . .131
Special Programming Exceptions . . . . . . . . . . . . . . .133
Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . .133
8.4.4
CGM External Connections. . . . . . . . . . . . . . . . . . . . . . .134
8.5
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . .135
Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . .135
External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . .135
Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . .136
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . .136
Crystal Output Frequency Signal (CGMXCLK) . . . . . . .136
CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .136
CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . .136
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.6
CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . .139
PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . .141
8.6.1
8.6.2
8.6.3
8.7
8.8
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
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Clock Generator Module (CGM)
8.8.1
8.8.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
8.9
CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .144
8.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . .144
8.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . .144
8.10.2 Parametric Influences on Reaction Time. . . . . . . . . . . .146
8.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . .147
8.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . .147
8.2 Introduction
The CGM generates the crystal clock signal, CGMXCLK, which operates
at the frequency of the crystal. The CGM also generates the base clock
signal, CGMOUT, from which the system clocks are derived. CGMOUT
is based on either the crystal clock divided by two or the phase-locked
loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency
generator designed for use with 1-MHz to 8-MHz crystals or ceramic
resonators. The PLL can generate an 8-MHz bus frequency without
using high frequency crystals.
8.3 Features
Features of the CGM include:
•
•
Phase-Locked Loop with Output Frequency in Integer Multiples of
the Crystal Reference
Programmable Hardware Voltage-Controlled Oscillator (VCO) for
Low-Jitter Operation
•
•
•
Automatic Bandwidth Control Mode for Low-Jitter Operation
Automatic Frequency Lock Detector
CPU Interrupt on Entry or Exit from Locked Condition
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Clock Generator Module (CGM)
Functional Description
8.4 Functional Description
The CGM consists of three major submodules:
•
•
•
Crystal oscillator circuit — The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.
Phase-locked loop (PLL) — The PLL generates the
programmable VCO frequency clock CGMVCLK.
Base clock selector circuit — This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The
system clocks are derived from CGMOUT.
Figure 8-1 shows the structure of the CGM.
8.4.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal
oscillator circuit. Connect the external clock to the OSC1 pin and let the
OSC2 pin float.
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Clock Generator Module (CGM)
Clock Generator Module (CGM)
CGMXCLK
CGMOUT
OSC1
CLOCK
SELECT
CIRCUIT
A
B
÷ 2
S*
*When S = 1,
CGMOUT = B
CGMRDV
CGMRCLK
BCS
PTC3
V
CGMXFC
V
SS
DDA
MONITOR MODE
VRS7–VRS4
USER MODE
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
DETECTOR
LOOP
FILTER
PLL ANALOG
CGMINT
LOCK
DETECTOR
BANDWIDTH
CONTROL
INTERRUPT
CONTROL
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL7–MUL4
CGMVDV
CGMVCLK
FREQUENCY
DIVIDER
Figure 8-1. CGM Block Diagram
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Functional Description
Register Name
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLL Control Register (PCTL) Write:
Reset:
0
LOCK
0
1
0
0
1
0
0
1
0
0
1
0
0
Read:
AUTO
0
ACQ
0
XLD
0
PLL Bandwidth Control Register
Write:
(PBWC)
Reset:
Read:
PLL Programming Register (PPG) Write:
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
VRS6
1
VRS5
1
VRS4
0
= Unimplemented
Figure 8-2. I/O Register Summary
Table 8-1. I/O Register Address Summary
Register
Address
PCTL
PBWC
$001D
PPG
$001C
$001E
8.4.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
8.4.2.1 Circuits
The PLL consists of these circuits:
•
•
•
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
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•
•
Loop filter
Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, fCGMVRS
Modulating the voltage on the CGMXFC pin changes the frequency
.
within this range. By design, fCGMVRS is equal to the nominal center-of-
range frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM
.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, fCGMRCLK, and is fed to the PLL through
a buffer. The buffer output is the final reference clock, CGMRDV,
running at a frequency fCGMRDV = fCGMRCLK
.
The VCO’s output clock, CGMVCLK, running at a frequency fCGMVCLK
,
is fed back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency
f
CGMVDV = fCGMVCLK/N. See Programming the PLL for more
information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode, as
described in Acquisition and Tracking Modes on page 129. The value
of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, fCGMRDV. The circuit determines the mode of the PLL and the
lock condition based on this comparison.
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Functional Description
8.4.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
•
Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. See PLL Bandwidth Control Register on page 139.
•
Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. See Base Clock Selector Circuit on page 133. The PLL
is automatically in tracking mode when it’s not in acquisition mode
or when the ACQ bit is set.
8.4.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See PLL Bandwidth Control Register on page 139. If PLL
CPU interrupt requests are enabled, the software can wait for a PLL
CPU interrupt request and then check the LOCK bit. If CPU interrupts
are disabled, software can poll the LOCK bit continuously (during PLL
startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock.
See Base Clock Selector Circuit on page 133. If the VCO is selected
as the source for the base clock and the LOCK bit is clear, the PLL has
suffered a severe noise hit and the software must take appropriate
action, depending on the application. See Interrupts on page 143.
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Clock Generator Module (CGM)
Clock Generator Module (CGM)
These conditions apply when the PLL is in automatic bandwidth control
mode:
•
The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a
read-only indicator of the mode of the filter. See Acquisition and
Tracking Modes on page 129.
•
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆trk, and is cleared when the VCO frequency is out of a
certain tolerance,
420.
∆unt. See Electrical Specifications on page
•
•
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance,
∆Lock, and is cleared when the VCO frequency is out of a
certain tolerance,
∆unl. See Electrical Specifications on page 420.
•
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See PLL Control
Register on page 137.
The PLL also can operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below fbusmax and
require fast startup. The following conditions apply when in manual
mode:
•
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
•
Before entering tracking mode (ACQ = 1), software must wait a
given time, tacq (see Electrical Specifications on page 420), after
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
•
Software must wait a given time, tal, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
•
•
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
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Functional Description
8.4.2.4 Programming the PLL
Use this 9-step procedure to program the PLL. The table below lists the
variables used and their meaning (Please also reference Figure 8-1 on
page 126).
Table 8-2. Variable Definitions
Variable
Definition
Desired Bus Clock Frequency
fBUSDES
fVCLKDES
fCGMRCLK
fCGMVCLK
fBUS
Desired VCO Clock Frequency
Chosen Reference Crystal Frequency
Calculated VCO Clock Frequency
Calculated Bus Clock Frequency
Nominal VCO Center Frequency
Shifted VCO Center Frequency
fNOM
fCGMVRS
1. Choose the desired bus frequency, fBUSDES
.
Example: fBUSDES = 8 MHz
2. Calculate the desired VCO frequency, fVCLKDES
fVCLKDES = 4 × fBUSDES
.
Example: fVCLKDES = 4 × 8 MHz = 32 MHz
3. Using a reference frequency, fRCLK, equal to the crystal frequency,
calculate the VCO frequency multiplier, N. Round the result to the
nearest integer.
fVCLKDES
N = -------------------------
fCGMRCLK
32 MHz
Example: N = -------------------- = 8
4 MHz
4. Calculate the VCO frequency, fCGMVCLK
.
fCGMVCLK = N × fCGMRCLK
Example: fCGMVCLK = 8 × 4 MHz = 32 MHz
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5. Calculate the bus frequency, fBUS, and compare fBUS with
fBUSDES
.
fCGMVCLK
fBUS = -----------------------
4
32 MHz
Example: fBUS= -------------------- = 8 MHz
4
6. If the calculated fbus is not within the tolerance limits of your
application, select another fBUSDES or another fRCLK
.
7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear
range multiplier, L. The linear range multiplier controls the
frequency range of the PLL.
fCGMVCLK
L = round -----------------------
fNOM
32 MHz
4.9152 MHz
Example: L =
= 7
-------------------------------
8. Calculate the VCO center-of-range frequency, fCGMVRS. The
center-of-range frequency is the midpoint between the minimum
and maximum frequencies attainable by the PLL.
fCGMVRS = L × fNOM
Example: fCGMVRS = 7 × 4.9152 MHz = 34.4 MHz
fNOM
NOTE: For proper operation,
.
----------------
fCGMVRS – fCGMVCLK
≤
2
Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG),
program the binary equivalent of N.
b. In the lower four bits of the PLL programming register (PPG),
program the binary equivalent of L.
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Clock Generator Module (CGM)
Functional Description
8.4.2.5 Special Programming Exceptions
The programming method described in Programming the PLL on page
131, does not account for two possible exceptions. A value of 0 for N or
L is meaningless when used in the equations given. To account for these
exceptions:
•
•
A 0 value for N is interpreted the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. See Base Clock Selector Circuit on
page 133.
8.4.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.
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8.4.4 CGM External Connections
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 8-3. Figure 8-3 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS (optional)
The series resistor (RS) may not be required for all ranges of operation,
especially with high-frequency crystals. Refer to the crystal
manufacturer’s data for more information.
Figure 8-3 also shows the external components for the PLL:
•
•
Bypass capacitor, CBYP
Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and
noise. (See Acquisition/Lock Time Specifications on page 144 for
routing information and more information on the filter capacitor’s value
and its effects on PLL performance).
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I/O Signals
SIMOSCEN
CGMXCLK
V
DD
*
R
C
S
F
C
R
BYP
B
X
1
C
C
2
1
*R can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data.
S
Figure 8-3. CGM External Connections
8.5 I/O Signals
The following paragraphs describe the CGM input/output (I/O) signals.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
8.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
8.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. A small external capacitor is connected to this pin.
NOTE: To prevent noise problems, CF should be placed as close to the
CGMXFC pin as possible with minimum routing distances and no routing
of other signals across the CF connection.
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Clock Generator Module (CGM)
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8.5.4 Analog Power Pin (VDDA
)
VDDA is a power pin used by the analog portions of the PLL. Connect the
VDDA pin to the same voltage potential as the VDD pin.
NOTE: Route VDDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
8.5.5 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal enables the oscillator and PLL.
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (fCGMXCLK) and comes directly from the crystal oscillator
circuit. Figure 8-3 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
8.5.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the
bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
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CGM Registers
8.6 CGM Registers
Three registers control and monitor operation of the CGM:
•
•
•
PLL control register (PCTL)
PLL bandwidth control register (PBWC)
PLL programming register (PPG)
8.6.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
PLLIE
0
6
5
PLLON
1
4
BCS
0
3
1
2
1
1
1
Bit 0
1
Read:
Write:
Reset:
PLLF
0
1
1
1
1
= Unimplemented
Figure 8-4. PLL Control Register (PCTL)
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
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Clock Generator Module (CGM)
PLLF — PLL Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates a CPU interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or read-
modify-write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit
on page 133. Reset sets this bit so that the loop can stabilize as the
MCU is powering up.
1 = PLL on
0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. See Base
Clock Selector Circuit on page 133. Reset and the STOP instruction
clear the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
NOTE: PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
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Clock Generator Module (CGM)
CGM Registers
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See Base Clock Selector Circuit on page 133.
PCTL3–PCTL0 — Unimplemented
These bits provide no function and always read as logic 1s.
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
•
Selects automatic or manual (software-controlled) bandwidth
control mode
•
•
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
•
In manual operation, forces the PLL into acquisition or tracking
mode
Address: $001D
Bit 7
6
5
ACQ
0
4
XLD
0
3
0
2
0
1
0
Bit 0
0
Read:
AUTO
Write:
LOCK
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 8-5. PLL Bandwidth Control Register (PBWC)
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Clock Generator Module (CGM)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this
read/write bit can indicate whether the crystal reference frequency is
active or not.
1 = Crystal reference not active
0 = Crystal reference active
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CGM Registers
To check the status of the crystal reference, do the following:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. N is the VCO frequency multiplier.
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
Bits 3–0 — Reserved for Test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to bits 3–0 when writing to PBWC.
8.6.3 PLL Programming Register
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
Address: $001E
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
1
4
MUL4
0
3
VRS7
0
2
VRS6
1
1
VRS5
1
Bit 0
VRS4
0
Read:
Write:
Reset:
Figure 8-6. PLL Programming Register (PPG)
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See Circuits on page 127 and
Programming the PLL on page 131). A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
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Table 8-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
VCO Frequency Multiplier (N)
0000
0001
0010
0011
1
1
2
3
1101
1110
1111
13
14
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency,
fVRS. (See Circuits on page 127, Programming the PLL on page
131, and PLL Control Register on page 137.) VRS7–VRS4 cannot
be written when the PLLON bit in the PLL control register (PCTL) is
set. See Special Programming Exceptions on page 133. A value of
$0 in the VCO range select bits disables the PLL and clears the BCS
bit in the PCTL. (See Base Clock Selector Circuit on page 133 and
Special Programming Exceptions on page 133 for more
information.) Reset initializes the bits to $6 to give a default range
multiply value of 6.
NOTE: The VCO range select bits have built-in protection that prevents them
from being written when the PLL is on (PLLON = 1) and prevents
selection of the VCO clock as the source of the base clock (BCS = 1) if
the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
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Interrupts
8.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupt requests from the PLL. PLLF, the interrupt flag in the
PCTL, becomes set whether CPU interrupt requests are enabled or not.
When the AUTO bit is clear, CPU interrupt requests from the PLL are
disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL CPU interrupt request to
see if the request was due to an entry into lock or an exit from lock. When
the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
CPU interrupt requests should be disabled to prevent PLL interrupt
service routines from impeding software performance or from exceeding
stack limitations.
NOTE: Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.
8.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
8.8.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
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Clock Generator Module (CGM)
8.8.2 Stop Mode
The STOP instruction disables the CGM and holds low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If CGMOUT is being driven by CGMVCLK and a STOP instruction is
executed; the PLL will clear the BCS bit in the PLL control register,
causing CGMOUT to be driven by CGMXCLK. When the MCU recovers
from STOP, the crystal clock divided by two drives CGMOUT and BCS
remains clear.
8.9 CGM During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module (BRK) on
page 157.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
8.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
8.10.1 Acquisition/Lock Time Definitions
Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percent of the
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Acquisition/Lock Time Specifications
step input or when the output settles to the desired value plus or minus
a percent of the frequency change. Therefore, the reaction time is
constant in this definition, regardless of the size of the step input. For
example, consider a system with a 5% acquisition time tolerance. If a
command instructs the system to change from 0 Hz to 1 MHz, the
acquisition time is the time taken for the frequency to reach
1 MHz ±50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is
operating at 1 MHz and suffers a –100 kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
•
Acquisition time, tacq, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆trk.
Acquisition time is based on an initial frequency error,
(fdes – forig)/fdes, of not more than ±100%. In automatic bandwidth
control mode (see Manual and Automatic PLL Bandwidth
Modes on page 129), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
•
Lock time, tLock, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆Lock. Lock
time is based on an initial frequency error, (fdes – forig)/fdes, of not
more than ±100%. In automatic bandwidth control mode, lock time
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Clock Generator Module (CGM)
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See Manual and Automatic PLL
Bandwidth Modes on page 129).
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
8.10.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, fCGMRDV (please reference Figure 8-1). This
frequency is the input to the phase detector and controls how often the
PLL makes corrections. For stability, the corrections must be small
compared to the desired frequency, so several corrections are required
to reduce the frequency error. Therefore, the slower the reference the
longer it takes to make these corrections. This parameter is also under
user control via the choice of crystal frequency fCGMXCLK
.
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small enough
adjustments to the voltage and the system cannot lock. If the capacitor
is too large, the PLL may not be able to adjust the voltage in a
reasonable time. See Choosing a Filter Capacitor on page 147.
Also important is the operating voltage potential applied to VDDA. The
power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.
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Acquisition/Lock Time Specifications
Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.
8.10.3 Choosing a Filter Capacitor
As described in Parametric Influences on Reaction Time on page
146, the external filter capacitor, CF, is critical to the stability and reaction
time of the PLL. The PLL is also dependent on reference frequency and
supply voltage. The value of the capacitor must, therefore, be chosen
with supply potential and reference frequency in mind. For proper
operation, the external filter capacitor must be chosen according to this
equation:
VDDA
CF = Cfact ------------------
f
CGMRDV
For acceptable values of Cfact, (see Electrical Specifications on page
420). For the value of VDDA, choose the voltage potential at which the
MCU is operating. If the power supply is variable, choose a value near
the middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor
size, so round to the nearest available size. If the value is between two
different sizes, choose the higher value for better stability. Choosing the
lower size may seem attractive for acquisition time improvement, but the
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
8.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
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Clock Generator Module (CGM)
Clock Generator Module (CGM)
•
Correct selection of filter capacitor, CF (see Choosing a Filter
Capacitor on page 147).
•
•
•
Room temperature operation
Negligible external leakage on CGMXFC
Negligible noise
The K factor in the equations is derived from internal PLL parameters.
Kacq is the K factor when the PLL is configured in acquisition mode, and
Ktrk is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 129).
VDDA
tacq = ------------------- ------------
fCGMRDV KACQ
8
VDDA
4
tal = ------------------- -----------
fCGMRDV KTRK
tLock = tACQ + tAL
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual
and Automatic PLL Bandwidth Modes on page 129). A certain
number of clock cycles, nACQ, is required to ascertain that the PLL is
within the tracking mode entry tolerance, ∆TRK, before exiting acquisition
mode. A certain number of clock cycles, nTRK, is required to ascertain
that the PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the
acquisition time, tACQ, is an integer multiple of nACQ CGMRDV
acquisition to lock time, tAL, is an integer multiple of nTRK/fCGMRDV
/f
, and the
. Also,
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
tLock as calculated above.
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Acquisition/Lock Time Specifications
In manual mode, it is usually necessary to wait considerably longer than
tLock before selecting the PLL clock (see Base Clock Selector Circuit
on page 133), because the factors described in Parametric Influences
on Reaction Time on page 146, may slow the lock time considerably.
When defining a limit in software for the maximum lock time, the value
must allow for variation due to all of the factors mentioned in this section,
especially due to the CF capacitor and application specific influences.
The calculated lock time is only an indication and it is the customer’s
responsibility to allow enough of a guard band for their application. Prior
to finalizing any software and while determining the maximum lock time,
take into account all device to device differences. Typically, applications
set the maximum lock time as an order of magnitude higher than the
measured value. This is considered sufficient for all such device to
device variation.
Motorola recommends measuring the lock time of the application system
by utilizing dedicated software, running in FLASH, EEPROM or RAM.
This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and
finally again when the PLL lock bit is set. The resultant waveform can be
captured on an oscilloscope and used to determine the typical lock time
for the microcontroller and the associated external application circuit.
e.g.
tLOCK
tACQ
tAL
Init. low
Signal on port pin
tTRKComplete and Lock Set
tACQComplete
PLL Configured and switched on
NOTE: The filter capacitor should be fully discharged prior to making any
measurements.
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Technical Data — MC68HC908AS32A
Section 9. Configuration Register (CONFIG-1)
9.1 Contents
9.2
9.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.2 Introduction
This section describes the configuration register (CONFIG-1), which
contains bits that configure these options:
•
•
•
•
Resets caused by the LVI module
Power to the LVI module
LVI enabled during stop mode
Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
•
•
Computer operating properly module (COP)
Stop instruction enable/disable.
9.3 Functional Description
The configuration register is a write-once register. Out of reset, the
configuration register will read the default value. Once the register is
written, further writes will have no effect until a reset occurs.
NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs
when VDD falls to a voltage, LVITRIPF, and remains at or below that level
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Configuration Register (CONFIG-1)
Configuration Register (CONFIG-1)
for at least nine consecutive CPU cycles. Once an LVI reset occurs, the
MCU remains in reset until VDD rises to a voltage, LVITRIPR
.
Address: $001F
Bit 7
6
5
4
3
2
COPL
0
1
Bit 0
COPD
0
Read:
LVISTOP
Write:
R
LVIRST LVIPWR SSREC
STOP
0
Reset:
0
1
1
1
0
R
=Reserved
Figure 9-1. Configuration Register (CONFIG-1)
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See Low Voltage
Inhibit (LVI) on page 181).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE: To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop IDD current will be higher.
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See Low
Voltage Inhibit (LVI) on page 181).
1 = LVI module resets enabled
0 = LVI module resets disabled
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Configuration Register (CONFIG-1)
Functional Description
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Low Voltage Inhibit (LVI) on
page 181).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See
System Integration Module (SIM) on page 101).
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout
COPL enables the shorter COP timeout period. (See Computer
Operating Properly (COP) on page 175).
1 = COP timeout period is 213 – 24 CGMXCLK cycles
0 = COP timeout period is 218 – 24 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Computer Operating
Properly (COP) on page 175).
1 = COP module disabled
0 = COP module enabled
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Configuration Register (CONFIG-1)
Configuration Register (CONFIG-1)
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Configuration Register (CONFIG-1)
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Technical Data — MC68HC908AS32A
Section 10. Configuration Register (CONFIG-2)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.2 Introduction
This section describes the configuration register (CONFIG-2). This
register contains bits that configure these options:
•
Configures the device to either the MC68HC08AZxx emulator or
the MC68HC08ASxx emulator
10.3 Functional Description
The configuration register is a write-once register. Out of reset, the
configuration register will read the default. Once the register is written,
further writes will have no effect until a reset occurs.
Address: $FE09
Bit 7
6
R
0
5
R
0
4
R
1
3
AS32A
1
2
R
0
1
R
0
Bit 0
R
Read:
Write:
Reset:
EEDIV
CLK
0
0
Figure 10-1. Configuration Register (CONFIG-2)
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Configuration Register (CONFIG-2)
Configuration Register (CONFIG-2)
EEDIVCLK — EEPROM Timebase Divider Clock select bit
This bit selects the reference clock source for the EEPROM timebase
divider module.
1 = EExDIV clock input is driven by internal bus clock
0 = EExDIV clock input is driven by CGMXCLK
AS32A— Device Indicator bit
This bit is used to distinguish MC68HC908AS60A from older non-’A’
suffix versions.
1 = ‘A’ version
0 = Non-’A’ version
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Technical Data — MC68HC908AS32A
Section 11. Break Module (BRK)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
11.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . .159
11.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . .160
11.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .160
11.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . .160
11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
11.5.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
11.6 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .161
11.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . .161
11.6.2 Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . .162
11.2 Introduction
11.3 Features
The break module can generate a break interrupt that stops normal
program flow at a defined address to enter a background program.
•
•
•
•
Accessible I/O Registers during Break Interrupts
CPU-Generated Break Interrupts
Software-Generated Break Interrupts
COP Disabling during Break Interrupts
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Break Module (BRK)
Break Module (BRK)
11.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
•
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 11-1 shows the structure of the break module.
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
BREAK
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 11-1. Break Module Block Diagram
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Break Module (BRK)
Functional Description
Register Name
Bit 7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Break Address Register High
(BRKH)
Read:
Write:
Reset:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Break Address Register Low
(BRKL)
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
BRKE
0
BRKA
0
Break Status and Control Register
(BSCR)
0
= Unimplemented
R = Reserved
Figure 11-2. I/O Register Summary
Table 11-1. I/O Register Address Summary
Register
Address
BRKH
$FE0C
BRKL
BSCR
$FE0E
$FE0D
11.4.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
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Break Module (BRK)
Break Module (BRK)
11.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when VHi is present on the
RST pin.
11.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
11.5.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait
bit (BW) in the SIM break status register indicates whether wait was
exited by a break interrupt. If so, the user can modify the return address
on the stack by subtracting one from it. (See SIM Break Status Register
on page 120).
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Break Module (BRK)
Break Module Registers
11.5.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does
not affect break module register states.
11.6 Break Module Registers
These registers control and monitor operation of the break module:
•
•
•
Break address register high (BRKH)
Break address register low (BRKL)
Break status and control register (BSCR)
11.6.1 Break Status and Control Register
The break status and control register contains break module enable and
status bits.
Address: $FE0E
Bit 7
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
BRKE
Write:
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
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Break Module (BRK)
161
Break Module (BRK)
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
11.6.2 Break Address Registers
The break address registers contain the high and low bytes of the
desired breakpoint address. Reset clears the break address registers.
Register: BRKH
Address: $FE0C
Bit 7
BRKL
$FE0D
6
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
1
0
Bit 0
Bit 8
0
Read:
Bit 15
Write:
14
0
Reset:
Read:
Write:
Reset:
0
Bit 7
0
6
5
4
3
2
Bit 0
0
0
0
0
0
0
Figure 11-4. Break Address Registers (BRKH and BRKL)
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Technical Data — MC68HC908AS32A
Section 12. Monitor ROM (MON)
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
12.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . .166
12.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12.4.6 MC68HC908AS60A Baud Rate . . . . . . . . . . . . . . . . . . . .172
12.4.7 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
12.2 Introduction
12.3 Features
This section describes the monitor ROM (MON). The monitor ROM
allows complete testing of the MCU through a single-wire interface with
a host computer.
Features of the monitor ROM include:
•
•
Normal User-Mode Pin Functionality
One Pin Dedicated to Serial Communication between Monitor
ROM and Host Computer
•
Standard Mark/Space Non-Return-to-Zero (NRZ) Communication
with Host Computer
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Monitor ROM (MON)
163
Monitor ROM (MON)
•
•
•
•
Up to 28.8 kBaud Communication with Host Computer
Execution of Code in RAM or FLASH
FLASH Security
FLASH Programming
12.4 Functional Description
Monitor ROM receives and executes commands from a host computer.
Figure 12-1 shows a sample circuit used to enter monitor mode and
communicate with a host computer via a standard RS-232 interface.
While simple monitor commands can access any memory address, the
MC68HC908AS60A has a FLASH security feature to prevent external
viewing of the contents of FLASH. Proper procedures must be followed
to verify FLASH content. Access to the FLASH is denied to unauthorized
users of customer specified software (see Security on page 173).
In monitor mode, the MCU can execute host-computer code in RAM
while all MCU pins except PTA0 retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
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Monitor ROM (MON)
Functional Description
V
DD
68HC08
10 kΩ
RST
0.1 µF
V
HI
1 KΩ
IRQ
9.1V
V
DDA
VDDA/VDDAREF
CGMXFC
0.1 µF
10 MΩ
1
20
MC145407
+
+
+
+
10 µF
10 µF
10 µF
10 µF
OSC1
OSC2
3
4
18
17
*
X1
20 pF
4.9152 MHz
V
DD
20 pF
2
19
V
SSA
V
SS
DB-25
2
5
6
16
15
3
7
V
DD
V
DD
0.1 µF
V
DD
V
DD
1
2
6
4
14
3
MC74HC125
10 kΩ
PTA0
PTC3
5
V
DD
V
DD
10 kΩ
7
10 kΩ
PTC0
PTC1
A
(SEE
NOTE.)
NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4
Position B — Bus clock = CGMXCLK ÷ 2
B
* = Refer to Table 12-9 for correct value.
Figure 12-1. Monitor Mode Circuit
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MOTOROLA
Monitor ROM (MON)
Monitor ROM (MON)
12.4.1 Entering Monitor Mode
Table 12-1 shows the pin conditions for entering monitor mode.
Table 12-1. Mode Selection
Bus
Frequency
Mode
CGMOUT
CGMXCLK
CGMVCLK
CGMOUT
--------------------------
2
(1)
(1)
1
1
0
0
1
1
1
0
Monitor
Monitor
----------------------------- or -----------------------------
VHI
2
2
CGMOUT
--------------------------
2
CGMXCLK
VHI
1. For VHI, 5.0 Volt DC Electrical Characteristics on page 422, and Maximum Ratings on
page 420.
Enter monitor mode by either
•
•
Executing a software interrupt instruction (SWI) or
Applying a logic 0 and then a logic 1 to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 173). After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as VHI (see
5.0 Volt DC Electrical Characteristics on page 422), is applied to
either the IRQ pin or the RESET pin. (See System Integration Module
(SIM) on page 101 for more information on modes of operation).
NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
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Monitor ROM (MON)
Functional Description
Table 12-2 is a summary of the differences between user mode and
monitor mode.
Table 12-2. Mode Differences
Functions
Reset
Vector Vector Vector Vector Vector Vector
High Low High Low High Low
Reset
Break
Break
SWI
SWI
Modes
COP
User
Enabled
$FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD
Disabled(1)
Monitor
1. If the high voltage (VHI) is removed from the IRQ pin while in monitor mode, the SIM asserts
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in
the configuration register. (see 5.0 Volt DC Electrical Characteristics on page 422).
12.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3.)
The data transmit and receive rate can be anywhereup to 28.8 kBaud.
Transmit and receive baud rates must be identical.
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Figure 12-2. Monitor Data Format
NEXT
START
BIT
START
STOP
$A5
BIT 0
BIT 0
BIT 1
BIT 2
BIT 2
BIT 3
BIT3
BIT 4
BIT4
BIT 5
BIT5
BIT 6
BIT6
BIT 7
BIT7
BIT
BIT
STOP
BIT
START
BIT
NEXT
START
BIT
BREAK
BIT 1
Figure 12-3. Sample Monitor Waveforms
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Monitor ROM (MON)
Monitor ROM (MON)
12.4.3 Echoing
As shown in Figure 12-4, the monitor ROM immediately echoes each
received byte back to the PTA0 pin for error checking.
Any result of a command appears after the echo of the last byte of the
command.
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
Figure 12-4. Read Transaction
12.4.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 12-5).
When the monitor receives a break signal, it drives the PTA0 pin high for
the duration of two bits before echoing the break signal.
MISSING STOP BIT
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 12-5. Break Transaction
12.4.5 Commands
The monitor ROM uses these commands:
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Monitor ROM (MON)
Functional Description
•
•
•
•
•
•
READ, read memory
WRITE, write memory
IREAD, indexed read
IWRITE, indexed write
READSP, read stack pointer
RUN, run user program
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
Table 12-3. READ (Read Memory) Command
Description
Operand
Read byte from memory
Specifies 2-byte address in high byte:low byte order
Returns contents of specified address
$4A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
ECHO
RESULT
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Monitor ROM (MON)
Monitor ROM (MON)
Table 12-4. WRITE (Write Memory) Command
Description
Operand
Write byte to memory
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
Opcode
None
$49
Command Sequence
SENT TO
MONITOR
WRITE
ECHO
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
Table 12-5. IREAD (Indexed Read) Command
Description
Operand
Read next 2 bytes in memory from last address accessed
Specifies 2-byte address in high byte:low byte order
Returns contents of next two addresses
$1A
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
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Monitor ROM (MON)
Functional Description
Table 12-6. IWRITE (Indexed Write) Command
Description
Operand
Write to last address accessed + 1
Specifies single data byte
Data Returned
Opcode
None
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
Table 12-7. READSP (Read Stack Pointer) Command
Description
Operand
Reads stack pointer
None
Data Returned
Opcode
Returns stack pointer in high byte:low byte order
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
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Monitor ROM (MON)
Monitor ROM (MON)
Table 12-8. RUN (Run User Program) Command
Description
Operand
Executes RTI instruction
None
None
$28
Data Returned
Opcode
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
12.4.6 MC68HC908AS60A Baud Rate
With a 4.9152-MHz crystal and the PTC3 pin at logic 1 during reset, data
is transferred between the monitor and host at 4800 baud. If the PTC3
pin is at logic 0 during reset, the monitor baud rate is 9600. When the
CGM output, CGMOUT, is driven by the PLL, the baud rate is
determined by the MUL[7:4] bits in the PLL programming register (PPG).
(See Clock Generator Module (CGM) on page 123).
Table 12-9. MC68HC908AS60A Monitor Baud Rate Selection
VCO Frequency Multiplier (N)
Monitor
Baud Rate
1
2
3
4
5
6
4.9152 MHz
4.194 MHz
4800
4096
9600
8192
14,400
12,288
19,200
16,384
24,000
20,480
28,800
24,576
Care should be taken when setting the baud rate since incorrect
baud rate setting can result in communications failure.
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Monitor ROM (MON)
Functional Description
12.4.7 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-
defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
If FLASH is unprogrammed, the eight security byte values to be sent are
$FF, the unprogrammed state of FLASH.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PA0.
V
DD
4096 + 32 CGMXCLK CYCLES
24 CGMXCLK CYCLES
RST
PA7
256 CGMXCLK CYCLES (ONE BIT TIME)
FROM HOST
FROM MCU
PA0
1
4
1
2
4
1
1
NOTE: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
4 = Wait 1 bit time before sending next byte.
Figure 12-6. Monitor Mode Entry Timing
If the received bytes match those at locations $FFF6–$FFFD, the host
bypasses the security feature and can read all FLASH locations and
execute code from FLASH. Security remains bypassed until a power-on
reset occurs. After the host bypasses security, any reset other than a
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Monitor ROM (MON)
Monitor ROM (MON)
power-on reset requires the host to send another eight bytes. If the reset
was not a power-on reset, the security remains bypassed regardless of
the data that the host sends.
If the received bytes do not match the data at locations $FFF6–$FFFD,
the host fails to bypass the security feature. The MCU remains in monitor
mode, but reading FLASH locations returns undefined data, and trying
to execute code from FLASH causes an illegal address reset. After the
host fails to bypass security, any reset other than a power-on reset
causes an endless loop of illegal address resets.
After receiving the eight security bytes from the host, the MCU transmits
a break character signalling that it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
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Technical Data — MC68HC908AS32A
Section 13. Computer Operating Properly (COP)
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
13.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
13.4.3 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.4.7 COPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.4.8 COPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
13.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
13.8.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
13.9 COP Module During Break Interrupts. . . . . . . . . . . . . . . . .180
13.2 Introduction
The COP module contains a free-running counter that generates a reset
if allowed to overflow. The COP module helps software recover from
runaway code. Prevent a COP reset by periodically clearing the COP
counter.
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Computer Operating Properly (COP)
13.3 Functional Description
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 213 – 24 or 218 – 24 CGMXCLK
cycles, depending on the state of the COP long timeout bit, COPL, in the
CONFIG-1. When COPL = 0, a 4.9152-MHz crystal gives a COP timeout
period of 53.3 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 4–12 of the SIM counter.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held
at VHi. During the break state, VHi on the RST pin disables the COP.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
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Computer Operating Properly (COP)
I/O Signals
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
12-BIT COP PRESCALER
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
RESET
RESET STATUS
REGISTER
6-BIT COP COUNTER
COPD FROM CONFIG-1
RESET
CLEAR COP
COPCTL WRITE
COUNTER
COPL FROM CONFIG-1
Figure 13-1. COP Block Diagram
13.4.1 CGMXCLK
CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.
13.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
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Computer Operating Properly (COP)
Computer Operating Properly (COP)
13.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see COP
Control Register on page 179), clears the COP counter and clears
stages 12 through 4 of the COP prescaler. Reading the COP control
register returns the reset vector.
13.4.4 Power-On Reset
The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.
13.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
13.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
13.4.7 COPD
13.4.8 COPL
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register. (See Configuration Register (CONFIG-1) on
page 151).
The COPL signal reflects the state of the COP rate select bit. (COPL) in
the configuration register. (See Configuration Register (CONFIG-1) on
page 151).
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Computer Operating Properly (COP)
COP Control Register
13.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low Byte of Reset Vector
Clear COP Counter
Unaffected by Reset
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when VHi is present on the IRQ
pin or on the RST pin.
13.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
13.8.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
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Computer Operating Properly (COP)
Computer Operating Properly (COP)
13.8.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.
13.9 COP Module During Break Interrupts
The COP is disabled during a break interrupt when VHi is present on the
RST pin.
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Technical Data — MC68HC908AS32A
Section 14. Low Voltage Inhibit (LVI)
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
14.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . .184
14.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . .184
14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
14.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
14.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14.2 Introduction
14.3 Features
This section describes the (TSMC .5u) low-voltage inhibit module
(lvim26or43_tsmc_b10), which monitors the voltage on the VDD pin and
can force a reset when the VDD voltage falls to the LVI trip voltage.
Features of the LVI module include:
•
•
Programmable LVI Reset
Programmable Power Consumption
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Low Voltage Inhibit (LVI)
Low Voltage Inhibit (LVI)
NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM
or Flash memory, then adequate programming time may not have been
allowed to ensure the integrity and retention of the data. It is the
responsibility of the user to ensure that in the event of an LVI any
addresses being programmed receive specification programming
conditions.
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when VDD falls below a voltage, LVITRIPF, and remains at or
below that level for nine or more consecutive CPU cycles.
Note that short VDD spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean VDD signal within the specified operating
voltage range if normal microcontroller operation is to be guaranteed.
LVISTOP, enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented, the LVI will continue to
monitor the voltage level on VDD. LVIPWR, LVISTOP, and LVIRST are
in the configuration register, CONFIG-1 (see Configuration Register
(CONFIG-1) on page 151).
Once an LVI reset occurs, the MCU remains in reset until VDD rises
above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one
CPU cycle to bring the MCU out of reset (see Forced Reset Operation
on page 184). The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
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182
MC68HC908AS32A — Rev 0.0
Low Voltage Inhibit (LVI)
MOTOROLA
Low Voltage Inhibit (LVI)
Functional Description
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V
DD
LVIPWR
FROM CONFIG-1
FROM CONFIG-1
LVIRST
CPU CLOCK
V
DD > LVITRIP = 0
LVI RESET
LOW V
Stop Mode
Filter Bypass
DD
DETECTOR
V
DD < LVITRIP = 1
LVISTOP
ANLGTRIP
LVIOUT
FROM CONFIG-1
Figure 14-1. LVI Module Block Diagram
Figure 14-2. LVI I/O Register Summary
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE0F
LVI Status Register (LVISR) LVIOUT
= Unimplemented
14.4.1 Polled LVI Operation
In applications that can operate at VDD levels below the LVITRIPF level,
software can monitor VDD by polling the LVIOUT bit. In the configuration
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
MC68HC908AS32A — Rev 0.0
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Advance Information
183
Low Voltage Inhibit (LVI)
Low Voltage Inhibit (LVI)
14.4.2 Forced Reset Operation
In applications that require VDD to remain above the LVITRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when VDD
falls to the LVITRIPF level and remains at or below that level for nine or
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
14.4.3 False Reset Protection
In order for the LVI module to reset the MCU,VDD must remain at or
below the LVITRIPF level for nine or more consecutive CPU cycles. VDD
must be above LVITRIPR for only one CPU cycle to bring the MCU out of
reset.
14.5 LVI Status Register
The LVI status register flags VDD voltages below the LVITRIPF level.
Address: $FE0F
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
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MC68HC908AS32A — Rev 0.0
Low Voltage Inhibit (LVI)
MOTOROLA
Low Voltage Inhibit (LVI)
LVI Interrupts
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 14-1).
Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
VDD
LVIOUT
For Number of
CGMXCLK Cycles:
At Level:
V
> LVI
Any
0
0
DD
TRIPR
V
V
V
< LVI
< 32 CGMXCLK Cycles
DD
DD
DD
TRIPF
Between 32 and 40
CGMXCLK Cycles
< LVI
< LVI
0 or 1
TRIPF
> 40 CGMXCLK Cycles
Any
1
TRIPF
LVI
TRIPF
< V
< LVI
Previous Value
DD
TRIPR
14.6 LVI Interrupts
The LVI module does not generate interrupt requests.
14.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
14.7.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.
MC68HC908AS32A — Rev 0.0
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185
MOTOROLA
Low Voltage Inhibit (LVI)
Low Voltage Inhibit (LVI)
14.7.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register
programmed to a logic 1, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI
trip will generate a reset and bring the MCU out of stop.
With the LVIPWR bit in the configuration register programmed to logic 1
and the LVISTOP bit at a logic 0, the LVI module will be inactive after a
STOP instruction.
Note that the LVI feature is intended to provide the safe shutdown of the
microcontroller and thus protection of related circuitry prior to any
application VDD voltage collapsing completely to an unsafe level. It is not
intended that users operate the microcontroller at lower than specified
operating voltage VDD
.
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186
MC68HC908AS32A — Rev 0.0
Low Voltage Inhibit (LVI)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 15. External Interrupt Module (IRQ)
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
15.5 IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . .192
15.7 IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .192
15.2 Introduction
15.3 Features
This section describes the nonmaskable external interrupt (IRQ) input.
Features include:
•
•
•
•
Dedicated External Interrupt Pin (IRQ)
Hysteresis Buffer
Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
Automatic Interrupt Acknowledge
MC68HC908AS32A — Rev 0.0
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MOTOROLA
External Interrupt Module (IRQ)
187
External Interrupt Module (IRQ)
15.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request. Figure 15-1 shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
•
Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.
•
Software clear — Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (ISCR). Writing a logic 1 to the ACK bit clears the
IRQ latch.
•
Reset — A reset automatically clears both interrupt latches.
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
V
DD
IRQF
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
CK
IRQ
IRQ
LATCH
IMASK
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 15-1. IRQ Block Diagram
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External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
Functional Description
Table 15-1. IRQ I/O Register Summary
Addr.
Register Name
Bit 7
6
0
5
0
4
0
3
IRQF
R
2
0
1
Bit 0
Read:
Write:
0
$001A IRQ Status/Control Register (ISCR)
IMASK MODE
R
R
R
R
ACK
R
=Reserved
The external interrupt pin is falling-edge triggered and is software-
configurable to be both falling-edge and low-level triggered. The MODE
bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 15-2).
MC68HC908AS32A — Rev 0.0
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Advance Information
189
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
FROM RESET
YES
I BIT SET?
NO
YES
INTERRUPT?
NO
STACK CPU REGISTERS.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
YES
NO
RTI
UNSTACK CPU REGISTERS.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 15-2. IRQ Interrupt Flowchart
Advance Information
MC68HC908AS32A — Rev 0.0
MOTOROLA
190
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
IRQ Pin
15.5 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-
level sensitive. With MODE set, both of the following actions must occur
to clear the IRQ latch:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ pin and require
software to clear the IRQ latch. Writing to the ACK bit can also
prevent spurious interrupts due to noise. Setting ACK does not
affect subsequent transitions on the IRQ pin. A falling edge on IRQ
that occurs after writing to the ACK bit latches another interrupt
request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and
$FFFB.
•
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ1 latch remains set.
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
The IRQF bit in the ISCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
MC68HC908AS32A — Rev 0.0
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Advance Information
191
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
15.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt
latch can be cleared during the break state. The BCFE bit in the SIM
break flag control register (SBFCR) enables software to clear the latches
during the break state. (See SIM Break Flag Control Register on page
122
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
15.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has these functions:
•
•
•
•
Shows the state of the IRQ interrupt flag
Clears the IRQ interrupt latch
Masks IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address: $001A
Bit 7
6
5
0
4
0
3
IRQF
R
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
0
R
0
0
R
R
0
R
0
ACK
0
0
0
R
=Reserved
Figure 15-3. IRQ Status and Control Register (ISCR)
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External Interrupt Module (IRQ)
MOTOROLA
External Interrupt Module (IRQ)
IRQ Status and Control Register
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
MC68HC908AS32A — Rev 0.0
MOTOROLA
Advance Information
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External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
Advance Information
MC68HC908AS32A — Rev 0.0
194
External Interrupt Module (IRQ)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 16. Serial Communications Interface (SCI)
16.1 Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.5.2.1
16.5.2.2
16.5.2.3
16.5.2.4
16.5.2.5
16.5.2.6
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Character Transmission . . . . . . . . . . . . . . . . . . . . . . .200
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
Inversion of Transmitted Output . . . . . . . . . . . . . . . .205
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .205
16.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
16.5.3.1
16.5.3.2
16.5.3.3
16.5.3.4
16.5.3.5
16.5.3.6
16.5.3.7
16.5.3.8
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . .208
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . .211
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . .216
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
16.8.1 PTE0/SCTxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . .217
16.8.2 PTE1/SCRxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . .217
MC68HC908AS32A — Rev 0.0
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195
MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
16.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
16.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .217
16.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .220
16.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .224
16.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
16.9.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .230
16.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
16.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . .231
16.2 Introduction
16.3 Features
The SCI allows asynchronous communications with peripheral devices
and other MCUs.
The SCI module’s features include:
•
•
•
•
•
•
•
•
Full Duplex Operation
Standard Mark/Space Non-Return-to-Zero (NRZ) Format
32 Programmable Baud Rates
Programmable 8-Bit or 9-Bit Character Length
Separately Enabled Transmitter and Receiver
Separate Receiver and Transmitter CPU Interrupt Requests
Programmable Transmitter Output Polarity
Two Receiver Wakeup Methods:
– Idle Line Wakeup
– Address Mark Wakeup
•
Interrupt-Driven Operation with Eight Interrupt Flags:
– Transmitter Empty
– Transmission Complete
– Receiver Full
Advance Information
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
Pin Name Conventions
– Idle Receiver Input
– Receiver Overrun
– Noise Error
– Framing Error
– Parity Error
•
•
•
Receiver Framing Error Detection
Hardware Parity Checking
1/16 Bit-Time Noise Detection
16.4 Pin Name Conventions
The generic names of the SCI input/output (I/O) pins are:
•
•
RxD (receive data)
TxD (transmit data)
SCI I/O lines are implemented by sharing parallel I/O port pins. The full
name of an SCI input or output reflects the name of the shared port pin.
Table 16-1 shows the full names and the generic names of the SCI I/O
pins.The generic pin names appear in the text of this section.
Table 16-1. Pin Name Conventions
Generic Pin Names
Full Pin Names
RxD
TxD
PTE1/SCRxD
PTE0/SCTxD
16.5 Functional Description
Figure 16-1 shows the structure of the SCI module. The SCI allows full-
duplex, asynchronous, NRZ serial communication between the MCU
and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.
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197
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
INTERNAL BUS
SCI DATA
REGISTER
SCI DATA
REGISTER
RECEIVE
SHIFT REGISTER
TRANSMIT
SHIFT REGISTER
RxD
TxD
TXINV
SCTIE
R8
T8
TCIE
SCRIE
ILIE
TE
SCTE
TC
RE
RWU
SBK
SCRF
IDLE
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
LOOPS
ENSCI
LOOPS
RECEIVE
CONTROL
FLAG
CONTROL
TRANSMIT
CONTROL
WAKEUP
CONTROL
M
BKF
RPF
ENSCI
WAKE
ILTY
PEN
PTY
PRE-
BAUD RATE
÷ 4
CGMXCLK
SCALER GENERATOR
DATA SELECTION
CONTROL
÷ 16
Figure 16-1. SCI Module Block Diagram
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Serial Communications Interface (SCI)
MOTOROLA
Serial Communications Interface (SCI)
Functional Description
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
TXINV
SCI Control Register 1 (SCC1) Write:
Reset:
Read:
0
SCRIE
0
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
0
1
0
0
0
0
0
0
0
0
0
0
BKF
0
RPF
Read:
SCI Status Register 2 (SCS2) Write:
Reset:
0
0
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
0
0
0
0
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 16-2. SCI I/O Register Summary
Table 16-2. SCI I/O Register Address Summary
Register
Address
SCC1
$0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
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MOTOROLA
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
16.5.1 Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 16-3.
8-BIT DATA FORMAT
(BIT M IN SCC1 CLEAR)
PARITY
OR DATA
BIT
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
9-BIT DATA FORMAT
(BIT M IN SCC1 SET)
PARITY
OR DATA
BIT
NEXT
START
BIT
START
BIT
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP
BIT
Figure 16-3. SCI Data Formats
16.5.2 Transmitter
Figure 16-4 shows the structure of the SCI transmitter.
16.5.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
16.5.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character
out to the TxD pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register. To initiate
an SCI transmission:
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable
bit (TE) in SCI control register 2 (SCC2).
3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI
Advance Information
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Serial Communications Interface (SCI)
Functional Description
status register 1 (SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD
pin goes to the idle condition, logic 1. If at any time software clears the
ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port E pins.
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
INTERNAL BUS
PRE-
BAUD
÷ 16
÷ 4
SCI DATA REGISTER
SCALER DIVIDER
SCP1
SCP0
SCR1
SCR2
SCR0
11-BIT
TRANSMIT
SHIFT REGISTER
H
8
7
6
5
4
3
2
1
0
L
TxD
TXINV
M
PEN
PTY
PARITY
GENERATION
T8
TRANSMITTER
CONTROL LOGIC
SCTE
SCTIE
SBK
SCTE
LOOPS
ENSCI
TE
SCTIE
TC
TC
TCIE
TCIE
Figure 16-4. SCI Transmitter
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Functional Description
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
Read:
TXINV
SCI Control Register 1 (SCC1) Write:
Reset:
0
SCRIE
0
Read:
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
SCI Control Register 2 (SCC2) Write:
Reset:
0
0
Read:
SCI Control Register 3 (SCC3) Write:
Reset:
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
SCI Status Register 1 (SCS1) Write:
Reset:
TC
SCRF
IDLE
OR
NF
FE
PE
1
1
0
0
0
0
0
0
Read:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SCI Data Register (SCDR) Write:
Reset:
Unaffected by Reset
Read:
SCI Baud Rate Register (SCBR) Write:
Reset:
0
0
0
0
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 16-5. SCI Transmitter I/O Register Summary
Table 16-3. SCI Transmitter I/O Address Summary
Register
SCC1
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCDR
$0018
SCBR
$0019
Address $0013
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16.5.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic
continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has the following effects on SCI registers:
•
•
•
•
•
•
Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits
16.5.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle
after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.
NOTE: When a break sequence is followed immediately by an idle character,
this SCI design exhibits a condition in which the break character length
is reduced by one half bit time. In this instance, the break sequence will
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Functional Description
consist of a valid start bit, eight or nine data bits (as defined by the M bit
in SCC1) of logic 0 and one half data bit length of logic 0 in the stop bit
position followed immediately by the idle character. To ensure a break
character of the proper length is transmitted, always queue up a byte of
data to be transmitted while the final break sequence is in progress.
NOTE: When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
16.5.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See SCI Control Register 1.)
16.5.2.6 Transmitter Interrupts
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
•
SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.
•
Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
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16.5.3 Receiver
Figure 16-6 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1
SCR2
SCR0
SCP1
SCP0
SCI DATA REGISTER
PRE-
BAUD
÷ 4
÷ 16
SCALER DIVIDER
11-BIT
RECEIVE SHIFT REGISTER
CGMXCLK
DATA
RECOVERY
H
8
7
6
5
4
3
2
1
0
L
RxD
ALL ZEROS
BKF
RPF
M
RWU
SCRF
IDLE
WAKE
ILTY
WAKEUP
LOGIC
PEN
PTY
R8
PARITY
CHECKING
IDLE
ILIE
ILIE
SCRF
SCRIE
SCRIE
OR
OR
ORIE
ORIE
NF
NF
NEIE
NEIE
FE
FE
FEIE
FEIE
PE
PE
PEIE
PEIE
Figure 16-6. SCI Receiver Block Diagram
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Functional Description
Register Name
Bit 7
LOOPS
0
6
ENSCI
0
5
4
M
0
3
WAKE
0
2
ILTY
0
1
PEN
0
Bit 0
PTY
0
SCI Control Register 1 (SCC1)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
TXINV
0
SCRIE
0
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
SCTIE
TCIE
0
ILIE
0
TE
RE
0
RWU
0
SBK
0
0
0
R8
T8
R
R
ORIE
NEIE
FEIE
PEIE
U
U
0
0
0
0
0
0
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
PE
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
1
0
1
0
0
0
0
0
0
0
0
0
0
0
BKF
RPF
0
0
0
0
0
0
0
0
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
Unaffected by Reset
SCI Baud Rate Register (SCBR) Read:
0
0
0
0
SCP1
0
SCP0
0
R
0
SCR2
0
SCR1
0
SCR0
0
Write:
Reset:
= Unimplemented
U = Unaffected
R
= Reserved
Figure 16-7. SCI I/O Receiver Register Summary
Table 16-4. SCI Receiver I/O Address Summary
Register SCC1
Address $0013
SCC2
$0014
SCC3
$0015
SCS1
$0016
SCS2
$0017
SCDR
$0018
SCBR
$0019
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Serial Communications Interface (SCI)
16.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
16.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
16.5.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 16-8):
•
•
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
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Functional Description
START BIT
LSB
RxD
START BIT
QUALIFICATION
START BIT
DATA
SAMPLES
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 16-8. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7. Table 16-5 summarizes the results of
the start bit verification samples.
Table 16-5. Start Bit Verification
RT3, RT5, and RT7 Samples
Start Bit Verification
Noise Flag
000
001
010
011
100
101
110
111
Yes
Yes
Yes
No
0
1
1
0
1
0
0
0
Yes
No
No
No
If start bit verification is not successful, the RT clock is reset and a new
search for a start bit begins.
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
To determine the value of a data bit and to detect noise, recovery logic
takes samples at RT8, RT9, and RT10. Table 16-6 summarizes the
results of the data bit samples.
Table 16-6. Data Bit Recovery
RT8, RT9, and RT10 Samples
Data Bit Determination
Noise Flag
000
001
010
011
100
101
110
111
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. Table 16-7 summarizes the results of the stop bit
samples.
Table 16-7. Stop Bit Recovery
RT8, RT9, and RT10 Samples
Framing Error Flag
Noise Flag
000
001
010
011
100
101
110
111
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
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Functional Description
16.5.3.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.
16.5.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate
tolerance is much more than the degree of misalignment that is likely to
occur.
As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.
Slow Data Tolerance
Figure 16-9 shows how much a slow received character can be
misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop
bit data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 16-9. Slow Data
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Serial Communications Interface (SCI)
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 16-9, the receiver
counts 154 RT cycles at the point when the count of the transmitting
device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is
154 – 147
× 100 = 4.54%
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 16-9, the receiver
counts 170 RT cycles at the point when the count of the transmitting
device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is
170 – 163
× 100 = 4.12%
-------------------------
170
Fast Data Tolerance
Figure 16-10 shows how much a fast received character can be
misaligned without causing a noise error or a framing error. The fast
stop bit ends at RT10 instead of RT16 but is still there for the stop bit
data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 16-10. Fast Data
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Functional Description
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 16-10, the receiver
counts 154 RT cycles at the point when the count of the transmitting
device is 10 bit times × 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is
154 – 160
× 100 = 3.90%.
-------------------------
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 16-10, the receiver
counts 170 RT cycles at the point when the count of the transmitting
device is 11 bit times × 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is
170 – 176
× 100 = 3.53%.
-------------------------
170
16.5.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.
Depending on the state of the WAKE bit in SCC1, either of two
conditions on the RxD pin can bring the receiver out of the standby state:
•
Address mark — An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
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Serial Communications Interface (SCI)
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle
character on the RxD pin wakes the receiver from the standby
state by clearing the RWU bit. The idle character that wakes the
receiver does not set the receiver idle bit, IDLE, or the SCI receiver
full bit, SCRF. The idle line type bit, ILTY, determines whether the
receiver begins counting logic 1s as idle character bits after the
start bit or after the stop bit.
NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
16.5.3.7 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI
receiver:
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.
•
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
16.5.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt
requests:
•
Receiver overrun (OR) — The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
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Serial Communications Interface (SCI)
Low-Power Modes
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.
•
•
•
Noise flag (NF) — The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.
Framing error (FE) — The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.
Parity error (PE) — The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
16.6.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU
interrupt request from the SCI module can bring the MCU out of wait
mode.
If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.
16.6.2 Stop Mode
The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. Any enabled CPU interrupt request from the
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Serial Communications Interface (SCI)
SCI module does not bring the MCU out of Stop mode. SCI module
operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.
16.7 SCI During Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module (BRK) on
page 157).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
16.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:
•
•
PTE0/SCTxD — Transmit data
PTE1/SCRxD — Receive data
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I/O Registers
16.8.1 PTE0/SCTxD (Transmit Data)
The PTE0/SCTxD pin is the serial data output from the SCI transmitter.
The SCI shares the PTE0/SCTxD pin with port E. When the SCI is
enabled, the PTE0/SCTxD pin is an output regardless of the state of the
DDRE2 bit in data direction register E (DDRE).
16.8.2 PTE1/SCRxD (Receive Data)
The PTE1/SCRxD pin is the serial data input to the SCI receiver. The
SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled,
the PTE1/SCRxD pin is an input regardless of the state of the DDRE1 bit
in data direction register E (DDRE).
16.9 I/O Registers
The following I/O registers control and monitor SCI operation:
•
•
•
•
•
•
•
SCI control register 1 (SCC1)
SCI control register 2 (SCC2)
SCI control register 3 (SCC3)
SCI status register 1 (SCS1)
SCI status register 2 (SCS2)
SCI data register (SCDR)
SCI baud rate register (SCBR)
16.9.1 SCI Control Register 1
SCI control register 1:
•
•
•
•
•
Enables loop mode operation
Enables the SCI
Controls output polarity
Controls character length
Controls SCI wakeup method
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•
•
•
Controls idle character detection
Enables parity function
Controls parity type
Address: $0013
Bit 7
6
ENSCI
0
5
TXINV
0
4
M
0
3
WAKE
0
2
ILLTY
0
1
PEN
0
Bit 0
PTY
0
Read:
LOOPS
Write:
Reset:
0
Figure 16-11. SCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the
RxD pin is disconnected from the SCI, and the transmitter output goes
into the receiver input. Both the transmitter and the receiver must be
enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE: Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
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I/O Registers
M — Mode (Character Length) Bit
This read/write bit determines whether SCI characters are eight or
nine bits long. (See Table 16-8).The ninth bit can serve as an extra
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the RxD pin. Reset clears the WAKE
bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY — Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN — Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 16-8).
When enabled, the parity function inserts a parity bit in the most
significant bit position. (See Table 16-7). Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 16-8). Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 16-8. Character Format Selection
Control Bits
PEN:PTY
Character Format
Start
Bits
Data
Bits
Stop
Parity
Character
Length
M
Bits
0
1
0
0
1
1
0X
0X
10
11
10
11
1
1
1
1
1
1
8
9
7
7
8
8
None
None
Even
Odd
1
1
1
1
1
1
10 Bits
11 Bits
10 Bits
10 Bits
11 Bits
11 Bits
Even
Odd
16.9.2 SCI Control Register 2
SCI control register 2:
Enables the following CPU interrupt requests:
•
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
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Serial Communications Interface (SCI)
I/O Registers
•
•
•
•
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Address: $0014
Bit 7
6
TCIE
0
5
SCRIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
SCTIE
Write:
Reset:
0
Figure 16-12. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the
SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE
bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
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Serial Communications Interface (SCI)
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the
SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE
bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
TE — Transmitter Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
(logic 1). Clearing and then setting TE during a transmission queues
an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
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I/O Registers
RE — Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU — Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
16.9.3 SCI Control Register 3
SCI control register 3:
•
•
Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted.
Enables the following interrupts:
– Receiver overrun interrupts
– Noise error interrupts
– Framing error interrupts
– Parity error interrupts
Address: $0015
Bit 7
6
T8
U
5
R
0
4
3
2
NEIE
0
1
FEIE
0
Bit 0
PEIE
0
Read:
Write:
Reset:
R8
R
ORIE
U
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 16-13. SCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
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Serial Communications Interface (SCI)
I/O Registers
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
16.9.4 SCI Status Register 1
SCI status register 1 contains flags to signal the following conditions:
•
•
•
•
•
•
•
•
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
PE
Read: SCTE
Write:
TC
SCRF
IDLE
OR
NF
FE
Reset:
1
1
0
0
0
0
0
0
= Unimplemented
Figure 16-14. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
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Serial Communications Interface (SCI)
I/O Registers
TC — Transmission Complete Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is cleared automatically when data, preamble, or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF — SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set
the SCRF generates a CPU interrupt request. In normal operation,
clear the SCRF bit by reading SCS1 with SCRF set and then reading
the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1
and SCDR in the flag-clearing sequence. Figure 16-15 shows the
normal flag-clearing sequence and an example of an overrun caused by
a delayed flag-clearing sequence. The delayed read of SCDR does not
clear the OR bit because OR was not set when SCS1 was read. Byte 2
caused the overrun and is lost. The next flag-clearing sequence reads
byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-clearing
routine can check the OR bit in a second read of SCS1 after reading the
data register.
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
BYTE 3
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 16-15. Flag Clearing Sequence
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I/O Registers
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in
SCC3 is also set. Clear the NF bit by reading SCS1 and then reading
the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
16.9.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
•
•
Break character detected
Incoming data
Address: $0017
Bit 7
6
0
5
0
4
0
3
0
2
0
1
Bit 0
RPF
Read:
Write:
Reset:
0
BKF
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-16. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the RxD pin followed by another break character. Reset clears the
BKF bit.
1 = Break character detected
0 = No break character detected
RPF — Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch), or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
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Serial Communications Interface (SCI)
I/O Registers
16.9.6 SCI Data Register
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
Address: $0018
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Unaffected by Reset
Figure 16-17. SCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
NOTE: Do not use read-modify-write instructions on the SCI data register.
16.9.7 SCI Baud Rate Register
The baud rate register selects the baud rate for both the receiver and the
transmitter.
Address: $0019
Bit 7
0
6
0
5
SCP1
0
4
3
2
SCR2
0
1
SCR1
0
Bit 0
SCR0
0
Read:
Write:
Reset:
SCP0
R
0
0
0
0
= Unimplemented
R
= Reserved
Figure 16-18. SCI Baud Rate Register (SCBR)
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCP1 and SCP0 — SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown
in Table 16-9. Reset clears SCP1 and SCP0.
Table 16-9. SCI Baud Rate Prescaling
SCP[1:0]
Prescaler Divisor (PD)
00
01
10
11
1
3
4
13
SCR2 – SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate divisor as shown in
Table 16-10. Reset clears SCR2–SCR0.
Table 16-10. SCI Baud Rate Selection
SCR[2:1:0]
000
Baud Rate Divisor (BD)
1
2
001
010
4
011
8
100
16
32
64
128
101
110
111
Use the following formula to calculate the SCI baud rate:
fCrystal
Baud rate = ------------------------------------
64 × PD × BD
where:
fCrystal = crystal frequency
PD = prescaler divisor
BD = baud rate divisor
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
Table 16-11 shows the SCI baud rates that can be generated with a
4.9152-MHz crystal.
Table 16-11. SCI Baud Rate Selection Examples
Prescaler
Divisor
(PD)
Baud Rate
Divisor
(BD)
Baud Rate
= 4.9152 MHz)
SCP[1:0]
SCR[2:1:0]
(f
Crystal
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
1
1
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
1
2
76,800
38,400
19,200
9600
4800
2400
1200
600
1
4
1
8
1
16
32
64
128
1
1
1
1
3
25,600
12,800
6400
3200
1600
800
3
2
3
4
3
8
3
16
32
64
128
1
3
3
400
3
200
4
19,200
9600
4800
2400
1200
600
4
2
4
4
4
8
4
16
32
64
128
1
4
4
300
4
150
13
13
13
13
13
13
13
13
5908
2954
1477
739
2
4
8
16
32
64
128
369
185
92
46
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Technical Data — MC68HC908AS32A
Section 17. Serial Peripheral Interface (SPI)
17.1 Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
17.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
17.4 Pin Name and Register Name Conventions. . . . . . . . . . . .237
17.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
17.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
17.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
17.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
17.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . .242
17.6.2 Transmission Format When CPHA = 0. . . . . . . . . . . . . .243
17.6.3 Transmission Format When CPHA = 1. . . . . . . . . . . . . .244
17.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . .245
17.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.7.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.7.2 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
17.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . .252
17.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
17.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
17.11.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
17.11.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
17.12 SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .255
17.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
17.13.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . .257
17.13.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . .257
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
17.13.3 SPSCK (Serial Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . .257
17.13.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
17.13.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
17.14 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
17.14.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
17.14.2 SPI Status and Control Register. . . . . . . . . . . . . . . . . . .262
17.14.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266
17.2 Introduction
17.3 Features
This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.
Features of the SPI module include:
•
•
•
Full-Duplex Operation
Master and Slave Modes
Double-Buffered Operation with Separate Transmit and Receive
Registers
•
•
•
•
Four Master Mode Frequencies (Maximum = Bus Frequency ÷ 2)
Maximum Slave Mode Frequency = Bus Frequency
Serial Clock with Programmable Polarity and Phase
Two Separately Enabled Interrupts with CPU Service:
– SPRF (SPI Receiver Full)
– SPTE (SPI Transmitter Empty)
•
•
•
•
Mode Fault Error Flag with CPU Interrupt Capability
Overflow Error Flag with CPU Interrupt Capability
Programmable Wired-OR Mode
I2C (Inter-Integrated Circuit) Compatibility
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Serial Peripheral Interface (SPI)
Pin Name and Register Name Conventions
17.4 Pin Name and Register Name Conventions
The generic names of the SPI input/output (I/O) pins are:
•
SS (slave select)
SPSCK (SPI serial clock)
•
•
•
MOSI (master out slave in)
MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an
SPI pin reflects the name of the shared port pin. Table 17-1 shows the
full names of the SPI I/O pins. The generic pin names appear in the text
that follows.
Table 17-1. Pin Name Conventions
SPI Generic Pin Name
Full SPI Pin Name
MISO
MOSI
SS
SPSCK
PTE5/MISO PTE6/MOSI PTE4/SS PTE7/SPSCK
The generic names of the SPI I/O registers are:
•
•
•
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Table 17-2 shows the names and the addresses of the SPI I/O registers.
Table 17-2. I/O Register Addresses
Register Name
SPI Control Register (SPCR)
SPI Status and Control Register (SPSCR)
SPI Data Register (SPDR)
Address
$0010
$0011
$0012
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17.5 Functional Description
Table 17-3 summarizes the SPI I/O registers and Figure 17-1 shows the
structure of the SPI module.
Table 17-3. SPI I/O Register Summary
Addr
Register Name
R/W Bit 7
6
R
0
5
4
3
2
1
Bit 0
SPTIE
0
Read:
SPRIE
Write:
SPI Control Register
$0010
SPMSTR CPOL
CPHA SPWOM SPE
(SPCR)
Reset:
0
1
0
1
SPTE
1
0
0
Read: SPRF
Write:
OVRF MODF
SPI Status and Control Register
(SPSCR)
$0011
$0012
ERRIE
0
MODFEN SPR1
SPR0
0
Reset:
0
0
0
0
0
Read:
Write:
Reset:
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
SPI Data Register
(SPDR)
Unaffected by Reset
= Unimplemented
R
=Reserved
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Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
SHIFT REGISTER
BUS CLOCK
MISO
MOSI
7
6
5
4
3
2
1
0
÷ 2
÷ 8
÷ 32
CLOCK
DIVIDER
RECEIVE DATA REGISTER
PIN
CONTROL
LOGIC
÷ 128
CLOCK
SPSCK
SPMSTR
SPE
SELECT
M
CLOCK
LOGIC
S
SS
SPR1
SPR0
SPMSTR
CPHA
CPOL
SPWOM
TRANSMITTER CPU INTERRUPT REQUEST
RECEIVER/ERROR CPU INTERRUPT REQUEST
MODFEN
ERRIE
SPTIE
SPI
CONTROL
SPRIE
SPE
SPRF
SPTE
OVRF
MODF
Figure 17-1. SPI Module Block Diagram
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices, including other MCUs.
Software can poll the SPI status flags or SPI operation can be interrupt
driven. All SPI interrupts can be serviced by the CPU.
The following paragraphs describe the operation of the SPI module.
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Serial Peripheral Interface (SPI)
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17.5.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR
(SPCR $0010), is set.
NOTE: Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. See SPI Control Register on page
260.
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR
$0011). The byte begins shifting out on the MOSI pin under the control
of the serial clock. (See Table 17-4).
The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. (See SPI Status and Control Register
on page 262). Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
MASTER MCU
SLAVE MCU
MISO
MOSI
MISO
MOSI
SHIFT REGISTER
SHIFT REGISTER
SPSCK
SS
SPSCK
SS
BAUD RATE
GENERATOR
V
DD
Figure 17-2. Full-Duplex Master-Slave Connections
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Serial Peripheral Interface (SPI)
Functional Description
As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master’s MISO pin. The transmission ends when
the receiver full bit, SPRF (SPSCR), becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register and
then reading the SPI data register. Writing to the SPI data register clears
the SPTIE bit.
17.5.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010)
is clear. In slave mode the SPSCK pin is the input for the serial clock
from the master MCU. Before a data transmission occurs, the SS pin of
the slave MCU must be at logic 0. SS must remain low until the
transmission is complete. (See Mode Fault Error on page 249).
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it is transferred to the receive data register, and
the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave
software then must read the SPI data register before another byte enters
the shift register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed, which is twice as fast as the fastest master
SPSCK clock that can be generated. The frequency of the SPSCK for an
SPI configured as a slave does not have to correspond to any SPI baud
rate. The baud rate only controls the speed of the SPSCK generated by
an SPI configured as a master. Therefore, the frequency of the SPSCK
for an SPI configured as a slave can be any frequency less than or equal
to the bus speed.
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise
the byte already in the slave shift register shifts out on the MISO pin.
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Data written to the slave shift register during a a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. See Transmission Formats on page 242.
If the write to the data register is late, the SPI transmits the data already
in the shift register from the previous transmission.
NOTE: To prevent SPSCK from appearing as a clock edge, SPSCK must be in
the proper idle state before the slave is enabled.
17.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock line
synchronizes shifting and sampling on the two serial data lines. A slave
select line allows individual selection of a slave SPI device; slave
devices that are not selected do not interfere with SPI bus activities. On
a master SPI device, the slave select line can be used optionally to
indicate a multiple-master bus contention.
17.6.1 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase
and polarity using two bits in the SPI control register (SPCR). The clock
polarity is specified by the CPOL control bit, which selects an active high
or low clock and has no significant effect on the transmission format.
The clock phase (CPHA) control bit (SPCR) selects one of two
fundamentally different transmission formats. The clock phase and
polarity should be identical for the master SPI device and the
communicating slave device. In some cases, the phase and polarity are
changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE: Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI
by clearing the SPI enable bit (SPE).
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Serial Peripheral Interface (SPI)
Transmission Formats
17.6.2 Transmission Format When CPHA = 0
Figure 17-3 shows an SPI transmission in which CPHA (SPCR) is
logic 0. The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI (see Mode Fault Error on page 249). When CPHA = 0, the first
SPSCK edge is the MSB capture strobe. Therefore, the slave must
begin driving its data before the first SPSCK edge, and a falling edge on
the SS pin is used to start the transmission. The SS pin must be toggled
high and then low again between each byte transmitted.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK CPOL = 0
SCK CPOL = 1
MOSI
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
LSB
FROM MASTER
MISO
FROM SLAVE
MSB
SS TO SLAVE
CAPTURE STROBE
Figure 17-3. Transmission Format (CPHA = 0)
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17.6.3 Transmission Format When CPHA = 1
Figure 17-4 shows an SPI transmission in which CPHA (SPCR) is
logic 1. The figure should not be used as a replacement for data sheet
parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See Mode Fault Error on page 249). When CPHA = 1, the master
begins driving its MOSI pin on the first SPSCK edge. Therefore, the
slave uses the first SPSCK edge as a start transmission signal. The SS
pin can remain low between transmissions. This format may be
preferable in systems having only one master and only one slave driving
the MISO data line.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK CPOL = 0
SCK CPOL =1
MOSI
FROM MASTER
MSB
MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
LSB
MISO
FROM SLAVE
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 17-4. Transmission Format (CPHA = 1)
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Transmission Formats
17.6.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions
are started by a software write to the SPDR ($0012). CPHA has no effect
on the delay to the start of the transmission, but it does affect the initial
state of the SCK signal. When CPHA = 0, the SCK signal remains
inactive for the first half of the first SCK cycle. When CPHA = 1, the first
SCK cycle begins with an edge on the SCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1–SPR0) affects the
delay from the write to SPDR and the start of the SPI transmission. (See
Figure 17-5). The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. It is only enabled when both the
SPE and SPMSTR bits (SPCR) are set to conserve power. SCK edges
occur half way through the low time of the internal MCU clock. Since the
SPI clock is free-running, it is uncertain where the write to the SPDR will
occur relative to the slower SCK. This uncertainty causes the variation
in the initiation delay shown in Figure 17-5. This delay will be no longer
than a single SPI bit time. That is, the maximum delay between the write
to SPDR and the start of the SPI transmission is two MCU bus cycles for
DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and
128 MCU bus cycles for DIV128.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
WRITE
TO SPDR
INITIATION DELAY
MSB
BUS
CLOCK
MOSI
BIT 6
BIT 5
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
BUS
CLOCK
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
EARLIEST LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
LATEST
LATEST
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
Figure 17-5. Transmission Start Delay (Master)
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Error Conditions
17.7 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRF in SPSCR) — Failing to read the SPI data
register before the next byte enters the shift register sets the
OVRF bit. The new byte does not transfer to the receive data
register, and the unread byte still can be read by accessing the
SPI data register. OVRF is in the SPI status and control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates
that the voltage on the slave select pin (SS) is inconsistent with the
mode of the SPI. MODF is in the SPI status and control register.
17.7.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data
register still has unread data from a previous transmission when the
capture strobe of bit 1 of the next transmission occurs. (See Figure 17-
3 and Figure 17-4.) If an overflow occurs, the data being received is not
transferred to the receive data register so that the unread data can still
be read. Therefore, an overflow error always indicates the loss of data.
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. MODF and OVRF can
generate a receiver/error CPU interrupt request. (See Figure 17-8). It is
not possible to enable only MODF or OVRF to generate a receiver/error
CPU interrupt request. However, leaving MODFEN low prevents MODF
from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out
of wait, having an overflow condition without overflow interrupts enabled
causes the MCU to hang in wait mode. If the OVRF is enabled to
generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 17-6 shows how it is possible to
miss an overflow.
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
2
5
READ SPSCR
READ SPDR
3
7
1
2
BYTE 1 SETS SPRF BIT.
5
CPU READS SPSCRW WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
6
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3
4
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 2 SETS SPRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 17-6. Missed Read of Overflow Condition
The first part of Figure 17-6 shows how to read the SPSCR and SPDR
to clear the SPRF without problems. However, as illustrated by the
second transmission example, the OVRF flag can be set in between the
time that SPSCR and SPDR are read.
In this case, an overflow can be easily missed. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it will not be
obvious that bytes are being lost as more transmissions are completed.
To prevent this, either enable the OVRF interrupt or do another read of
the SPSCR after the read of the SPDR. This ensures that the OVRF was
not set before the SPRF was cleared and that future transmissions will
complete with an SPRF interrupt. Figure 17-7 illustrates this process.
Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
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Serial Peripheral Interface (SPI)
Error Conditions
BYTE 1
1
BYTE 2
5
BYTE 3
7
BYTE 4
11
SPI RECEIVE
COMPLETE
SPRF
OVRF
2
4
6
9
12
14
READ SPSCR
READ SPDR
3
8
10
13
1
2
8
9
BYTE 1 SETS SPRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
3
4
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
10
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
11
12
13
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
5
6
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
7
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
14
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 17-7. Clearing SPRF When OVRF Interrupt Is Not Enabled
17.7.2 Mode Fault Error
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
17-8). It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
•
If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
•
•
•
•
The SPE bit is cleared.
The SPTE bit is set.
The SPI state counter is cleared.
The data direction register of the shared I/O port regains control of
port drivers.
NOTE: To prevent bus contention with another master SPI after a mode fault
error, clear all data direction register (DDR) bits associated with the SPI
shared port pins.
NOTE: Setting the MODF flag (SPSCR) does not clear the SPMSTR bit.
Reading SPMSTR when MODF = 1 will indicate a MODE fault error
occurred in either master mode or slave mode.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK returns to its idle
level after the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
IDLE level after the shift of the last data bit. (See Transmission
Formats on page 242).
NOTE: When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later deselected (SS is at logic 1) even if no SPSCK is sent to that
slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later deselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
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Interrupts
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by toggling the SPE bit of the slave.
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if a transmission has begun.
To clear the MODF flag, read the SPSCR and then write to the SPCR
register. This entire clearing procedure must occur with no MODF
condition existing or else the flag will not be cleared.
17.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 17-4. SPI Interrupts
Flag
Request
SPTE (Transmitter Empty) SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPRF (Receiver Full)
OVRF (Overflow)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1, MODFEN = 1)
MODF (Mode Fault)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt, provided that the SPI is enabled
(SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPTE
SPTIE
SPRF
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPRIE
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
Figure 17-8. SPI Interrupt Request Generation
Two sources in the SPI status and control register can generate CPU
interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
17.9 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high. Figure 17-9 shows the
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
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MOTOROLA
Serial Peripheral Interface (SPI)
Queuing Transmission Data
1
3
8
WRITE TO SPDR
SPTE
5
10
2
SPSCK (CPHA:CPOL = 1:0)
MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT
6
5
4
3
2
1
6
5
4
3
2
1
6
5
4
BYTE 1
BYTE 2
BYTE 3
4
9
SPRF
READ SPSCR
READ SPDR
6
11
7
12
1
2
3
4
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
7
8
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
10
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
11
12
CPU READS SPSCR WITH SPRF BIT SET.
CPU READS SPDR, CLEARING SPRF BIT.
5
6
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
Figure 17-9. SPRF/SPTE CPU Interrupt Timing
For a slave, the transmit data buffer allows back-to-back transmissions
to occur without the slave having to time the write of its data between the
transmissions. Also, if no new data is written to the data buffer, the last
value contained in the shift register will be the next data word
transmitted.
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
17.10 Resetting the SPI
Any system reset completely resets the SPI. Partial reset occurs
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:
•
•
•
•
The SPTE flag is set.
Any transmission currently in progress is aborted.
The shift register is cleared.
The SPI state counter is cleared, making it ready for a new
complete transmission.
•
All the SPI port logic is defaulted back to being general-purpose
I/O.
The following additional items are reset only by a system reset:
•
•
All control bits in the SPCR register
All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)
•
The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to reset all control bits when SPE
is set back to high for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.
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MOTOROLA
Serial Peripheral Interface (SPI)
Low-Power Modes
17.11 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
17.11.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction.
In wait mode, the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). (See Interrupts on page 251).
17.11.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after the MCU exits stop mode. If stop mode is exited by reset,
any transfer in progress is aborted and the SPI is reset.
17.12 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See SIM Break Flag Control
Register on page 122).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
17.13 I/O Signals
The SPI module has four I/O pins and shares three of them with a
parallel I/O port.
•
•
•
•
•
MISO — Data received
MOSI — Data transmitted
SPSCK — Serial clock
SS — Slave select
V
SS — Clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I2C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I2C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I2C peripheral and through a pullup resistor
to VDD
.
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MOTOROLA
Serial Peripheral Interface (SPI)
I/O Signals
17.13.1 MISO (Master In/Slave Out)
MISO is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.
Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-
slave system, a logic 1 on the SS pin puts the MISO pin in a high-
impedance state.
When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.
17.13.2 MOSI (Master Out/Slave In)
MOSI is one of the two SPI module pins that transmit serial data. In full
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.
When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.
17.13.3 SPSCK (Serial Clock)
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation, the
master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
17.13.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
Transmission Formats.) Since it is used to indicate the start of a
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See Figure 17-10.
MISO/MOSI
MASTER SS
BYTE 1
BYTE 2
BYTE 3
SLAVE SS
CPHA = 0
SLAVE SS
CPHA = 1
Figure 17-10. CPHA/SS Timing
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See SPI Status
and Control Register on page 262).
NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if a transmission already has begun.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See Mode Fault Error on page 249). For the state
of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK
register must be set. If the MODFEN bit is low for an SPI master, the SS
pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an
input-only pin to the SPI regardless of the state of the data direction
register of the shared I/O port.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
I/O Registers
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register. (See Table 17-
5).
Table 17-5. SPI Configuration
SPE SPMSTR MODFEN SPI Configuration
State of SS Logic
General-Purpose I/O;
SS Ignored by SPI
0
1
1
1
X
0
1
1
X
X
0
Not Enabled
Slave
Input-Only to SPI
General-Purpose I/O;
SS Ignored by SPI
Master without MODF
Master with MODF
1
Input-Only to SPI
X = don’t care
17.13.5 VSS (Clock Ground)
VSS is the ground return for the serial clock pin, SPSCK, and the ground
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the VSS pin.
17.14 I/O Registers
Three registers control and monitor SPI operation:
•
•
•
SPI control register (SPCR $0010)
SPI status and control register (SPSCR $0011)
SPI data register (SPDR $0012)
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
17.14.1 SPI Control Register
The SPI control register:
•
•
•
•
•
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
•
Enables the SPI module
Address: $0010
Bit 7
6
5
4
3
2
1
SPE
0
Bit 0
SPTIE
0
Read:
SPRIE
Write:
R
SPMSTR CPOL
CPHA SPWOM
Reset:
0
0
1
0
1
0
R
=Reserved
Figure 17-11. SPI Control Register (SPCR)
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
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MOTOROLA
Serial Peripheral Interface (SPI)
I/O Registers
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 17-3 and Figure 17-4.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL bits. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 17-3 and Figure 17-4.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must
be set to logic 1 between bytes. (See Figure 17-10). Reset sets the
CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See Mode Fault Error on page 249). A logic 1
on the SS pin does not in any way affect the state of the SPI state
machine.
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPWOM — SPI Wired-OR Mode Bit
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
SPE — SPI Enable Bit
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI (see Resetting the SPI on page 254). Reset
clears the SPE bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE — SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
17.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following
conditions:
•
•
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow
error)
•
•
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
•
•
•
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
I/O Registers
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
SPR0
0
Read: SPRF
Write:
OVRF
MODF
SPTE
ERRIE
MODFEN SPR1
Reset:
0
0
0
0
1
0
0
R
=Reserved
= Unimplemented
Figure 17-12. SPI Status and Control Register (SPSCR)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Any read of the SPI data register clears the SPRF
bit.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This read-only bit enables the MODF and OVRF flags to generate
CPU interrupt requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the SPI data register. Reset clears the OVRF flag.
1 = Overflow
0 = No overflow
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Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission. In a master SPI, the MODF flag is set if
the SS pin goes low at any time. Clear the MODF bit by reading the
SPI status and control register with MODF set and then writing to the
SPI data register. Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request if the SPTIE bit in the SPI control register
is set also.
NOTE: Do not write to the SPI data register unless the SPTE bit is high.
For an idle master or idle slave that has no data loaded into its
transmit buffer, the SPTE will be set again within two bus cycles since
the transmit buffer empties into the shift register. This allows the user
to queue up a 16-bit value to send. For an already active slave, the
load of the shift register cannot occur until the transmission is
completed. This implies that a back-to-back write to the transmit data
register is not possible. The SPTE indicates when the next write can
occur.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general
purpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. (See SS (Slave Select) on page 258).
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
I/O Registers
If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. (See Mode Fault Error on page 249).
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as
shown in Table 17-6. SPR1 and SPR0 have no effect in slave mode.
Reset clears SPR1 and SPR0.
Table 17-6. SPI Master Baud Rate Selection
SPR1:SPR0
Baud Rate Divisor (BD)
00
01
10
11
2
8
32
128
Use this formula to calculate the SPI baud rate:
CGMOUT
Baud rate = --------------------------
2 × BD
where:
CGMOUT = base clock output of the clock generator module (CGM),
see Clock Generator Module (CGM) on page 123.
BD = baud rate divisor
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265
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
17.14.3 SPI Data Register
The SPI data register is the read/write buffer for the receive data register
and the transmit data register. Writing to the SPI data register writes data
into the transmit data register. Reading the SPI data register reads data
from the receive data register. The transmit data and receive data
registers are separate buffers that can contain different values. See
Figure 17-1
Address: $0012
Bit 7
R7
6
5
4
3
2
1
Bit 0
R0
Read:
Write:
Reset:
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
T7
T0
Indeterminate after Reset
Figure 17-13. SPI Data Register (SPDR)
R7–R0/T7–T0 — Receive/Transmit Data Bits
NOTE: Do not use read-modify-write instructions on the SPI data register since
the buffer read is not the same as the buffer written.
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MOTOROLA
Technical Data — MC68HC908AS32A
Section 18. Timer Interface Module B (TIMB)
18.1 Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
18.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
18.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . .271
18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
18.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
18.4.3.1
18.4.3.2
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . .273
Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . .274
18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .274
18.4.4.1
18.4.4.2
18.4.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . .275
Buffered PWM Signal Generation. . . . . . . . . . . . . . . .276
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .277
18.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
18.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
18.7 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .279
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
18.8.1 TIMB Clock Pin (PTD4/ATD12/TBCLK). . . . . . . . . . . . . .280
18.8.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0) . .280
18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
18.9.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . .281
18.9.2 TIMB Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .283
18.9.3 TIMB Counter Modulo Registers. . . . . . . . . . . . . . . . . . .285
18.9.4 TIMB Channel Status and Control Registers. . . . . . . . .286
18.9.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .290
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
18.2 Introduction
This section describes the timer interface module (TIMB). The TIMB is a
2-channel timer that provides a timing reference with input capture,
output compare and pulse width modulation functions. Figure 18-1 is a
block diagram of the TIMB.
The TIMB module is feature of the MC68HC908AZ60A only.
For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.
18.3 Features
Features of the TIMB include:
•
Two Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger
– Set, Clear or Toggle Output Compare Action
•
•
Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
Programmable TIMB Clock Input
– 7 Frequency Internal Bus Clock Prescaler Selection
– External TIMB Clock Input (4 MHz Maximum Frequency)
Free-Running or Modulo Up-Count Operation
Toggle Any Channel Pin on Overflow
•
•
•
TIMB Counter Stop and Reset Bits
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Timer Interface Module B (TIMB)
MOTOROLA
Timer Interface Module B (TIMB)
Features
TCLK
PTD4/ATD12/TBCLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
ELS0B
ELS0A
ELS1A
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
TOV0
CH0MAX
PTF4
PTF4/TBCH0
PTF5/TBCH1
LOGIC
CH0F
MS0B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
ELS1B
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
TOV1
CH1MAX
PTF5
LOGIC
CH1F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
Figure 18-1. TIMB Block Diagram
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
Figure 18-2. TIMB I/O Register Summary
Addr.
$0040
$0041
$0042
Register Name
Bit 7
6
5
4
3
0
2
PS2
10
2
1
PS1
9
Bit 0
PS0
TIMB Status/Control Register (TBSC) TOF
TIMB Counter Register High (TBCNTH) Bit 15
TIMB Counter Register Low (TBCNTL) Bit 7
TOIE TSTOP TRST
14
6
13
5
12
4
11
3
Bit 8
Bit 0
Bit 8
Bit 0
1
$0043 TIMB Counter Modulo Reg. High (TBMODH) Bit 15
$0044 TIMB Counter Modulo Reg. Low (TBMODL) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
$0045 TIMB Ch. 0 Status/Control Register (TBSC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
$0046
$0047
TIMB Ch. 0 Register High (TBCH0H) Bit 15
TIMB Ch. 0 Register Low (TBCH0L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0048 TIMB Ch. 1 Status/Control Register (TBSC1) CH1F CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$0049
$004A
TIMB Ch. 1 Register High (TBCH1H) Bit 15
TIMB Ch. 1 Register Low (TBCH1L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
R
=Reserved
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Timer Interface Module B (TIMB)
Functional Description
18.4 Functional Description
Figure 18-1 shows the TIMB structure. The central component of the
TIMB is the 16-bit TIMB counter that can operate as a free-running
counter or a modulo up-counter. The TIMB counter provides the timing
reference for the input capture and output compare functions. The TIMB
counter modulo registers, TBMODH–TBMODL, control the modulo
value of the TIMB counter. Software can read the TIMB counter value at
any time without affecting the counting sequence.
The two TIMB channels are programmable independently as input
capture or output compare channels.
18.4.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the
TIMB clock pin, PTD4/ATD12/TBCLK. The prescaler generates seven
clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMB status and control register select the TIMB clock source.
18.4.2 Input Capture
An input capture function has three basic parts: edge select logic, an
input capture latch and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TBSC0 through TBSC1 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIMB latches the contents of the TIMB counter into
the TIMB channel registers, TBCHxH–TBCHxL. Input captures can
generate TIMB CPU interrupt requests. Software can determine that an
input capture event has occurred by enabling input capture interrupts or
by polling the status flag bit.
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
The free-running counter contents are transferred to the TIMB channel
register (TBCHxH–TBCHxL, see TIMB Channel Registers on page
290) on each proper signal transition regardless of whether the TIMB
channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear.
When the status flag is set, a CPU interrupt is generated if enabled. The
value of the count latched or “captured” is the time of the event. Because
this value is stored in the input capture register 2 bus cycles after the
actual event occurs, user software can respond to this event at a later
time and determine the actual time of the event. However, this must be
done prior to another input capture on the same pin; otherwise, the
previous time value will be lost.
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see TIMB
Channel Registers on page 290). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture channel register
(TBCHxH–TBCHxL).
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Timer Interface Module B (TIMB)
Functional Description
18.4.3 Output Compare
With the output compare function, the TIMB can generate a periodic
pulse with a programmable polarity, duration and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMB can set, clear or toggle the channel pin. Output compares can
generate TIMB CPU interrupt requests.
18.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare on page 273. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable TIMB
overflow interrupts and write the new value in the TIMB overflow
interrupt routine. The TIMB overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
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Timer Interface Module B (TIMB)
18.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTF4/TBCH0 pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last.
TBSC0 controls and monitors the buffered output compare function and
TIMB channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a
general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
18.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIMB can generate a PWM signal. The value in the TIMB counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMB counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 18-3 shows, the output compare value in the TIMB channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMB to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMB to set the pin if the state of the PWM
pulse is logic 0.
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MOTOROLA
Timer Interface Module B (TIMB)
Functional Description
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-3. PWM Period and Pulse Width
The value in the TIMB counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMB counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see TIMB Status and Control Register).
The value in the TIMB channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMB channel registers
produces a duty cycle of 128/256 or 50%.
18.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM) on page 274. The pulses
are unbuffered because changing the pulse width requires writing the
new pulse width value over the value currently in the TIMB channel
registers.
An unsynchronized write to the TIMB channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMB overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
to be missed. The TIMB may pass the new value before it is written to
the TIMB channel registers.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
•
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
When changing to a longer pulse width, enable TIMB overflow
interrupts and write the new value in the TIMB overflow interrupt
routine. The TIMB overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
18.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTF4/TBCH0 pin. The TIMB channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers
initially control the pulse width on the PTF4/TBCH0 pin. Writing to the
TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMB channel registers (0 or
1) that control the pulse width are the ones written to last. TBSC0
controls and monitors the buffered PWM function, and TIMB channel 1
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MOTOROLA
Timer Interface Module B (TIMB)
Functional Description
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O
pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
18.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMB status and control register (TBSC):
a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.
b. Reset the TIMB counter and prescaler by setting the TIMB
reset bit, TRST.
2. In the TIMB counter modulo registers (TBMODH–TBMODL) write
the value for the required PWM period.
3. In the TIMB channel x registers (TBCHxH–TBCHxL) write the
value for the required pulse width.
4. In TIMB channel x status and control register (TBSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA (see Table 18-2).
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level (see Table 18-2).
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMB status control register (TBSC) clear the TIMB stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L)
initially control the buffered PWM output. TIMB status control register 0
(TBSC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMB overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output (see TIMB Channel
Status and Control Registers on page 286).
18.5 Interrupts
The following TIMB sources can generate interrupt requests:
•
TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value reaches the modulo value programmed in the TIMB
counter modulo registers. The TIMB overflow interrupt enable bit,
TOIE, enables TIMB overflow CPU interrupt requests. TOF and
TOIE are in the TIMB status and control register.
•
TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMB CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
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Timer Interface Module B (TIMB)
MOTOROLA
Timer Interface Module B (TIMB)
Low-Power Modes
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
18.6.1 Wait Mode
The TIMB remains active after the execution of a WAIT instruction. In
wait mode, the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
18.6.2 Stop Mode
The TIMB is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMB counter. TIMB operation resumes when the MCU exits stop mode.
18.7 TIMB During Break Interrupts
A break interrupt stops the TIMB counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see SIM Break Flag Control Register
on page 122).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
18.8 I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins
with the TIMB. PTD4/ATD12/TBCLK is an external clock input to the
TIMB prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and
PTF5/TBCH1.
18.8.1 TIMB Clock Pin (PTD4/ATD12/TBCLK)
PTD4/ATD12/TBCLK is an external clock input that can be the clock
source for the TIMB counter instead of the prescaled internal bus clock.
Select the PTD4/ATD12/TBCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see TIMB Status and Control Register).
The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD4/ATD12/TBCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMB clock input. When the
PTD4/ATD12/TBCLK pin is the TIMB clock input, it is an input regardless
of the state of the DDRD4 bit in data direction register D.
18.8.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTF4/TBCH0 and PTF5/TBCH1
can be configured as buffered output compare or buffered PWM pins.
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MOTOROLA
Timer Interface Module B (TIMB)
I/O Registers
18.9 I/O Registers
These I/O registers control and monitor TIMB operation:
•
•
•
•
•
TIMB status and control register (TBSC)
TIMB control registers (TBCNTH–TBCNTL)
TIMB counter modulo registers (TBMODH–TBMODL)
TIMB channel status and control registers (TBSC0 and TBSC1)
TIMB channel registers (TBCH0H–TBCH0L, TBCH1H–TBCH1L)
18.9.1 TIMB Status and Control Register
The TIMB status and control register:
•
•
•
•
•
Enables TIMB overflow interrupts
Flags TIMB overflows
Stops the TIMB counter
Resets the TIMB counter
Prescales the TIMB counter clock
Address: $0040
Bit 7
6
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TOF
0
TOIE
TRST
0
R
0
0
0
R
=Reserved
Figure 18-4. TIMB Status and Control Register (TBSC)
TOF — TIMB Overflow Flag Bit
This read/write flag is set when the TIMB counter reaches the modulo
value programmed in the TIMB counter modulo registers. Clear TOF
by reading the TIMB status and control register when TOF is set and
then writing a logic 0 to TOF. If another TIMB overflow occurs before
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281
Timer Interface Module B (TIMB)
the clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIMB counter has reached modulo value
0 = TIMB counter has not reached modulo value
TOIE — TIMB Overflow Interrupt Enable Bit
This read/write bit enables TIMB overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMB overflow interrupts enabled
0 = TIMB overflow interrupts disabled
TSTOP — TIMB Stop Bit
This read/write bit stops the TIMB counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB
counter until software clears the TSTOP bit.
1 = TIMB counter stopped
0 = TIMB counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMB is
required to exit wait mode. Also, when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until TSTOP is cleared.
TRST — TIMB Reset Bit
Setting this write-only bit resets the TIMB counter and the TIMB
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMB counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMB counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMB
counter at a value of $0000.
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MOTOROLA
Timer Interface Module B (TIMB)
I/O Registers
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD4/ATD12/TBCLK pin or
one of the seven prescaler outputs as the input to the TIMB counter
as Table 18-1 shows. Reset clears the PS[2:0] bits.
Table 18-1. Prescaler Selection
PS[2:0]
000
001
010
011
TIMB Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD4/ATD12/TBCLK
100
101
110
111
18.9.2 TIMB Counter Registers
The two read-only TIMB counter registers contain the high and low bytes
of the value in the TIMB counter. Reading the high byte (TBCNTH)
latches the contents of the low byte (TBCNTL) into a buffer. Subsequent
reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL
is read. Reset clears the TIMB counter registers. Setting the TIMB reset
bit (TRST) also clears the TIMB counter registers.
NOTE: If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL
by reading TBCNTL before exiting the break interrupt. Otherwise,
TBCNTL retains the value latched during the break.
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
Register Name and Address TBCNTH — $0041
Bit 7
6
BIT 14
R
5
BIT 13
R
4
BIT 12
R
3
BIT 11
R
2
BIT 10
R
1
BIT 9
R
Bit 0
BIT 8
R
Read: BIT 15
Write:
R
0
Reset:
0
0
0
0
0
0
0
Register Name and Address TBCNTL — $0042
Bit 7
6
BIT 6
R
5
BIT 5
R
4
BIT 4
R
3
BIT 3
R
2
BIT 2
R
1
BIT 1
R
Bit 0
BIT 0
R
Read: BIT 7
Write:
R
0
Reset:
0
0
0
0
0
0
0
R
R =Reserved
Figure 18-5. TIMB Counter Registers (TBCNTH and TBCNTL)
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MOTOROLA
Timer Interface Module B (TIMB)
I/O Registers
18.9.3 TIMB Counter Modulo Registers
The read/write TIMB modulo registers contain the modulo value for the
TIMB counter. When the TIMB counter reaches the modulo value, the
overflow flag (TOF) becomes set and the TIMB counter resumes
counting from $0000 at the next timer clock. Writing to the high byte
(TBMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TBMODL) is written. Reset sets the TIMB counter modulo registers.
Register Name and Address TBMODH — $0043
Bit 7
BIT 15
1
6
BIT 14
1
5
BIT 13
1
4
BIT 12
1
3
BIT 11
1
2
BIT 10
1
1
BIT 9
1
Bit 0
BIT 8
1
Read:
Write:
Reset:
Register Name and Address TBMODL — $0044
Bit 7
BIT 7
1
6
BIT 6
1
5
BIT 5
1
4
BIT 4
1
3
BIT 3
1
2
BIT 2
1
1
BIT 1
1
Bit 0
BIT 0
1
Read:
Write:
Reset:
Figure 18-6. TIMB Counter Modulo Registers (TBMODH and
TBMODL)
NOTE: Reset the TIMB counter before writing to the TIMB counter modulo
registers.
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
18.9.4 TIMB Channel Status and Control Registers
Each of the TIMB channel status and control registers:
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare or PWM operation
Selects high, low or toggling output on output compare
Selects rising edge, falling edge or any edge as the active input
capture trigger
•
•
•
Selects output toggling on TIMB overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TBSC0 — $0045
Bit 7
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read: CH0F
Write:
0
0
Reset:
Register Name and Address TBSC1 — $0048
Bit 7
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
CH1IE
Write:
0
0
R
0
Reset:
0
R
R =Reserved
Figure 18-7. TIMB Channel Status and Control Registers
(TBSC0–TBSC1)
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Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
I/O Registers
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMB
counter registers matches the value in the TIMB channel x registers.
When CHxIE = 1, clear CHxF by reading TIMB channel x status and
control register with CHxF set, and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMB channel 0.
Setting MS0B disables the channel 1 status and control register and
reverts TBCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908AS32A — Rev 0.0
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Advance Information
287
Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation (see Table
18-2).
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TBCHx pin once PWM, input capture or output compare
operation is enabled (see Table 18-2). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMB status and control register
(TBSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port F and pin PTFx/TBCHx is available as a general-purpose I/O
pin. However, channel x is at a state determined by these bits and
becomes transparent to the respective pin when PWM, input capture,
or output compare mode is enabled. Table 18-2 shows how ELSxB
and ELSxA work. Reset clears the ELSxB and ELSxA bits.
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MC68HC908AS32A — Rev 0.0
Timer Interface Module B (TIMB)
MOTOROLA
Timer Interface Module B (TIMB)
I/O Registers
Table 18-2. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under Port Control;
Initialize Timer
Output Level High
X0
X1
00
00
Output
Preset
Pin under Port Control;
Initialize Timer
Output Level Low
00
00
00
01
01
01
1X
1X
01
10
11
01
10
11
01
10
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compare
orBuffered
PWM
Toggle Output on Compare
Clear Output on Compare
1X
11
Set Output on Compare
NOTE: Before enabling a TIMB channel register for input capture operation,
make sure that the PTFx/TBCHx pin is stable for at least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMB counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMB counter overflow.
0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE: When TOVx is set, a TIMB counter overflow takes precedence over a
channel x output compare if both occur at the same time.
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Advance Information
289
Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 18-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-8. CHxMAX Latency
18.9.5 TIMB Channel Registers
These read/write registers contain the captured TIMB counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMB channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the
TIMB channel x registers (TBCHxH) inhibits input captures until the low
byte (TBCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of
the TIMB channel x registers (TBCHxH) inhibits output compares and
the CHxF bit until the low byte (TBCHxL) is written.
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Timer Interface Module B (TIMB)
MOTOROLA
Timer Interface Module B (TIMB)
I/O Registers
Register Name and Address TBCH0H — $0046
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TBCH0L — $0047
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TBCH1H — $0049
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TBCH1L — $004A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 18-9. TIMB Channel Registers (TBCH0H/L–TBCH1H/L)
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Timer Interface Module B (TIMB)
291
Timer Interface Module B (TIMB)
Advance Information
MC68HC908AS32A — Rev 0.0
292
Timer Interface Module B (TIMB)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 19. Programmable Interrupt Timer (PIT)
19.1 Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
19.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .294
19.5 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
19.7 PIT During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .297
19.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297
19.8.1 PIT Status and Control Register . . . . . . . . . . . . . . . . . . .297
19.8.2 PIT Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .300
19.8.3 PIT Counter Modulo Registers . . . . . . . . . . . . . . . . . . . .301
19.2 Introduction
This section describes the Programmable Interrupt Timer (PIT) which is
a periodic interrupt timer whose counter is clocked internally via software
programmable options. Figure 19-1 is a block diagram of the PIT.
For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.
MC68HC908AS32A — Rev 0.0
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293
MOTOROLA
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
19.3 Features
Features of the PIT include:
•
•
•
Programmable PIT Clock Input
Free-Running or Modulo Up-Count Operation
PIT Counter Stop and Reset Bits
19.4 Functional Description
Figure 19-1 shows the structure of the PIT. The central component of
the PIT is the 16-bit PIT counter that can operate as a free-running
counter or a modulo up-counter. The counter provides the timing
reference for the interrupt. The PIT counter modulo registers,
PMODH–PMODL, control the modulo value of the counter. Software can
read the counter value at any time without affecting the counting
sequence.
PRESCALER SELECT
PRESCALER
INTERNAL
BUS CLOCK
CSTOP
CRST
PPS2
PPS1
PPS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
POF
POIE
16-BIT COMPARATOR
TIMPMODH:TIMPMODL
Figure 19-1. PIT Block Diagram
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Programmable Interrupt Timer (PIT)
MOTOROLA
Programmable Interrupt Timer (PIT)
Functional Description
Register Name
Bit 7
6
5
4
0
3
2
1
Bit 0
Read: POF
0
POIE
PSTOP
PPS2
PPS1
PPS0
PIT Status and Control Register
(PSC)
Write:
0
0
PRST
0
Reset:
0
1
0
0
0
9
0
Read: Bit 15
Write:
14
13
12
11
10
Bit 8
PIT Counter Register High
(PCNTH)
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 7
Bit 0
PIT Counter Register Low
(PCNTL)
0
Bit 15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
1
0
9
1
1
1
0
Bit 8
1
PIT Counter Modulo Register High
(PMODH)
Bit 7
1
6
5
4
3
2
Bit 0
1
PIT Counter Modulo Register Low
(PMODL)
1
1
1
1
1
=Unimplemented
Figure 19-2. PIT I/O Register Summary
Table 19-1. PIT I/O Register Address Summary
Register
PSC
PCNTH PCNTL PMODH PMODL
$004C $004D $004E $004F
Address $004B
MC68HC908AS32A — Rev 0.0
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295
MOTOROLA
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
19.5 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PPS[2:0], in the status and control register select
the PIT clock source.
The value in the PIT counter modulo registers and the selected prescaler
output determines the frequency of the periodic interrupt. The PIT
overflow flag (POF) is set when the PIT counter value reaches the
modulo value programmed in the PIT counter modulo registers. The PIT
interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests.
POF and POIE are in the PIT status and control register.
19.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
19.6.1 Wait Mode
The PIT remains active after the execution of a WAIT instruction. In wait
mode the PIT registers are not accessible by the CPU. Any enabled CPU
interrupt request from the PIT can bring the MCU out of wait mode.
If PIT functions are not required during wait mode, reduce power
consumption by stopping the PIT before executing the WAIT instruction.
19.6.2 Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the PIT
counter. PIT operation resumes when the MCU exits stop mode after an
external interrupt.
Advance Information
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Programmable Interrupt Timer (PIT)
MOTOROLA
Programmable Interrupt Timer (PIT)
PIT During Break Interrupts
19.7 PIT During Break Interrupts
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see SIM Break Flag Control Register
on page 122).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
19.8 I/O Registers
The following I/O registers control and monitor operation of the PIT:
•
•
•
PIT status and control register (PSC)
PIT counter registers (PCNTH–PCNTL)
PIT counter modulo registers (PMODH–PMODL)
19.8.1 PIT Status and Control Register
The PIT status and control register:
•
•
•
Enables PIT interrupt
Flags PIT overflows
Stops the PIT counter
MC68HC908AS32A — Rev 0.0
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297
MOTOROLA
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
•
•
Resets the PIT counter
Prescales the PIT counter clock
Address: $004B
Bit 7
6
POIE
0
5
PSTOP
1
4
0
3
0
2
PPS2
0
1
PPS1
0
Bit 0
PPS0
0
Read:
Write:
Reset:
POF
0
PRST
0
0
0
= Unimplemented
Figure 19-3. PIT Status and Control Register (PSC)
POF — PIT Overflow Flag Bit
This read/write flag is set when the PIT counter reaches the modulo
value programmed in the PIT counter modulo registers. Clear POF by
reading the PIT status and control register when POF is set and then
writing a logic 0 to POF. If another PIT overflow occurs before the
clearing sequence is complete, then writing logic 0 to POF has no
effect. Therefore, a POF interrupt request cannot be lost due to
inadvertent clearing of POF. Reset clears the POF bit. Writing a logic
1 to POF has no effect.
1 = PIT counter has reached modulo value
0 = PIT counter has not reached modulo value
POIE — PIT Overflow Interrupt Enable Bit
This read/write bit enables PIT overflow interrupts when the POF bit
becomes set. Reset clears the POIE bit.
1 = PIT overflow interrupts enabled
0 = PIT overflow interrupts disabled
PSTOP — PIT Stop Bit
This read/write bit stops the PIT counter. Counting resumes when
PSTOP is cleared. Reset sets the PSTOP bit, stopping the PIT
counter until software clears the PSTOP bit.
1 = PIT counter stopped
0 = PIT counter active
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Programmable Interrupt Timer (PIT)
MOTOROLA
Programmable Interrupt Timer (PIT)
I/O Registers
NOTE: Do not set the PSTOP bit before entering wait mode if the PIT is required
to exit wait mode.
PRST — PIT Reset Bit
Setting this write-only bit resets the PIT counter and the PIT prescaler.
Setting PRST has no effect on any other registers. Counting resumes
from $0000. PRST is cleared automatically after the PIT counter is
reset and always reads as logic zero. Reset clears the PRST bit.
1 = Prescaler and PIT counter cleared
0 = No effect
NOTE: Setting the PSTOP and PRST bits simultaneously stops the PIT counter
at a value of $0000.
PPS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the PIT counter as Table 19-2 shows. Reset clears the
PPS[2:0] bits.
Table 19-2. Prescaler Selection
PPS[2:0]
000
PIT Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Internal Bus Clock ÷ 64
001
010
011
100
101
110
111
MC68HC908AS32A — Rev 0.0
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299
MOTOROLA
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
19.8.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes
of the value in the PIT counter. Reading the high byte (PCNTH) latches
the contents of the low byte (PCNTL) into a buffer. Subsequent reads of
PCNTH do not affect the latched PCNTL value until PCNTL is read.
Reset clears the PIT counter registers. Setting the PIT reset bit (PRST)
also clears the PIT counter registers.
NOTE: If you read PCNTH during a break interrupt, be sure to unlatch PCNTL
by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL
retains the value latched during the break.
Address: $004C
Bit 7
Read: Bit 15
Write:
6
5
4
3
2
1
9
Bit 0
Bit 8
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
Address: $004D
Bit 7
6
5
4
3
2
1
9
Bit 0
Bit 8
Read: Bit 15
Write:
14
13
12
11
10
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-4. PIT Counter Registers (PCNTH–PCNTL)
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Programmable Interrupt Timer (PIT)
MOTOROLA
Programmable Interrupt Timer (PIT)
I/O Registers
19.8.3 PIT Counter Modulo Registers
The read/write PIT modulo registers contain the modulo value for the PIT
counter. When the PIT counter reaches the modulo value the overflow
flag (POF) becomes set and the PIT counter resumes counting from
$0000 at the next timer clock. Writing to the high byte (PMODH) inhibits
the POF bit and overflow interrupts until the low byte (PMODL) is written.
Reset sets the PIT counter modulo registers.
Address: $004E:$004F
Bit 7
Bit 15
1
6
14
1
5
13
1
4
12
1
3
11
1
2
10
1
1
9
1
Bit 0
Bit 8
1
Read:
Write:
Reset:
Address: $004E:$004F
Bit 7
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
Bit 0
Bit 0
1
Read:
Bit 7
Write:
Reset:
1
Figure 19-5. PIT Counter Modulo Registers (PMODH–PMODL)
NOTE: Reset the PIT counter before writing to the PIT counter modulo registers.
MC68HC908AS32A — Rev 0.0
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301
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
Advance Information
MC68HC908AS32A — Rev 0.0
302
Programmable Interrupt Timer (PIT)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 20. Input/Output Ports
20.1 Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
20.3 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .305
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . .305
20.4 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . .308
20.5 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . .311
20.6 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . .314
20.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Port E Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . .318
20.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
Port F Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . .321
MC68HC908AS32A — Rev 0.0
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Advance Information
303
Input/Output Ports
Input/Output Ports
20.2 Introduction
On the52-pin MC68HC908AS60A, forty bidirectional input/output (I/O)
form six parallel ports. All I/O pins are programmable as inputs or
outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Figure 20-1. I/O Port Register Summary
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000C
$000D
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PTA0
PTB0
PTC0
PTD0
Port A Data Register (PTA) PTA7
Port B Data Register (PTB) PTB7
PTA6
PTB6
0
PTA5
PTB5
0
PTA4
PTB4
PTC4
PTD4
PTA3
PTB3
PTC3
PTD3
PTA2
PTB2
PTC2
PTD2
PTA1
PTB1
PTC1
PTD1
Port C Data Register (PTC)
Port D Data Register (PTD)
0
0
PTD6
PTD5
Data Direction Register A (DDRA) DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Data Direction Register B (DDRB) DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Data Direction Register C (DDRC) MCLKEN
Data Direction Register D (DDRD)
Port E Data Register (PTE) PTE7
Port F Data Register (PTF)
0
0
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
PTE6
0
PTE5
0
PTE4
0
PTE3
PTF3
PTE2
PTF2
PTE1
PTF1
PTE0
PTF0
0
Data Direction Register E (DDRE) DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
Data Direction Register F (DDRF)
0
0
0
0
DDRF3 DDRF2 DDRF1 DDRF0
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MOTOROLA
Input/Output Ports
Port A
20.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port.
20.3.1 Port A Data Register
The port A data register contains a data latch for each of the eight
port A pins.
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTA7
Write:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by Reset
Figure 20-2. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
20.3.2 Data Direction Register A
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
0
0
0
Figure 20-3. Data Direction Register A (DDRA)
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Input/Output Ports
Input/Output Ports
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 20-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
Figure 20-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-1 summarizes
the operation of the port A pins.
Table 20-1. Port A Pin Functions
Accesses
Accesses to PTA
DDRA
Bit
PTA
Bit
I/O Pin
Mode
to DDRA
Read/Write
DDRA[7:0]
DDRA[7:0]
Read
Pin
Write
PTA[7:0](1)
PTA[7:0]
0
X
X
Input, Hi-Z
Output
1
PTA[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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MOTOROLA
Input/Output Ports
Port B
20.4 Port B
Port B is an 8-bit special function port that shares all of its pins with the
analog-to-digital converter.
20.4.1 Port B Data Register
The port B data register contains a data latch for each of the eight port
B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTB7
Write:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by Reset
ATD4 ATD3
Alternate
ATD7
ATD6
ATD5
ATD2
ATD1
ATD0
Functions:
Figure 20-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
MC68HC908AS32A — Rev 0.0
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307
Input/Output Ports
ATD[7:0] — ADC Channels
PTB7/ATD7–PTB0/ATD0 are eight of the analog-to-digital converter
channels. The ADC channel select bits, CH[4:0], determine whether
the PTB7/ATD7–PTB0/ATD0 pins are ADC channels or general-
purpose I/O pins. If an ADC channel is selected and a read of this
corresponding bit in the port B data register occurs, the data will be 0
if the data direction for this bit is programmed as an input. Otherwise,
the data will reflect the value in the data latch. (See Analog-to-Digital
Converter (ADC) on page 361). Data direction register B (DDRB)
does not affect the data direction of port B pins that are being used by
the ADC. However, the DDRB bits always determine whether reading
port B returns to the states of the latches or logic 0.
20.4.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
0
0
0
Figure 20-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 20-7 shows the port B I/O logic.
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MOTOROLA
Input/Output Ports
Port B
READ DDRB ($0005)
WRITE DDRB ($0005)
DDRBx
PTBx
RESET
WRITE PTB ($0001)
READ PTB ($0001)
PTBx
Figure 20-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx
data latch. When bit DDRBx is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-2 summarizes
the operation of the port B pins.
Table 20-2. Port B Pin Functions
Accesses
Accesses to PTB
DDRB
Bit
PTB
Bit
I/O Pin
Mode
to DDRB
Read/Write
DDRB[7:0]
DDRB[7:0]
Read
Pin
Write
PTB[7:0](1)
PTB[7:0]
0
X
X
Input, Hi-Z
Output
1
PTB[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AS32A — Rev 0.0
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Input/Output Ports
Input/Output Ports
20.5 Port C
Port C is an 5-bit general-purpose bidirectional I/O port.
20.5.1 Port C Data Register
The port C data register contains a data latch for each of the five port C
pins.
Address: $0002
Bit 7
6
0
5
0
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
PTC4
PTC3
PTC2
PTC1
PTC0
R
R
R
Unaffected by Reset
R
=Reserved
Alternate
Functions:
MCLK
Figure 20-8. Port C Data Register (PTC)
PTC[4:0] — Port C Data Bits
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data (4:0).
MCLK — System Clock Bit
The system clock is driven out of PTC2 when enabled by MCLKEN bit
in PTCDDR7.
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MOTOROLA
Input/Output Ports
Port C
20.5.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for
the corresponding port C pin; a logic 0 disables the output buffer.
Address: $0006
Bit 7
6
5
0
4
3
2
1
Bit 0
Read:
Write:
Reset:
0
MCLKEN
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
R
R
0
0
0
0
0
0
0
0
R
=Reserved
Figure 20-9. Data Direction Register C (DDRC)
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, DDRC2 has no effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[4:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE: Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 20-10 shows the port C I/O logic.
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Input/Output Ports
Input/Output Ports
READ DDRC ($0006)
WRITE DDRC ($0006)
DDRCx
PTCx
RESET
WRITE PTC ($0002)
READ PTC ($0002)
PTCx
Figure 20-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx
data latch. When bit DDRCx is a logic 0, reading address $0002 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-3 summarizes
the operation of the port C pins.
Table 20-3. Port C Pin Functions
Accesses
Accesses to PTC
Bit
Value
PTC
Bit
I/O Pin
Mode
to DDRC
Read/Write
DDRC[2]
Read
Pin
Write
PTC2
—
0
2
2
Input, Hi-Z
Output
1
DDRC[2]
0
PTC[4:0](1)
PTC[4:0]
0
X
X
Input, Hi-Z
Output
DDRC[4:0]
DDRC[4:0]
Pin
1
PTC[4:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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MOTOROLA
Input/Output Ports
Port D
20.6 Port D
Port D is an 7-bit general-purpose I/O port.
20.6.1 Port D Data Register
Port D is a 7-bit special function port that shares seven of its pins with
the analog to digital converter and two with the timer interface
modules.
Address: $0003
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
R
Unaffected by Reset
Alternate
Functions:
ATD14/
TACLK
ATD12/
ATD11
TBCLK
R
ATD13
ATD10
ATD9
ATD8
Figure 20-11. Port D Data Register (PTD)
PTD[6:0] — Port D Data Bits
PTD[6:0] are read/write, software programmable bits. Data direction
of PTD[6:0] pins are under the control of the corresponding bit in data
direction register D.
ATD[14:8] — ADC Channel Status Bits
PTD6/ATD14/TACLK–PTD0/ATD8 are seven of the 15 analog-to-
digital converter channels. The ADC channel select bits, CH[4:0],
determine whether the PTD6/ATD14/TACLK–PTD0/ATD8 pins are
ADC channels or general-purpose I/O pins. If an ADC channel is
selected and a read of this corresponding bit in the port B data register
occurs, the data will be 0 if the data direction for this bit is
programmed as an input. Otherwise, the data will reflect the value in
the data latch. (See Analog-to-Digital Converter (ADC) on page 361).
Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the TIMA. However, the DDRD bits
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Input/Output Ports
Input/Output Ports
always determine whether reading port D returns the states of the
latches or logic 0.
TACLK/TBCLK — Timer Clock Input Bit
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA.
The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK as the
TIM clock input. (See TIMA Channel Status and Control Registers
on page 352). When not selected as the TIM clock,
PTD6/ATD14/TACLK is available for general-purpose I/O. While
TACLK is selected corresponding DDRD bits have no effect.
20.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
R
0
0
0
0
0
0
0
0
Figure 20-12. Data Direction Register D (DDRD)
DDRD[6:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[6:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 20-13 shows the port D I/O logic.
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MOTOROLA
Input/Output Ports
Port D
READ DDRD ($0007)
WRITE DDRD ($0007)
DDRDx
PTDx
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
Figure 20-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-4 summarizes
the operation of the port D pins.
Table 20-4. Port D Pin Functions
Accesses to
Accesses to PTD
DDRD PTD
I/O Pin
Mode
DDRD
Bit
Bit
Read/Write
DDRD[6:0]
DDRD[6:0]
Read
Write
PTD[6:0](1)
PTD[6:0]
0
1
X
X
Input, Hi-Z
Output
Pin
PTD[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AS32A — Rev 0.0
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Input/Output Ports
20.7 Port E
Port E is an 8-bit special function port that shares two of its pins with the
timer interface module (TIMA), two of its pins with the serial
communications interface module (SCI), and four of its pins with the
serial peripheral interface module (SPI).
20.7.1 Port E Data Register
The port E data register contains a data latch for each of the eight port
E pins.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTE7
Write:
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Reset:
Unaffected by Reset
SS TACH1
Alternate
SPSCK
MOSI
MISO
TACH0
RxD
TxD
Function:
Figure 20-14. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction
of each port E pin is under the control of the corresponding bit in data
direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module
and serial clock output of an SPI master module. When the SPE bit is
clear, the PTE7/SPSCK pin is available for general-purpose I/O. (See
SPI Control Register on page 260).
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTE6/MOSI pin is available for
general-purpose I/O.
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MOTOROLA
Input/Output Ports
Port E
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See SPI Control Register on page 260).
SS — Slave Select Bit
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See SS (Slave Select) on page 258). When the SPI is enabled
as a slave, the DDRF0 bit in data direction register E (DDRE) has no
effect on the PTE4/SS pin.
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 20-5).
TACH[1:0] — Timer Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIM input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. (See
TIMA Channel Status and Control Registers on page 352).
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIM. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 20-5).
RxD — SCI Receive Data Input Bit
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See SCI
Control Register 1 on page 217).
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Input/Output Ports
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See SCI
Control Register 1 on page 217).
NOTE: Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See Table 20-5).
20.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
0
0
0
0
Figure 20-15. Data Direction Register E (DDRE)
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 20-16 shows the port E I/O logic.
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MOTOROLA
Input/Output Ports
Port E
READ DDRE ($000C)
WRITE DDRE ($000C)
DDREx
PTEx
RESET
WRITE PTE ($0008)
READ PTE ($0008)
PTEx
Figure 20-16. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx
data latch. When bit DDREx is a logic 0, reading address $0008 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-5 summarizes
the operation of the port E pins.
Table 20-5. Port E Pin Functions
Accesses
Accesses to PTE
DDRE
Bit
PTE
Bit
I/O Pin
Mode
to DDRE
Read/Write
DDRE[7:0]
DDRE[7:0]
Read
Pin
Write
PTE[7:0](1)
PTE[7:0]
0
X
X
Input, Hi-Z
Output
1
PTE[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Input/Output Ports
20.8 Port F
Port F is a 4-bit special function port that shares four of its pins with the
timer interface module (TIMA-6).
20.8.1 Port F Data Register
The port F data register contains a data latch for each of the four port F
pins.
Address: $0009
Bit 7
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
PTF3
PTF2
PTF1
PTF0
R
R
R
R
Unaffected by Reset
TACH5
Alternate
Function:
TACH4
TACH3
TACH2
R
=Reserved
Figure 20-17. Port F Data Register (PTF)
PTF[3:0] — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PTF[3:0].
TACH[5:2] — Timer A Channel I/O Bits
The PTF3–PTF0/TACH2 pins are the TIM input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTF3–PTF0/TACH2 pins are timer channel I/O pins or
general-purpose I/O pins. (See TIMA Status and Control Register
on page 347).
NOTE: Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the TIM. However, the DDRF bits always
determine whether reading port F returns the states of the latches or the
states of the pins. (See Table 20-6).
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MOTOROLA
Input/Output Ports
Port F
20.8.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
Address: $000D
Bit 7
0
6
5
0
4
0
3
DDRF3
0
2
DDRF2
0
1
DDRF1
0
Bit 0
DDRF0
0
Read:
Write:
Reset:
0
R
R
R
0
R
0
0
0
R
=Reserved
Figure 20-18. Data Direction Register F (DDRF)
DDRF[3:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears
DDRF[3:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 20-19 shows the port F I/O logic.
READ DDRF ($000D)
WRITE DDRF ($000D)
DDRFx
RESET
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 20-19. Port F I/O Circuit
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Input/Output Ports
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx
data latch. When bit DDRFx is a logic 0, reading address $0009 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 20-6 summarizes
the operation of the port F pins.
Table 20-6. Port F Pin Functions
Accesses
Accesses to PTF
DDRF
Bit
PTF
Bit
I/O Pin
Mode
to DDRF
Read/Write
DDRF[3:0]
DDRF[3:0]
Read
Pin
Write
PTF[3:0](1)
PTF[3:0]
0
X
X
Input, Hi-Z
Output
1
PTF[3:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
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Input/Output Ports
MOTOROLA
Technical Data — MC68HC908AS32A
Section 21. Keyboard Module (KBD)
21.1 Contents
21.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
21.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
21.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
21.5 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
21.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
21.7 Keyboard Module During Break Interrupts . . . . . . . . . . . .328
21.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
21.8.1 Keyboard Status and Control Register . . . . . . . . . . . . .329
21.8.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . .330
21.2 Introduction
The keyboard interrupt module (KBD) provides five independently
maskable external interrupt pins.
This module is only available on 64-pin package options.
MC68HC908AS32A — Rev 0.0
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Keyboard Module (KBD)
Keyboard Module (KBD)
21.3 Features
KBD features include:
•
Five Keyboard Interrupt Pins with Separate Keyboard Interrupt
Enable Bits and One Keyboard Interrupt Mask
•
•
•
•
Hysteresis Buffers
Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity
Automatic Interrupt Acknowledge
Exit from Low-Power Modes
21.4 Functional Description
Writing to the KBIE4–KBIE0 bits in the keyboard interrupt enable register
independently enables or disables each port G or port H pin as a
keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its
internal pullup device. A logic 0 applied to an enabled keyboard interrupt
pin latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes
low after all were high. The MODEK bit in the keyboard status and
control register controls the triggering mode of the keyboard interrupt.
•
•
If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard pin does not latch an interrupt request if another
keyboard pin is already low. To prevent losing an interrupt request
on one pin because another pin is still low, software can disable
the latter pin while it is low.
If the keyboard interrupt is falling edge- and low level-sensitive, an
interrupt request is present as long as any keyboard pin is low.
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Keyboard Module (KBD)
MOTOROLA
Keyboard Module (KBD)
Functional Description
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Keyboard Module (KBD)
Keyboard Module (KBD)
If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low level-sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:
•
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine also can prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFDE and
$FFDF.
•
Return of all enabled keyboard interrupt pins to logic 1. As long as
any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling edge-
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.
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Keyboard Module (KBD)
MOTOROLA
Keyboard Module (KBD)
Keyboard Initialization
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
21.5 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRG bits in data direction register G.
2. Configure the keyboard pins as outputs by setting the appropriate
DDRH bits in data direction register H.
3. Write logic 1s to the appropriate port G and port H data register
bits.
4. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
MC68HC908AS32A — Rev 0.0
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Advance Information
327
Keyboard Module (KBD)
Keyboard Module (KBD)
21.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
21.6.1 Wait Mode
21.6.2 Stop Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
21.7 Keyboard Module During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. See Break Module (BRK) on
page 157.
To allow software to clear the KEYF bit during a break interrupt, write a
logic 1 to the BCFE bit. If KEYF is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the KEYF bit during the break state, write a logic 0 to the
BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit
(ACKK) in the keyboard status and control register during the break state
has no effect. See Keyboard Status and Control Register on page
329.
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Keyboard Module (KBD)
MOTOROLA
Keyboard Module (KBD)
I/O Registers
21.8 I/O Registers
The following registers control and monitor operation of the keyboard
module:
•
•
Keyboard status and control register (KBSCR)
Keyboard interrupt enable register (KBIER)
21.8.1 Keyboard Status and Control Register
The keyboard status and control register:
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
Address: $001A
Bit 7
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
KEYF
0
ACKK
0
IMASKK MODEK
0
0
0
0
0
0
0
= Unimplemented
Figure 21-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending. Reset
clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
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329
Keyboard Module (KBD)
Keyboard Module (KBD)
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.
IMASKK — Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
21.8.2 Keyboard Interrupt Enable Register
The keyboard interrupt enable register enables or disables each port G
and each port H pin to operate as a keyboard interrupt pin.
Address: $001B
Bit 7
0
6
0
5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
0
0
= Unimplemented
Figure 21-4. Keyboard Interrupt Enable Register (KBIER)
KBIE4–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.
1 = PDx pin enabled as keyboard interrupt pin
0 = PDx pin not enabled as keyboard interrupt pin
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MC68HC908AS32A — Rev 0.0
Keyboard Module (KBD)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 22. Timer Interface Module A (TIMA)
22.1 Contents
22.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
22.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
22.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
22.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . .335
22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
22.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
22.4.3.1
22.4.3.2
Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . .337
Buffered Output Compare. . . . . . . . . . . . . . . . . . . . . .338
22.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .339
22.4.4.1
22.4.4.2
22.4.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . .340
Buffered PWM Signal Generation. . . . . . . . . . . . . . . .341
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
22.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
22.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
22.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .345
22.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
22.8.1 TIMA Clock Pin (PTD6/ATD14/ TACLK) . . . . . . . . . . . . .346
22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and
PTE3/TACH1–PTE2/TACH0)346
22.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
22.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . .347
22.9.2 TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . .349
22.9.3 TIMA Counter Modulo Registers. . . . . . . . . . . . . . . . . . .351
22.9.4 TIMA Channel Status and Control Registers. . . . . . . . .352
22.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . .357
MC68HC908AS32A — Rev 0.0
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331
MOTOROLA
Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
22.2 Introduction
This section describes the timer interface module (TIMA). The TIMA is a
6-channel timer that provides a timing reference with input capture,
output compare and pulse-width-modulation functions. Figure 22-1 is a
block diagram of the TIMA.
For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.
22.3 Features
Features of the TIMA include:
•
Six Input Capture/Output Compare Channels
– Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger
– Set, Clear or Toggle Output Compare Action
•
•
Buffered and Unbuffered Pulse Width Modulation (PWM) Signal
Generation
Programmable TIMA Clock Input
– 7 Frequency Internal Bus Clock Prescaler Selection
– External TIMA Clock Input (4 MHz Maximum Frequency)
Free-Running or Modulo Up-Count Operation
Toggle Any Channel Pin on Overflow
•
•
•
TIMA Counter Stop and Reset Bits
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MC68HC908AS32A — Rev 0.0
Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Features
TCLK
PTD6/ATD14/TACLK
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
INTER-
RUPT
LOGIC
TOF
TOIE
16-BIT COMPARATOR
TMODH:TMODL
ELS0B
ELS0A
ELS1A
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
TOV0
CH0MAX
PTE2
PTE2/TACH0
PTE3/TACH1
LOGIC
CH0F
MS0B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
ELS1B
ELS2B
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
TOV1
CH1MAX
PTE3
LOGIC
CH1F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
ELS2A
CHANNEL 2
16-BIT COMPARATOR
TCH2H:TCH2L
TOV2
CH2MAX
PTF0
PTF0/TACH2
PTF1/TACH3
LOGIC
CH2F
MS2B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH2IE
MS2A
ELS3B
ELS4B
ELS3A
CHANNEL 3
16-BIT COMPARATOR
TCH3H:TCH3L
TOV3
CH3MAX
PTF1
LOGIC
CH3F
INTER-
RUPT
16-BIT LATCH
LOGIC
CH3IE
MS3A
ELS4A
CHANNEL 4
16-BIT COMPARATOR
TCH4H:TCH4L
TOV4
CH5MAX
PTF2
LOGIC
PTF2/TACH4
PTF3/TACH5
CH4F
MS4B
INTER-
RUPT
LOGIC
16-BIT LATCH
CH4IE
MS4A
ELS5B
ELS5A
CHANNEL 5
16-BIT COMPARATOR
TCH5H:TCH5L
TOV5
CH5MAX
PTF3
LOGIC
CH5F
INTER-
RUPT
LOGIC
16-BIT LATCH
CH5IE
MS5A
Figure 22-1. TIMA Block Diagram
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Figure 22-2. TIMA I/O Register Summary
Addr.
$0020
$0021
$0022
$0023
Register Name
TIMA Status/Control Register (TASC) TOF
Reserved
Bit 7
6
5
4
3
0
2
PS2
R
1
PS1
R
Bit 0
PS0
R
TOIE TSTOP TRST
R
R
14
6
R
13
5
R
12
4
R
11
3
TIMA Counter Register High (TACNTH) Bit 15
TIMA Counter Register Low (TACNTL) Bit 7
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
1
$0024 TIMA Counter Modulo Reg. High (TAMODH) Bit 15
$0025 TIMA Counter Modulo Reg. Low (TAMODL) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
$0026 TIMA Ch. 0 Status/Control Register (TASC0) CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
$0027
$0028
TIMA Ch. 0 Register High (TACH0H) Bit 15
TIMA Ch. 0 Register Low (TACH0L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0029 TIMA Ch. 1 Status/Control Register (TASC1) CH1F CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
$002A
$002B
TIMA Ch. 1 Register High (TACH1H) Bit 15
TIMA Ch. 1 Register Low (TACH1L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$002C TIMA Ch. 2 Status/Control Register (TASC2) CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
$002D
$002E
TIMA Ch. 2 Register High (TACH2H) Bit 15
TIMA Ch. 2 Register Low (TACH2L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$002F TIMA Ch. 3 Status/Control Register (TASC3) CH3F CH3IE
0
MS3A ELS3B ELS3A TOV3 CH3MAX
$0030
$0031
TIMA Ch. 3 Register High (TACH3H) Bit 15
TIMA Ch. 3 Register Low (TACH3L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0032 TIMA Ch. 4 Status/Control Register (TASC4) CH4F CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX
$0033
$0034
TIMA Ch. 4 Register High (TACH4H) Bit 15
TIMA Ch. 4 Register Low (TACH4L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
$0035 TIMA Ch. 5 Status/Control Register (TASC5) CH5F CH5IE
0
MS5A ELS5B ELS5A TOV5 CH5MAX
$0036
$0037
TIMA Ch. 5 Register High (TACH5H) Bit 15
TIMA Ch. 5 Register Low (TACH5L) Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
R
=Reserved
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MC68HC908AS32A — Rev 0.0
Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Functional Description
22.4 Functional Description
Figure 22-1 shows the TIMA structure. The central component of the
TIMA is the 16-bit TIMA counter that can operate as a free-running
counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA
counter modulo registers, TAMODH–TAMODL, control the modulo
value of the TIMA counter. Software can read the TIMA counter value at
any time without affecting the counting sequence.
The six TIMA channels are programmable independently as input
capture or output compare channels.
22.4.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the
TIMA clock pin, PTD6/ATD14/TACLK. The prescaler generates seven
clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMA status and control register select the TIMA clock source.
22.4.2 Input Capture
An input capture function has three basic parts: edge select logic, an
input capture latch and a 16-bit counter. Two 8-bit registers, which make
up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector
senses a defined transition. The polarity of the active edge is
programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in
TASC0 through TASC5 control registers with x referring to the active
channel number). When an active edge occurs on the pin of an input
capture channel, the TIMA latches the contents of the TIMA counter into
the TIMA channel registers, TACHxH–TACHxL. Input captures can
generate TIMA CPU interrupt requests. Software can determine that an
input capture event has occurred by enabling input capture interrupts or
by polling the status flag bit.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
The free-running counter contents are transferred to the TIMA channel
register (TACHxH–TACHxL see TIMA Channel Registers on page 357)
on each proper signal transition regardless of whether the TIMA channel
flag (CH0F–CH5F in TASC0–TASC5 registers) is set or clear. When the
status flag is set, a CPU interrupt is generated if enabled. The value of
the count latched or “captured” is the time of the event. Because this
value is stored in the input capture register 2 bus cycles after the actual
event occurs, user software can respond to this event at a later time and
determine the actual time of the event. However, this must be done prior
to another input capture on the same pin; otherwise, the previous time
value will be lost.
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added to
this captured value and stored to an output compare register (see TIMA
Channel Registers on page 357). Because both input captures and
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the TIMA channel register
(TACHxH–TACHxL).
Advance Information
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MC68HC908AS32A — Rev 0.0
Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Functional Description
22.4.3 Output Compare
With the output compare function, the TIMA can generate a periodic
pulse with a programmable polarity, duration and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMA can set, clear or toggle the channel pin. Output compares can
generate TIMA CPU interrupt requests.
22.4.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in Output Compare on page 337. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMA channel registers.
An unsynchronized write to the TIMA channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMA overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMA may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
•
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
•
When changing to a larger output compare value, enable TIMA
overflow interrupts and write the new value in the TIMA overflow
interrupt routine. The TIMA overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
MC68HC908AS32A — Rev 0.0
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Timer Interface Module A (TIMA)
337
Timer Interface Module A (TIMA)
22.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE2/TACH0 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The output compare value in the
TIMA channel 0 registers initially controls the output on the
PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the
TIMA channel 1 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (0 or 1) that control the output are the ones written to last.
TASC0 controls and monitors the buffered output compare function and
TIMA channel 1 status and control register (TASC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a
general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered output compare
channel whose output appears on the PTF0/TACH2 pin. The TIMA
channel registers of the linked pair alternately control the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The output compare value in the
TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the
TIMA channel 3 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (2 or 3) that control the output are the ones written to last.
TASC2 controls and monitors the buffered output compare function, and
TIMA channel 3 status and control register (TASC3) is unused. While the
MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a
general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2 pin. The TIMA channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TASC4) links channel 4 and channel 5. The output compare value in the
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Functional Description
TIMA channel 4 registers initially controls the output on the PTF2 pin.
Writing to the TIMA channel 5 registers enables the TIMA channel 5
registers to synchronously control the output after the TIMA overflows.
At each subsequent overflow, the TIMA channel registers (4 or 5) that
control the output are the ones written to last. TASC4 controls and
monitors the buffered output compare function and TIMA channel 5
status and control register (TASC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
22.4.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIMA can generate a PWM signal. The value in the TIMA counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIMA counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 22-3 shows, the output compare value in the TIMA channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIMA to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIMA to set the pin if the state of the PWM
pulse is logic 0.
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
PTEx/TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-3. PWM Period and Pulse Width
The value in the TIMA counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIMA counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000 (see TIMA Status and Control Register on page 347).
The value in the TIMA channel registers determines the pulse width of
the PWM output. The pulse width of an 8-bit PWM signal is variable in
256 increments. Writing $0080 (128) to the TIMA channel registers
produces a duty cycle of 128/256 or 50%.
22.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in Pulse Width Modulation (PWM) on page 339. The pulses
are unbuffered because changing the pulse width requires writing the
new pulse width value over the value currently in the TIMA channel
registers.
An unsynchronized write to the TIMA channel registers to change a
pulse width value could cause incorrect operation for up to two PWM
periods. For example, writing a new value before the counter reaches
the old value but after the counter reaches the new value prevents any
compare during that PWM period. Also, using a TIMA overflow interrupt
routine to write a new, smaller pulse width value may cause the compare
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Functional Description
to be missed. The TIMA may pass the new value before it is written to
the TIMA channel registers.
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
•
When changing to a longer pulse width, enable TIMA overflow
interrupts and write the new value in the TIMA overflow interrupt
routine. The TIMA overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
22.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE2/TACH0 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTE2/TACH0 pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function and TIMA channel 1
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O
pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose
output appears on the PTF0/TACH2 pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The TIMA channel 2 registers
initially control the pulse width on the PTF0/TACH2 pin. Writing to the
TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (2 or
3) that control the pulse width are the ones written to last. TASC2
controls and monitors the buffered PWM function and TIMA channel 3
status and control register (TASC3) is unused. While the MS2B bit is set,
the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O
pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose
output appears on the PTF2 pin. The TIMA channel registers of the
linked pair alternately control the pulse width of the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TASC4) links channel 4 and channel 5. The TIMA channel 4 registers
initially control the pulse width on the PTF2 pin. Writing to the TIMA
channel 5 registers enables the TIMA channel 5 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (4 or
5) that control the pulse width are the ones written to last. TASC4
controls and monitors the buffered PWM function and TIMA channel 5
status and control register (TASC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Functional Description
22.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMA status and control register (TASC):
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter and prescaler by setting the TIMA
reset bit, TRST.
2. In the TIMA counter modulo registers (TAMODH–TAMODL) write
the value for the required PWM period.
3. In the TIMA channel x registers (TACHxH–TACHxL) write the
value for the required pulse width.
4. In TIMA channel x status and control register (TASCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB–MSxA (see Table 22-2).
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level (see Table 22-2).
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIMA status control register (TASC) clear the TIMA stop bit,
TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L)
initially control the buffered PWM output. TIMA status control register 0
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
(TASC0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMA channel 2 registers (TACH2H–TACH2L)
initially control the buffered PWM output. TIMA status control register 2
(TASC2) controls and monitors the PWM signal from the linked
channels. MS2B takes priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered
PWM operation. The TIMA channel 4 registers (TACH4H–TACH4L)
initially control the buffered PWM output. TIMA status control register 4
(TASC4) controls and monitors the PWM signal from the linked
channels. MS4B takes priority over MS4A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output (see TIMA Channel
Status and Control Registers on page 352).
22.5 Interrupts
The following TIMA sources can generate interrupt requests:
•
TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter reaches the modulo value programmed in the TIMA
counter modulo registers. The TIMA overflow interrupt enable bit,
TOIE, enables TIMA overflow CPU interrupt requests. TOF and
TOIE are in the TIMA status and control register.
•
TIMA channel flags (CH5F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
Low-Power Modes
22.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
22.6.1 Wait Mode
The TIMA remains active after the execution of a WAIT instruction. In
wait mode, the TIMA registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMA can bring the MCU out of
wait mode.
If TIMA functions are not required during wait mode, reduce power
consumption by stopping the TIMA before executing the WAIT
instruction.
22.6.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The
STOP instruction does not affect register conditions or the state of the
TIMA counter. TIMA operation resumes when the MCU exits stop mode.
22.7 TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see SIM Break Flag Control Register
on page 122).
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
22.8 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA and port F shares four of its pins with the TIMA.
PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler.
The six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1,
PTF0/TACH2, PTF1/TACH3, PTF2, and PTF3.
22.8.1 TIMA Clock Pin (PTD6/ATD14/
TACLK)
PTD6/ATD14/TACLK is an external clock input that can be the clock
source for the TIMA counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see TIMA Status and Control Register).
The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:
1
------------------------------------- + t SU
bus frequency
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIMA clock input. When the
PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless
of the state of the DDRD6 bit in data direction register D.
22.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TACH0, PTF0/TACH2 and
PTF2 can be configured as buffered output compare or buffered PWM
pins.
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
22.9 I/O Registers
These I/O registers control and monitor TIMA operation:
•
•
•
•
TIMA status and control register (TASC)
TIMA control registers (TACNTH–TACNTL)
TIMA counter modulo registers (TAMODH–TAMODL)
TIMA channel status and control registers (TASC0, TASC1,
TASC2, TASC3, TASC4 and TASC5)
•
TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L,
TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L and
TACH5H–TACH5L)
22.9.1 TIMA Status and Control Register
The TIMA status and control register:
•
•
•
•
•
Enables TIMA overflow interrupts
Flags TIMA overflows
Stops the TIMA counter
Resets the TIMA counter
Prescales the TIMA counter clock
Address: $0020
Bit 7
6
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TOF
0
TOIE
TRST
0
R
0
0
0
R
=Reserved
Figure 22-4. TIMA Status and Control Register (TASC)
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
TOF — TIMA Overflow Flag Bit
This read/write flag is set when the TIMA counter reaches the modulo
value programmed in the TIMA counter modulo registers. Clear TOF
by reading the TIMA status and control register when TOF is set and
then writing a logic 0 to TOF. If another TIMA overflow occurs before
the clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
TSTOP — TIMA Stop Bit
This read/write bit stops the TIMA counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA
counter until software clears the TSTOP bit.
1 = TIMA counter stopped
0 = TIMA counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIMA is
required to exit wait mode. Also, when the TSTOP bit is set and input
capture mode is enabled, input captures are inhibited until TSTOP is
cleared.
TRST — TIMA Reset Bit
Setting this write-only bit resets the TIMA counter and the TIMA
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMA counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = Prescaler and TIMA counter cleared
0 = No effect
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA
counter at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/ATD14/TACLK pin or
one of the seven prescaler outputs as the input to the TIMA counter
as Table 22-1 shows. Reset clears the PS[2:0] bits.
Table 22-1. Prescaler Selection
PS[2:0]
000
001
010
011
TIMA Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD6/ATD14/TACLK
100
101
110
111
22.9.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes
of the value in the TIMA counter. Reading the high byte (TACNTH)
latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL
is read. Reset clears the TIMA counter registers. Setting the TIMA reset
bit (TRST) also clears the TIMA counter registers.
NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL
by reading TACNTL before exiting the break interrupt. Otherwise,
TACNTL retains the value latched during the break.
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Register Name and Address TACNTH — $0022
Bit 7
6
BIT 14
R
5
BIT 13
R
4
BIT 12
R
3
BIT 11
R
2
BIT 10
R
1
BIT 9
R
Bit 0
BIT 8
R
Read: BIT 15
Write:
R
0
Reset:
0
0
0
0
0
0
0
Register Name and Address TACNTL — $0023
Bit 7
6
5
BIT 5
R
4
BIT 4
R
3
BIT 3
R
2
BIT 2
R
1
BIT 1
R
Bit 0
BIT 0
R
Read: BIT 7
BIT 6
Write:
R
0
R
Reset:
0
0
0
0
0
0
0
R
=Reserved
Figure 22-5. TIMA Counter Registers (TACNTH and TACNTL)
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
22.9.3 TIMA Counter Modulo Registers
The read/write TIMA modulo registers contain the modulo value for the
TIMA counter. When the TIMA counter reaches the modulo value, the
overflow flag (TOF) becomes set and the TIMA counter resumes
counting from $0000 at the next timer clock. Writing to the high byte
(TAMODH) inhibits the TOF bit and overflow interrupts until the low byte
(TAMODL) is written. Reset sets the TIMA counter modulo registers.
Register Name and Address TAMODH — $0024
Bit 7
BIT 15
1
6
BIT 14
1
5
BIT 13
1
4
BIT 12
1
3
BIT 11
1
2
BIT 10
1
1
BIT 9
1
Bit 0
BIT 8
1
Read:
Write:
Reset:
Register Name and Address TAMODL — $0025
Bit 7
BIT 7
1
6
BIT 6
1
5
BIT 5
1
4
BIT 4
1
3
BIT 3
1
2
BIT 2
1
1
BIT 1
1
Bit 0
BIT 0
1
Read:
Write:
Reset:
Figure 22-6. TIMA Counter Modulo Registers (TAMODH and
TAMODL)
NOTE: Reset the TIMA counter before writing to the TIMA counter modulo
registers.
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
22.9.4 TIMA Channel Status and Control Registers
Each of the TIMA channel status and control registers:
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare or PWM operation
Selects high, low or toggling output on output compare
Selects rising edge, falling edge or any edge as the active input
capture trigger
•
•
•
Selects output toggling on TIMA overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TASC0 — $0026
Bit 7
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read: CH0F
Write:
0
0
Reset:
Register Name and Address TASC1 — $0029
Bit 7
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
CH1IE
Write:
0
0
R
0
Reset:
0
R
=Reserved
Figure 22-7. TIMA Channel Status and Control Registers
(TASC0–TASC5)
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MC68HC908AS32A — Rev 0.0
MOTOROLA
Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
I/O Registers
Register Name and Address TASC2 — $002C
Bit 7
6
CH2IE
0
5
MS2B
0
4
MS2A
0
3
ELS2B
0
2
ELS2A
0
1
TOV2
0
Bit 0
CH2MAX
0
Read: CH2F
Write:
0
0
Reset:
Register Name and Address TASC3 — $002F
Bit 7
6
CH3IE
0
5
0
4
MS3A
0
3
ELS3B
0
2
ELS3A
0
1
TOV3
0
Bit 0
CH3MAX
0
Read: CH3F
Write:
0
0
R
0
Reset:
Register Name and Address TASC4 — $0032
Bit 7
6
CH4IE
0
5
MS4B
0
4
MS4A
0
3
ELS4B
0
2
ELS4A
0
1
TOV4
0
Bit 0
CH4MAX
0
Read: CH4F
Write:
0
0
Reset:
Register Name and Address TASC5 — $0035
Bit 7
6
5
0
4
MS5A
0
3
ELS5B
0
2
ELS5A
0
1
TOV5
0
Bit 0
CH5MAX
0
Read: CH5F
CH5IE
Write:
0
0
R
0
Reset:
0
R
=Reserved
Figure 22-7. TIMA Channel Status and Control Registers
(TASC0–TASC5) (Continued)
MC68HC908AS32A — Rev 0.0
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and
control register with CHxF set and then writing a logic 0 to CHxF. If
another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0, TIMA channel 2 and TIMA
channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TACH1 pin to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TACH3 pin to general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and
reverts TACH5 pin to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
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MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation. See Table
22-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TACHx pin once PWM, output compare mode or input capture
mode is enabled. See Table 22-2. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIMA status and control register
(TASC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E or port F and pin PTEx/TACHx or pin PTFx/TACHx is
available as a general-purpose I/O pin. However, channel x is at a
state determined by these bits and becomes transparent to the
respective pin when PWM, input capture mode or output compare
operation mode is enabled. Table 22-2 shows how ELSxB and
ELSxA work. Reset clears the ELSxB and ELSxA bits.
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Table 22-2. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
Pin under Port Control;
Initialize Timer
Output Level High
X0
X1
00
00
Output
Preset
Pin under Port Control;
Initialize Timer
Output Level Low
00
00
00
01
01
01
1X
1X
01
10
11
01
10
11
01
10
Capture on Rising Edge Only
Capture on Falling Edge Only
Capture on Rising or Falling Edge
Toggle Output on Compare
Input
Capture
Output
Compare Clear Output on Compare
or PWM
Set Output on Compare
Buffered
Output
Compare
orBuffered
PWM
Toggle Output on Compare
Clear Output on Compare
1X
11
Set Output on Compare
NOTE: Before enabling a TIMA channel register for input capture operation,
make sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at
least two bus clocks.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIMA counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE: When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 22-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-8. CHxMAX Latency
22.9.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares and
the CHxF bit until the low byte (TACHxL) is written.
MC68HC908AS32A — Rev 0.0
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Register Name and Address TACH0H — $0027
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH0L — $0028
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH1H — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH1L — $002B
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH2H — $002D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH5H/L) (Sheet
1 of 3)
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Timer Interface Module A (TIMA)
MOTOROLA
Timer Interface Module A (TIMA)
I/O Registers
Register Name and Address TACH2L — $002E
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH3H — $0030
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH3L — $0031
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Register Name and Address TACH4H — $0033
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH4L — $0034
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH5H/L) (Sheet
2 of 3)
MC68HC908AS32A — Rev 0.0
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Timer Interface Module A (TIMA)
Timer Interface Module A (TIMA)
Register Name and Address TACH5H — $0036
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after Reset
Register Name and Address TACH5L — $0037
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after Reset
Figure 22-9. TIMA Channel Registers (TACH0H/L–TACH5H/L) (Sheet
3 of 3)
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MOTOROLA
Technical Data — MC68HC908AS32A
Section 23. Analog-to-Digital Converter (ADC)
23.1 Contents
23.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
23.4.1 ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
23.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
23.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
23.4.4 Continuous Conversion. . . . . . . . . . . . . . . . . . . . . . . . . .365
23.4.5 Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . .365
23.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
23.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
23.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage
Reference Pin (VREFH) . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference
Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366
23.7.3 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . .366
23.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
23.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . .367
23.8.2 ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370
23.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . .370
MC68HC908AS32A — Rev 0.0
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Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
23.2 Introduction
This section describes the analog-to-digital converter (ADC-15). The
ADC is an 8-bit analog-to-digital converter.
For further information regarding analog-to-digital converters on
Motorola microcontrollers, please consult the HC08 ADC Reference
Manual, ADCRM/AD.
23.3 Features
Features of the ADC module include:
•
•
•
•
•
•
15 Channels with Multiplexed Input
Linear Successive Approximation
8-Bit Resolution
Single or Continuous Conversion
Conversion Complete Flag or Conversion Complete Interrupt
Selectable ADC Clock
23.4 Functional Description
Fifteen ADC channels are available for sampling external sources at
pins PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0.
An analog multiplexer allows the single ADC converter to select one of
15 ADC channels as ADC voltage in (ADCVIN). ADCVIN is converted by
the successive approximation register-based counters. When the
conversion is completed, ADC places the result in the ADC data register
and sets a flag or generates an interrupt. See Figure 23-1.
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Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
Functional Description
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
DISABLE
DDRBx/DDRDx
PTBx/PTDx
RESET
WRITE PTB/PTD
READ PTB/PTD
PTBx/PTDx
ADC CHANNEL x
DISABLE
ADC DATA REGISTER
CONVERSION
COMPLETE
ADC VOLTAGE IN
ADCVIN
ADCH[4:0]
INTERRUPT
LOGIC
CHANNEL
SELECT
ADC
AIEN
COCO
ADC CLOCK
CGMXCLK
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
ADICLK
Figure 23-1. ADC Block Diagram
23.4.1 ADC Port I/O Pins
PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are
general-purpose I/O pins that share with the ADC channels.
The channel select bits define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port I/O logic by forcing that
pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
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Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
NOTE: Do not use ADC channels ATD14 or ATD12 when using the
PTD6/ATD14/TACLK or PTD4/ATD12/TBCLK pins as the clock inputs
for the 16-bit Timers.
23.4.2 Voltage Conversion
When the input voltage to the ADC equals VREFH (see ADC
Characteristics on page 424), the ADC converts the signal to $FF (full
scale). If the input voltage equals VSSA, the ADC converts it to $00. Input
voltages between VREFH and VSSA are a straight-line linear conversion.
Conversion accuracy of all other input voltages is not guaranteed. Avoid
current injection on unused ADC inputs to prevent potential conversion
error.
NOTE: Input voltage should not exceed the analog supply voltages.
23.4.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control
register, $0038), and requires between 16 and 17 ADC clock cycles to
complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and
ADIV prescaler bits. For example, with a CGMXCLK frequency of 4
MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 µs and there will be between
128 bus cycles between each conversion. Sample rate is approximately
60 kHz.
Refer to ADC Characteristics on page 424.
16 to 17 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
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MOTOROLA
Analog-to-Digital Converter (ADC)
Interrupts
23.4.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled
with new data after each conversion. Data from the previous conversion
will be overwritten whether that data has been read or not. Conversions
will continue until the ADCO bit (ADC status control register, $0038) is
cleared. The COCO bit is set after the first conversion and will stay set
for the next several conversions until the next write of the ADC status
and control register or the next read of the ADC data register.
23.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See
ADC Characteristics on page 424 for accuracy information.
23.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit (ADC status control register, $0038) is at logic 0. If the
COCO bit is set, an interrupt is generated. The COCO bit is not used as
a conversion complete flag when interrupts are enabled.
23.6 Low-Power Modes
The following subsections describe the low-power modes.
23.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register before executing the WAIT instruction.
MC68HC908AS32A — Rev 0.0
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Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
23.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
23.7 I/O Signals
The ADC module has 15 channels that are shared with I/O ports B and
D. Refer to ADC Characteristics on page 424 for voltages referenced
below.
23.7.1 ADC Analog Power Pin (VDDAREF)/ADC Voltage Reference Pin (VREFH
)
The ADC analog portion uses VDDAREF as its power pin. Connect the
DDA/VDDAREF pin to the same voltage potential as VDD. External
V
filtering may be necessary to ensure clean VDDAREF for good results.
VREFH is the high reference voltage for all analog-to-digital conversions.
NOTE: Route VDDAREF carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package. VDDAREF must be
present for operation of the ADC.
23.7.2 ADC Analog Ground Pin (VSSA)/ADC Voltage Reference Low Pin (VREFL
)
The ADC analog portion uses VSSA as its ground pin. Connect the VSSA
pin to the same voltage potential as VSS.
VREFL is the lower reference supply for the ADC.
23.7.3 ADC Voltage In (ADCVIN)
ADCVIN is the input voltage signal from one of the 15 ADC channels to
the ADC module.
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MOTOROLA
Analog-to-Digital Converter (ADC)
I/O Registers
23.8 I/O Registers
These I/O registers control and monitor ADC operation:
•
•
•
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
23.8.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and
control register.
Address: $0038
Bit 7
6
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Read: COCO
AIEN
Write:
R
0
Reset:
0
R
=Reserved
Figure 23-2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects
the CPU to service the ADC interrupt request. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
or
CPU interrupt enabled (AIEN = 1)
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Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the
ADR register at the end of each conversion. Only one conversion is
allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field
which is used to select one of 15 ADC channels. Channel selection is
detailed in the following table. Care should be taken when using a port
pin as both an analog and a digital input simultaneously to prevent
switching noise from corrupting the analog signal. See Table 23-1.
The ADC subsystem is turned off when the channel select bits are all
set to one. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets these bits.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
Table 23-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD6
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MOTOROLA
Analog-to-Digital Converter (ADC)
I/O Registers
Table 23-1. Mux Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
Input Select
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
PTB7/ATD7
PTD0/ATD8/ATD8
PTD1/ATD9/ATD9
PTD2/ATD10/ATD10
PTD3/ATD11/ATD11
PTD4/ATD12/TBCLK/
ATD12
0
0
1
1
1
1
0
1
1
0
PTD5/ATD13/ATD13
PTD6/ATD14/TACLK/
ATD14
Unused (see Note 1)
Unused (see Note 1)
Reserved
Range 01111 ($0F) to 11010 ($1A)
1
1
1
1
1
1
0
1
1
1
0
0
1
0
1
Unused (see Note 1)
V
REFH
(see Note 2)
1
1
1
1
1
1
1
1
0
1
V
SSA/VREFL (see Note 2)
[ADC power off]
NOTES:
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes as specified in the
table are used to verify the operation of the ADC converter both in production
test and for user applications.
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Analog-to-Digital Converter (ADC)
23.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $0039
Bit 7
AD7
R
6
AD6
R
5
AD5
R
4
AD4
R
3
AD3
R
2
AD2
R
1
AD1
R
Bit 0
AD0
R
Read:
Write:
Reset:
Indeterminate after Reset
R
=Reserved
Figure 23-3. ADC Data Register (ADR)
23.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003A
Bit 7
6
5
ADIV0
0
4
ADICLK
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
ADIV2
ADIV1
R
0
R
0
R
0
R
0
0
0
R
=Reserved
Figure 23-4. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 23-
2 shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
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Analog-to-Digital Converter (ADC)
I/O Registers
Table 23-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
ADC Input Clock /1
ADC Input Clock / 2
ADC Input Clock / 4
ADC Input Clock / 8
ADC Input Clock / 16
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
X = don’t care
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. See ADC
Characteristics on page 424.
1 = Internal bus clock
0 = External clock (CGMXCLK)
fXCLK or Bus Frequency
1 MHz =
ADIV[2:0]
NOTE: During the conversion process, changing the ADC clock will result in an
incorrect conversion.
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Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 24. Byte Data Link Controller (BDLC)
24.1 Contents
24.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
24.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
24.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
24.4.1 BDLC Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . .377
24.4.1.1
24.4.1.2
24.4.1.3
24.4.1.4
24.4.1.5
24.4.1.6
24.4.1.7
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377
Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
BDLC Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . .379
Analog Loopback Mode. . . . . . . . . . . . . . . . . . . . . . . .379
24.5 BDLC MUX Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
24.5.1 Rx Digital Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
24.5.1.1
24.5.1.2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382
24.5.2 J1850 Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .383
24.5.3 J1850 VPW Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
24.5.4 J1850 VPW Valid/Invalid Bits and Symbols. . . . . . . . . .390
24.5.5 Message Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .394
24.6 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
24.6.1 Protocol Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . .397
24.6.2 Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . .397
24.6.3 Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . .398
24.6.4 Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . .398
24.6.5 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
24.6.5.1
24.6.5.2
24.6.5.3
24.6.5.4
4X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
Receiving a Message in Block Mode . . . . . . . . . . . . .399
Transmitting a Message in Block Mode. . . . . . . . . . .399
J1850 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
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373
Byte Data Link Controller (BDLC)
24.6.5.5
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
24.7 BDLC CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402
24.7.1 BDLC Analog and Roundtrip Delay Register. . . . . . . . .403
24.7.2 BDLC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .404
24.7.3 BDLC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .407
24.7.4 BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . .414
24.7.5 BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
24.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
24.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
24.8.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418
24.2 Introduction
The byte data link controller (BDLC) provides access to an external
serial communication multiplex bus, operating according to the Society
of Automotive Engineers (SAE) J1850 protocol.
The BDLC-D is only available on the MC68HC908AS60A.
24.3 Features
Features of the BDLC module include:
•
SAE J1850 class B data communications network interface
compatible and ISO compatible for low speed (<125 kbps) serial
data communications in automotive applications
•
•
•
•
10.4 kbps variable pulse width (VPW) bit format
Digital noise filter
Collision detection
Hardware cyclical redundancy check (CRC) generation and
checking
•
•
Two power-saving modes with automatic wakeup on network
activity
Polling and CPU interrupts available
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Byte Data Link Controller (BDLC)
MOTOROLA
Byte Data Link Controller (BDLC)
Functional Description
•
•
•
•
•
Block mode receive and transmit supported
Supports 4X receive mode, 41.6 kbps
Digital loopback mode
Analog loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
24.4 Functional Description
Figure 24-1 shows the organization of the BDLC module. The CPU
interface contains the software addressable registers and provides the
link between the CPU and the buffers. The buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The
protocol handler is responsible for the encoding and decoding of data
bits and special message symbols during transmission and reception.
The MUX interface provides the link between the BDLC digital section
and the analog physical interface. The wave shaping, driving, and
digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
specification.
NOTE: It is recommended that the reader be familiar with the SAE J1850
document and ISO Serial Communication document prior to proceeding
with this section of the MC68HC908AS32A specification.
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 24-1. BDLC Block Diagram
Table 24-1. BDLC I/O Register Summary
Addr.
Name
Bit 7
6
5
0
4
0
3
2
1
Bit 0
Read:
Write:
BDLC Analog and Rou5ndtrip
Delay Register (BARD)
$003B
ATE
RXPOL
BO3
BO2
BO1
BO0
R
R
Read:
Write:
0
0
BDLC Control Register 1
(BCR1)
$003C
$003D
$003E
$003F
IMSG
CLKS
R1
R0
IE
WCM
R
R
Read:
Write:
BDLC Control Register 2
(BCR2)
ALOOP DLOOP RX4XE
NBFS
TEOD
TSIFR TMIFR1 TMIFR0
Read:
Write:
0
0
I3
R
I2
R
I1
R
I0
R
0
0
BDLC State Vector Register
(BSVR)
R
R
R
R
Read:
Write:
BDLC Data Register (BDR)
BD7
R
BD6
BD5
BD4
BD3
BD2
BD1
BD0
=Reserved
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Byte Data Link Controller (BDLC)
MOTOROLA
Byte Data Link Controller (BDLC)
Functional Description
24.4.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the
power supplies, pins, and the remainder of the MCU as shown in Figure
24-2.
POWER OFF
V
DD > VDD (MINIMUM) AND
VDD ≤ VDD (MINIMUM)
ANY MCU RESET SOURCE ASSERTED
RESET
ANY MCU RESET SOURCE ASSERTED
(FROM ANY MODE)
COP, ILLADDR, PU, RESET, LVR, POR
NO MCU RESET SOURCE ASSERTED
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
RUN
BDLC STOP
BDLC WAIT
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
WAIT INSTRUCTION AND WCM = 0
Figure 24-2. BDLC Operating Modes State Diagram
24.4.1.1 Power Off Mode
This mode is entered from reset mode whenever the BDLC supply
voltage, VDD, drops below its minimum specified value for the BDLC to
guarantee operation. The BDLC will be placed in reset mode by low-
voltage reset (LVR) before being powered down. In this mode, the pin
input and output specifications are not guaranteed.
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
24.4.1.2 Reset Mode
This mode is entered from the power off mode whenever the BDLC
supply voltage, VDD, rises above its minimum specified value
(VDD –10%) and some MCU reset source is asserted. The internal MCU
reset must be asserted while powering up the BDLC or an unknown state
will be entered and correct operation cannot be guaranteed. Reset mode
is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, and reset
pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative; VDD
is supplied to the internal circuits which are held in their reset state; and
the internal BDLC system clock is running. Registers will assume their
reset condition. Outputs are held in their programmed reset state.
Therefore, inputs and network activity are ignored.
24.4.1.3 Run Mode
This mode is entered from the reset mode after all MCU reset sources
are no longer asserted. Run mode is entered from the BDLC wait mode
whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network
activity is sensed, although messages will not be received properly until
the clocks have stabilized and the CPU is in run mode also.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
24.4.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in the
BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first passive-
to-active transition of the bus generates a CPU interrupt request from the
BDLC which wakes up the BDLC and the CPU. In addition, if the BDLC
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Byte Data Link Controller (BDLC)
MOTOROLA
Byte Data Link Controller (BDLC)
Functional Description
receives a valid EOF symbol while operating in wait mode, then the
BDLC also will generate a CPU interrupt request which wakes up the
BDLC and the CPU. See Wait Mode.
24.4.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR1 register is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks. See Stop Mode.
24.4.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD)
and the receive digital input pin (BDRxD) of the digital interface are
disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own
messages without driving the J1850 bus.
24.4.1.7 Analog Loopback Mode
Analog loopback is used to determine if a bus fault has been caused by
a failure in the node’s off-chip analog transceiver or elsewhere in the
network. The BCLD analog loopback mode does not modify the digital
transmit or receive functions of the BDLC. It does, however, ensure that
once analog loopback mode is exited, the BDLC will wait for an idle bus
condition before participation in network communication resumes. If the
off-chip analog transceiver has a loopback mode, it usually causes the
input to the output drive stage to be looped back into the receiver,
allowing the node to receive messages it has transmitted without driving
the J1850 bus. In this mode, the output to the J1850 bus is typically high
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
impedance. This allows the communication path through the analog
transceiver to be tested without interfering with network activity. Using
the BDLC analog loopback mode in conjunction with the analog
transceiver’s loopback mode ensures that, once the off-chip analog
transceiver has exited loopback mode, the BCLD will not begin
communicating before a known condition exists on the J1850 bus.
24.5 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 24-3. BDLC Block Diagram
24.5.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in Figure 24-4.
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Byte Data Link Controller (BDLC)
BDLC MUX Interface
INPUT
SYNC
DATA
LATCH
4-BIT UP/DOWN COUTER
FILTERED
RX DATA
FROM
RX DATA OUT
D
Q
UP/DOWN
OUT
D
Q
PHYSICAL
INTERFACE
(BDRxD)
MUX INTERFACE
CLOCK
Figure 24-4. BDLC Rx Digital Filter Block Diagram
24.5.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see
fBDLC parameter in Table 24-4). At each positive edge of the clock
signal, the current state of the receiver physical interface (BDRxD) signal
is sampled. The BDRxD signal state is used to determine whether the
counter should increment or decrement at the next negative edge of the
clock signal.
The counter will increment if the input data sample is high but decrement
if the input sample is low. Therefore, the counter will thus progress either
up toward 15 if, on average, the BDRxD signal remains high or progress
down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the BDRxD signal is at a stable logic level
1 and the data latch is set, causing the filtered Rx data signal to become
a logic level 1. Furthermore, the counter is prevented from overflowing
and can only be decremented from this state.
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the signal.
24.5.1.2 Performance
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
For example, if the frequency of the MUX interface clock (fBDLC) is
1.0486 MHz, then the period (tBDLC) is 954 ns and the maximum filter
delay in the absence of noise will be 15.259 µs.
The effect of random noise on the BDRxD signal depends on the
characteristics of the noise itself. Narrow noise pulses on the BDRxD
signal will be ignored completely if they are shorter than the filter delay.
This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition
can be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length, will be detected by the next stage of
the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length
will be detected normally as an invalid symbol or as invalid data when
the frame’s CRC is checked.
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Byte Data Link Controller (BDLC)
BDLC MUX Interface
24.5.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the
format shown in Figure 24-5.
J1850 states that each message has a maximum length of 101 PWM bit
times or 12 VPW bytes, excluding SOF, EOD, NB, and EOF, with each
byte transmitted MSB first.
All VPW symbol lengths in the following descriptions are typical values
at a 10.4 kbps bit rate.
DATA
OPTIONAL
IFR
E
O
D
I
F
S
PRIORITY
(DATA0)
MESSAGE ID
(DATA1)
N
B
DATA
IDLE
SOF
CRC
EOF
IDLE
N
Figure 24-5. J1850 Bus Message Format (VPW)
SOF — Start-of-Frame Symbol
All messages transmitted onto the J1850 bus must begin with a long-
active 200-µs period SOF symbol. This indicates the start of a new
message transmission. The SOF symbol is not used in the CRC
calculation.
Data — In-Message Data Bytes
The data bytes contained in the message include the message
priority/type, message ID byte (typically the physical address of the
responder), and any actual data being transmitted to the receiving
node. The message format used by the BDLC is similar to the 3-byte
consolidated header message format outlined by the SAE J1850
document. See SAE J1850 — Class B Data Communications
Network Interface for more information about 1- and 3-byte headers.
Messages transmitted by the BDLC onto the J1850 bus must contain
at least one data byte and, therefore, can be as short as one data byte
and one CRC byte. Each data byte in the message is eight bits in
length and is transmitted MSB to LSB.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
CRC — Cyclical Redundancy Check Byte
This byte is used by the receiver(s) of each message to determine if
any errors have occurred during the transmission of the message.
The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus. It also performs CRC
detection on any messages it receives from the J1850 bus.
CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1.
The remainder polynomial initially is set to all ones. Each byte in the
message after the start of frame (SOF) symbol is processed serially
through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to
the message after the data bytes in MSB-to-LSB order.
When receiving a message, the BDLC uses the same divisor
polynomial. All data bytes, excluding the SOF and end of data
symbols (EOD) but including the CRC byte, are used to check the
CRC. If the message is error free, the remainder polynomial will equal
X7 + X6 + X2 = $C4, regardless of the data contained in the message.
If the calculated CRC does not equal $C4, the BDLC will recognize
this as a CRC error and set the CRC error flag in the BSVR.
EOD — End-of-Data Symbol
The EOD symbol is a long 200-µs passive period on the J1850 bus
used to signify to any recipients of a message that the transmission
by the originator has completed. No flag is set upon reception of the
EOD symbol.
IFR — In-Frame Response Bytes
The IFR section of the J1850 message format is optional. Users
desiring further definition of in-frame response should review the SAE
J1850 — Class B Data Communications Network Interface
specification.
EOF — End-of-Frame Symbol
This symbol is a long 280-µs passive period on the J1850 bus and is
longer than an end-of-data (EOD) symbol, which signifies the end of
a message. Since an EOF symbol is longer than a 200-µs EOD
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MOTOROLA
Byte Data Link Controller (BDLC)
BDLC MUX Interface
symbol, if no response is transmitted after an EOD symbol, it
becomes an EOF, and the message is assumed to be completed. The
EOF flag is set upon receiving the EOF symbol.
IFS — Inter-Frame Separation Symbol
The IFS symbol is a 20-µs passive period on the J1850 bus which
allows proper synchronization between nodes during continuous
message transmission. The IFS symbol is transmitted by a node after
the completion of the end-of-frame (EOF) period and, therefore, is
seen as a 300-µs passive period.
When the last byte of a message has been transmitted onto the J1850
bus and the EOF symbol time has expired, all nodes then must wait
for the IFS symbol time to expire before transmitting a start-of-frame
(SOF) symbol, marking the beginning of another message.
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will synchronize internally to that edge. If a write
to the BDR register (for instance, to initiate transmission) occurred on
or before 104 • tBDLC from the received rising edge, then the BDLC
will transmit and arbitrate for the bus. If a CPU write to the BDR
register occurred after 104 • tBDLC from the detection of the rising
edge, then the BDLC will not transmit, but will wait for the next IFS
period to expire before attempting to transmit the byte.
A rising edge may occur during the IFS period because of varying
clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times.
To allow for individual clock tolerances, receivers must synchronize to
any SOF occurring during an IFS period.
NOTE: If two messages are received with a 300µs (± 1µs) interframe separation
(IFS) as measured at the RX pin, the start-of-frame (SOF) symbol of the
second message will generate an invalid symbol interrupt. This interrupt
results in the second message being lost and will therefore be
unavailable to the application software. Implementations of this BDLC
design on silicon have not been exposed to interframe separation rates
faster than 320µs in practical application and have therefore previously
not exhibited this behavior. Ensuring that no nodes on the J1850
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385
Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
network transmit messages at 300µs (± 1µs) IFS will avoid this missed
message frame. In addition, developing application software to robustly
handle lost messages will minimize application impact.
BREAK — Break
The BDLC cannot transmit a BREAK symbol.
If the BDLC is transmitting at the time a BREAK is detected, it treats
the BREAK as if a transmission error had occurred and halts
transmission.
If the BDLC detects a BREAK symbol while receiving a message, it
treats the BREAK as a reception error and sets the invalid symbol flag
in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK
symbol, it treats the BREAK as a reception error, sets the invalid
symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK
symbol is received and the IFS time has elapsed, the programmer
must resend the transmission byte using highest priority.
NOTE: The J1850 protocol BREAK symbol is not related to the HC08 break
module. See Break Module (BRK) on page 157.
IDLE — Idle Bus
An idle condition exists on the bus during any passive period after
expiration of the IFS period (for instance, ≥ 300 µs). Any node sensing
an idle bus condition can begin transmission immediately.
24.5.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This
encoding technique is used to reduce the number of bus transitions for
a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
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(tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame
(EOF), and inter-frame separation (IFS) symbols always will be encoded
at an assigned level and length. See Figure 24-6.
Each message will begin with an SOF symbol an active symbol and,
therefore, each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values
at a 10.4 kbps bit rate.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period
64 µs in length, or
– A passive-to-active transition followed by an active period
128 µs in length
See Figure 24-6(a).
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Byte Data Link Controller (BDLC)
ACTIVE
128 µs
64 µs
OR
PASSIVE
(A) LOGIC 0
ACTIVE
128 µs
64 µs
OR
PASSIVE
(B) LOGIC 1
ACTIVE
≥ 240 µs
200 µs
200 µs
PASSIVE
(C) BREAK
(D) START OF FRAME
(E) END OF DATA
300 µs
ACTIVE
280 µs
20 µs
IDLE > 300 µs
PASSIVE
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 24-6. J1850 VPW Symbols with Nominal Symbol Times
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period
128 µs in length, or
– A passive-to-active transition followed by an active period
64 µs in length
See Figure 24-6(b).
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Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is
only used in IFR message responses.
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition
followed by an active period of at least 240 µs (See Figure 24-6(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by
an active period 200 µs in length (See Figure 24-6(d)). This allows
the data bytes which follow the SOF symbol to begin with a passive
bit, regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition
followed by a passive period 200 µs in length (See Figure 24-6(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed
by a passive period 280 µs in length (See Figure 24-6(f)). If no IFR
byte is transmitted after an EOD symbol is transmitted, after another
80 µs the EOD becomes an EOF, indicating completion of the
message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The
20-µs IFS symbol contains no transition, since when used it always
appends to an EOF symbol (See Figure 24-6(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
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24.5.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the
J1850 bus have been defined to allow for variations in oscillator
frequencies. In many cases the maximum time allowed to define a data
bit or symbol is equal to the minimum time allowed to define another data
bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(tBDLC), an apparent separation in these maximum time/minimum time
concurrences equal to one cycle of tBDLC occurs.
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols. This is done without reducing the
valid window for receiving bits and symbols from transmitters onto the
J1850 bus which have varying oscillator frequencies.
In Huntsinger’s’ variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the
symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See Figure 24-7(1). If the passive-to-active received transition
beginning the next data bit or symbol occurs between the active-to-
passive transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
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BDLC MUX Interface
200 µs
128 µs
64 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) INVALID PASSIVE BIT
(2) VALID PASSIVE LOGIC 0
(3) VALID PASSIVE LOGIC 1
a
a
b
b
ACTIVE
PASSIVE
ACTIVE
PASSIVE
c
(4) VALID EOD SYMBOL
d
c
Figure 24-7. J1850 VPW Received Passive Symbol Times
Valid Passive Logic 0
See Figure 24-7(2). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 24-7(3). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 24-7(4). If the passive-to-active received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid end-of-data symbol
(EOD).
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300 µs
280 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 24-8. J1850 VPW Received Passive EOF and IFS Symbol
Times
Valid EOF and IFS Symbol
In Figure 24-8(1), if the passive-to-active received transition
beginning the SOF symbol of the next message occurs between a
and b, the current symbol will be considered a valid end-of-frame
(EOF) symbol.
See Figure 24-8(2). If the passive-to-active received transition
beginning the SOF symbol of the next message occurs between c
and d, the current symbol will be considered a valid EOF symbol
followed by a valid inter-frame separation symbol (IFS). All nodes
must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node
waiting to transmit detects a passive-to-active transition once a valid
EOF has been detected, it should immediately begin transmission,
initiating the arbitration process.
Idle Bus
In Figure 24-8(2), if the passive-to-active received transition
beginning the start-of-frame (SOF) symbol of the next message does
not occur before d, the bus is considered to be idle, and any node
wishing to transmit a message may do so immediately.
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BDLC MUX Interface
200 µs
128 µs
64 µs
ACTIVE
PASSIVE
ACTIVE
(1) INVALID ACTIVE BIT
(2) VALID ACTIVE LOGIC 1
(3) VALID ACTIVE LOGIC 0
a
a
PASSIVE
ACTIVE
b
b
PASSIVE
ACTIVE
c
c
(4) VALID SOF↕SYMBOL
PASSIVE
d
Figure 24-9. J1850 VPW Received Active Symbol Times
Invalid Active Bit
In Figure 24-9(1), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between the passive-
to-active transition beginning the current data bit (or symbol) and a,
the current bit would be invalid.
Valid Active Logic 1
In Figure 24-9(2), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 1.
Valid Active Logic 0
In Figure 24-9(3), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 0.
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Valid SOF Symbol
In Figure 24-9(4), if the active-to-passive received transition
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 24-10, if the next active-to-passive received transition does
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a start-of-
frame (SOF) symbol beginning the next message to be transmitted
onto the J1850 bus. See J1850 Frame Format for BDLC response to
BREAK symbols.
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 24-10. J1850 VPW Received BREAK Symbol Times
24.5.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-
destructive manner, allowing the message with the highest priority to be
transmitted, while any transmitters which lose arbitration simply stop
transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and will continue with each bit thereafter.
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BDLC MUX Interface
The variable pulse width modulation (VPW) symbols and J1850 bus
electrical characteristics are chosen carefully so that a logic 0 (active or
passive type) will always dominate over a logic 1 (active or passive type)
that is simultaneously transmitted. Hence, logic 0s are said to be
dominant and logic 1s are said to be recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted
a recessive bit, the node loses arbitration and immediately stops
transmitting. This is known as bitwise arbitration.
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
0
0
1
1
1
1
1
1
1
ACTIVE
TRANSMITTER A
PASSIVE
0
0
0
0
ACTIVE
TRANSMITTER B
PASSIVE
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
ACTIVE
J1850 BUS
PASSIVE
DATA
BIT 2
DATA
BIT 3
DATA
BIT 4
DATA
BIT 5
DATA
BIT 1
SOF
Figure 24-11. J1850 VPW Bitwise Arbitrations
Since a logic 0 dominates a logic 1, the message with the lowest value
will have the highest priority and will always win arbitration. For instance,
a message with priority 000 will win arbitration over a message with
priority 011.
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
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another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
24.6 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 — Class B Data Communications Network
Interface.
NOTE: Motorola assumes that the reader is familiar with the J1850 specification
before this protocol handler description is read.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 24-12. BDLC Block Diagram
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BDLC Protocol Handler
24.6.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 24-13.
TO PHYSICAL INTERFACE
BDRxD
BDTxD
DLOOP FROM BCR2
LOOPBACK
LOOPBACK CONTROL
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
Rx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 24-13. BDLC Protocol Handler Outline
24.6.2 Rx and Tx Shift Registers
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register. The
Tx shift register takes data, in parallel form, from the Tx shadow register
and presents it serially to the state machine so that it can be transmitted
onto the J1850 bus.
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24.6.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set (see BDLC State Vector Register) and an interrupt is
generated if the interrupt enable bit (IE) in BCR1 is set. After the transfer
takes place, this new data byte in the Rx shadow register is available to
the CPU interface, and the Rx shift register is ready to shift in the next
byte of data. Data in the Rx shadow register must be retrieved by the
CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register is
ready to accept new data from the CPU when TDRE flag in BSVR is set.
24.6.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or
BDRxD, depending on the state of the DLOOP bit in the BCR2 register
(See BDLC Control Register 2).
24.6.5 State Machine
All of the functions associated with performing the protocol are executed
or controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
24.6.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 variable pulse width modulation
(VPW) operation. The BDLC cannot transmit in 4X mode, but can
receive messages in 4X mode, if the RX4X bit is set in BCR2 register. If
the RX4X bit is not set in the BCR2 register, any 4X message on the
J1850 bus is treated as noise by the BDLC and is ignored.
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BDLC Protocol Handler
24.6.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All of the other features of
the frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
24.6.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR register until the message is complete.
The programmer should wait until the TDRE flag (see BDLC State
Vector Register) is set prior to writing a new byte of data into the BDR
register. The BDLC does not contain any predefined maximum J1850
message length requirement.
24.6.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or
framing symbols on non-byte boundaries, this constitutes a
transmission error. When a transmission error is detected, the BDLC
immediately will cease transmitting. The error condition ($1C) is
reflected in the BSVR register (see Table 24-6). If the interrupt enable
bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is
generated.
CRC Error
A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed and the
CRC calculation result is not equal to $C4. The CRC code will detect
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any single and 2-bit errors, as well as all 8-bit burst errors and almost
all other types of errors. The CRC error flag ($18 in BSVR) is set when
a CRC error is detected. (See BDLC State Vector Register.)
Symbol Error
A symbol error is detected when an abnormal (invalid) symbol is
detected in a message being received from the J1850 bus. However,
if the BDLC is transmitting when this happens, it will be treated as a
loss of arbitration ($14 in BSVR) rather than a transmitter error. The
($1C) symbol invalid or the out-of-range flag is set when a symbol
error is detected. Therefore, ($1C) symbol invalid flag is stacked
behind the ($14) LOA flag during a transmission error process. (See
BDLC State Vector Register.)
Framing Error
A framing error is detected if an EOD or EOF symbol is detected on a
non-byte boundary from the J1850 bus. A framing error also is
detected if the BDLC is transmitting the EOD and instead receives an
active symbol. The ($1C) symbol invalid or the out-of-range flag is set
when a framing error is detected. (See BDLC State Vector
Register.)
Bus Fault
If a bus fault occurs, the response of the BDLC will depend upon the
type of bus fault.
If the bus is shorted to battery, the BDLC will wait for the bus to fall to
a passive state before it will attempt to transmit a message. As long
as the short remains, the BDLC will never attempt to transmit a
message onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin
to transmit the message, and then detect a transmission error ($1C in
BSVR), since the short to ground would not allow the bus to be driven
to the active (dominant) SOF state. The BDLC will abort that
transmission and wait for the next CPU command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is
cleared, the BDLC will resume normal operation. If the bus fault is
permanent, it may result in permanent loss of communication on the
J1850 bus. (See BDLC State Vector Register.)
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BDLC Protocol Handler
BREAK — Break
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol ($1C in BSVR) interrupt will be
generated. Reading the BSVR register (see BDLC State Vector
Register) will clear this interrupt condition. The BDLC will wait for the
bus to idle, then wait for a start-of-frame (SOF) symbol.
The BDLC cannot transmit a BREAK symbol. It can only receive a
BREAK symbol from the J1850 bus.
24.6.5.5 Summary
Table 24-2. BDLC J1850 Bus Error Summary
Error Condition
BDLC Function
For invalid bits or framing symbols on non-byte
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
Transmission Error
Cyclical Redundancy Check
(CRC) Error
CRC error interrupt will be generated. The
BDLC will wait for SOF.
Invalid Symbol: BDLC Receives
Invalid Bits (Noise)
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Invalid symbol interrupt will be generated. The
BDLC will wait for start-of-frame (SOF).
Framing Error
Bus Short to VDD
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical
interface. Fault condition is reflected in BSVR
as an invalid symbol.
Bus Short to GND
The BDLC will wait for the next valid SOF.
Invalid symbol interrupt will be generated.
BDLC Receives BREAK Symbol.
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24.7 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
•
•
•
•
•
BDLC analog and roundtrip delay register (BARD)
BDLC control register 1 (BCR1)
BDLC control register 2 (BCR2)
BDLC state vector register (BSVR)
BDLC data register (BDR)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 24-14. BDLC Block Diagram
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BDLC CPU Interface
24.7.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is16 µs.
Timing adjustments from 9 µs to 24 µs in steps of 1 µs are available. The
BARD register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Address: $003B
Bit 7
6
5
0
4
0
3
BO3
0
2
BO2
1
1
BO1
1
Bit 0
BO0
1
Read:
Write:
Reset:
ATE
RXPOL
R
0
R
0
1
1
R
=Reserved
Figure 24-15. BDLC Analog and Roundtrip Delay Register (BARD)
ATE — Analog Transceiver Enable Bit
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE: This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from the
J1850 bus; for example, the external transceiver does not
invert the receive signal
0 = Select inverted polarity, where an external transceiver inverts
the receive signal from the J1850 bus
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B03–B00 — BARD Offset Bits
Table 24-3 shows the expected transceiver delay with respect to
BARD offset values.
Table 24-3. BDLC Transceiver Delay
Corresponding Expected
BARD Offset Bits B0[3:0]
Transceiver’s Delays (µs)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
24.7.2 BDLC Control Register 1
This register is used to configure and control the BDLC.
Address: $003C
Bit 7
6
5
R1
1
4
R0
0
3
0
2
0
1
IE
0
Bit 0
WCM
0
Read:
Write:
Reset:
IMSG
CLKS
R
0
R
0
1
1
R
=Reserved
Figure 24-16. BDLC Control Register 1 (BCR1)
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IMSG — Ignore Message Bit
This bit is used to disable the receiver until a new start-of-frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked and the status bits will be held in their reset state. If
this bit is set while the BDLC is receiving a message, the rest
of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
CLKS — Clock Bit
The nominal BDLC operating frequency (fBDLC) must always be
1.048576 MHz or 1 MHz for J1850 bus communications to take place.
The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to adjust symbol timing automatically.
1 = Binary frequency (1.048576 MHz) selected for fBDLC
0 = Integer frequency (1 MHz) selected for fBDLC
R1 and R0 — Rate Select Bits
These bits determine the amount by which the frequency of the MCU
CGMXCLK signal is divided to form the MUX interface clock (fBDLC
)
which defines the basic timing resolution of the MUX interface. They
may be written only once after reset, after which they become read-
only bits.
The nominal frequency of fBDLC must always be 1.048576 MHz or 1.0
MHz for J1850 bus communications to take place. Hence, the value
programmed into these bits is dependent on the chosen MCU system
clock frequency per Table 24-4
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Byte Data Link Controller (BDLC)
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Byte Data Link Controller (BDLC)
.
Table 24-4. BDLC Rate Selection
fXCLK Frequency
fBDLC
R1
0
R0
0
Division
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
1
2
4
8
1
2
4
8
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
0
1
1
0
1
1
0
0
0
1
1
0
1
1
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See BDLC
State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode.
See Stop Mode and Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
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Byte Data Link Controller (BDLC)
BDLC CPU Interface
24.7.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
Address: $003D
Bit 7
6
5
RX4XE
0
4
NBFS
0
3
TEOD
0
2
TSIFR
0
1
Bit 0
Read:
Write:
Reset:
ALOOP DLOOP
TMIFR1 TMIFR0
1
1
0
0
Figure 24-17. BDLC Control Register 2 (BCR2)
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the off-
chip analog transceiver is placed in loopback mode. When the user
clears ALOOP, to indicate that the off-chip analog transceiver is no
longer in loopback mode, the BDLC waits for an EOF symbol before
attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is
looped back to the BDLC receiver. The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (tTRV4) before message reception or
a minimum of inter-frame symbol time (tTRV6) before message
transmission. (See BDLC Transmitter VPW Symbol
Timings.)
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Byte Data Link Controller (BDLC)
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input
(BDRxD) is connected and can be used to isolate bus fault conditions
(see Figure 24-13). If a fault condition has been detected on the bus,
this control bit allows the programmer to connect the digital transmit
output to the digital receive input. In this configuration, data sent from
the transmit buffer will be reflected back into the receive buffer. If no
faults exist in the BDLC, the fault is in the physical interface block or
elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now
in digital loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC
is taken out of digital loopback mode and can now drive the
J1850 bus normally.
RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast download of data into a J1850 node for diagnostic or
factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure
24-18.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
1 = NB that is received or transmitted is a 0 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
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Byte Data Link Controller (BDLC)
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Byte Data Link Controller (BDLC)
BDLC CPU Interface
TEOD — Transmit End of Data Bit
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an in-
frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See Rx and Tx Shadow Registers for a description of
the transmit shadow register.) Once TEOD is set, the transmit data
register empty flag (TDRE) in the BDLC state vector register (BSVR)
is cleared to allow lower priority interrupts to occur. (See BDLC State
Vector Register.)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1
at any given time. However, if more than one of these three control
bits are set to 1, the priority encoding logic will force these register bits
to a known value as shown in Table 24-5. For example, if 011 is
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
Table 24-5. BDLC Transmit In-Frame Response Control Bit
Priority Encoding
Write/Read
TSIFR
Write/Read
TMIFR1
Write/Read
TMIFR0
Actual
TSIFR
Actual
TMIFR1
Actual
TMIFR0
0
1
0
0
0
X
1
0
0
X
X
1
0
1
0
0
0
0
1
0
0
0
0
1
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
The BDLC supports the in-frame response (IFR) feature of J1850 by
setting these bits correctly. The four types of J1850 IFR are shown
below. The purpose of the in-frame response modes is to allow
multiple nodes to acknowledge receipt of the data by responding with
their personal ID or physical address in a concatenated manner after
they have seen the EOD symbol. If transmission arbitration is lost by
a node while sending its response, it continues to transmit its
ID/address until observing its unique byte in the response stream. For
VPW modulation, because the first bit of the IFR is always passive, a
normalization bit (active) must be generated by the responder and
sent prior to its ID/address byte. When there are multiple responders
on the J1850 bus, only one normalization bit is sent which assists all
other transmitting nodes to sync up their response.
HEADER
DATA FIELD
CRC
TYPE 0 — NO IFR
NB
ID
HEADER
DATA FIELD
CRC
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
NB
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
CRC
HEADER
DATA FIELD
ID1
ID N
CRC
(OPTIONAL)
HEADER
NB
IFR DATA FIELD
DATA FIELD
CRC
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier (usually the physical address of the responder(s))
HEADER = Specifies one of three frame lengths
Figure 24-18. Types of In-Frame Response (IFR)
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Byte Data Link Controller (BDLC)
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Byte Data Link Controller (BDLC)
BDLC CPU Interface
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the
BDLC data register (BDR, $003F) as a single byte IFR with no CRC.
Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See Figure 24-18.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the
EOD symbol has been received from the bus, the TSIFR bit will remain
in the reset state and no attempt will be made to transmit the IFR byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and
after the IFR byte winning arbitration completes transmission, the BDLC
will again attempt to transmit the BDR (with no normalization bit). The
BDLC will continue transmission attempts until an error is detected on
the bus, or TEOD is set, or the BDLC transmission is successful.
If loss or arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will not be sent out because the BDLC will attempt to
retransmit the byte in the transmit shift register after the IRF byte winning
arbitration completes transmission.
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC
data register (BDR) as the first byte of a multiple byte IFR with CRC
or as a single byte IFR with CRC. Response IFR bytes are still subject
to J1850 message length maximums (see J1850 Frame Format and
Figure 24-18).
If this bit is set prior to a valid EOD being received with no CRC error,
once the EOD symbol has been received the BDLC will attempt to
transmit the appropriate normalization bit followed by IFR bytes. The
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
programmer should set TEOD after the last IFR byte has been written
into the BDR register. After TEOD has been set and the last IFR byte
has been transmitted, the CRC byte is transmitted.
0 = The TMIFR1 bit will be cleared automatically – once the BDLC
has successfully transmitted the CRC byte and EOD
symbol – by the detection of an error on the multiplex bus or by
a transmitter underrun caused when the programmer does not
write another byte to the BDR after the TDRE interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see BDLC State Vector Register) will occur similar to the
main message transmit sequence. The programmer should then load
the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should
set the TEOD bit in the BDLC control register 2 (BCR2). This will
instruct the BDLC to transmit a CRC byte once the byte in the BDR is
transmitted and then transmit an EOD symbol, indicating the end of
the IFR portion of the message frame.
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the BDR
before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set
the TEOD bit in the BCR2. This will result in the byte in the BDR being
the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte
of a multiple byte IFR, the BDLC will go to the loss of arbitration state,
set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be
cleared and no attempt will be made to retransmit the byte in the BDR.
If loss of arbitration occurs in the last two bits of the IFR byte, two
additional 1 bits will be sent out.
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MOTOROLA
Byte Data Link Controller (BDLC)
BDLC CPU Interface
NOTE: The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
from going onto the J1850 bus from a corrupted message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
The TMIFR0 bit is used to request the BDLC to transmit the byte in
the BDLC data register (BDR) as the first byte of a multiple byte IFR
without CRC. Response IFR bytes are still subject to J1850 message
length maximums (see J1850 Frame Format and Figure 24-18).
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR register. After TEOD
has been set, the last IFR byte to be transmitted will be the last
byte which was written into the BDR register.
0 = The TMIFR0 bit will be cleared automatically; once the BDLC
has successfully transmitted the EOD symbol; by the detection
of an error on the multiplex bus; or by a transmitter underrun
caused when the programmer does not write another byte to
the BDR after the TDRE interrupt.
If the TMIFR0 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see BDLC State Vector Register) will occur similar to the
main message transmit sequence. The programmer should then load
the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should
set the TEOD bit in the BCR2. This will instruct the BDLC to transmit
an EOD symbol once the byte in the BDR is transmitted, indicating the
end of the IFR portion of the message frame. The BDLC will not
append a CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD
symbol has been received from the bus, the TMIFR0 bit will remain in
the reset state, and no attempt will be made to transmit an IFR byte.
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional 1 bits (active short bits) will be sent out.
NOTE: The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
from going onto the J1850 bus from a corrupted message.
24.7.4 BDLC State Vector Register
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a multiplex
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user-supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
Address: $003E
Bit 7
0
6
5
I3
R
0
4
I2
R
0
3
I1
R
0
2
I0
R
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
R
R
R
0
R
0
0
0
R
=Reserved
Figure 24-19. BDLC State Vector Register (BSVR)
I0, I1, I2, and I3 — Interrupt Source Bits
These bits indicate the source of the interrupt request that currently is
pending. The encoding of these bits are listed in Table 24-6.
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Byte Data Link Controller (BDLC)
MOTOROLA
Byte Data Link Controller (BDLC)
BDLC CPU Interface
Table 24-6. BDLC Interrupt Sources
BSVR I3 I2 I1 I0
Interrupt Source
No Interrupts Pending
Priority
$00
$04
$08
$0C
$10
$14
$18
$1C
$20
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0 (Lowest)
Received EOF
1
Received IFR Byte (RXIFR)
BDLC Rx Data Register Full (RDRF)
BDLC Tx Data Register Empty (TDRE)
Loss of Arbitration
2
3
4
5
Cyclical Redundancy Check (CRC) Error
Symbol Invalid or Out of Range
Wakeup
6
7
8 (Highest)
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR except when the
BDLC data register needs servicing (RDRF, RXIFR, or TDRE
conditions). RXIFR and RDRF can be cleared only by a read of the
BSVR followed by a read of the BDLC data register (BDR). TDRE can
either be cleared by a read of the BSVR followed by a write to the BDLC
BDR or by setting the TEOD bit in BCR2.
Upon receiving a BDLC interrupt, the user can read the value within the
BSVR, transferring it to the CPU’s index register. The value can then be
used to index into a jump table, with entries four bytes apart, to quickly
enter the appropriate service routine. For example:
Service
LDX
JMP
BSVR
Fetch State Vector Number
Enter service routine,
(must end in RTI)
JMPTAB,X
*
*
JMPTAB
JMP
NOP
JMP
NOP
JMP
NOP
SERVE0
SERVE1
SERVE2
Service condition #0
Service condition #1
Service condition #2
*
JMP
END
SERVE8
Service condition #8
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Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
NOTE: The NOPs are used only to align the JMPs onto 4-byte boundaries so
that the value in the BSVR can be used intact. Each of the service
routines must end with an RTI instruction to guarantee correct continued
operation of the device. Note also that the first entry can be omitted since
it corresponds to no interrupt occurring.
The service routines should clear all of the sources that are causing the
pending interrupts. Note that the clearing of a high priority interrupt may
still leave a lower priority interrupt pending, in which case bits I0, I1, and
I2 of the BSVR will then reflect the source of the remaining interrupt
request.
If fewer states are used or if a different software approach is taken, the
jump table can be made smaller or omitted altogether.
24.7.5 BDLC Data Register
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
D0
Read:
D7
Write:
D6
D5
D4
D3
D2
D1
Reset:
Unaffected by Reset
Figure 24-20. BDLC Data Register (BDR)
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU. Each data byte (after the first one) should be
written only after a Tx data register empty (TDRE) state is indicated in
the BSVR.
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after an Rx data
register full (RDRF) interrupt has occurred. (See BDLC State Vector
Register.)
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Byte Data Link Controller (BDLC)
Low-Power Modes
The BDR is double buffered via a transmit shadow register and a receive
shadow register. After the byte in the transmit shift register has been
transmitted, the byte currently stored in the transmit shadow register is
loaded into the transmit shift register. Once the transmit shift register has
shifted the first bit out, the TDRE flag is set, and the shadow register is
ready to accept the next data byte. The receive shadow register works
similarly. Once a complete byte has been received, the receive shift
register stores the newly received byte into the receive shadow register.
The RDRF flag is set to indicate that a new byte of data has been
received. The programmer has one BDLC byte reception time to read
the shadow register and clear the RDRF flag before the shadow register
is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop
loading data into the BDR. This will cause a transmitter underrun error
and the BDLC automatically will disable the transmitter on the next non-
byte boundary. This means that the earliest a transmission can be halted
is after at least one byte plus two extra logic 1s have been transmitted.
The receiver will pick this up as an error and relay it in the state vector
register as an invalid symbol error.
NOTE: The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
from going onto the J1850 bus from a corrupted message.
24.8 Low-Power Modes
The following information concerns wait mode and stop mode.
24.8.1 Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
MC68HC908AS32A — Rev 0.0
Advance Information
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MOTOROLA
Byte Data Link Controller (BDLC)
Byte Data Link Controller (BDLC)
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set. (See BDLC
Control Register 1 for a better understanding of IE.) This results in less
of a power saving, but the BDLC is guaranteed to receive correctly the
message which woke it up, since the BDLC internal operating clocks are
kept running.
NOTE: Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
24.8.2 Stop Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
A subsequent passive-to-active transition on the J1850 bus will cause
the BDLC to wake up and generate a non-maskable CPU interrupt
request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which
woke it up, since it may take some time for the BDLC internal operating
clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the
byte which woke it up, if and only if an end-of-frame (EOF) has been
detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
If this mode is entered while the BDLC is receiving a message, the first
subsequent received edge will cause the BDLC to wake up immediately,
generate a CPU interrupt request, and wait for the BDLC internal
operating clocks to restart and stabilize before normal communications
can resume. Therefore, the BDLC is not guaranteed to receive that
message correctly.
NOTE: It is important to ensure all transmissions are complete or aborted prior
to putting the BDLC into stop mode.
Advance Information
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Byte Data Link Controller (BDLC)
MOTOROLA
Technical Data — MC68HC908AS32A
Section 25. Electrical Specification
25.1 Contents
25.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .420
25.2.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
25.2.2 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . .421
25.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .421
25.2.4 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . .422
25.2.5 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
25.2.6 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
25.2.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing425
25.2.8 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .428
25.2.9 CGM Component Information . . . . . . . . . . . . . . . . . . . . .428
25.2.10 CGM Acquisition/Lock Time Information. . . . . . . . . . . .429
25.2.11 Timer Module Characteristics. . . . . . . . . . . . . . . . . . . . .430
25.2.12 RAM Memory Characteristics . . . . . . . . . . . . . . . . . . . . .430
25.2.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . .432
25.2.14 FLASH Memory Characteristics . . . . . . . . . . . . . . . . . . .432
25.2.15 BDLC Transmitter VPW Symbol Timings. . . . . . . . . . . .432
25.2.16 BDLC Receiver VPW Symbol Timings . . . . . . . . . . . . . .432
25.2.17 BDLC Transmitter DC Electrical Characteristics . . . . .433
25.2.18 BDLC Receiver DC Electrical Characteristics . . . . . . . .433
25.3 Mechanical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .434
25.3.1 52-pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . .434
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
25.2 Electrical Specifications
25.2.1 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 5.0 Volt DC Electrical Characteristics on page 422 for
guaranteed operating conditions.
Rating
Supply Voltage
Symbol
Value
Unit
V
VDD
–0.3 to +6.0
VIN
I
VSS –0.3 to VDD +0.3
Input Voltage
V
Maximum Current Per Pin
Excluding VDD and VSS
± 25
mA
TSTG
IMVSS
IMVDD
VHI
Storage Temperature
–55 to +150
100
°C
mA
mA
V
Maximum Current out of VSS
Maximum Current into VDD
100
VDD + 4.5
Reset and IRQ Input Voltage
NOTE: Voltages are referenced to VSS
.
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
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MC68HC908AS32A — Rev 0.0
Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
25.2.2 Functional Operating Range
Rating
Symbol
Value
Unit
°C
Operating Temperature Range(1)
Operating Voltage Range
TA
–40 to TA(MAX)
5.0 ± 0.5v
VDD
V
1. TA(MAX) = 125°C for part suffix MFN
TA(MAX) = 105°C for part suffix VFN
TA(MAX) = 85°C for part suffix CFN
NOTE: For applications which use the LVI, Motorola guarantee the functionality
of the device CPU only down to the LVI trip point (VLVI) within the
constraints outlined in Low Voltage Inhibit (LVI).
25.2.3 Thermal Characteristics
Characteristic
Thermal Resistance
Symbol
Value
Unit
θJA
70
°C/W
QFP (64 Pins)
Thermal Resistance
PLCC (52 Pins)
θJA
50
°C/W
PI/O
I/O Pin Power Dissipation
User Determined
W
PD = (IDD x VDD) +
I/O = K/(TJ + 273 °C)
PD
Power Dissipation (see Note 1)
W
P
PD x (TA + 273 °C)
Constant (see Note 2)
K
W/°C
°C
+ (PD2 x θJA
)
TJ
TA + PD x θJA
Average Junction Temperature
NOTES:
1.Power dissipation is a function of temperature.
2.K is a constant unique to the device. K can be determined from a known TA and
measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
25.2.4 5.0 Volt DC Electrical Characteristics
Characteristic
Output High Voltage
Symbol
Min
Typical
Max
Unit
(ILOAD = –2.0 mA) All Ports
(ILOAD = –5.0 mA) All Ports
VDD –0.8
VDD –1.5
—
---
---
---
—
—
10
V
V
VOH
I
OH(TOT)
Total source current
Output Low Voltage
mA
(ILOAD = 1.6 mA) All Ports
—
—
—
---
---
---
0.4
1.5
15
V
V
VOL
(ILOAD = 10.0 mA) All Ports
Total sink current
I
OL(TOT)
mA
Input High Voltage
VIH
0.7 x VDD
VDD
---
---
V
V
All Ports, IRQs, RESET, OSC1
Input Low Voltage
VIL
VSS
0.3 x VDD
All Ports, IRQs, RESET, OSC1
VDD Supply Current
Run (see Note 2)
Wait (see Note 3)
Stop (see Note 4)
LVI enabled, TA=25 °C
—
—
25
14
35
20
mA
mA
IDD
—
—
—
—
100
35
400
50
500
100
µA
µA
µA
µA
LVI disabled, TA=25 °C
LVI enabled, –40 °C to +125 °C
LVI disabled, –40 °C to +125 °C
IL
I/O Ports Hi-Z Leakage Current
Input Current
–1
–1
1
µA
µA
IIN
1
COUT
CIN
Capacitance
Ports (As Input or Output)
—
—
12
8
pF
V
Low-Voltage Reset Inhibit (trip)
3.80
VLVI
(recover)
4.49
200
VPOR
POR ReArm Voltage (see Note 5)
0
mV
mV
V/ms
V
VPORRST
RPOR
VHI
POR Reset Voltage (see Note 6)
0
800
POR Rise Time Ramp Rate (see Note 7)
High COP Disable Voltage (see Note 8)
Monitor mode entry voltage on IRQ (see Note 10)
0.02
—
VDD + 3.0
VDD + 3.0
VDD + 4.5
VDD + 4.5
VHI
V
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MC68HC908AS32A — Rev 0.0
422
Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
Characteristic
Symbol
Min
Typical
Max
Unit
NOTES:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +TA(MAX), unless otherwise noted.
2. Run (Operating) IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs
0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports
configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled.
Typical values at midpoint of voltage range, 25C only.
3. Wait IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 Vdc
from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as
inputs.
OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled.
Typical values at midpoint of voltage range, 25C only.
4. Stop IDD measured with OSC1 = VSS
.
Typical values at midpoint of voltage range, 25C only.
5. Maximum is highest voltage that POR is guaranteed.
6. Maximum is highest voltage that POR is possible.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low
externally until minimum VDD is reached.
8. See COP Module During Break Interrupts on page 180. VHI applied to RST.
9. Although IDD is proportional to bus frequency, a current of several mA is present even at very low
frequencies.
10. See Monitor mode description within Computer Operating Properly (COP). VHI applied to
IRQ or RST
25.2.5 Control Timing
Characteristic
Symbol
Min
—
Max
8.4
—
Unit
Bus Operating Frequency (4.5–5.5 V — VDD Only)
fBUS
MHz
tcyc
tRL
tILHI
tILIL
RESET Pulse Width Low
1.5
tcyc
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
1.5
—
tcyc
Note 4
—
16-Bit Timer (see Note 2)
Input Capture Pulse Width (see Note 3)
Input Capture Period
tTH, TL
tTLTL
t
tcyc
2
—
—
Note 4
NOTES:
1.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, TA = –40 °C to TA(MAX), unless otherwise noted.
2.The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3.Refer to Table 22-2 and supporting note.
4.The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt
service routine plus TBD t
.
cyc
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
25.2.6 ADC Characteristics
Characteristic
Min
Max
Unit
Comments
Resolution
8
8
Bits
Absolute Accuracy
(VREFL = 0 V, VDDA/VDDAREF = VREFH = 5 V ±
0.5v)
Includes
Quantization
–1
+1
LSB
VREFL
16
VREFH
17
VREFL = VSSA
Conversion Range (see Note 1)
V
Conversion Time
Period
Power-Up Time
µs
Input Leakage (see Note 3)
Ports B and D
–1
1
µA
ADC
Clock
Cycles
Includes Sampling
Time
Conversion Time
16
17
Monotonicity
Inherent within Total Error
VIN = VREFL
IN = VREFH
Zero Input Reading
Full-Scale Reading
00
01
FF
Hex
Hex
V
FE
ADC
Clock
Cycles
Sample Time (see Note 2)
5
—
Input Capacitance
ADC Internal Clock
Analog Input Voltage
NOTES:
—
8
pF
Hz
V
Not Tested
500 k
VREFL
1.048 M
VREFH
Tested Only at 1 MHz
1.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc ± 0.5v, VSSA = 0 Vdc, VREFH = 5.0 Vdc ± 0.5v
2.Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
3.The external system error caused by input leakage current is approximately equal to the product of R
source and input current.
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MC68HC908AS32A — Rev 0.0
MOTOROLA
Electrical Specification
Electrical Specification
Electrical Specifications
25.2.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency (see Note 3)
Master
Slave
fBUS(M)
fBUS(S)
f
BUS/2
fBUS
fBUS/128
dc
MHz
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
tcyc
1
2
1
128
—
tLead
tLag
2
3
Enable Lead Time
Enable Lag Time
15
15
—
—
ns
ns
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
4
5
6
7
100
50
—
—
ns
ns
ns
ns
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
100
50
—
—
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
45
5
—
—
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
0
15
—
—
Access Time, Slave (see Note 4)
CPHA = 0
tA(CP0)
tA(CP1)
0
0
40
20
ns
ns
ns
8
9
CPHA = 1
tDIS
Slave Disable Time (Hold Time to High-Impedance State)
—
25
Enable Edge Lead Time to Data Valid (see Note 6)
Master
Slave
tEV(M)
tEV(S)
10
—
—
10
40
Data Hold Time (Outputs, after Enable Edge)
Master
Slave
tHO(M)
tHO(S)
11
12
0
5
—
—
ns
Data Valid
Master (Before Capture Edge)
tV(M)
90
—
—
ns
ns
Data Hold Time (Outputs)
Master (Before Capture Edge)
tHO(M)
13
100
NOTES:
1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI
pins.
2. Item numbers refer to dimensions in Figure 25-1 and Figure 25-2.
3. fBUS = the currently active bus frequency for the microcontroller.
4. Time to data active from high-impedance state.
5. With 100 pF on all SPI pins
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
SS
(INPUT)
SS pin of master held high.
1
5
4
SCK (CPOL = 0)
(OUTPUT)
NOTE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10
11
10
11
MOSI
(OUTPUT)
MASTER MSB OUT
13
MASTER LSB OUT
12
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS pin of master held high.
1
SCK (CPOL = 0)
(OUTPUT)
5
4
NOTE
NOTE
4
5
SCK (CPOL = 1)
(OUTPUT)
6
7
LSB IN
11
MISO
MSB IN
BITS 6–1
BITS 6–1
(INPUT)
10
11
10
MOSI
(OUTPUT)
MASTER MSB OUT
12 13
MASTER LSB OUT
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 25-1. SPI Master Timing Diagram
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Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
SS
(INPUT)
3
1
SCK (CPOL = 0)
(INPUT)
11
4
4
5
2
SCK (CPOL = 1)
(INPUT)
9
8
MISO
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
11
NOTE
(INPUT)
11
6
7
10
MOSI
(OUTPUT)
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
SCK (CPOL = 0)
(INPUT)
5
4
5
2
3
SCK (CPOL = 1)
(INPUT)
4
10
9
8
MISO
NOTE
SLAVE MSB OUT
BITS 6–1
BITS 6–1
SLAVE LSB OUT
(OUTPUT)
11
6
7
10
MOSI
(INPUT)
MSB IN
LSB IN
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 25-2. SPI Slave Timing Diagram
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
25.2.8 CGM Operating Conditions
Characteristic
Symbol
VDDA
Min
Typ
—
Max
Unit
V
Comments
VDD -0.3
VDD+0.3
Operating Voltage
VSSA
VSS-0.3
1
VSS+0.3
16
—
V
fCGMRCLK
Crystal Reference Frequency
4.9152
MHz
Same Frequency
as fCGMRCLK
Module Crystal Reference
Frequency
fCGMXCLK
—
4.9152
—
MHz
fNOM
Range Nom. Multiplier
—
4.9152
—
—
MHz
MHz
fCGMVRS
fCGMVCLK
VCO Center-of-Range Frequency
VCO Operating Frequency
4.9152
4.9152
Note 1
32.0
—
1. fCGMVRS is a nominal value described and calulated as an example in the Clock Generator Module (CGM) section for the
desired VCO operating frequency, fCGMVCLK
.
25.2.9 CGM Component Information
Description
Symbol
Min
Typ
Max
Unit
Comments
Consult Crystal
Manufacturer’s Data
CL
Crystal Load Capacitance
—
—
—
—
Consult Crystal
Manufacturer’s Data
Crystal Fixed Capacitance
C1
—
2 x CL
—
—
Consult Crystal
Manufacturer’s Data
Crystal Tuning Capacitance
C2
—
—
2 x CL
0.0154
—
—
—
Cfact
Filter Capacitor Multiply Factor
F/s V
CFACT
(VDDA
x
See External Filter
Capacitor Pin (CGMXFC)
on page 135
CF
/
Filter Capacitor
—
—
—
fXCLK
)
CBYP must provide low
AC impedance from f =
fCGMXCLK/100 to 100 x
CBYP
Bypass Capacitor
—
0.1
—
µF
fCGMVCLK, so series
resistance must be
considered.
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MC68HC908AS32A — Rev 0.0
Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
25.2.10 CGM Acquisition/Lock Time Information
Description
Symbol
Min
Typ
Max
Unit
Notes
(8 x VDDA) /
If CF Chosen
Correctly
tACQ
Manual Mode Time to Stable
—
—
s
(fCGMXCLK x KACQ)
(4 x VDDA) /
If CF Chosen
Correctly
tAL
Manual Stable to Lock Time
Manual Acquisition Time
—
—
s
(fCGMXCLK x KTRK
)
tLOCK
DTRK
tACQ+tAL
—
—
s
Tracking Mode Entry
Frequency Tolerance
0
—
± 3.6
%
Acquisition Mode Entry
Frequency Tolerance
DUNT
± 6.3
—
± 7.2
%
DLOCK
DUNL
LOCK Entry Freq. Tolerance
LOCK Exit Freq. Tolerance
0
—
—
± 0.9
± 1.8
%
%
± 0.9
Reference Cycles per
Acquisition Mode
Measurement
nACQ
—
—
32
—
—
—
Reference Cycles per
Tracking Mode
nTRK
128
—
Measurement
(8 x VDDA) /
If CF Chosen
Correctly
Automatic Mode Time
to Stable
tACQ
nACQ/fXCLK
s
(fXCLK x KACQ)
(4 x VDDA) /
If CF Chosen
Correctly
Automatic Stable to Lock
Time
tAL
nTRK/fXCLK
—
s
(fXCLK x KTRK
)
tLOCK
Automatic Lock Time
—
0.65
25
ms
± (fCRYS
x (.025%)
x (N/4)
)
PLL Jitter, Deviation of
Average Bus Frequency
over 2 ms (note 1)
N = VCO
Freq. Mult.
0
—
%
K value for automatic mode
time to stable
Kacq
Ktrk
—
—
0.2
—
—
—
—
K value
0.004
NOTES:
1. Guaranteed but not tested.
2. VDD = 5.0 Vdc ± 0.5 V, VSS = 0 Vdc, TA = -40C to TA (MAX), unless otherwise noted.
3. Conditions for typical and maximum values are for Run mode with fCGMXCLK = 8MHz, fBUSDES = 8MHz, N = 4, L = 7,
discharged CF = 15 nF, VDD = 5Vdc.
4. Refer to Phase-Locked Loop (PLL) section for guidance on the use of the PLL.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Electrical Specification
Electrical Specification
25.2.11 Timer Module Characteristics
Characteristic
Input Capture Pulse Width
Symbol
tTIH, TIL
Min
125
Max
—
Unit
ns
t
tTCH, TCL
t
(1/fOP) + 5
Input Clock Pulse Width
—
ns
25.2.12 RAM Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
VRDR
RAM Data Retention Voltage
0.7
—
V
25.2.13 EEPROM Memory Characteristics
Characteristic
EEPROM Programming Time per Byte
EEPROM Erasing Time per Byte
EEPROM Erasing Time per Block
EEPROM Erasing Time per Bulk
Symbol
Min
10
Max
—
Unit
ms
ms
ms
ms
tEEPGM
tEEBYTE
tEEBLOCK
tEEBULK
10
—
10
—
10
—
EEPROM Programming Voltage Discharge
Period
tEEFPV
100
—
—
8
µs
—
Number of Programming Operations to the Same
EEPROM Byte Before Erase (1)
—
—
—
---
---
EEPROM Write/Erase Cycles
@ 10 ms Write Time
10,000
10
—
—
500
8
Cycles
Years
µs
EEPROM Data Retention
After 10,000 Write/Erase Cycles
EEPROM Programming Maximum Time to
‘AUTO’ Bit Set
---
EEPROM Erasing Maximum Time to ‘AUTO’ Bit
Set
---
ms
NOTES:
1. Programming a byte more times than the specified maximum may affect the data integrity of that byte. The byte must
be erased before it can be programmed again.
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MC68HC908AS32A — Rev 0.0
Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
25.2.14 FLASH Memory Characteristics
Characteristic
Symbol
Min
Max
Unit
FLASH Program Bus Clock Frequency
—
1
—
MHz
(1)
FLASH Read Bus Clock Frequency
FLASH Page Erase Time
32K
1
8.4M
Hz
fREAD
(2)
—
ms
tERASE
(3)
FLASH Mass Erase Time
FLASH PGM/ERASE to HVEN Set Up Time
FLASH High Voltage Hold Time
FLASH High Voltage Hold Time (Mass)
FLASH Program Hold Time
4
10
5
—
—
—
—
—
40
ms
µs
µs
µs
µs
µs
µs
tMERASE
tNVS
tNVH
tNVHL
tPGS
100
5
tPROG
FLASH Program Time
30
1
(4)
FLASH Return to Read Time
tRCV
(5)
FLASH Cumulative Program HV Period
—
4
ms
tHV
FLASH Row Erase Endurance(6)
FLASH Row Program Endurance(7)
FLASH Data Retention Time(8)
10,000
10,000
10
—
—
—
cycles
cycles
years
1. fREAD is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than tERASE(MIN), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tMERASE(MIN), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS+ tNVH + tPGS + (tPROGX 64) ð tHV max.
6. The minimum row erase endurance value specifies each row of the FLASH memory is guaranteed to work for at least this
many erase cycles.
7. The minimum row program endurance value specifies each row of the FLASH memory is guaranteed to work for at least
this many program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time spec-
ified.
MC68HC908AS32A — Rev 0.0
Advance Information
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MOTOROLA
Electrical Specification
Electrical Specification
25.2.15 BDLC Transmitter VPW Symbol Timings
Characteristic(1), (2)
Passive Logic 0
Number
10
Symbol
tTVP1
tTVP2
tTVA1
tTVA2
tTVA3
tTVP3
tTV4
Min
62
Typ
64
Max
66
Unit
µs
µs
µs
µs
µs
µs
µs
µs
Passive Logic 1
11
126
126
62
128
128
64
130
130
66
Active Logic 0
12
Active Logic 1
13
Start-of-Frame (SOF)
End-of-Data (EOD)
End-of-Frame (EOF)
Inter-Frame Separator (IFS)
14
198
198
278
298
200
200
280
300
202
202
282
302
15
16
tTV6
17
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V
2. See Figure 25-3.
25.2.16 BDLC Receiver VPW Symbol Timings
Characteristic(1), (2), (3)
Passive Logic 0
Number
10
Symbol
Min
34
Typ
64
Max
96
Unit
µs
µs
µs
µs
µs
µs
µs
µs
tTRVP1
tTRVP2
tTRVA1
tTRVA2
tTRVA3
tTRVP3
tTRV4
Passive Logic 1
Active Logic 0
11
96
128
128
64
163
163
96
12
96
Active Logic 1
13
34
Start-of-Frame (SOF)
End-of-Data (EOD)
End-of-Frame (EOF)
Break
14
163
163
239
280
200
200
280
—
239
239
320
—
15
16
tTRV6
18
1. fBDLC = 1.048576 or 1.0 MHz, VDD = 5.0 V ± 10%, VSS = 0 V
2. The receiver symbol timing boundaries are subject to an uncertainty of 1 tBDLC µs due to sampling considerations.
3. See Figure 25-3.
Advance Information
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MC68HC908AS32A — Rev 0.0
Electrical Specification
MOTOROLA
Electrical Specification
Electrical Specifications
14
10
12
SOF
0
0
13
11
15
1
1
0
EOD
16
EOF
18
BRK
Figure 25-3. BDLC Variable Pulse Width Modulation (VPW) Symbol Timing
25.2.17 BDLC Transmitter DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
BDTxD Output Low Voltage
(IBDTxD = 1.6 mA)
VOLTX
—
0.4
V
BDTxD Output High Voltage
(IBDTx = –800 µA)
VOHTX
VDD –0.8
—
V
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40 oC to +125 oC, unless otherwise noted
25.2.18 BDLC Receiver DC Electrical Characteristics
Characteristic(1)
BDRxD Input Low Voltage
Symbol
VILRX
Min
VSS
Max
0.3 x VDD
VDD
Unit
V
VIHRX
0.7 x VDD
–1
BDRxD Input High Voltage
BDRxD Input Low Current
BDRxD Input High Current
V
IILBDRXI
IHBDRX
+1
µA
µA
–1
+1
1. VDD = 5.0 Vdc + 10%, VSS = 0 Vdc, TA = –40 oC to +125 oC, unless otherwise noted
MC68HC908AS32A — Rev 0.0
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433
MOTOROLA
Electrical Specification
Electrical Specification
25.3 Mechanical Specifications
25.3.1 52-pin Plastic Leaded Chip Carrier (PLCC)
B
S
S
S
S
–M
M
0.18
T N
–P
L
–N–
Y BRK
–L–
–M–
G1
W
Z1
pin 52
pin 1
X
–P–
V
U
S
S
S
S
–M
M
0.18
T N
–P
L
A
R
S
S
S
S
S
S
S
S
M
M
0.18
0.18
T L
T L
–M
–M
N
N
–P
–P
Z
C
0.10
G
–T–
SEATING PLANE
J
E
G1
S
S
S
S
S
0.25
T L
–M
N
–P
Dim.
A
B
Min.
19.94
19.94
4.20
Max.
Notes
Dim.
U
Min.
19.05
Max.
20.19
20.19
4.57
19.20
1.21
1.21
1.42
0.50
10°
V
1.07
1.07
1.07
—
1. Datums –L–, –M–, –N– and –P– are determined where top of lead
shoulder exits plastic body at mould parting line.
2. Dimension G1, true position to be measured at datum –T– (seating
plane).
3. Dimensions R and U do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side.
C
W
X
E
2.29
2.79
F
0.33
0.48
Y
G
H
J
1.27 BSC
Z
2°
0.66
0.81
—
G1
K1
Z1
18.04
1.02
2°
18.54
—
4. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
5. All dimensions in mm.
0.51
0.64
K
R
—
10°
19.05
19.20
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MC68HC908AS32A — Rev 0.0
Electrical Specification
MOTOROLA
Technical Data — MC68HC908AS32A
Glossary
A — See “accumulator (A).”
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see "tracking mode."
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Glossary
Glossary
binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CGM — See “clock generator module (CGM).”
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MC68HC908AS32A — Rev 0.0
Glossary
MOTOROLA
Glossary
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a
crystal oscillator circuit and or phase-locked loop (PLL) circuit.
comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
counter clock — The input clock to the TIM counter. This clock is the output of the TIM
prescaler.
CPU — See “central processor unit (CPU).”
CPU08 — The central processor unit of the M68HC08 Family.
CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU
clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
MC68HC908AS32A — Rev 0.0
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MOTOROLA
Glossary
Glossary
CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC08 are:
•
•
•
•
•
A (8-bit accumulator)
H:X (16-bit index register)
SP (16-bit stack pointer)
PC (16-bit program counter)
CCR (condition code register containing the V, H, I, N, Z, and C
bits)
CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster
and more code-efficient than CPU interrupts.
DMA — See "direct memory access module (DMA)."
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
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Glossary
MOTOROLA
Glossary
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
H — The upper byte of the 16-bit index register (H:X) in the CPU08.
H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry
bit is required for binary-coded decimal arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C bits to determine the
appropriate correction factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of
H:X to determine the effective address of the operand. H:X can also serve as a temporary
data storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
MC68HC908AS32A — Rev 0.0
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439
MOTOROLA
Glossary
Glossary
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
IRQ — See "external interrupt module (IRQ)."
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
LVI — See "low voltage inhibit module (LVI)."
M68HC08 — A Motorola family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
mask option — A optional microcontroller feature that the customer chooses to enable or
disable.
mask option register (MOR) — An EPROM location containing bits that enable or disable
certain MCU features.
MCU — Microcontroller unit. See “microcontroller.”
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MC68HC908AS32A — Rev 0.0
Glossary
MOTOROLA
Glossary
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
MC68HC908AS32A — Rev 0.0
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441
MOTOROLA
Glossary
Glossary
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
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Glossary
MOTOROLA
Glossary
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
reset — To force a device to a known condition.
ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
MC68HC908AS32A — Rev 0.0
Advance Information
443
MOTOROLA
Glossary
Glossary
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
TIM — See "timer interface module (TIM)."
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see "acquisition mode."
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444
MC68HC908AS32A — Rev 0.0
Glossary
MOTOROLA
Glossary
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE,
and BLT use the overflow bit.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.
MC68HC908AS32A — Rev 0.0
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445
MOTOROLA
Glossary
Glossary
Advance Information
446
MC68HC908AS32A — Rev 0.0
Glossary
MOTOROLA
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MC68HC908AS32A/D
相关型号：
MC908AS60AVFU
Microcontroller, 8-Bit, FLASH, 8.4MHz, HCMOS, PQFP64, 20 X 20 MM, PLASTIC, QFP-64
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