MC908QL2C [MOTOROLA]
Microcontrollers; 微控制器
| 型号： | MC908QL2C |
| 厂家： | 
MOTOROLA |
| 描述： | Microcontrollers |
| 文件： | 总222页 (文件大小：2876K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908QL4
MC68HC908QL3
MC68HC908QL2
Data Sheet
M68HC08
Microcontrollers
MC68HC908QL4
Rev. 4
12/2004
freescale.com
MC68HC908QL4
MC68HC908QL3
MC68HC908QL2
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History (Sheet 1 of 2)
Revision
Level
Page
Number(s)
Date
Description
September,
2003
N/A
Initial release
N/A
226
228
17.3 Functional Operating Range — Corrected operating voltage range
17.6 Control Timing — Corrected values for internal operating frequency
and internal clock period
November,
2003
1.0
17.14 5.0-Volt ADC Characteristics — Replaced ADC characteristic table
found in initial release
236
237
17.15 3.3-Volt ADC Characteristics — Added
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
3
Revision History
Revision History (Sheet 2 of 2)
Revision
Level
Page
Number(s)
Date
Description
Figure 2-2. Control, Status, and Data Registers
Corrected reset state for the FLASH Block Protect Register.
Corrected reset value for the Internal Oscillator Time Value
33
34
Table 7-1. Instruction Set Summary — Added WAIT instruction
83
11.8.1 Oscillator Status and Control Register — Revised description of
ECGON bit for clarity
117
Table 13-3. Interrupt Sources — Corrected address locations for SLIC,
KBI, and ADC
140
14.3.5 SLIC Wait (Core Specific) — Revised description for clarity
14.3.7 SLIC Stop (Core Specific) — Revised description for clarity
144
144
14.6.6.2 Byte Transfer Mode Operation — Revised definition of Receiver
Buffer Overrun Error
156
161
174
196
196
March,
2004
2.0
14.7.1 LIN Message Frame Header — Revised third paragraph of
description
14.14 Sleep and Wakeup Operation — Revised second paragraph of
description
15.8 Input/Output Signals — Corrected reference from PTA0/TCH) to
PTB0/TCH0
15.8.2 TIM Channel I/O Pins (PTB0/TCH0 and PTA1/TCH1) —
Corrected reference to from PTA0/TCH) to PTB0/TCH0
Figure 16-1. Block Diagram Highlighting BRK and MON Blocks — Added
17.5 5-V DC Electrical Characteristics — Updated table notes
17.8 5-V Oscillator Characteristics — Updated table notes
206
227
230
231
17.9 3.3-V DC Electrical Characteristics — Updated table notes
June,
2004
3.0
4.0
Modular sections reworked for clarity.
Throughout
Updated to final Freescale format. Corrections per email review.
Replaced ADC chapter with latest.
Throughout
Table 1-3. Function Priority in Shared Pins — Updated entry for PTA2
23
21
Figure 1-2. MCU Pin Assignments — Corrected pin assignments for the
TSSOP packages.
December,
2004
17.11 Oscillator Characteristics — Updated deviation from trimmed
internal oscillator specifications.
210
17.8 3.3-V DC Electrical Characteristics — Corrected capacitance values
17.11 Oscillator Characteristics — Corrected Note 8
208
211
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
4
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 3 Analog-to-Digital Converter (ADC10) Module. . . . . . . . . . . . . . . . . . . . . . . . . . .43
Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Chapter 6 Computer Operating Properly (COP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Chapter 9 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 10 Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 11 Oscillator Module (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Chapter 12 Input/Output Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Chapter 13 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Chapter 14 Slave LIN Interface Controller (SLIC) Module . . . . . . . . . . . . . . . . . . . . . . . . .133
Chapter 15 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .219
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
5
List of Chapters
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
6
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Function Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Direct Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6
FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
Chapter 3
Analog-to-Digital Converter (ADC10) Module
3.1
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.3.3.3
3.3.3.4
3.3.4
3.3.4.1
3.3.4.2
3.3.4.3
3.3.4.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Clock Select and Divide Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Input Select and Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Conversion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Initiating Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Completing Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Aborting Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Total Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Sources of Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Code Width and Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Table of Contents
3.3.4.5
3.3.4.6
Linearity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Code Jitter, Non-Monotonicity and Missing Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5
3.5.1
3.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6
ADC10 During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC10 Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC10 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC10 Voltage Reference High Pin (VREFH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC10 Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
ADC10 Channel Pins (ADn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ADC10 Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ADC10 Result High Register (ADRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC10 Result Low Register (ADRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ADC10 Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.8.1
3.8.2
3.8.3
3.8.4
Chapter 4
Auto Wakeup Module (AWU)
4.1
4.2
4.3
4.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5
4.5.1
4.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Chapter 5
Configuration Register (CONFIG)
5.1
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 6
Computer Operating Properly (COP)
6.1
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
8
Freescale Semiconductor
6.3
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.4
6.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7
6.8
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 7
Central Processor Unit (CPU)
7.1
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.5
7.5.1
7.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.6
7.7
7.8
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 8
External Interrupt (IRQ)
8.1
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8.3
8.3.1
8.3.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MODE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
8.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.5
8.5.1
8.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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Table of Contents
8.6
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.7
8.7.1
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
IRQ Input Pins (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Chapter 9
Keyboard Interrupt Module (KBI)
9.1
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Keyboard Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
MODEK = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
MODEK = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.1
9.3.1.1
9.3.1.2
9.3.2
9.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.5
9.5.1
9.5.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.6
KBI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.7
9.7.1
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
KBI Input Pins (KBI5:KBI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Keyboard Status and Control Register (KBSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Keyboard Interrupt Polarity Register (KBIPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.8.1
9.8.2
9.8.3
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.3.1
10.3.2
10.3.3
10.3.4
Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LVI Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.4 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.5.1
10.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 11
Oscillator Module (OSC)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Freescale Semiconductor
11.3.1
Internal Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Bus Clock Times 4 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Bus Clock Times 2 (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Internal to External Clock Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External to Internal Clock Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.3.1.1
11.3.1.2
11.3.1.3
11.3.1.4
11.3.1.5
11.3.1.6
11.3.2
11.3.2.1
11.3.2.2
11.3.2.3
11.3.3
11.3.4
11.3.5
11.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.5.1
11.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.6 OSC During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.7.1
11.7.2
Oscillator Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Oscillator Output Pin (OSC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.8.1
11.8.2
Oscillator Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2 Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2.1
12.2.2
12.2.3
12.2.4
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port A Input Pullup/Down Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Port A Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3 Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.3.1
12.3.2
12.3.3
12.3.4
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Port B Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Chapter 13
System Integration Module (SIM)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.3 SIM Bus Clock Control and Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.3.1
13.3.2
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Table of Contents
13.3.3
Clocks in Stop Mode and Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4.1
13.4.2
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
13.4.2.5
13.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.5.1
13.5.2
13.5.3
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.6.1.1
13.6.1.2
13.6.2
13.6.2.1
13.6.2.2
13.6.3
13.6.4
13.6.5
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.7.1
13.7.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.8.1
13.8.2
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Chapter 14
Slave LIN Interface Controller (SLIC) Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
14.5.9
14.5.10
Power Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SLIC Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SLIC Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SLIC Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Wakeup from SLIC Wait with CPU in WAIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SLIC Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Normal and Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Special Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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14.6 SLIC During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
14.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.7.1
14.7.2
SLCTX — SLIC Transmit Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SLCRX — SLIC Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
14.8.1
14.8.2
14.8.3
14.8.4
14.8.5
14.8.6
14.8.6.1
14.8.6.2
14.8.7
14.8.8
SLIC Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SLIC Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SLIC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SLIC Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SLIC Bit Time Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLIC State Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LIN Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Byte Transfer Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SLIC Data Length Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SLIC Identifier and Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.9 Initialization/Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.9.1
14.9.2
14.9.3
14.9.4
14.9.5
14.9.6
LIN Message Frame Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
LIN Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
LIN Checksum Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SLIC Module Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SLCSV Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SLIC Module Initialization Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
LIN Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Byte Transfer Mode Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Handling LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
LIN Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Possible Errors on Message Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Handling Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Standard Command Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Extended Command Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Possible Errors on Command Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Handling Request LIN Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Standard Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Extended Request Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Transmit Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Possible Errors on Request Message Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Handling IMSG to Minimize Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Sleep and Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Polling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
LIN Data Integrity Checking Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
High-Speed LIN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Byte Transfer Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Oscillator Trimming with SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Digital Receive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Digital Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Digital Filter Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
14.9.6.1
14.9.6.2
14.9.7
14.9.7.1
14.9.7.2
14.9.8
14.9.8.1
14.9.8.2
14.9.8.3
14.9.9
14.9.9.1
14.9.9.2
14.9.9.3
14.9.9.4
14.9.10
14.9.11
14.9.12
14.9.13
14.9.14
14.9.15
14.9.16
14.9.17
14.9.17.1
14.9.17.2
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Table of Contents
Chapter 15
Timer Interface Module (TIM)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
15.3.1
15.3.2
15.3.3
15.3.3.1
15.3.3.2
15.3.4
15.3.4.1
15.3.4.2
15.3.4.3
TIM Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.5.1
15.5.2
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.6 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
15.7.1
15.7.2
TIM Channel I/O Pins (TCH1:TCH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
TIM Clock Pin (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
15.8.1
15.8.2
15.8.3
15.8.4
15.8.5
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 16
Development Support
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
16.2.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Break Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.2.1.1
16.2.1.2
16.2.1.3
16.2.2
16.2.2.1
16.2.2.2
16.2.2.3
16.2.2.4
16.2.2.5
16.2.3
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16.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Normal Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
16.3.1.1
16.3.1.2
16.3.1.3
16.3.1.4
16.3.1.5
16.3.1.6
16.3.1.7
16.3.2
Chapter 17
Electrical Specifications
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
17.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
17.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
17.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
17.5 5-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
17.6 Typical 5-V Output Drive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
17.7 5-V Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
17.8 3.3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
17.9 Typical 3.3-V Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
17.10 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
17.12 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
17.13 ADC10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
17.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
17.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Chapter 18
Ordering Information and Mechanical Specifications
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.3 16-Pin Small Outline Integrated Circuit Package (Case #751G) . . . . . . . . . . . . . . . . . . . . . . . 220
18.4 16-Pin Thin Shrink Small Outline Package (Case #948F). . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
15
Table of Contents
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
16
Chapter 1
General Description
1.1 Introduction
The MC68HC908QL4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
0.4
Table 1-1. Summary of Device Variations
FLASH
Memory Size
RAM
Memory Size
Analog-to-Digital
Converter
Device
MC68HC908QL4
MC68HC908QL3
MC68HC908QL2
4096 bytes
4096 bytes
2048 bytes
128 bytes
128 bytes
128 bytes
6 ch, 10 bit
—
6 ch, 10 bit
1.2 Features
Features include:
•
•
•
•
•
•
High-performance M68HC08 CPU core
Fully upward-compatible object code with M68HC05 Family
5-V and 3.3-V operating voltages (VDD
8-MHz internal bus operation at 5 V, 4-MHz at 3.3 V
)
Software configurable input clock from either internal or external source
Trimmable internal oscillator
–
–
–
–
Selectable 1 MHz, 2 MHz, or 3.2MHz or 6.4 MHz internal bus operation
8-bit trim capability
Trimmable to approximately 0.4%(1)
25% untrimmed
•
•
•
Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz, and 8–32 MHz
Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source
On-chip in-application programmable FLASH memory
–
–
–
Internal program/erase voltage generation
Monitor ROM containing user callable program/erase routines
FLASH security(2)
1. See 17.11 Oscillator Characteristics for internal oscillator specifications
2. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
17
General Description
•
•
On-chip random-access memory (RAM)
Slave LIN interface controller (SLIC) module
–
–
Full LIN messaging buffering of Identifier and 8 data bytes
Automatic baud rate and LIN message frame synchronization:
No prior programming of bit rate required, 1–20 kbps LIN bus speed operation
All LIN messages will be received (no message loss due to synchronization process)
Input clock tolerance as high as ±±0%, allowing internal oscillator to remain untrimmed
Incoming break symbols allowed to be 10 to 20 bit times without message loss
Supports automatic software trimming of internal oscillator using LIN synchronization data
Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE
Automatic checksum calculation and verification with error reporting
Maximum of 2 interrupts per LIN message frame
Full LIN error checking and reporting
High-speed LIN capability up to 83.33 kbps to 120.00 kbps
Switchable UART-like byte transfer mode for processing bytes one at a time without LIN
message framing constraints
–
–
–
–
–
–
–
Configurable digital receive filter
•
•
2-channel, 16-bit timer interface module (TIM) with external clock source input
6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel
(ADC10)
•
6-bit keyboard interrupt with wakeup feature (KBI)
–
–
Programmable for rising/falling or high/low level detect
Software selectable to use internal or external pullup/pulldown device
•
•
•
External asynchronous interrupt pin with internal pullup (IRQ)
Master asynchronous reset pin with internal pullup (RST)
13 bidirectional input/output (I/O) lines and one input only:
–
–
–
–
–
–
–
–
–
Six shared with keyboard interrupt function
Six shared with ADC10
Two shared with TIM
Two shared with SLIC
One shared with reset
One input only shared with external interrupt (IRQ)
High current sink/source capability
Selectable pullups on all ports (pullup/down on port A), selectable on an individual bit basis
Three-state ability on all port pins
•
•
Low-voltage inhibit (LVI) module features:
Software selectable trip point in CONFIG register
System protection features:
–
–
–
–
–
Computer operating properly (COP) watchdog
Low-voltage detection with reset
Illegal opcode detection with reset
Illegal address detection with reset
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
18
Freescale Semiconductor
MCU Block Diagram
•
•
•
•
Power-on reset
Memory mapped I/O registers
Power saving stop and wait modes
Available packages:
–
–
16-pin small outline integrated circuit (SOIC) package
16-pin thin shrink small outline package (TSSOP)
Features of the CPU08 include the following:
•
•
•
•
•
•
•
•
•
•
Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 × 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QL4.
1.4 Pin Functions
Table 1-2 provides a description of the pin functions.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
19
General Description
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER RAM
USER FLASH
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
VSS
POWER SUPPLY
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 1-1. Block Diagram
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
20
Freescale Semiconductor
Pin Functions
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTA0/KBI0
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTB4/SLCRx
PTA4/OSC2/KBI4
PTA5/OSC1/KBI5
PTA0/KBI0
PTB4/SLCRx
PTB5/SLCTx
PTB6
PTB7
PTB1
PTB2
PTB3
PTB0/TCH0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTB0/TCH0
VSS
PTB3
PTB2
PTB5/SLCTx
PTB6
VDD
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB7
PTB1
16-PIN ASSIGNMENT
MC68HC908QL3 SOIC
16-PIN ASSIGNMENT
MC68HC908QL3 TSSOP
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VSS
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTA0/AD0/KBI0
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTB4/SLCRx
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
PTA0/AD0/KBI0
VSS
PTB4/SLCRx
PTB5/SLCTx
PTB6
PTB7
PTB1
PTB2/AD4
PTB3/AD5
PTB0/TCH0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PTB0/TCH0
PTB3/AD5
PTB2/AD4
PTB5/SLCTx
PTB6
VDD
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
PTB1
PTB7
16-PIN ASSIGNMENT
MC68HC908QL4 AND MC68HC908QL2 SOIC
16-PIN ASSIGNMENT
MC68HC908QL4 AND MC68HC908QL2 TSSOP
Figure 1-2. MCU Pin Assignments
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
21
General Description
Table 1-2. Pin Functions
Pin
Name
Description
Input/Output
VDD
VSS
Power supply
Power supply ground
Power
Power
PTA0 — General purpose I/O port
Input/Output
Input
PTA0
AD0 — A/D channel 0 input
KBI0 — Keyboard interrupt input 0
Input
PTA1 — General purpose I/O port
Input/Output
Input
AD1 — A/D channel 1 input
PTA1
TCH1 — Timer Channel 1 I/O
Input/Output
Input
KBI1— Keyboard interrupt input 1
PTA2 — General purpose input-only port
IRQ — External interrupt with programmable pullup and Schmitt trigger input
KBI2 — Keyboard interrupt input 2
Input
Input
PTA2
PTA3
Input
TCLK — External clock source input for the TIM module
PTA3 — General purpose I/O port
Input
Input/Output
Input
RST — Reset input, active low with internal pullup and Schmitt trigger input
KBI3 — Keyboard interrupt input 3
Input
PTA4 — General purpose I/O port
Input/Output
OSC2 — XTAL oscillator output (XTAL option only)
Output
Output
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
PTA4
PTA5
AD2 — A/D channel 2 input
Input
Input
KBI4 — Keyboard interrupt input 4
PTA5 — General purpose I/O port
OSC1 — XTAL, RC, or external oscillator input
AD3 — A/D channel 3 input
Input/Output
Input
Input
KBI5 — Keyboard interrupt input 5
PTB0 — General purpose I/O port
TCH0 — Timer Channel 0 I/O
PTB1 — General purpose I/O port
PTB2 — General purpose I/O port
AD4 — A/D channel 4 input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input
PTB0
PTB1
PTB2
PTB3 — General purpose I/O port
AD5 — A/D channel 5 input
Input/Output
Input
PTB3
PTB4
PTB5
PTB4 — General purpose I/O port
SLCRx — SLC receive input
Input/Output
Input
PTB5 — General purpose I/O port
SLCTx — SLC transmit output
Input/Output
Output
PTB6, PTB7 General-purpose I/O port
Input/Output
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
22
Freescale Semiconductor
Pin Function Priority
1.5 Pin Function Priority
Table 1-3 defines the priority of a shared pin if multiple functions are enabled. Only the shared pins are
shown in the table.
Table 1-3. Function Priority in Shared Pins
Pin Name
PTA0(1)
PTA1(1)
PTA2
Highest-to-Lowest Priority Sequence
AD0 → TCH1 → KBI0 → PTA0
AD1 → KBI1 → PTA1
TCLK → IRQ → KBI2 → PTA2(2)
RST → KBI3 → PTA3
OSC2 → AD2 → KBI4 → PTA4
OSC1 → AD3 → KBI5 → PTA5
TCH0 → PTB0
PTA3
PTA4(1)
PTA5(1)
PTB0
PTB1
PTB1
PTB2(1)
PTB3(1)
PTB4
AD4 → PTB2
AD5 → PTB3
SLCRx → PTB4
PTB5
SLCTx → PTB5
1. When a pin is to be used as an ADC pin, the I/O port function should be
left as an input. The ADC does not override the port data direction
register.
2. TCLK is not included in the priority scheme. When TCLK is enabled the
other shared functions in the pin should be disabled.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
23
General Description
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
24
Chapter 2
Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map is shown
in Figure 2-1.
2.2 Unimplemented Memory Locations
Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1,
unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1, reserved
locations are marked with the word reserved or with the letter R.
2.4 Direct Page Registers
Figure 2-2 shows the memory mapped registers of the MC68HC908QL4. Registers with addresses
between $0000 and $00FF are considered direct page registers and all instructions including those with
direct page addressing modes can access them. Registers between $0100 and $FFFF require non-direct
page addressing modes. See Chapter 7 Central Processor Unit (CPU) for more information on
addressing modes.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
25
Memory
$0000
↓
$0051
DIRECT PAGE REGISTERS
81 BYTES
$0052
↓
$007F
UNIMPLEMENTED
47 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$2B7D
UNIMPLEMENTED
10,878 BYTES
$2B7E
↓
$2E1F
AUXILIARY ROM
674 BYTES
$2E20
↓
$EDFF
UNIMPLEMENTED
49120 BYTES
$EE00
$EE00
↓
$F5FF
RESERVED
2048 BYTES
FLASH MEMORY
4096 BYTES
↓
$F600
↓
$FDFF
FLASH MEMORY
2048 BYTES
$FDFF
$FE00
↓
$FE0F
MISCELLANEOUS REGISTERS
16 BYTES
$FE00
↓
$FE0F
UNIMPLEMENTED
16 BYTES
$FE10
↓
$FF7D
MONITOR ROM
350 BYTES
$FF7E
↓
$FFBD
UNIMPLEMENTED
64 BYTES
$FFBE
↓
$FFC1
MISCELLANEOUS REGISTERS
4 BYTES
$FFC2
↓
$FFCF
UNIMPLEMENTED
14 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
MC68HC908QL4, MC68HC908QL3
Memory Map
MC68HC908QL2
Memory Map
Figure 2-1. Memory Map
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
26
Freescale Semiconductor
Direct Page Registers
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PTA0
U
Read:
0
AWUL
PTA2
Port A Data Register
PTA5
U
PTA4
U
PTA3
U
PTA1
U
$0000
(PTA) Write:
See page 112.
Reset:
Read:
U
0
U
Port B Data Register
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
$0001
(PTB) Write:
See page 114.
Reset:
Unaffected by reset
$0002
↓
Reserved
$0003
Read:
0
0
0
Data Direction Register A
DDRA5
DDRA4
DDRA3
DDRA1
DDRA0
$0004
$0005
(DDRA) Write:
See page 112.
Reset:
Read:
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
(DDRB) Write:
See page 115.
Reset:
$0006
↓
Reserved
$000A
Read:
0
0
Port A Input Pullup/Down
Enable Register (PTAPUE) Write:
OSC2EN
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000B
$000C
See page 113.
Reset:
0
0
0
0
0
0
Read:
Port B Input Pullup Enable
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
Register (PTBPUE) Write:
See page 116.
Reset:
0
0
0
0
0
0
0
0
$000D
↓
$0019
Reserved
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status and
Control Register (KBSCR) Write:
IMASKK
MODEK
$001A
$001B
See page 94.
Reset:
0
0
0
AWUIE
0
0
KBIE5
0
0
0
0
KBIE1
0
0
KBIE0
0
Read:
Keyboard Interrupt
Enable Register (KBIER) Write:
KBIE4
KBIE3
KBIE2
0
See page 95.
Reset:
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
27
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
KBIP1
0
Bit 0
KBIP0
0
Read:
0
0
Keyboard Interrupt
Polarity Register (KBIPR) Write:
KBIP5
KBIP4
KBIP3
KBIP2
$001C
$001D
$001E
See page 95.
Reset:
0
0
0
0
0
0
0
0
0
0
0
Read:
IRQF
IRQ Status and Control
Register (INTSCR) Write:
IMASK
0
MODE
0
ACK
0
See page 87.
Reset:
0
IRQPUD
0
0
IRQEN
0
0
R
0
0
R
0
0
R
0
Read:
OSCENIN-
STOP
Configuration Register 2
R
0
RSTEN
0(2)
(CONFIG2)(1) Write:
See page 63.
Reset:
0
1. One-time writable register after each reset.
2. RSTEN reset to 0 by a power-on reset (POR) only.
Read:
Configuration Register 1
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVITRIP
0(2)
SSREC
0
STOP
0
COPD
0
$001F
(CONFIG1)(1) Write:
See page 64.
Reset:
0
0
0
1. One-time writable register after each reset.
2. LVITRIP reset to 0 by a power-on reset (POR) only.
Read:
TOF
0
0
0
TIM Status and Control
TOIE
TSTOP
PS2
PS1
PS0
$0020
$0021
$0022
$0023
$0024
$0025
Register (TSC) Write:
See page 180.
Reset:
TRST
0
0
0
1
0
0
0
0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TIM Counter Register High
(TCNTH) Write:
See page 182.
Reset:
0
0
0
0
0
0
0
0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM Counter Register
Low (TCNTL) Write:
See page 182.
Reset:
0
Bit 15
1
0
Bit 14
1
0
Bit 13
1
0
Bit 12
1
0
Bit 11
1
0
Bit 10
1
0
Bit 9
1
0
Read:
TIM Counter Modulo
Register High (TMODH) Write:
Bit 8
See page 182.
Reset:
1
Read:
TIM Counter Modulo
Register Low (TMODL) Write:
Bit 7
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
See page 182.
Reset:
1
CH0F
0
1
CH0MAX
0
Read:
TIM Channel 0 Status and
Control Register (TSC0) Write:
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
See page 183.
Reset:
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
28
Freescale Semiconductor
Direct Page Registers
Addr.
Register Name
TIM Channel 0
Register High (TCH0H) Write:
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$0026
See page 185.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 0
Register Low (TCH0L) Write:
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
$0027
$0028
$0029
$002A
See page 185.
Reset:
Read:
CH1F
0
TIM Channel 1 Status and
Control Register (TSC1) Write:
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
0
0
See page 183.
Reset:
0
0
Read:
TIM Channel 1
Register High (TCH1H) Write:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See page 185.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 1
Register Low (TCH1L) Write:
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
See page 185.
Reset:
$002B
↓
$0035
Reserved
Read:
ECGST
0
Oscillator Status and Control
OSCOPT1 OSCOPT0
ICFS1
1
ICFS0
0
ECFS1
0
ECFS0
0
ECGON
0
$0036
$0037
Register (OSCSC) Write:
See page 108.
Reset:
0
0
Reserved
Oscillator Trim Register Read:
TRIM7
1
TRIM6
0
TRIM5
0
TRIM4
0
TRIM3
0
TRIM2
0
TRIM1
0
TRIM0
0
(OSCTRIM)
Write:
See page 109.
$0038
Reset:
$0039
↓
Reserved
$003B
Read: COCO
ADC10 Status and Control
Register (ADSCR) Write:
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
$003C
$003D
See page 52.
Reset:
Read:
0
0
0
0
0
0
1
0
1
1
0
1
AD9
R
1
AD8
R
0
ADC10 Data Register High
(ADRH) Write:
See page 54.
R
0
R
0
R
0
R
0
R
R
0
Reset:
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
29
Memory
Addr.
Register Name
Bit 7
AD7
R
6
AD6
R
5
AD5
R
4
AD4
R
3
AD3
R
2
AD2
R
1
AD1
R
Bit 0
AD0
R
Read:
ADC10 Data Register Low
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
$0048
$0049
(ADRL) Write:
See page 54.
Reset:
Read:
0
0
0
0
0
0
0
0
ADC10 Clock Register
ADLPC
ADIV1
ADIV0
0
ADICLK
MODE1
0
MODE0
0
ADLSMP ADACKEN
(ADCLK) Write:
See page 55.
Reset:
Read:
0
0
0
0
0
0
0
0
SLCIE
0
SLIC Control Register 1
INITREQ
WAKETX TXABRT
IMSG
(SLCC1) Write:
See page 139.
Reset:
Read:
0
0
0
0
1
0
0
0
0
0
0
0
SLIC Control Register 2
SLCWCM
BTM
SLCE
0
(SLCC2) Write:
See page 140.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read: SLCACT
INITACK
SLIC Status Register
(SLCS) Write:
SLCF
See page 141.
Reset:
Read:
0
0
1
0
0
0
0
0
0
0
0
0
0
0
SLIC Prescale Register
RXFP1
RXFP0
(SLCP) Write:
See page 142.
Reset:
Read:
1
0
0
0
0
0
0
BT12
0
0
BT11
0
0
BT10
0
0
0
SLIC Bit Time Register High
BT9
0
BT8
(SLCBTH) Write:
See page 143.
Reset:
Read:
0
0
0
0
0
SLIC Bit Time Register Low
BT7
BT6
BT5
BT4
BT3
BT2
BT1
(SLCBTL) Write:
See page 143.
Reset:
Read:
0
0
0
0
0
0
0
0
0
0
0
0
I3
I2
I1
I0
SLIC State Vector Register
(SLCSV) Write:
See page 144.
Reset:
Read:
0
0
0
0
0
0
0
0
SLIC Data Length Code
TXGO
CHKMOD
DLC5
DLC4
DLC3
DLC2
DLC1
DLC0
Register (SLCDLC) Write:
See page 148.
Reset:
0
R7
T7
0
0
R6
T6
0
0
R5
T5
0
0
R4
T4
0
0
0
R2
T2
0
0
R1
T1
0
0
R0
T0
0
Read:
R3
SLIC Identifier Register
(SLCID) Write:
See page 149.
Reset:
T3
0
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 7
(SLCD7) Write:
See page 149.
Reset:
T3
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
30
Freescale Semiconductor
Direct Page Registers
Addr.
Register Name
Bit 7
R7
T7
0
6
R6
T6
0
5
R5
T5
0
4
R4
T4
0
3
R3
T3
0
2
R2
T2
0
1
R1
T1
0
Bit 0
R0
T0
0
Read:
SLIC Data Register 6
$004A
(SLCD6) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 5
$004B
$004C
$004D
$004E
$004F
$0050
(SLCD5) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 4
(SLCD4) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 3
(SLCD3) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 2
(SLCD2) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 1
(SLCD1) Write:
See page 149.
Reset:
Read:
R7
T7
0
R6
T6
0
R5
T5
0
R4
T4
0
R3
T3
0
R2
T2
0
R1
T1
0
R0
T0
0
SLIC Data Register 0
(SLCD0) Write:
See page 149.
Reset:
$0051
↓
Reserved
$005F
Read:
SBSW
See note 1
0
Break Status Register
R
R
R
R
R
R
R
$FE00
(BSR) Write:
See page 191.
Reset:
1. Writing a 0 clears SBSW.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
SIM Reset Status Register
$FE01
$FE02
(SRSR) Write:
See page 131.
POR:
Read:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BDCOP
0
Break Auxiliary
Register (BRKAR) Write:
See page 191.
Reset:
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
31
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Break Flag Control
Register (BFCR) Write:
BCFE
R
R
R
R
R
R
R
$FE03
$FE04
$FE05
See page 191.
Reset:
0
IF6
R
Read:
IF5
R
IF4
R
IF3
R
IF2
R
IF1
R
0
R
0
R
Interrupt Status Register 1
(INT1) Write:
See page 127.
Reset:
Read:
0
0
0
0
0
0
0
0
IF14
R
IF13
R
IF12
R
IF11
R
IF10
R
IF9
R
IF8
R
IF7
R
Interrupt Status Register 2
(INT2) Write:
See page 127.
Reset:
Read:
0
0
0
0
0
0
0
0
IF22
R
IF21
R
IF20
R
IF19
R
IF18
R
IF17
R
IF16
R
IF15
R
Interrupt Status Register 3
$FE06
$FE07
(INT3) Write:
See page 128.
Reset:
0
0
0
0
0
0
0
0
Reserved
Read:
0
0
0
0
FLASH Control Register
HVEN
0
MASS
0
ERASE
0
PGM
0
$FE08
$FE09
$FE0A
$FE0B
$FE0C
(FLCR) Write:
See page 35.
Reset:
Read:
0
Bit 15
0
0
Bit 14
0
0
Bit 13
0
0
Bit 12
0
Break Address High
Bit 11
0
Bit 10
0
Bit 9
0
Bit 8
0
Register (BRKH) Write:
See page 190.
Reset:
Read:
Break Address Low
Register (BRKL) Write:
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See page 190.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
Register (BRKSCR) Write:
BRKE
0
BRKA
See page 191.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
Read: LVIOUT
R
LVI Status Register
(LVISR) Write:
See page 99.
Reset:
0
0
0
0
0
0
0
0
0
$FE0D
↓
$FE0F
Reserved
Read:
FLASH Block Protect
Register (FLBPR) Write:
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
$FFBE
See page 40.
Reset:
Unaffected by reset
= Reserved
= Unimplemented
R
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 7)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
32
Freescale Semiconductor
Direct Page Registers
Addr.
Register Name
Reserved
Bit 7
6
5
4
3
2
1
Bit 0
$FFBF
Read:
Write:
Reset:
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
Internal Oscillator Trim
Value (Optional)
$FFC0
$FFC1
Resets to factory programmed value
Reserved
Read:
LOW BYTE OF RESET VECTOR
WRITING CLEARS COP COUNTER (ANY VALUE)
Unaffected by reset
COP Control Register
$FFFF
(COPCTL) Write:
See page 69.
Reset:
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 7)
Table 2-1. Vector Addresses
Vector Priority
Vector
IF22–IF16
IF15
IF14
IF13
IF12
IF11
IF10
IF9
Address
Vector
$FFD0,1–$FFDC,D Unused vectors
Lowest
$FFDE,F
$FFE0,1
$FFE2,3
$FFE4,5
$FFE6,7
$FFE8,9
$FFEA,B
$FFFC,D
$FFEE,F
$FFF0,1
$FFF2,3
$FFF4,5
$FFF6,7
$FFF8,9
$FFFA,B
$FFFC,D
$FFFE,F
ADC conversion complete vector
Keyboard vector
Unused vector
Unused vector
Unused vector
Unused vector
SLIC vector
IF8
Unused vector
IF7
Unused vector
IF6
Unused vector
IF5
TIM overflow vector
TIM channel 1 vector
TIM channel 0 vector
Unused vector
IF4
IF3
IF2
IF1
IRQ vector
—
SWI vector
Highest
—
Reset vector
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
33
Memory
2.5 Random-Access Memory (RAM)
This MCU includes static RAM. The locations in RAM below $0100 can be accessed using the more
efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation
instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program
variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait or stop mode. At power-on, the contents of
RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop
below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HC08 resets the stack pointer to $00FF. In the devices
that have RAM above $00FF, it is usually best to reinitialize the stack pointer to the top of the RAM so the
direct page RAM can be used for frequently accessed RAM variables and bit-addressable program
variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM).
LDHX
TXS
#RamLast+1
;point one past RAM
;SP<-(H:X-1)
2.6 FLASH Memory (FLASH)
The FLASH memory is intended primarily for program storage. In-circuit programming allows the
operating program to be loaded into the FLASH memory after final assembly of the application product.
It is possible to program the entire array through the single-wire monitor mode interface. Because no
special voltages are needed for FLASH erase and programming operations, in-application programming
is also possible through other software-controlled communication paths.
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from the internal VDD supply. The program and erase operations are
enabled through the use of an internal charge pump.
The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH
memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations
are facilitated through control bits in the FLASH control register (FLCR). Details for these operations
appear later in this section.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0. A security
feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult
for unauthorized users.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
34
Freescale Semiconductor
FLASH Memory (FLASH)
2.6.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass erase operation selected
0 = Mass erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
35
Memory
2.6.2 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, tNVS
5. Set the HVEN bit.
.
6. Wait for a time, tErase
7. Clear the ERASE bit.
.
8. Wait for a time, tNVH
9. Clear the HVEN bit.
.
10. After time, tRCV, the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps
5-9, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, other unrelated operations may
occur between the steps.
CAUTION
A page erase of the vector page will erase the internal oscillator trim value at $FFC0.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
36
Freescale Semiconductor
FLASH Memory (FLASH)
2.6.3 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read as a 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH memory address range.
4. Wait for a time, tNVS
5. Set the HVEN bit.
.
6. Wait for a time, tMErase
.
7. Clear the ERASE and MASS bits.
NOTE
Mass erase is disabled whenever any block is protected (FLBPR does not
equal $FF).
8. Wait for a time, tNVHL
9. Clear the HVEN bit.
.
10. After time, tRCV, the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, other unrelated operations may
occur between the steps.
CAUTION
A mass erase will erase the internal oscillator trim value at $FFC0.
1. When in monitor mode, with security sequence failed (see 16.3.2 Security), write to the FLASH block protect register
instead of any FLASH address.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
37
Memory
2.6.4 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the
following step-by-step procedure to program a row of FLASH memory
Figure 2-4 shows a flowchart of the programming algorithm.
NOTE
Do not program any byte in the FLASH more than once after a successful
erase operation. Reprogramming bits to a byte which is already
programmed is not allowed without first erasing the page in which the byte
resides or mass erasing the entire FLASH memory. Programming without
first erasing may disturb data stored in the FLASH.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, tNVS
5. Set the HVEN bit.
.
6. Wait for a time, tPGS
7. Write data to the FLASH address being programmed(1).
8. Wait for time, tPROG
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit (1)
11. Wait for time, tNVH
12. Clear the HVEN bit.
.
.
.
.
13. After time, tRCV, the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps
5-12, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum, see 17.15
Memory Characteristics.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
PGM bit, must not exceed the maximum programming time, tPROG maximum.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
38
Freescale Semiconductor
FLASH Memory (FLASH)
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
1
2
3
SET PGM BIT
READ THE FLASH BLOCK PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
WAIT FOR A TIME, tNVS
SET HVEN BIT
WAIT FOR A TIME, tPGS
7
8
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
WAIT FOR A TIME, tPROG
COMPLETED
Y
PROGRAMMING
THIS ROW?
9
N
10
CLEAR PGM BIT
WAIT FOR A TIME, tNVH
CLEAR HVEN BIT
11
12
13
NOTES:
The time between each FLASH address change (step 7 to step 7 loop),
,
or the time between the last FLASH address programmed
WAIT FOR A TIME, tRCV
END OF PROGRAMMING
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tPROG max.
This row program algorithm assumes the row/s
to be programmed is initially erased.
Figure 2-4. FLASH Programming Flowchart
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
39
Memory
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, a provision is made to protect blocks of memory from unintentional erase or program
operations due to system malfunction. This protection is done by use of a FLASH block protect register
(FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range
of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH
memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into monitor mode.
2.6.6 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can
only be written during a programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH memory.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Unaffected by reset. Initial value from factory is $FF.
Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and
bits [5:0] are 0s.
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be $XX00, $XX40, $XX80, or $XXC0 within the
FLASH memory. See Figure 2-6 and Table 2-2.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
40
Freescale Semiconductor
FLASH Memory (FLASH)
16-BIT MEMORY ADDRESS
FLBPR VALUE
START ADDRESS OF
1
1
0
0
0
0
0
0
FLASH BLOCK PROTECT
Figure 2-6. FLASH Block Protect Start Address
Table 2-2. Examples of Protect Start Address
Start of Address of Protect Range(1)
The entire FLASH memory is protected.
$EE40 (1110 1110 0100 0000)
$EE80 (1110 1110 1000 0000)
$EEC0 (1110 1110 1100 0000)
$EF00 (1110 1111 0000 0000)
and so on...
BPR[7:0]
$00–$B8
$B9 (1011 1001)
$BA (1011 1010)
$BB (1011 1011)
$BC (1011 1100)
$DE (1101 1110)
$DF (1101 1111)
$F780 (1111 0111 1000 0000)
$F7C0 (1111 0111 1100 0000)
$FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
$FE (1111 1110)
$FF
The entire FLASH memory is not protected.
1. The end address of the protected range is always $FFFF.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
41
Memory
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
42
Chapter 3
Analog-to-Digital Converter (ADC10) Module
3.1 Introduction
This section describes the 10-bit successive approximation analog-to-digital converter (ADC10).
The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for
port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference
pins. This MCU uses BUSCLKX4 as its alternate clock source for the ADC. This MCU does not have a
hardware conversion trigger.
3.2 Features
Features of the ADC10 module include:
•
•
•
•
•
•
•
•
Linear successive approximation algorithm with 10-bit resolution
Output formatted in 10- or 8-bit right-justified format
Single or continuous conversion (automatic power-down in single conversion mode)
Configurable sample time and conversion speed (to save power)
Conversion complete flag and interrupt
Input clock selectable from up to three sources
Operation in wait and stop modes for lower noise operation
Selectable asynchronous hardware conversion trigger
3.3 Functional Description
The ADC10 uses successive approximation to convert the input sample taken from ADVIN to a digital
representation. The approximation is taken and then rounded to the nearest 10- or 8-bit value to provide
greater accuracy and to provide a more robust mechanism for achieving the ideal code-transition voltage.
Figure 3-2 shows a block diagram of the ADC10
For proper conversion, the voltage on ADVIN must fall between VREFH and VREFL. If ADVIN is equal to
or exceeds VREFH, the converter circuit converts the signal to $3FF for a 10-bit representation or $FF for
a 8-bit representation. If ADVIN is equal to or less than VREFL, the converter circuit converts it to $000.
Input voltages between VREFH and VREFL are straight-line linear conversions.
NOTE
Input voltage must not exceed the analog supply voltages.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
43
Analog-to-Digital Converter (ADC10) Module
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER FLASH
USER RAM
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
POWER SUPPLY
VSS
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 3-1. Block Diagram Highlighting ADC10 Block and Pins
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
44
Functional Description
ADCSC
ADCLK
ASYNC
CLOCK
GENERATOR
ACLKEN
ACLK
1
2
ADCK
MCU STOP
ADHWT
CLOCK
DIVIDE
BUS CLOCK
CONTROL SEQUENCER
ALTERNATE CLOCK SOURCE
AD0
ADn
1
2
AIEN
INTERRUPT
COCO
ADVIN
SAR CONVERTER
VREFH
VREFL
DATA REGISTERS ADRH:ADRL
Figure 3-2. ADC10 Block Diagram
The ADC10 can perform an analog-to-digital conversion on one of the software selectable channels. The
output of the input multiplexer (ADVIN) is converted by a successive approximation algorithm into a 10-bit
digital result. When the conversion is completed, the result is placed in the data registers (ADRH and
ADRL). In 8-bit mode, the result is rounded to 8 bits and placed in ADRL. The conversion complete flag
is then set and an interrupt is generated if the interrupt has been enabled.
3.3.1 Clock Select and Divide Circuit
The clock select and divide circuit selects one of three clock sources and divides it by a configurable value
to generate the input clock to the converter (ADCK). The clock can be selected from one of the following
sources:
•
The asynchronous clock source (ACLK) — This clock source is generated from a dedicated clock
source which is enabled when the ADC10 is converting and the clock source is selected by setting
the ACLKEN bit. When the ADLPC bit is clear, this clock operates from 1–2 MHz; when ADLPC is
set it operates at 0.5–1 MHz. This clock is not disabled in STOP and allows conversions in stop
mode for lower noise operation.
•
•
Alternate Clock Source — This clock source is equal to the external oscillator clock or a four times
the bus clock. The alternate clock source is MCU specific, see 3.1 Introduction to determine source
and availability of this clock source option. This clock is selected when ADICLK and ACLKEN are
both low.
The bus clock — This clock source is equal to the bus frequency. This clock is selected when
ADICLK is high and ACLKEN is low.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
45
Analog-to-Digital Converter (ADC10) Module
Whichever clock is selected, its frequency must fall within the acceptable frequency range for ADCK. If
the available clocks are too slow, the ADC10 will not perform according to specifications. If the available
clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified
by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8.
3.3.2 Input Select and Pin Control
Only one analog input may be used for conversion at any given time. The channel select bits in ADCSC
are used to select the input signal for conversion.
3.3.3 Conversion Control
Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits.
Conversions can be initiated by either a software or hardware trigger. In addition, the ADC10 module can
be configured for low power operation, long sample time, and continuous conversion.
3.3.3.1 Initiating Conversions
A conversion is initiated:
•
•
•
Following a write to ADCSC (with ADCH bits not all 1s) if software triggered operation is selected.
Following a hardware trigger event if hardware triggered operation is selected.
Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
3.3.3.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is
high at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADRH and ADRL if the
previous data is in the process of being read while in 10-bit mode (ADRH has been read but ADRL has
not). In this case the data transfer is blocked, COCO is not set, and the new result is lost. When a data
transfer is blocked, another conversion is initiated regardless of the state of ADCO (single or continuous
conversions enabled). If single conversions are enabled, this could result in several discarded
conversions and excess power consumption. To avoid this issue, the data registers must not be read after
initiating a single conversion until the conversion completes.
3.3.3.3 Aborting Conversions
Any conversion in progress will be aborted when:
•
A write to ADCSC occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
•
•
•
A write to ADCLK occurs.
The MCU is reset.
The MCU enters stop mode with ACLK not enabled.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
46
Freescale Semiconductor
Functional Description
When a conversion is aborted, the contents of the data registers, ADRH and ADRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case
that the conversion was aborted by a reset, ADRH and ADRL return to their reset states.
Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive
state. In this state, all internal clocks and references are disabled. This state is entered asynchronously
and immediately upon aborting of a conversion.
3.3.3.4 Total Conversion Time
The total conversion time depends on many factors such as sample time, bus frequency, whether
ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1.
Table 3-1. Total Conversion Time versus Control Conditions
Conversion Mode
ACLKEN
Maximum Conversion Time
8-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
0
1
X
18 ADCK + 3 bus clock
18 ADCK + 3 bus clock + 5 µs
16 ADCK
Subsequent continuous (fBus ≥ fADCK
)
8-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
0
1
X
38 ADCK + 3 bus clock
38 ADCK + 3 bus clock + 5 µs
36 ADCK
Subsequent continuous (fBus ≥ fADCK
)
10-Bit Mode (short sample — ADLSMP = 0):
Single or 1st continuous
Single or 1st continuous
0
1
X
21 ADCK + 3 bus clock
21 ADCK + 3 bus clock + 5 µs
19 ADCK
Subsequent continuous (fBus ≥ fADCK
)
10-Bit Mode (long sample — ADLSMP = 1):
Single or 1st continuous
Single or 1st continuous
0
1
X
41 ADCK + 3 bus clock
41 ADCK + 3 bus clock + 5 µs
39 ADCK
Subsequent continuous (fBus ≥ fADCK
)
The maximum total conversion time for a single conversion or the first conversion in continuous
conversion mode is determined by the clock source chosen and the divide ratio selected. The clock
source is selectable by the ADICLK and ACLKEN bits, and the divide ratio is specified by the ADIV bits.
For example, if the alternate clock source is 16 MHz and is selected as the input clock source, the input
clock divide-by-8 ratio is selected and the bus frequency is 4 MHz, then the conversion time for a single
10-bit conversion is:
21 ADCK cycles
16 MHz/8
3 bus cycles
4 MHz
= 11.25 µs
Maximum Conversion time =
+
Number of bus cycles = 11.25 µs x 4 MHz = 45 cycles
NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet A/D specifications.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
47
Analog-to-Digital Converter (ADC10) Module
3.3.4 Sources of Error
Several sources of error exist for ADC conversions. These are discussed in the following sections.
3.3.4.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given
the maximum input resistance of approximately 15 kΩ and input capacitance of approximately 10 pF,
sampling to within
1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles / 2 MHz
maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept below 10
kΩ. Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase
the sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
3.3.4.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.
If this error cannot be tolerated by the application, keep RAS lower than VADVIN / (4096*ILeak) for less than
1/4LSB leakage error (at 10-bit resolution).
3.3.4.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC10 accuracy numbers are guaranteed as specified only if the following conditions
are met:
•
•
•
There is a 0.1µF low-ESR capacitor from VREFH to VREFL (if available).
There is a 0.1µF low-ESR capacitor from VDDA to VSSA (if available).
If inductive isolation is used from the primary supply, an additional 1µF capacitor is placed from
VDDA to VSSA (if available).
•
•
V
SSA and VREFL (if available) is connected to VSS at a quiet point in the ground plane.
The MCU is placed in wait mode immediately after initiating the conversion (next instruction after
write to ADCSC).
•
There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions
or excessive VDD noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed
in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on
the accuracy:
•
Place a 0.01 µF capacitor on the selected input channel to VREFL or VSSA (if available). This will
improve noise issues but will affect sample rate based on the external analog source resistance.
•
Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADCSC, and
executing a STOP instruction. This will reduce VDD noise but will increase effective conversion time
due to stop recovery.
•
•
Average the input by converting the output many times in succession and dividing the sum of the
results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and
averaging. Noise that is synchronous to the ADCK cannot be averaged out.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
48
Freescale Semiconductor
Functional Description
3.3.4.4 Code Width and Quantization Error
The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or
10), defined as 1LSB, is:
1LSB = (VREFH–VREFL) / 2N
Because of this quantization, there is an inherent quantization error. Because the converter performs a
conversion and then rounds to 8 or 10 bits, the code will transition when the voltage is at the midpoint
between the points where the straight line transfer function is exactly represented by the actual transfer
function. Therefore, the quantization error will be 1/2LSB in 8- or 10-bit mode. As a consequence,
however, the code width of the first ($000) conversion is only 1/2LSB and the code width of the last ($FF
or $3FF) is 1.5LSB.
3.3.4.5 Linearity Errors
The ADC10 may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the user should be aware of them because they affect overall accuracy. These errors are:
•
Zero-Scale Error (EZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first
conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is
used.
•
Full-Scale Error (EFS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the
difference between the actual $3FE code width and its ideal (1LSB) is used.
•
•
Differential Non-Linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
Integral Non-Linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual transition
voltage to a given code and its corresponding ideal transition voltage, for all codes.
•
Total Unadjusted Error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.
3.3.4.6 Code Jitter, Non-Monotonicity and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
•
Code jitter is when, at certain points, a given input voltage converts to one of two values when
sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition
voltage, the converter yields the lower code (and vice-versa). However, even very small amounts
of system noise can cause the converter to be indeterminate (between two codes) for a range of
input voltages around the transition voltage. This range is normally around 1/2 LSB but will
increase with noise.
•
•
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code
for a higher input voltage.
Missing codes are those which are never converted for any input value. In 8-bit or 10-bit mode, the
ADC10 is guaranteed to be monotonic and to have no missing codes.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
49
Analog-to-Digital Converter (ADC10) Module
3.4 Interrupts
When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU
interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at
the end of a conversion regardless of the state of AIEN.
3.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
3.5.1 Wait Mode
The ADC10 will continue the conversion process and will generate an interrupt following a conversion if
AIEN is set. If the ADC10 is not required to bring the MCU out of wait mode, ensure that the ADC10 is not
in continuous conversion mode by clearing ADCO in the ADC10 status and control register before
executing the WAIT instruction. In single conversion mode the ADC10 automatically enters a low-power
state when the conversion is complete. It is not necessary to set the channel select bits (ADCH[4:0]) to
all 1s to enter a low power state.
3.5.2 Stop Mode
If ACLKEN is clear, executing a STOP instruction will abort the current conversion and place the ADC10
in a low-power state. Upon return from stop mode, a write to ADCSC is required to resume conversions,
and the result stored in ADRH and ADRL will represent the last completed conversion until the new
conversion completes.
If ACLKEN is set, the ADC10 continues normal operation during stop mode. The ADC10 will continue the
conversion process and will generate an interrupt following a conversion if AIEN is set. If the ADC10 is
not required to bring the MCU out of stop mode, ensure that the ADC10 is not in continuous conversion
mode by clearing ADCO in the ADC10 status and control register before executing the STOP instruction.
In single conversion mode the ADC10 automatically enters a low-power state when the conversion is
complete. It is not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state.
If ACLKEN is set, a conversion can be initiated while in stop using the external hardware trigger
ADEXTCO when in external convert mode. The ADC10 will operate in a low-power mode until the trigger
is asserted, at which point it will perform a conversion and assert the interrupt when complete (if AIEN is
set).
3.6 ADC10 During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits during
the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
50
Freescale Semiconductor
I/O Signals
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
3.7 I/O Signals
The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for
port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference
pins. This MCU does not have an external trigger source.
3.7.1 ADC10 Analog Power Pin (V
)
DDA
The ADC10 analog portion uses VDDA as its power pin. In some packages, VDDA is connected internally
to VDD. If externally available, connect the VDDA pin to the same voltage potential as VDD. External filtering
may be necessary to ensure clean VDDA for good results.
NOTE
If externally available, route VDDA carefully for maximum noise immunity
and place bypass capacitors as near as possible to the package.
3.7.2 ADC10 Analog Ground Pin (V
)
SSA
The ADC10 analog portion uses VSSA as its ground pin. In some packages, VSSA is connected internally
to VSS. If externally available, connect the VSSA pin to the same voltage potential as VSS.
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies should be at the VSSA pin. This should be the only ground connection between
these supplies if possible. The VSSA pin makes a good single point ground location.
3.7.3 ADC10 Voltage Reference High Pin (V
)
REFH
VREFH is the power supply for setting the high-reference voltage for the converter. In some packages,
REFH is connected internally to VDDA. If externally available, VREFH may be connected to the same
V
potential as VDDA, or may be driven by an external source that is between the minimum VDDA spec and
the VDDA potential (VREFH must never exceed VDDA).
NOTE
Route VREFH carefully for maximum noise immunity and place bypass
capacitors as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each
successive approximation step is drawn through the VREFH and VREFL loop. The best external component
to meet this current demand is a 0.1 µF capacitor with good high frequency characteristics. This capacitor
is connected between VREFH and VREFL and must be placed as close as possible to the package pins.
Resistance in the path is not recommended because the current will cause a voltage drop which could
result in conversion errors. Inductance in this path must be minimum (parasitic only).
3.7.4 ADC10 Voltage Reference Low Pin (V
)
REFL
VREFL is the power supply for setting the low-reference voltage for the converter. In some packages,
VREFL is connected internally to VSSA. If externally available, connect the VREFL pin to the same voltage
potential as VSSA. There will be a brief current associated with VREFL when the sampling capacitor is
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
51
Analog-to-Digital Converter (ADC10) Module
charging. If externally available, connect the VREFL pin to the same potential as VSSA at the single point
ground location.
3.7.5 ADC10 Channel Pins (ADn)
The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs
improve performance in the presence of noise or when the source impedance is high. 0.01 µF capacitors
with good high-frequency characteristics are sufficient. These capacitors are not necessary in all cases,
but when used they must be placed as close as possible to the package pins and be referenced to VSSA
.
3.8 Registers
These registers control and monitor operation of the ADC10:
•
•
•
ADC10 status and control register, ADCSC
ADC10 data registers, ADRH and ADRL
ADC10 clock register, ADCLK
3.8.1 ADC10 Status and Control Register
This section describes the function of the ADC10 status and control register (ADCSC). Writing ADCSC
aborts the current conversion and initiates a new conversion (if the ADCH[4:0] bits are equal to a value
other than all 1s).
Bit 7
6
AIEN
0
5
ADCO
0
4
ADCH4
1
3
ADCH3
1
2
ADCH2
1
1
ADCH1
1
Bit 0
ADCH0
1
Read:
Write:
Reset:
COCO
0
= Unimplemented
Figure 3-3. ADC10 Status and Control Register (ADCSC)
COCO — Conversion Complete Bit
COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever
the status and control register is written or whenever the data register (low) is read.
1 = Conversion completed
0 = Conversion not completed
AIEN — ADC10 Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of a conversion. The interrupt signal is cleared
when the data register is read or the status/control register is written.
1 = ADC10 interrupt enabled
0 = ADC10 interrupt disabled
ADCO — ADC10 Continuous Conversion Bit
When this bit is set, the ADC10 will begin to convert samples continuously (continuous conversion
mode) and update the result registers at the end of each conversion, provided the ADCH[4:0] bits do
not decode to all 1s. The ADC10 will continue to convert until the MCU enters reset, the MCU enters
stop mode (if ACLKEN is clear), ADCLK is written, or until ADCSC is written again. If stop is entered
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Registers
(with ACLKEN low), continuous conversions will cease and can be restarted only with a write to
ADCSC. Any write to ADCSC with ADCO set and the ADCH bits not all 1s will abort the current
conversion and begin continuous conversions.
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADCSC
is written (assuming the ADCH[4:0] bits do not decode all 1s).
1 = Continuous conversion following a write to ADCSC
0 = One conversion following a write to ADCSC
ADCH[4:0] — Channel Select Bits
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
Table 3-2. Input Channel Select
Input Select(1)
AD0
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
AD1
0
AD2
0
AD3
1
AD4
1
AD5
1
Unused
Unused
Unused
BANDGAP REF(2)
Reserved
Reserved
VREFH
Continuing through
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
VREFL
Low-power state
1. If any unused or reserved channels are selected, the resulting conversion will be unknown.
2. Requires LVI to be powered (LVIPWRD = 0, in CONFIG1)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
53
Analog-to-Digital Converter (ADC10) Module
3.8.2 ADC10 Result High Register (ADRH)
This register holds the MSBs of the result and is updated each time a conversion completes. All other bits
read as 0s. Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the
result registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then
the intermediate conversion result will be lost. In 8-bit mode, this register contains no interlocking with
ADRL.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
Bit 0
AD8
Read:
Write:
Reset:
AD9
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode
3.8.3 ADC10 Result Low Register (ADRL)
This register holds the LSBs of the result. This register is updated each time a conversion completes.
Reading ADRH prevents the ADC10 from transferring subsequent conversion results into the result
registers until ADRL is read. If ADRL is not read until the after next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode, there is no interlocking with ADRH.
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-6. ADC10 Data Register Low (ADRL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Registers
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
Bit 7
ADLPC
0
6
ADIV1
0
5
ADIV0
0
4
ADICLK
0
3
MODE1
0
2
MODE0
0
1
Bit 0
Read:
Write:
Reset:
ADLSMP ACLKEN
0
0
Figure 3-7. ADC10 Clock Register (ADCLK)
ADLPC — ADC10 Low-Power Configuration Bit
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
ADIV[1:0] — ADC10 Clock Divider Bits
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3 shows the available clock configurations.
Table 3-3. ADC10 Clock Divide Ratio
ADIV1
ADIV0
Divide Ratio (ADIV)
Clock Rate
Input clock ÷ 1
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
0
0
1
1
0
1
0
1
1
2
4
8
ADICLK — Input Clock Select Bit
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (fADCK) between
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of 1/2LSB.
Reset returns 8-bit mode.
00 = 8-bit, right-justified, ADCSC software triggered mode enabled
01 = 10-bit, right-justified, ADCSC software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
55
Analog-to-Digital Converter (ADC10) Module
ADLSMP — Long Sample Time Configuration
This bit configures the sample time of the ADC10 to either 3.5 or 23.5 ADCK clock cycles. This adjusts
the sample period to allow higher impedance inputs to be accurately sampled or to maximize
conversion speed for lower impedance inputs. Longer sample times can also be used to lower overall
power consumption in continuous conversion mode if high conversion rates are not required.
1 = Long sample time (23.5 cycles)
0 = Short sample time (3.5 cycles)
ACLKEN — Asynchronous Clock Source Enable
This bit enables the asynchronous clock source as the input clock to generate the internal clock ADCK,
and allows operation in stop mode. The asynchronous clock source will operate between 1 MHz and
2 MHz if ADLPC is clear, and between 0.5 MHz and 1 MHz if ADLPC is set.
1 = The asynchronous clock is selected as the input clock source (the clock generator is only
enabled during the conversion)
0 = ADICLK specifies the input clock source and conversions will not continue in stop mode
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Chapter 4
Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during
stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the
AWU.
COPRS (FROM CONFIG1)
VDD
AUTOWUGEN
TO PTA READ, BIT 6
1 = DIV 29
D
E
AWUL
Q
OSCENINSTOP (FROM CONFIG2)
BUSCLKX4
SHORT
0 = DIV 214
OVERFLOW
AWUIREQ
M
U
X
R
EN
32 kHz
CLK
RST
TO KBI INTERRUPT LOGIC
(SEE Figure 9-2)
INT RC OSC
CLRLOGIC
CLEAR
RESET
ACKK
(CGMXCLK)
BUSCLKX4
CLK
RST
RESET
ISTOP
RESET
AWUIE
Figure 4-1. Auto Wakeup Interrupt Request Generation Logic
4.2 Features
Features of the auto wakeup module include:
•
One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector
and keyboard interrupt mask bit
•
•
•
•
Exit from low-power stop mode without external signals
Selectable timeout periods
Dedicated low-power internal oscillator separate from the main system clock sources
Option to allow bus clock source to run the AWU if enabled in STOP
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
57
Auto Wakeup Module (AWU)
4.3 Functional Description
The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller
unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests,
with the difference that instead of a pin, the interrupt signal is generated by an internal logic.
Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup
interrupt input (see Figure 4-1). A 1 applied to the AWUIREQ input with auto wakeup interrupt request
enabled, latches an auto wakeup interrupt request.
There exists two clock sources for the AWU. An internal RC oscillator (exclusive for the auto wakeup
feature, AWU oscillator) drives the wakeup request generator provided the OSCENINSTOP bit in the
CONFIG2 register Figure 4-1is cleared. If the application employs a crystal, for example, by setting the
OSCENINSTOP bit the BUSCLKX4 will drive the wakeup request generator to allow a more accurate
wakeup.
Entering stop mode will enable the auto wakeup generation logic.
Once the overflow count is reached in the generator counter, a wakeup request, AWUIREQ, is latched
and sent to the KBI logic. See Figure 4-1.
Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER
is set. The AWU shares the keyboard interrupt vector.
The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was
“borrowed” from the computer operating properly (COP) using the fact that the COP feature is idle (no
MCU clock available) in stop mode.
The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is
not recommended for use as a time-keeping function.
The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can
be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an
empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6
pullup/down exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register.
Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-1) has no effect on
AWUL reading.
The AWU oscillator and counters are inactive in normal operating mode and become active only upon
entering stop mode.
4.4 Interrupts
The AWU can generate an interrupt requests:.
AWU Latch (AWUL) — The AWUL bit is set when the AWU counter overflows. The auto wakeup interrupt
mask bit, AWUIE, is used to enable or disable AWU interrupt requests.
The AWU shares its interrupt with the KBI vector.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Low-Power Modes
4.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode
The AWU module remains inactive in wait mode.
4.5.2 Stop Mode
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated
automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control
register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start
from 0 each time stop mode is entered.
4.6 Registers
The AWU shares registers with the keyboard interrupt (KBI) module, the port A I/O module and
configuration register 2. The following I/O registers control and monitor operation of the AWU:
•
•
•
•
•
Port A data register (PTA)
Keyboard interrupt status and control register (KBSCR)
Keyboard interrupt enable register (KBIER)
Configuration register 1 (CONFIG1)
Configuration register 2 (CONFIG2)
4.6.1 Port A I/O Register
The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition
to the data latches for port A.
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
AWUL
PTA2
PTA5
PTA4
PTA3
PTA1
PTA0
0
0
Unaffected by reset
= Unimplemented
Figure 4-2. Port A Data Register (PTA)
AWUL — Auto Wakeup Latch
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally. There is no PTA6 port or any of the associated bits such as
PTA6 data direction or pullup/down bits.
1 = Auto wakeup interrupt request is pending
0 = Auto wakeup interrupt request is not pending
NOTE
PTA5–PTA0 bits are not used in conjuction with the auto wakeup feature.
To see a description of these bits, see 12.2.1 Port A Data Register.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
59
Auto Wakeup Module (AWU)
4.6.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
•
•
•
Flags keyboard/auto wakeup interrupt requests
Acknowledges keyboard/auto wakeup interrupt requests
Masks keyboard/auto wakeup interrupt requests
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 4-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears
the KEYF bit.
1 = Keyboard/auto wakeup interrupt pending
0 = No keyboard/auto wakeup interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto
wakeup logic. ACKK always reads as 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating
interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit.
1 = Keyboard/auto wakeup interrupt requests masked
0 = Keyboard/auto wakeup interrupt requests not masked
NOTE
MODEK is not used in conjuction with the auto wakeup feature. For a
description of this bit, see 9.8.1 Keyboard Status and Control Register
(KBSCR).
4.6.3 Keyboard Interrupt Enable Register
The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a
keyboard/auto wakeup interrupt input.
Bit 7
0
6
AWUIE
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 4-4. Keyboard Interrupt Enable Register (KBIER)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Registers
AWUIE — Auto Wakeup Interrupt Enable Bit
This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears
AWUIE.
1 = Auto wakeup enabled as interrupt input
0 = Auto wakeup not enabled as interrupt input
NOTE
KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature.
For a description of these bits, see 9.8.2 Keyboard Interrupt Enable
Register (KBIER).
4.6.4 Configuration Register 2
The configuration register 2 (CONFIG2), is used to allow the bus clock source to run in STOP. In this case,
the clock, BUSCLKX4 will be used to drive the AWU request generator.
Bit 7
IRQPUD
0
6
IRQEN
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
Read:
Write:
Reset:
OSCENINSTOP RSTEN
0
0
Figure 4-5. Configuration Register 2 (CONFIG2)
OSCENINSTOP — Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the bus clock source (BUSCLKX4) to generate clocks for the
AWU in stop mode. See 11.8.1 Oscillator Status and Control Register for information on enabling the
external clock sources.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
NOTE
IRQPUD, IRQEN, and RSTEN bits are not used in conjuction with the auto
wakeup feature. For a description of these bits, see Chapter 5
Configuration Register (CONFIG).
4.6.5 Configuration Register 1
The configuration register 1 (CONFIG1), is used to select the period for the AWU. The timeout will be
based on the COPRS bit along with the clock source for the AWU.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
COPRS
LVISTOP LVIRSTD LVIPWRD LVITRIP
SSREC
STOP
COPD
Reset:
POR:
0
0
0
0
0
0
0
0
U
0
0
0
0
0
0
0
U = Unaffected
Figure 4-6. Configuration Register 1 (CONFIG1)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
61
Auto Wakeup Module (AWU)
COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in
CONFIG2 and bus clock source (BUSCLKX4).
1 = Auto wakeup short cycle = (29) × (INTRCOSC or BUSCLKX4)
0 = Auto wakeup long cycle = (214) × (INTRCOSC or BUSCLKX4)
NOTE
LVISTOP, LVIRST, LVIPWRD, LVITRIP, SSREC and COPD bits are not
used in conjuction with the auto wakeup feature. For a description of these
bits, see Chapter 5 Configuration Register (CONFIG).
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers
enable or disable the following options:
•
•
•
•
•
•
•
•
•
•
Stop mode recovery time (32 × BUSCLKX4 cycles or 4096 × BUSCLKX4 cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS): (213–24) × BUSCLKX4 or (218–24) × BUSCLKX4
Low-voltage inhibit (LVI) enable and trip voltage selection
Auto wakeup timeout period
Allow clock source to remain enabled in STOP
Enable IRQ pin
Disable IRQ pin pullup device
Enable RST pin
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. Most of the configuration register bits are cleared during reset. Since the
various options affect the operation of the microcontroller unit (MCU) it is recommended that this register
be written immediately after reset. The configuration registers are located at $001E and $001F, and may
be read at anytime.
NOTE
The CONFIG registers are one-time writable by the user after each reset.
Upon a reset, the CONFIG registers default to predetermined settings as
shown in Figure 5-1 and Figure 5-2.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
POR:
IRQPUD
IRQEN
R
R
R
R
OSCENINSTOP RSTEN
0
0
0
0
0
0
0
0
0
0
0
0
U
0
0
0
= Reserved
U = Unaffected
R
Figure 5-1. Configuration Register 2 (CONFIG2)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
63
Configuration Register (CONFIG)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCENINSTOP— Oscillator Enable in Stop Mode Bit
OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
This function can be used to keep the auto-wakeup running while the rest of the microcontroller stops.
When clear, the clock source is disabled when the microcontroller enters stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE
The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will
leave this bit unaffected.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
POR:
COPRS
LVISTOP LVIRSTD LVIPWRD LVITRIP
SSREC
STOP
COPD
0
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1)
COPRS (Out of Stop Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = (213 – 24) × BUSCLKX4
0 = COP reset long cycle = (218 – 24) × BUSCLKX4
COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in
CONFIG2 and external clock source
1 = Auto wakeup short cycle = (29) × (INTRCOSC or BUSCLKX4)
0 = Auto wakeup long cycle = (214) × (INTRCOSC or BUSCLKX4)
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Functional Description
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVITRIP — LVI Trip Point Selection Bit
LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI
should match the operating VDD for the LVI’s voltage trip points for each of the modes.
1 = LVI operates for a 5-V protection
0 = LVI operates for a 3.3-V protection
NOTE
The LVITRIP bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Configuration Register (CONFIG)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
66
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
configuration 1 (CONFIG1) register.
6.2 Functional Description
SIM MODULE
SIM RESET CIRCUIT
12-BIT SIM COUNTER
BUSCLKX4
RESET STATUS REGISTER
INTERNAL RESET SOURCES(1)
STOP INSTRUCTION
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
CLEAR
COP COUNTER
RESET
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
1. See Chapter 13 System Integration Module (SIM) for more details.
Figure 6-1. COP Block Diagram
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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67
Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. With a 218 – 24 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator
gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12–5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 × BUSCLKX4
cycles and sets the COP bit in the reset status register (RSR). See 13.8.1 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1.
6.3.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency or the
RC-oscillator frequency.
6.3.2 STOP Instruction
The STOP instruction clears the SIM counter.
6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see Figure 6-2) clears the COP counter and
clears stages 12–5 of the SIM counter. Reading the COP control register returns the low byte of the reset
vector.
6.3.4 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 × BUSCLKX4 cycles after power
up.
6.3.5 Internal Reset
An internal reset clears the SIM counter and the COP counter.
6.3.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG).
See Chapter 5 Configuration Register (CONFIG).
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Interrupts
6.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1
(CONFIG1). See Chapter 5 Configuration Register (CONFIG).
6.4 Interrupts
The COP does not generate CPU interrupt requests.
6.5 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.6.1 Wait Mode
The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter.
6.6.2 Stop Mode
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
6.7 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
6.8 Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing
any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
LOW BYTE OF RESET VECTOR
CLEAR COP COUNTER
Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Computer Operating Properly (COP)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Chapter 7
Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a
description of the CPU instruction set, addressing modes, and architecture.
7.2 Features
Features of the CPU include:
•
•
•
•
•
•
•
•
•
•
Object code fully upward-compatible with M68HC05 Family
16-bit stack pointer with stack manipulation instructions
16-bit index register with x-register manipulation instructions
8-MHz CPU internal bus frequency
64-Kbyte program/data memory space
16 addressing modes
Memory-to-memory data moves without using accumulator
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
Enhanced binary-coded decimal (BCD) data handling
Modular architecture with expandable internal bus definition for extension of addressing range
beyond 64 Kbytes
•
Low-power stop and wait modes
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Central Processor Unit (CPU)
7
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
7
0
V
1
1
H
I
N
Z
C
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
7.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-2. Accumulator (A)
7.3.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
15 14 13 12 11 10
Bit
0
9
0
8
0
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 7-3. Index Register (H:X)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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CPU Registers
7.3.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in
random-access memory (RAM). Moving the SP out of page 0 ($0000 to
$00FF) frees direct address (page 0) space. For correct operation, the
stack pointer must point only to RAM locations.
7.3.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
15 14 13 12 11 10
Bit
0
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with vector from $FFFE and $FFFF
Figure 7-5. Program Counter (PC)
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Freescale Semiconductor
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Central Processor Unit (CPU)
7.3.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
1
1
5
1
1
4
H
X
3
2
N
X
1
Z
X
Bit 0
Read:
Write:
Reset:
V
I
C
X
1
X
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test
and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the
instructions and addressing modes and more detail about the architecture of the CPU.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.5.1 Wait Mode
The WAIT instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
•
7.5.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
7.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Central Processor Unit (CPU)
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
ꢀ
ꢀ
ꢀ
ꢀ
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
9EEB ff
9EDB ee ff
2
3
4
4
3
2
4
5
Add without Carry
A ← (A) + (M)
IX1
IX
SP1
SP2
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
AND #opr
AND opr
IMM
DIR
EXT
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IX2
Logical AND
A ← (A) & (M)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F4
SP1
SP2
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
DIR
INH
38 dd
48
4
1
1
4
3
5
ASLX
Arithmetic Shift Left
(Same as LSL)
INH
58
C
0
ꢀ
ꢀ
ASL opr,X
ASL ,X
IX1
68 ff
78
b7
b7
b0
b0
IX
ASL opr,SP
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
37 dd
47
4
1
1
4
3
5
INH
57
C
Arithmetic Shift Right
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
IX1
67 ff
77
IX
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
BGT opr
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
PC ← (PC) + 2 + rel ? (N ⊕ V) = 0
Branch if Greater Than (Signed
Operands)
3
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
76
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 2 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
3
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IX2
Bit Test
(A) & (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
F5
SP1
SP2
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
–
–
–
–
–
– REL
93 rr
3
PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 1
BLO rel
BLS rel
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
– REL
25 rr
23 rr
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
PC ← (PC) + 2 + rel ? (N ⊕ V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ꢀ
BRN rel
Branch Never
– REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
ꢀ
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
–
–
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
0
–
–
–
–
0 INH
– INH
98
9A
1
2
Clear Interrupt Mask
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
77
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
5F
CLRH
Clear
0
–
–
–
–
0
1
– INH
IX1
8C
CLR opr,X
CLR ,X
6F ff
7F
IX
SP1
CLR opr,SP
9E6F ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
IX2
Compare A with M
(A) – (M)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
F1
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
33 dd
43
4
1
1
4
3
5
COMX
INH
53
Complement (One’s Complement)
Compare H:X with M
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
1
COM opr,X
COM ,X
COM opr,SP
IX1
63 ff
73
9E63 ff
IX
SP1
CPHX #opr
CPHX opr
IMM
ꢀ
65 ii ii+1
75 dd
3
4
(H:X) – (M:M + 1)
ꢀ
DIR
CPX #opr
CPX opr
IMM
DIR
EXT
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
CPX opr
CPX ,X
IX2
Compare X with M
(X) – (M)
(A)10
ꢀ
–
–
ꢀ
ꢀ
ꢀ
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
IX1
IX
F3
SP1
SP2
9EE3 ff
9ED3 ee ff
DAA
Decimal Adjust A
U
–
–
–
–
–
ꢀ
ꢀ
ꢀ INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DIR
INH
3B dd rr
4B rr
DBNZX rel
Decrement and Branch if Not Zero
–
–
– INH
IX1
5B rr
DBNZ opr,X,rel
DBNZ X,rel
6B ff rr
7B rr
IX
SP1
DBNZ opr,SP,rel
9E6B ff rr
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
3A dd
4A
4
1
1
4
3
5
DECX
INH
5A
Decrement
Divide
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
–
DEC opr,X
DEC ,X
DEC opr,SP
IX1
6A ff
7A
9E6A ff
IX
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
ꢀ INH
52
7
EOR #opr
EOR opr
IMM
DIR
EXT
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IX2
Exclusive OR M with A
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
A ← (A ⊕ M)
IX1
IX
F8
SP1
SP2
9EE8 ff
9ED8 ee ff
INC opr
INCA
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
3C dd
4C
4
1
1
4
3
5
INCX
INH
5C
Increment
ꢀ
–
INC opr,X
INC ,X
IX1
6C ff
7C
IX
INC opr,SP
SP1
9E6C ff
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
78
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 4 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
JMP opr
DIR
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
EXT
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
– IX2
IX1
IX
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IX2
Load A from M
Load H:X from M
Load X from M
A ← (M)
H:X ← (M:M + 1)
X ← (M)
0
0
0
–
–
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
F6
SP1
SP2
9EE6 ff
9ED6 ee ff
LDHX #opr
LDHX opr
IMM
–
45 ii jj
55 dd
3
4
DIR
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
IX2
–
IX1
IX
SP1
SP2
LSL opr
LSLA
DIR
INH
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
INH
58
C
0
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
LSL opr,X
LSL ,X
LSL opr,SP
IX1
68 ff
78
9E68 ff
b7
b7
b0
b0
IX
SP1
LSR opr
LSRA
DIR
INH
34 dd
44
4
1
1
4
3
5
LSRX
INH
54
0
C
Logical Shift Right
0
ꢀ
LSR opr,X
LSR ,X
IX1
64 ff
74
IX
LSR opr,SP
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
Move
0
–
–
0
–
–
ꢀ
ꢀ
–
IMD
IX+D
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
X:A ← (X) × (A)
MUL
Unsigned multiply
–
–
0 INH
42
5
NEG opr
NEGA
DIR
INH
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
INH
50
Negate (Two’s Complement)
ꢀ
–
–
ꢀ
ꢀ
ꢀ
NEG opr,X
NEG ,X
NEG opr,SP
IX1
60 ff
70
9E60 ff
IX
SP1
NOP
NSA
No Operation
Nibble Swap A
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IX2
Inclusive OR A and M
A ← (A) | (M)
0
–
–
ꢀ
ꢀ
–
IX1
IX
FA
SP1
SP2
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
87
8B
89
2
2
2
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
79
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 5 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PULA
PULH
PULX
Pull A from Stack
Pull H from Stack
Pull X from Stack
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
86
8A
88
2
2
2
ROL opr
ROLA
DIR
INH
39 dd
49
4
1
1
4
3
5
ROLX
INH
59
C
Rotate Left through Carry
Rotate Right through Carry
ꢀ
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ROL opr,X
ROL ,X
ROL opr,SP
IX1
69 ff
79
9E69 ff
b7
b0
IX
SP1
ROR opr
RORA
DIR
INH
36 dd
46
4
1
1
4
3
5
RORX
INH
56
C
ꢀ
ROR opr,X
ROR ,X
IX1
66 ff
76
b7
b0
IX
ROR opr,SP
SP1
9E66 ff
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
–
–
–
– INH
81
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
IX2
A ← (A) – (M) – (C)
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
1
–
–
–
–
1 INH
– INH
99
9B
1
2
Set Interrupt Mask
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
ꢀ
ꢀ
– IX1
IX
F7
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
–
0
ꢀ
ꢀ
– DIR
35 dd
4
Enable Interrupts, Stop Processing,
Refer to MCU Documentation
STOP
I ← 0; Stop Processing
–
–
– INH
8E
1
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
– IX1
IX
FF
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
IX2
Subtract
A ← (A) – (M)
ꢀ
ꢀ
IX1
IX
F0
SP1
SP2
9EE0 ff
9ED0 ee ff
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
80
Opcode Map
Table 7-1. Instruction Set Summary (Sheet 6 of 6)
Effect
on CCR
Source
Form
Operation
Description
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
DIR
INH
3D dd
4D
3
1
1
3
2
4
TSTX
INH
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
ꢀ
ꢀ
–
TST opr,X
TST ,X
TST opr,SP
IX1
6D ff
7D
9E6D ff
IX
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
I bit ← 0; Inhibit CPU clocking
WAIT
Enable Interrupts; Wait for Interrupt
–
–
0
–
–
– INH
8F
1
until interrupted
A
Accumulator
n
Any bit
C
Carry/borrow bit
opr Operand (one or two bytes)
PC Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
Relative program counter offset byte
Relative program counter offset byte
H
H
Undefined
Overflow bit
Index register low byte
Zero bit
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
ii
Logical AND
Logical OR
IMD
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
⊕
Logical EXCLUSIVE OR
Contents of
( )
–( ) Negation (two’s complement)
#
IX+
Immediate value
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
:
ꢀ
—
N
Negative bit
7.8 Opcode Map
See Table 7-2.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
81
Table 7-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
NEGX
INH
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEG
NEG
NEG
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
2
IX1 3 SP1 1 IX
5
1
1
INH
2
2
2
2
1
1
REL 2 IMM 2 DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2 2 IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1 1 IX
3
BRN
REL 3 DIR
5
4
4
6
4
4
3
BLT
2
3
4
4
5
3
4
2
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
CBEQ
CBEQ
RTS
CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
IMM 3 IMM 3 IX1+
4
SP1 2 IX+
INH
REL 2 IMM 2 DIR
EXT 3 IX2
SP2 2 IX1
SP1 1 IX
3
5
7
3
2
DAA
3
BGT
2
SBC
3
SBC
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
SBC
5
SBC
SP2 2 IX1
5
CPX
SP2 2 IX1
5
AND
SP2 2 IX1
5
BIT
SP2 2 IX1
5
LDA
SP2 2 IX1
5
STA
SP2 2 IX1
5
EOR
SP2 2 IX1
5
ADC
SP2 2 IX1
3
SBC
4
SBC
SP1 1 IX
4
CPX
SP1 1 IX
4
AND
SP1 1 IX
4
BIT
SP1 1 IX
4
LDA
SP1 1 IX
4
STA
SP1 1 IX
4
EOR
SP1 1 IX
4
ADC
SP1 1 IX
2
SBC
BRSET1 BSET1
BHI
MUL
INH
DIV
INH
NSA
3
DIR
5
2
DIR
4
REL
1
1
1
2
2
3
2
2
2
2
2
INH
1
INH
3
REL 2 IMM 2 DIR
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
4
1
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
9
3
BLE
2
CPX
3
CPX
4
CPX
3
CPX
2
CPX
3
BRCLR1 BCLR1
COM
COMA
COMX
COM
COM
SWI
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
SP1 1 IX
1
1
1
1
1
1
1
1
1
1
INH
REL 2 IMM 2 DIR
4
LSR
1
LSRA
INH
1
LSRX
INH
5
LSR
SP1 1 IX
3
LSR
2
2
2
AND
IMM 2 DIR
3
AND
4
AND
3
AND
2
AND
4
BRSET2 BSET2
TAP
TXS
3
DIR
5
2
DIR
4
1
3
1
INH
INH
2
2
2
2
2
2
2
2
4
3
4
4
1
2
2
BIT
3
BIT
4
BIT
3
BIT
2
BIT
5
BRCLR2 BCLR2
STHX
LDHX
LDHX
CPHX
TPA
TSX
3
DIR
5
2
DIR
4
IMM 2 DIR
2
DIR
3
INH
INH
IMM 2 DIR
4
ROR
1
1
5
2
PULA
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
2
LDA
IMM 2 DIR
2
AIS
IMM 2 DIR
2
EOR
IMM 2 DIR
2
ADC
IMM 2 DIR
2
ORA
IMM 2 DIR
2
ADD
IMM 2 DIR
3
LDA
4
LDA
3
LDA
2
LDA
6
BRSET3 BSET3
RORA
RORX
ROR
SP1 1 IX
5
ASR
SP1 1 IX
5
LSL
SP1 1 IX
5
ROL
SP1 1 IX
ROR
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
3
BEQ
REL 2 DIR
3
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
3
ASR
1
3
STA
4
STA
3
STA
2
STA
7
BRCLR3 BCLR3
TAX
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INH
4
LSL
3
LSL
1
3
EOR
4
EOR
3
EOR
2
EOR
8
BRSET4 BSET4 BHCC
CLC
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
INH
4
ROL
3
ROL
1
3
ADC
4
ADC
3
ADC
2
ADC
9
BRCLR4 BCLR4 BHCS
SEC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
INH
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
4
DEC
5
DEC
SP1 1 IX
3
DEC
2
3
ORA
4
ORA
5
ORA
SP2 2 IX1
5
ADD
SP2 2 IX1
3
ORA
4
ORA
SP1 1 IX
4
ADD
SP1 1 IX
2
ORA
A
B
C
D
E
F
BRSET5 BSET5
CLI
3
DIR
5
2
DIR
4
INH
5
3
3
5
6
4
2
3
ADD
4
ADD
3
ADD
2
ADD
BRCLR5 BCLR5
DBNZ DBNZA DBNZX DBNZ
DBNZ
DBNZ
SEI
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
3
2
2
3
2
IX1
4
SP1 2 IX
INH
3
4
INC
5
INC
SP1 1 IX
4
TST
SP1 1 IX
3
INC
1
2
JMP
4
JMP
3
JMP
2
BRSET6 BSET6
BMC
INCA
INCX
INC
RSP
JMP
3
DIR
5
2
DIR
4
REL 2 DIR
INH
1
INH
1
IX1
3
INH
2
DIR
4
2
2
IX1
5
1
1
IX
3
BMS
3
TST
2
TST
1
4
BSR
REL 2 DIR
2
LDX
IMM 2 DIR
2
AIX
IMM 2 DIR
6
JSR
4
JSR
IX
2
LDX
BRCLR6 BCLR6
TSTA
TSTX
TST
NOP
JSR
JSR
3
DIR
5
2
DIR
4
REL 2 DIR
3
INH
5
INH
4
IX1
4
INH
2
2
2
IX1
3
4
1
STOP
INH
1
WAIT
INH
3
LDX
4
LDX
5
LDX
SP2 2 IX1
5
STX
SP2 2 IX1
4
LDX
SP1 1 IX
4
STX
SP1 1 IX
BRSET7 BSET7
BIL
MOV
MOV
MOV
MOV
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
DD
DIX+
IMD
3
2
IX+D
1
1
4
4
3
3
3
CLR
1
CLRA
INH
1
CLRX
INH
4
CLR
SP1 1 IX
2
CLR
3
STX
4
STX
3
STX
2
STX
BRCLR7 BCLR7
BIH
CLR
IX1
3
DIR
2
DIR
REL 2 DIR
3
1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
LSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
Chapter 8
External Interrupt (IRQ)
8.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero
disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the IRQ
function. See Chapter 5 Configuration Register (CONFIG) for more information on enabling the IRQ pin.
The IRQ pin shares its pin with general-purpose input/output (I/O) port pins. See Figure 8-1 for port
location of this shared pin.
8.2 Features
Features of the IRQ module include:
•
•
•
•
•
A dedicated external interrupt pin IRQ
IRQ interrupt control bits
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Internal pullup device
8.3 Functional Description
A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request. Figure 8-2
shows the structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the
following actions occurs:
•
•
•
IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that
clears the latch that caused the vector fetch.
Software clear. Software can clear the IRQ latch by writing a 1 to the ACK bit in the interrupt status
and control register (INTSCR).
Reset. A reset automatically clears the IRQ latch.
The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling
edge or falling edge and low level sensitive. The MODE bit in INTSCR controls the triggering sensitivity
of the IRQ pin.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
83
External Interrupt (IRQ)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
LOW-VOLTAGE
INHIBIT
PTB5/SLCTX
PTB6
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER RAM
USER FLASH
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
VSS
POWER SUPPLY
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 8-1. Block Diagram Highlighting IRQ Block and Pin
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
84
Freescale Semiconductor
Functional Description
RESET
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ VECTOR
FETCH
DECODER
VDD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
CLR
D
Q
IRQ
INTERRUPT
REQUEST
SYNCHRONIZER
CK
IRQ
IMASK
IRQ LATCH
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 8-2. IRQ Module Block Diagram
8.3.1 MODE = 1
If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ interrupt request:
•
•
Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear
the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling
edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK,
is clear, the CPU loads the program counter with the IRQ vector address.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
8.3.2 MODE = 0
If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch
or software clear immediately clears the IRQ latch.
The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by
IMASK, which makes it useful in applications where polling is preferred.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
85
External Interrupt (IRQ)
8.4 Interrupts
The following IRQ source can generate interrupt requests:
•
Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode..
The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
8.5.2 Stop Mode
The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of stop mode.
8.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
8.7 I/O Signals
The IRQ module does not share its pin with any module on this MCU.
8.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
86
Freescale Semiconductor
Registers
8.8 Registers
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR:
•
•
•
•
Shows the state of the IRQ flag
Clears the IRQ latch
Masks the IRQ interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Bit 7
0
6
0
5
0
4
0
3
2
0
1
IMASK
0
Bit 0
MODE
0
Read:
Write:
Reset:
IRQF
ACK
0
0
0
0
0
0
= Unimplemented
Figure 8-3. IRQ Status and Control Register (INTSCR)
IRQF — IRQ Flag Bit
This read-only status bit is set when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads 0.
IMASK — IRQ Interrupt Mask Bit
Writing a 1 to this read/write bit disables the IRQ interrupt request.
1 = IRQ interrupt request disabled
0 = IRQ interrupt request enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
1 = IRQ interrupt request on falling edges and low levels
0 = IRQ interrupt request on falling edges only
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
87
External Interrupt (IRQ)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
88
Chapter 9
Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides independently maskable external interrupts.
The KBI shares its pins with general-purpose input/output (I/O) port pins. See Figure 9-1 for port location
of these shared pins.
9.2 Features
Features of the keyboard interrupt module include:
•
Keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt
mask
•
•
•
•
Programmable edge-only or edge and level interrupt sensitivity
Edge sensitivity programmable for rising or falling edge
Level sensitivity programmable for high or low level
KBI can be configured to use either internal or external pullup/pulldown devices using PTAPUE,
see 12.2.3 Port A Input Pullup/Down Enable Register
–
When in internal device is enabled, pullup or pulldown device automatically configured based
on the polarity of edge or level detect
•
Exit from low-power modes
9.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the KBI pins.
These pins can be enabled/disabled independently of each other. See Figure 9-2.
9.3.1 Keyboard Operation
Writing to the KBIEx bits in the keyboard interrupt enable register (KBIER) independently enables or
disables each KBI pin. The polarity of the keyboard interrupt is controlled using the KBIPx bits in the
keyboard interrupt polarity register (KBIPR). Edge-only or edge and level sensitivity is controlled using the
MODEK bit in the keyboard status and control register (KBISCR).
Enabling a keyboard interrupt pin also enables its internal pullup or pulldown device based on the polarity
enabled and the corresponding port pullup/down enable bit, PTAPUEx see 12.2.3 Port A Input
Pullup/Down Enable Register. On falling edge or low level detection, a pullup device is configured. On
rising edge or high level detection, a pulldown device is configured.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
89
Keyboard Interrupt Module (KBI)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER FLASH
USER RAM
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
POWER SUPPLY
VSS
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 9-1. Block Diagram Highlighting KBI Block and Pins
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
90
Freescale Semiconductor
Functional Description
The keyboard interrupt latch is set when one or more enabled keyboard interrupt inputs are asserted.
•
If the keyboard interrupt sensitivity is edge-only, for KBIPx = 0, a falling (for KBIPx = 1, a rising)
edge on a keyboard interrupt input does not latch an interrupt request if another enabled keyboard
pin is already asserted. To prevent losing an interrupt request on one input because another input
remains asserted, software can disable the latter input while it is asserted.
•
If the keyboard interrupt is edge and level sensitive, an interrupt request is present as long as any
enabled keyboard interrupt input is asserted.
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
RESET
1
0
KBI0
VDD
S
KBIE0
KEYF
CLR
TO PULLUP/
PULLDOWN ENABLE
(see Note)
D
Q
SYNCHRONIZER
KBIP0
CK
1
0
IMASKK
KBI LATCH
KBIx
KEYBOARD
INTERRUPT
REQUEST
S
KBIEx
MODEK
TO PULLUP/
PULLDOWN ENABLE
(see Note)
KBIPx
AWUIREQ
(SEE Figure 4-1)
NOTE:
To enable internal pullup/pulldown, requires both the KBIPx and the corresponding PTAPUEN to both be set.
Figure 9-2. Keyboard Interrupt Block Diagram
9.3.1.1 MODEK = 1
If the MODEK bit is set, the keyboard interrupt inputs are both edge and level sensitive. The KBIPx bit will
determine whether a edge sensitive pin detects rising or falling edges and on level sensitive pins whether
the pin detects low or high levels. With MODEK set, both of the following actions must occur to clear a
keyboard interrupt request:
•
Return of all enabled keyboard interrupt inputs to a deasserted level. As long as any enabled
keyboard interrupt pin is asserted, the keyboard interrupt remains active.
•
Vector fetch or software clear. A KBI vector fetch generates an interrupt acknowledge signal to
clear the KBI latch. Software generates the interrupt acknowledge signal by writing a 1 to ACKK in
KBSCR. The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require
software to clear the KBI latch. Writing to ACKK prior to leaving an interrupt service routine can
also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
91
Keyboard Interrupt Module (KBI)
on the keyboard interrupt inputs. An edge detect that occurs after writing to ACKK latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the KBI vector address.
The KBI vector fetch or software clear and the return of all enabled keyboard interrupt pins to a deasserted
level may occur in any order.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt input stays asserted.
9.3.1.2 MODEK = 0
If the MODEK bit is clear, the keyboard interrupt inputs are edge sensitive. The KBIPx bit will determine
whether an edge sensitive pin detects rising or falling edges. A KBI vector fetch or software clear
immediately clears the KBI latch.
The keyboard flag bit (KEYF) in KBSCR can be read to check for pending interrupts. The KEYF bit is not
affected by IMASKK, which makes it useful in applications where polling is preferred.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
9.3.2 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device if selected
to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting IMASKK in KBSCR.
2. Enable the KBI polarity by setting the appropriate KBIPx bits in KBIPR.
3. Enable the KBI pins by setting the appropriate KBIEx bits in KBIER.
4. Write to ACKK in KBSCR to clear any false interrupts.
5. Clear IMASKK.
An interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on
the external load.
9.4 Interrupts
The following KBI source can generate interrupt requests:
•
Keyboard flag (KEYF) — The KEYF bit is set when any enabled KBI pin is asserted based on the
KBI mode and pin polarity. The keyboard interrupt mask bit, IMASKK, is used to enable or disable
KBI interrupt requests.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
92
Freescale Semiconductor
Low-Power Modes
9.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.5.1 Wait Mode
The KBI module remains active in wait mode. Clearing IMASKK in KBSCR enables keyboard interrupt
requests to bring the MCU out of wait mode.
9.5.2 Stop Mode
The KBI module remains active in stop mode. Clearing IMASKK in KBSCR enables keyboard interrupt
requests to bring the MCU out of stop mode.
9.6 KBI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
9.7 I/O Signals
The KBI module can share its pins with the general-purpose I/O pins. See Figure 9-1 for the port pins that
are shared.
9.7.1 KBI Input Pins (KBI5:KBI0)
Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be
controlled independently. Each KBI pin when enabled can be configured to use an internal pullup/pulldown
device using the corresponding PTAPUEx bit see 12.2.3 Port A Input Pullup/Down Enable Register. The
selection of pullup or pulldown is automatically configured to match the polarity selected in KBIPR.
9.8 Registers
The following registers control and monitor operation of the KBI module:
•
•
•
KBSCR (keyboard interrupt status and control register)
KBIER (keyboard interrupt enable register)
KBIPR (keyboard interrupt polarity register)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
93
Keyboard Interrupt Module (KBI)
9.8.1 Keyboard Status and Control Register (KBSCR)
Features of the KBSCR:
•
•
•
•
Flags keyboard interrupt requests
Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
Bit 7
0
6
0
5
0
4
0
3
2
1
IMASKK
0
Bit 0
MODEK
0
Read:
Write:
Reset:
KEYF
0
ACKK
0
0
0
0
0
0
= Unimplemented
Figure 9-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a 1 to this write-only bit clears the KBI request. ACKK always reads 0.
IMASKK— Keyboard Interrupt Mask Bit
Writing a 1 to this read/write bit prevents the output of the KBI latch from generating interrupt requests.
1 = Keyboard interrupt requests disabled
0 = Keyboard interrupt requests enabled
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins.
1 = Keyboard interrupt requests on edge and level
0 = Keyboard interrupt requests on edge only
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
94
Freescale Semiconductor
Registers
9.8.2 Keyboard Interrupt Enable Register (KBIER)
KBIER enables or disables each keyboard interrupt pin.
Bit 7
0
6
AWUIE
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 9-4. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt
requests.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
NOTE
KBIEx bit does not automatically enable the internal pullup/pulldown
device. Internal pullup/pulldown device is selected using the corresponding
PTAPUEx bit. Refer to PTAPUE bit description, see 12.2.3 Port A Input
Pullup/Down Enable Register.
AWUIE bit is not used in conjunction with the keyboard interrupt feature. To
see a description of this bit, see Chapter 4 Auto Wakeup Module (AWU)
9.8.3 Keyboard Interrupt Polarity Register (KBIPR)
KBIPR determines the polarity of the enabled keyboard interrupt pin and enables the appropriate pullup
or pulldown device.
Bit 7
0
6
0
5
KBIP5
0
4
KBIP4
0
3
KBIP3
0
2
KBIP2
0
1
KBIP1
0
Bit 0
KBIP0
0
Read:
Write:
Reset:
0
0
= Unimplemented
Figure 9-5. Keyboard Interrupt Polarity Register (KBIPR)
KBIP5–KBIP0 — Keyboard Interrupt Polarity Bits
Each of these read/write bits enables the polarity of the keyboard interrupt detection.
1 = Keyboard polarity is high level and/or rising edge. Port pulldown is enabled if the corresponding
PTAPUE bit is set.
0 = Keyboard polarity is low level and/or falling edge. Port pullup is enabled if the corresponding
PTAPUE bit is set.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
95
Keyboard Interrupt Module (KBI)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
96
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU
from operating below a certain operating supply voltage level. The module has several configuration
options to allow functionality to be tailored to different system level demands.
The configuration registers (see Chapter 5 Configuration Register (CONFIG)) contain control bits for this
module.
10.2 Features
Features of the LVI module include:
•
•
•
Programmable LVI reset
Selectable LVI trip voltage
Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVITRIP, and LVIRSTD are
user selectable options found in the configuration register.
VDD
STOP INSTRUCTION
LVISTOP
FROM CONFIGURATION REGISTER
FROM CONFIGURATION REGISTER
LVIRSTD
LVIPWRD
FROM CONFIGURATION REGISTER
0 IF VDD > VTRIPR
LVI RESET
LOW VDD
DETECTOR
1 IF VDD ≤ VTRIPF
LVIOUT
LVITRIP
FROM CONFIGURATION REGISTER
Figure 10-1. LVI Module Block Diagram
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
97
Low-Voltage Inhibit (LVI)
The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared,
the default state at power-on reset, VTRIPF is configured for the lower VDD operating range. The actual
trip points are specified in 17.5 5-V DC Electrical Characteristics and 17.8 3.3-V DC Electrical
Characteristics.
Because the default LVI trip point after power-on reset is configured for low voltage operation, a system
requiring high voltage LVI operation must set the LVITRIP bit during system initialization. VDD must be
above the LVI trip rising voltage, VTRIPR, for the high voltage operating range or the MCU will immediately
go into LVI reset.
After an LVI reset occurs, the MCU remains in reset until VDD rises above VTRIPR. See Chapter 13 System
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
The LVI is enabled out of reset. The following bits located in the configuration register can alter the default
conditions.
•
•
•
•
Setting the LVI power disable bit, LVIPWRD, disables the LVI.
Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (VTRIPF) for the higher VDD
operating range.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and
LVIRSTD must be set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, LVIPWRD
and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 LVI Hysteresis
The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having
VDD fall below VTRIPF), the MCU will remain in reset until VDD rises above the rising trip point voltage,
VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is
approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the typical hysteresis voltage, VHYS
.
10.3.4 LVI Trip Selection
LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is
for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range
cannot be changed after initialization.
NOTE
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (VTRIPF) may be lower than this. See Chapter 17 Electrical
Specifications for the actual trip point voltages.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
98
Freescale Semiconductor
LVI Interrupts
10.4 LVI Interrupts
The LVI module does not generate interrupt requests.
10.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.5.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.5.2 Stop Mode
If the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active. If enabled to generate resets, the LVI module can generate
a reset and bring the MCU out of stop mode.
10.6 Registers
The LVI status register (LVISR) contains a status bit that is useful when the LVI is enabled and LVI reset
is disabled.
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
R
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 10-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared
when VDD voltage rises above VTRIPR. (See Table 10-1).
Table 10-1. LVIOUT Bit Indication
VDD
LVIOUT
VDD > VTRIPR
0
VDD < VTRIPF
1
VTRIPF < VDD < VTRIPR
Previous value
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
99
Low-Voltage Inhibit (LVI)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
100
Chapter 11
Oscillator Module (OSC)
11.1 Introduction
The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus.
The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port
location of these shared pins. The OSC2EN bit is located in the port A pull enable register (PTAPUEN)
on this MCU. See Chapter 12 Input/Output Ports (PORTS) for information on PTAPUEN register.
11.2 Features
The bus clock frequency is one fourth of any of these clock source options:
1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to ± 0.4%. There are
four choices for the internal oscillator, 25.6 MHz, 12.8 MHz, 8 MHz or 4 MHz. The 12.8-MHz
internal oscillator is the default option out of reset.
2. External oscillator: An external clock that can be driven directly into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only.
The capacitor is internal to the chip.
4. External crystal: A built-in XTAL oscillator that requires an external crystal or ceramic-resonator.
There are three crystal frequency ranges supported, 8–32 MHz, 1–8 MHz, and 32–100 kHz.
11.3 Functional Description
The oscillator contains these major subsystems:
•
•
•
•
•
Internal oscillator circuit
Internal or external clock switch control
External clock circuit
External crystal circuit
External RC clock circuit
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
101
Oscillator Module (OSC)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
LOW-VOLTAGE
INHIBIT
PTB5/SLCTX
PTB6
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER RAM
USER FLASH
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
VSS
POWER SUPPLY
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 11-1. Block Diagram Highlighting OSC Block and Pins
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
102
Functional Description
11.3.1 Internal Signal Definitions
The following signals and clocks are used in the functional description and figures of the OSC module.
11.3.1.1 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM) and disables the XTAL oscillator
circuit, the RC oscillator, or the internal oscillator in stop mode. OSCENINSTOP in the configuration
register can be used to override this signal.
11.3.1.2 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. The frequency of XTALCLK can be unstable at start up.
11.3.1.3 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the
external R (REXT) and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may
not represent the actual circuitry.
11.3.1.4 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. INTCLK is software selectable to be nominally 25.6 MHz,
12.8 MHz, 8.0 MHz, or 4.0 MHz. INTCLK can be digitally adjusted using the oscillator trimming feature of
the OSCTRIM register (see 11.3.2.1 Internal Oscillator Trimming).
11.3.1.5 Bus Clock Times 4 (BUSCLKX4)
BUSCLKX4 is the same frequency as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is
driven to the SIM module and is used during recovery from reset and stop and is the clock source for the
COP module.
11.3.1.6 Bus Clock Times 2 (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4. This signal is driven to the SIM for
generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided
by two in the SIM. The internal bus frequency is one fourth of the XTALCLK, RCCLK, or INTCLK
frequency.
11.3.2 Internal Oscillator
The internal oscillator circuit is designed for use with no external components to provide a clock source
with a tolerance of less than 25% untrimmed. An 8-bit register (OSCTRIM) allows the digital adjustment
to a tolerance of ACCINT. See
the oscillator characteristics in the Electrical section of this data sheet.
The internal oscillator is capable of generating clocks of 25.6 MHz, 12.8 MHz, 8.0 MHz, or 4.0 MHz
(INTCLK) resulting in a bus frequency (INTCLK divided by 4) of 6.4 MHz, 3.2 MHz, 2.0 MHz, or 1.0 MHz
respectively. The bus clock is software selectable and defaults to the 3.2-MHz bus out of reset. Users can
increase the bus frequency based on the voltage range of their application.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
103
Oscillator Module (OSC)
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and OSC2 can output BUSCLKX4 by setting
OSC2EN.
11.3.2.1 Internal Oscillator Trimming
OSCTRIM allows a clock period adjustment of +127 and –128 steps. Increasing the OSCTRIM value
increases the clock period, which decreases the clock frequency. Trimming allows the internal clock
frequency to be fine tuned to the target frequency.
All devices are factory programmed with a trim value in a reserved memory location. This value can be
copied to the OSCTRIM register during reset initialization. For finer precision, the user can trim the
internal oscillator in the application.
11.3.2.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following
steps:
1. For external crystal circuits only, configure OSCOPT[1:0] to external crystal. To help precharge an
external crystal oscillator, momentarily configure OSC2 as an output and drive it high for several
cycles. This can help the crystal circuit start more robustly.
2. Configure OSCOPT[1:0] and ECFS[1:0] according to 11.8.1 Oscillator Status and Control Register.
The oscillator module control logic will then enable OSC1 as an external clock input and, if the
external crystal option is selected, OSC2 will also be enabled as the clock output. If RC oscillator
option is selected, enabling the OSC2 output may change the bus frequency.
3. Create a software delay to provide the stabilization time required for the selected clock source
(crystal, resonator, RC). A good rule of thumb for crystal oscillators is to wait 4096 cycles of the
crystal frequency; i.e., for a 4-MHz crystal, wait approximately 1 ms.
4. After the stabilization delay has elapsed, set ECGON.
After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external clock
rising edges. The OSC module then switches to the external clock. Logic provides a coherent transition.
The OSC module first sets ECGST and then stops the internal oscillator.
11.3.2.3 External to Internal Clock Switching
After following the procedures to switch to an external clock source, it is possible to go back to the internal
source. By clearing the OSCOPT[1:0] bits and clearing the ECGON bit, the external circuit will be
disengaged. The bus clock will be derived from the selected internal clock source based on the ICFS[1:0]
bits.
11.3.3 External Oscillator
The external oscillator option is designed for use when a clock signal is available in the application to
provide a clock source to the MCU. The OSC1 pin is enabled as an input by the oscillator module. The
clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4. The OSC2EN bit will be forced clear to
enable alternative functions on the pin.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
104
Freescale Semiconductor
Functional Description
11.3.4 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an
accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The
OSC2EN bit has no effect when this clock mode is selected.
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 11-2. This figure shows only the logical representation of the internal components and may not
represent actual circuitry.
The oscillator configuration uses five components:
•
•
•
•
•
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS (optional)
NOTE
The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the oscillator
characteristics table in the Electricals section for more information.
SIMOSCEN (internal signal) OR
OSCENINSTOP (bit located in
configuration register))
BUSCLKX4
BUSCLKX2
XTALCLK
÷ 2
MCU
OSC1
OSC2
RS
RB
X1
C1
C2
See the electrical section for details.
Figure 11-2. XTAL Oscillator External Connections
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
105
Oscillator Module (OSC)
11.3.5 RC Oscillator
The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with
a tolerance within 25% of the expected frequency. See Figure 11-3.
The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of
1% or less to minimize its effect on the frequency.
In this configuration, the OSC2 pin can be used as general-purpose input/output (I/O) port pins or other
alternative pin function. The OSC2EN bit can be set to enable the OSC2 output function on the pin.
Enabling the OSC2 output can affect the external RC oscillator frequency, fRCCLK
.
OSCOPT = EXTERNAL RC SELECTED
SIMOSCEN (internal signal) OR
OSCENINSTOP (bit located in
configuration register))
BUSCLKX2
BUSCLKX4
INTCLK
RCCLK
0
1
EXTERNAL RC
EN
÷ 2
OSCILLATOR
1
0
ALTERNATIVE
PIN FUNCTION
OSC2EN
MCU
OSC1
OSC2- available for alternative pin function
VDD
See the electricals section
for component value.
REXT
Figure 11-3. RC Oscillator External Connections
11.4 Interrupts
There are no interrupts associated with the OSC module.
11.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
11.5.1 Wait Mode
The OSC module remains active in wait mode.
11.5.2 Stop Mode
The OSC module can be configured to remain active in stop mode by setting OSCENINSTOP located in
a configuration register.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
106
Freescale Semiconductor
OSC During Break Interrupts
11.6 OSC During Break Interrupts
There are no status flags associated with the OSC module.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
11.7 I/O Signals
The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port
location of these shared pins.
11.7.1 Oscillator Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or an input
from an external clock source.
When the OSC is configured for internal oscillator, the OSC1 pin can be used as a general-purpose
input/output (I/O) port pin or other alternative pin function.
11.7.2 Oscillator Output Pin (OSC2)
For the XTAL oscillator option, the OSC2 pin is the output of the crystal oscillator amplifier.
When the OSC is configured for internal oscillator, external clock, or RC, the OSC2 pin can be used as a
general-purpose I/O port pin or other alternative pin function. When the oscillator is configured for internal
or RC, the OSC2 pin can be used to output BUSCLKX4.
Table 11-1. OSC2 Pin Function
Option
OSC2 Pin Function
XTAL oscillator
External clock
Inverting OSC1
General-purpose I/O or alternative pin function
Internal oscillator
or
RC oscillator
Controlled by OSC2EN bit
OSC2EN = 0: General-purpose I/O or alternative pin function
OSC2EN = 1: BUSCLKX4 output
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
107
Oscillator Module (OSC)
11.8 Registers
The oscillator module contains two registers:
•
•
Oscillator status and control register (OSCSC)
Oscillator trim register (OSCTRIM)
11.8.1 Oscillator Status and Control Register
The oscillator status and control register (OSCSC) contains the bits for switching between internal and
external clock sources. If the application uses an external crystal, bits in this register are used to select
the crystal oscillator amplifier necessary for the desired crystal. While running off the internal clock source,
the user can use bits in this register to select the internal clock source frequency.
Bit 7
6
5
ICFS1
1
4
ICFS0
0
3
ECFS1
0
2
ECFS0
0
1
ECGON
0
Bit 0
Read:
Write:
Reset:
ECGST
OSCOPT1 OSCOPT0
0
0
0
= Unimplemented
Figure 11-4. Oscillator Status and Control Register (OSCSC)
OSCOPT1:OSCOPT0 — OSC Option Bits
These read/write bits allow the user to change the clock source for the MCU. The default reset
condition has the bus clock being derived from the internal oscillator. See 11.3.2.2 Internal to External
Clock Switching for information on changing clock sources.
OSCOPT1
OSCOPT0
Oscillator Modes
Internal oscillator (frequency selected using ICFSx bits)
External oscillator clock
0
0
1
1
0
1
0
1
External RC
External crystal (range selected using ECFSx bits)
ICFS1:ICFS0 — Internal Clock Frequency Select Bits
These read/write bits enable the frequency to be increased for applications requiring a faster bus clock
when running off the internal oscillator. The WAIT instruction has no effect on the oscillator logic.
BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module.
ICFS1
ICFS0
Internal Clock Frequency
0
0
1
1
0
1
0
1
4.0 MHz
8.0 MHz
12.8 MHz — default reset condition
25.6 MHz
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
108
Registers
ECFS1:ECFS0 — External Crystal Frequency Select Bits
These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator
characteristics table in the Electricals section for information on maximum external clock frequency
versus supply voltage.
ECFS1
ECFS0
External Crystal Frequency
8 MHz – 32 MHz
0
0
1
1
0
1
0
1
1 MHz – 8 MHz
32 kHz – 100 kHz
Reserved
ECGON — External Clock Generator On Bit
This read/write bit enables the OSC1 pin as the clock input to the MCU, so that the switching process
can be initiated. This bit is cleared by reset. This bit is ignored in monitor mode with the internal
oscillator bypassed.
1 = External clock enabled
0 = External clock disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether an external clock source is engaged to drive the system clock.
1 = An external clock source engaged
0 = An external clock source disengaged
11.8.2 Oscillator Trim Register (OSCTRIM)
Bit 7
TRIM7
1
6
TRIM6
0
5
TRIM5
0
4
TRIM4
0
3
TRIM3
0
2
TRIM2
0
1
TRIM1
0
Bit 0
TRIM0
0
Read:
Write:
Reset:
Figure 11-5. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the internal capacitance used by the internal oscillator. By measuring the
period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can
be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the period by
approximately 0.2% of the untrimmed oscillator period. The oscillator period is based on the oscillator
frequency selected by the ICFS bits in OSCSC.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
109
Oscillator Module (OSC)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
110
Chapter 12
Input/Output Ports (PORTS)
12.1 Introduction
The MC68HC908QL4 has thirteen bidirectional input-output (I/O) pins and one input only pin. All I/O pins
are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
12.2 Port A
Port A is an 6-bit special function port that shares its pins with the keyboard interrupt (KBI) module (see
Chapter 9 Keyboard Interrupt Module (KBI), the 2-channel timer interface module (TIM) (see Chapter 15
Timer Interface Module (TIM)), the 10-bit ADC (see Chapter 3 Analog-to-Digital Converter (ADC10)
Module), the external interrupt (IRQ) pin (see Chapter 8 External Interrupt (IRQ)), the reset (RST) pin
enabled using a configuration register (see Chapter 5 Configuration Register (CONFIG)) and the
oscillator pins (see Chapter 11 Oscillator Module (OSC)).
Each port A pin also has a software configurable pullup/down device if the corresponding port pin is
configured as an input port.
NOTE
PTA2 is input only.
When the IRQ function is enabled in the configuration register 2
(CONFIG2), bit 2 of the port A data register (PTA) will always read a logic 0.
In this case, the BIH and BIL instructions can be used to read the logic level
on the PTA2 pin. When the IRQ function is disabled, these instructions will
behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will
read the actual logic level on the pin.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Input/Output Ports (PORTS)
12.2.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
Bit 7
R
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
AWUL
PTA2
PTA5
PTA4
PTA3
PTA1
PTA0
Unaffected by reset
= Unimplemented
R
= Reserved
Figure 12-1. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6
port nor any of the associated bits such as PTA6 data register, pullup/down enable or direction.
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a
1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Bit 7
R
6
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
R
0
0
0
R
= Reserved
= Unimplemented
Figure 12-2. Data Direction Register A (DDRA)
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-3 shows the port A I/O logic.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Port A
PTAPUEx
KBIPx
READ DDRA
WRITE DDRA
DDRAx
PTAx
RESET
RPULL
WRITE PTA
READ PTA
PTAx
Figure 12-3. Port A I/O Circuit
NOTE
Figure 12-3 does not apply to PTA2
When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads
the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data
direction bit.
12.2.3 Port A Input Pullup/Down Enable Register
The port A input pullup/down enable register (PTAPUE) contains a software configurable pullup/down
device for each of the port A pins. Each bit is individually configurable and requires the corresponding
data direction register, DDRAx, to be configured as input. Each pullup/down device is automatically and
dynamically disabled when its corresponding DDRAx bit is configured as output. The pull device polarity
is defined by the KBIPR register, see 9.8.3 Keyboard Interrupt Polarity Register (KBIPR).
Bit 7
OSC2EN
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-4. Port A Input Pullup/Down Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is
selected. This bit has no effect for the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup/down functions
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Input/Output Ports (PORTS)
PTAPUE[5:0] — Port A Input Pullup/Down Enable Bits
These read/write bits are software programmable to enable pullup/down devices on port A pins.
1 = Corresponding port A pin configured to have internal pullup/down if its DDRA bit is set to 0
0 = Pullup/down device is disconnected on the corresponding port A pin regardless of the state of
its DDRA bit
12.2.4 Port A Summary Table
The following table summarizes the operation of the port A pins when used as a general-purpose
input/output pins.
Table 12-1. Port A Pin Functions
Accesses to DDRA
Read/Write
Accesses to PTA
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
Read
Write
(2)
X(1)
X
PTA5–PTA0(3)
PTA5–PTA0(3)
PTA5–PTA0(5)
1
0
X
0
0
1
DDRA5–DDRA0
DDRA5–DDRA0
DDRA5–DDRA0
Pin
Pin
Input, VPull
Input, Hi-Z(4)
Output
X
PTA5–PTA0
1. X = don’t care
2. I/O pin pulled to VPull (VDD or VSS) by internal pullup or pulldown.
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
12.3 Port B
Port B is an 8-bit special function port that shares its pins with the 2-channel timer interface module (TIM)
(see Chapter 15 Timer Interface Module (TIM)), the 10-bit ADC (see Chapter 3 Analog-to-Digital
Converter (ADC10) Module), and the slave LIN interface controller (SLIC) module (see Chapter 14 Slave
LIN Interface Controller (SLIC) Module).
Each port B pin also has a software configurable pullup device if the corresponding port pin is configured
as an input port.
12.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the port B pins.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
Figure 12-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
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Port B
12.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
Figure 12-6. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-7 shows the
port B I/O logic.
READ DDRB
PTBPUEx
WRITE DDRB
DDRBx
RESET
PULLUP
WRITE PTB
PTBx
PTBx
READ PTB
Figure 12-7. Port B I/O Circuit
When DDRBx is a 1, reading PTB reads the PTBx data latch. When DDRBx is a 0, reading PTB reads
the logic level on the PTBx pin. The data latch can always be written, regardless of the state of its data
direction bit.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Input/Output Ports (PORTS)
12.3.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each
of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled
when its corresponding DDRBx bit is configured as output.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
0
0
0
0
0
0
0
0
Figure 12-8. Port B Input Pullup Enable Register (PTBPUE)
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its
DDRB bit.
12.3.4 Port B Summary Table
The following table summarizes the operation of the port A pins when used as a general-purpose
input/output pins.
Table 12-2. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Read
Write
X(1)
X
Input, Hi-Z(2)
Output
PTB7–PTB0(3)
PTB7–PTB0
0
1
DDRB7–DDRB0
DDRB7–DDRB0
Pin
Pin
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit
(MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller
that coordinates CPU and exception timing.
The SIM is responsible for:
•
Bus clock generation and control for CPU and peripherals
–
–
Stop/wait/reset/break entry and recovery
Internal clock control
•
•
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt control:
–
–
–
Acknowledge timing
Arbitration control timing
Vector address generation
•
CPU enable/disable timing
Table 13-1. Signal Name Conventions
Signal Name
Description
BUSCLKX4
Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again
divided by two in the SIM to generate the internal bus clocks
(bus clock = BUSCLKX4 ÷ 4).
BUSCLKX2
Address bus
Data bus
PORRST
IRST
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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System Integration Module (SIM)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
÷2
VDD
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
SIM RESET STATUS REGISTER
FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 13-1. SIM Block Diagram
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RST and IRQ Pins Initialization
13.2 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be
activated by programing CONFIG2 accordingly. Refer to Chapter 5 Configuration Register (CONFIG).
13.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 13-2.
FROM
OSCILLATOR
BUSCLKX4
BUSCLKX2
SIM COUNTER
FROM
OSCILLATOR
BUS CLOCK
GENERATORS
÷ 2
SIM
Figure 13-2. SIM Clock Signals
13.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four.
13.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The
IBUS clocks start upon completion of the time out.
13.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See 13.7.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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System Integration Module (SIM)
13.4 Reset and System Initialization
The MCU has these reset sources:
•
•
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 13.5 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 13.8 SIM Registers.
13.4.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum tRL time. Figure 13-3 shows the relative timing. The RST pin function is only available
if the RSTEN bit is set in the CONFIG1 register.
BUSCLKX2
RST
VECT H VECT L
ADDRESS BUS
PC
Figure 13-3. External Reset Timing
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG1 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles.
The internal reset signal then follows the sequence from the falling edge of
RST shown in Figure 13-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
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Reset and System Initialization
(see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 13-5).
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
BUSCLKX4
ADDRESS
BUS
VECTOR HIGH
Figure 13-4. Internal Reset Timing
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 13-5. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
•
•
•
•
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
•
The POR bit of the SIM reset status register (SRSR) is set.
See Figure 13-6.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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System Integration Module (SIM)
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
BUSCLKX4
BUSCLKX2
RST
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)
ADDRESS BUS
$FFFE
$FFFF
Figure 13-6. POR Recovery
13.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down
the RST pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12–5 of the SIM counter. The SIM counter output, which occurs at least
every (212 – 24) BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break
auxiliary register (BRKAR).
13.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
13.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.
13.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI
bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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SIM Counter
SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
The SIM actively pulls down the (RST) pin for all internal reset sources.
13.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of BUSCLKX4.
13.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
13.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the
normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared in the configuration
register 1 (CONFIG1).
13.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 13.7.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. See 13.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
13.6 Exception Control
Normal sequential program execution can be changed in three different ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
13.6.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 13-7 flow charts the handling of system interrupts.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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System Integration Module (SIM)
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
YES
NO
RTI
INSTRUCTION?
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
NO
Figure 13-7. Interrupt Processing
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Exception Control
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 13-8 shows
interrupt entry timing. Figure 13-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
Figure 13-8. Interrupt Entry
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
Figure 13-9. Interrupt Recovery
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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System Integration Module (SIM)
13.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 13-10 demonstrates what happens when two interrupts are pending. If an interrupt
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 13-10. Interrupt Recognition Example
13.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
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Exception Control
13.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 13-3. Interrupt Sources
INT
Register Flag
Vector
Address
Mask(1)
Priority
Source
Flag
Highest
Reset
—
—
—
—
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFEA–$FFEB
$FFE0–$FFE1
$FFDE–$FFDF
SWI instruction
IRQ pin
—
—
IRQF1
CH0F
CH1F
TOF
IMASK1
CH0IE
CH1IE
TOIE
IF1
IF3
IF4
IF5
IF9
IF14
IF15
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer overflow interrupt
SLIC interrupt
SLCF
KEYF
COCO
SLCIE
IMASKK
AIEN
Keyboard interrupt
Lowest
ADC conversion complete interrupt
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
Bit 7
IF6
R
6
5
IF4
R
4
IF3
R
3
0
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
IF5
R
R
0
R
0
R
0
0
0
0
0
0
R
= Reserved
Figure 13-11. Interrupt Status Register 1 (INT1)
IF1 and IF3–IF6 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, and 3— Always read 0
13.6.2.1 Interrupt Status Register 2
Bit 7
IF14
R
6
5
IF12
R
4
IF11
R
3
IF10
R
2
IF9
R
1
IF8
R
Bit 0
IF7
R
Read:
Write:
Reset:
IF13
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-12. Interrupt Status Register 2 (INT2)
IF7–IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
127
System Integration Module (SIM)
13.6.2.2 Interrupt Status Register 3
Bit 7
IF22
R
6
5
IF20
R
4
IF19
R
3
IF18
R
2
IF17
R
1
IF16
R
Bit 0
IF15
R
Read:
Write:
Reset:
IF21
R
0
0
0
0
0
0
0
0
R
= Reserved
Figure 13-13. Interrupt Status Register 3 (INT3)
IF15–IF22 — Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 13-3.
1 = Interrupt request present
0 = No interrupt request present
13.6.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
13.6.4 Break Interrupts
The break module can stop normal program flow at a software programmable break point by asserting its
break interrupt output. (See Chapter 16 Development Support.) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.
13.6.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
13.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power- consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Low-Power Modes
13.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 13-14 shows
the timing for wait mode entry.
ADDRESS BUS
DATA BUS
R/W
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 13-14. Wait Mode Entry Timing
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 13-15 and Figure 13-16 show the timing for wait recovery.
ADDRESS BUS
DATA BUS
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 13-15. Wait Recovery from Interrupt
32
CYCLES
32
CYCLES
ADDRESS BUS
$6E0B
$A6
RSTVCTH RSTVCTL
DATA BUS $A6
$A6
RST(1)
BUSCLKX4
1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
Figure 13-16. Wait Recovery from Internal Reset
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
129
System Integration Module (SIM)
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. If OSCENINSTOP is set, BUSCLKX4 will remain running in STOP and can be used to
run the AWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and
Figure 13-18 shows the stop mode recovery time from interrupt or break
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
CPUSTOP
ADDRESS BUS
DATA BUS
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 13-17. Stop Mode Entry Timing
STOP RECOVERY PERIOD
BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 13-18. Stop Mode Recovery from Interrupt
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Freescale Semiconductor
SIM Registers
13.8 SIM Registers
The SIM has two memory mapped registers.
13.8.1 SIM Reset Status Register
This register contains seven flags that show the source of the last reset. Clear the SIM reset status
register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Bit 7
POR
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 13-19. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented
address)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQB = VDD
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
131
System Integration Module (SIM)
13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
= Reserved
R
Figure 13-20. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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Freescale Semiconductor
Chapter 14
Slave LIN Interface Controller (SLIC) Module
14.1 Introduction
The slave LIN interface controller (SLIC) is designed to provide slave node connectivity on a local
interconnect network (LIN) sub-bus. LIN is an open-standard serial protocol developed for the automotive
industry to connect sensors, motors, and actuators.
The SLIC shares its pins with general-purpose input/output (I/O) port pins. See Figure 14-1 for port
location of these shared pins.
14.2 Features
The SLIC includes these distinctive features:
•
•
Full LIN message buffering of identifier and 8 data bytes
Automatic bit rate and LIN message frame synchronization:
–
–
–
–
–
No prior programming of bit rate required, 1–20 kbps LIN bus speed operation
All LIN messages will be received (no message loss due to synchronization process)
Input clock tolerance as high as 50%, allowing internal oscillator to remain untrimmed
Incoming break symbols always allowed to be 10 or more bit times without message loss
Supports automatic software trimming of internal oscillator using LIN synchronization data
•
•
•
•
•
•
•
•
Automatic processing and verification of LIN SYNCH BREAK and SYNCH BYTE
Automatic checksum calculation and verification with error reporting
Maximum of two interrupts per standard LIN message frame with no errors
Full LIN error checking and reporting
High-speed LIN capability up to 83.33 kbps to 120.00 kbps(1)
Configurable digital receive filter
Streamlined interrupt servicing through use of a state vector register
Switchable UART-like byte transfer mode for processing bytes one at a time without LIN message
framing constraints
•
Enhanced checksum (includes ID) generation and verification
1. Maximum bit rate of SLIC module dependent upon frequency of SLIC input clock.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
133
Slave LIN Interface Controller (SLIC) Module
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER FLASH
USER RAM
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
POWER SUPPLY
VSS
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 14-1. Block Diagram Highlighting SLIC Block and Pins
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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134
Functional Description
14.3 Functional Description
The SLIC provides full standard LIN message buffering for a slave node, minimizing the need for CPU
intervention. Routine protocol functions (such as synchronization to the communication channel,
reception, and verification of header data) and generation of the checksum are handled automatically by
the SLIC. This allows application software to be greatly simplified relative to standard UART
implementations, as well as reducing the impact of interrupts needed in those applications to handle each
byte of a message independently.
Additionally, the SLIC has the ability to automatically synchronize to any LIN message, regardless of the
LIN bus bit rate (1–20 kbps), properly receiving that message without prior programming of the target LIN
bit rate. Furthermore, this can even be accomplished using an untrimmed internal oscillator, provided its
accuracy is at least 50% of nominal.
The SLIC also has a simple UART-like byte transfer mode, which allows the user to send and receive
single bytes of data in half-duplex 8-N-1 format (8-bit data, no parity, 1 stop bit) without the need for LIN
message framing.
LSVR AND LINIF
SLCSVR CONTROL
STATUS REGISTERS
CONTROL REGISTERS
LIN PROTOCOL STATE MACHINE
(PSM)
MESSAGE BUFFER — 9 BYTES
SLCID
SLCD7, SLCD6, SLCD5, SLCD4
SLCD3, SLCD2, SLCD1, SLCD0
SHADOW REGISTER
1 BYTE
SLIC CLOCK
BUS CLOCK
DIGITAL RX FILTER
DIGITAL RX FILTER
PRESCALER (RXFP[1:0])
SLCTX
SLCRX
Figure 14-2. SLIC Module Block Diagram
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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135
Slave LIN Interface Controller (SLIC) Module
14.4 Interrupts
The SLIC module contains one interrupt vector, which can be triggered by sources encoded in the SLIC
state vector register. See 14.8.6 SLIC State Vector Register.
14.5 Modes of Operation
Figure 14-3 shows the modes in which the SLIC will operate.
POWER OFF
VDD <= VDD (MIN)
VDD > VDD (MIN) AND ANY
MCU RESET SOURCE ASSERTED
(FROM ANY MODE)
ANY MCU RESET SOURCE
ASSERTED
SLIC RESET
NO MCU RESET SOURCE ASSERTED
INITREQ = 0; (INITACK = 0)
SLIC INIT
REQUESTED
(INITACK = 1)
SLIC DISABLED
(FROM ANY MODE)
INITREQ SET TO 1 IN
SLCC1 REGISTER
SLCE SET IN SLCC2 REGISTER
SLCE CLEARED IN
SLCC2 REGISTER
NETWORK ACTIVITY
OR OTHER MCU
WAKEUP
NETWORK ACTIVITY OR OTHER
MCU WAKEUP
SLIC RUN
SLIC WAIT
SLIC STOP
(WAIT INSTRUCTION
AND SLCWCM = 0)
STOP INSTRUCTION
(WAIT INSTRUCTION
AND SLCWCM = 1)
Figure 14-3. SLIC Operating Modes
14.5.1 Power Off
This mode is entered from the reset mode whenever the SLIC module supply voltage VDD drops below
its minimum specified value for the SLIC module to guarantee operation. The SLIC module will be placed
in the reset mode by a system low-voltage reset (LVR) before being powered down. In this mode, the pin
input and output specifications are not guaranteed.
14.5.2 Reset
This mode is entered from the power off mode whenever the SLIC module supply voltage VDD rises above
its minimum specified value (VDD(MIN)) and some MCU reset source is asserted. To prevent the SLIC from
entering an unknown state, the internal MCU reset is asserted while powering up the SLIC module. SLIC
reset mode is also entered from any other mode as soon as one of the MCU's possible reset sources (e.g.,
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Modes of Operation
LVR, POR, COP watchdog, RST pin, etc.) is asserted. SLIC reset mode may also be entered by the user
software by asserting the INITREQ bit. INITACK indicates whether the SLIC module is in the reset mode
as a result of writing INITREQ in SLCC1. While in the reset state the SLIC module clocks are stopped.
Clearing the INITREQ allows the SLIC to proceed and enter SLIC run mode (if SLCE is set). The module
will clear INITACK after the module has left reset mode and the SLIC will seek the next LIN header. It is
the responsibility of the user to verify that this operation is compatible with the application before
implementing this feature.
In this mode, the internal SLIC module voltage references are operative, VDD is supplied to the internal
circuits, which are held in their reset state and the internal SLIC module system clock is running. Registers
will assume their reset condition. Outputs are held in their programmed reset state, inputs and network
activity are ignored.
14.5.3 SLIC Disabled
This mode is entered from the reset mode after all MCU reset sources are no longer asserted or INITREQ
is cleared by the user and the SLIC module clears INITACK. It is entered from the run mode whenever
SLCE in SLCC2 is cleared. In this mode the SLIC clock is stopped to conserve power and allow the SLIC
module to be configured for proper operation on the LIN bus.
14.5.4 SLIC Run
This mode is entered from the SLIC disabled mode when SLCE in SLCC2 is set. It is entered from the
SLIC wait mode whenever activity is sensed on the LIN bus or some other MCU source wakes the CPU
out of wait mode.
It is entered from the SLIC stop mode whenever network activity is sensed or some other MCU source
wakes the CPU out of stop mode. Messages will not be received properly until the clocks have stabilized
and the CPU is also in the run mode.
14.5.5 SLIC Wait
This power conserving mode is automatically entered from the run mode whenever the CPU executes a
WAIT instruction and SLCWCM in SLCC1 is previously cleared. In this mode, the SLIC module internal
clocks continue to run. Any activity on the LIN network will cause the SLIC module to exit SLIC wait mode
and return to SLIC run.
14.5.6 Wakeup from SLIC Wait with CPU in WAIT
If the CPU executes the WAIT instruction and the SLIC module enters the wait mode (SLCWCM = 0), the
clocks to the SLIC module as well as the clocks in the MCU continue to run. Therefore, the message that
wakes up the SLIC module from WAIT and the CPU from wait mode will also be received correctly by the
SLIC module. This is because all of the required clocks continue to run in the SLIC module in wait mode.
14.5.7 SLIC Stop
This power conserving mode is automatically entered from the run mode whenever the CPU executes a
STOP instruction, or if the CPU executes a WAIT instruction and SLCWCM in SLCC1 is previously set.
In this mode, the SLIC internal clocks are stopped. Any activity on the network will cause the SLIC module
to exit SLIC stop mode and generate an unmaskable interrupt of the CPU. This wakeup interrupt state is
reflected in the SLCSV, encoded as the highest priority interrupt. This interrupt can be cleared by the CPU
with a read of the SLCSV and clearing of the SLCF interrupt flag. Depending upon which low-power mode
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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137
Slave LIN Interface Controller (SLIC) Module
instruction the CPU executes to cause the SLIC module to enter SLIC stop, the message which wakes
up the SLIC module (and the CPU) may or may not be received.
There are two different possibilities:
1. Wakeup from SLIC Stop with CPU in STOP
When the CPU executes the STOP instruction, all clocks in the MCU, including clocks to the SLIC
module, are turned off. Therefore, the message which wakes up the SLIC module and the CPU
from stop mode will not be received. This is due primarily to the amount of time required for the
MCU's oscillator to stabilize before the clocks can be applied internally to the other MCU modules,
including the SLIC module.
2. Wakeup from SLIC Stop with CPU in WAIT If the CPU executes the WAIT instruction and the SLIC
module enters the stop mode (SLCWCM = 1), the clocks to the SLIC module are turned off, but the
clocks in the MCU continue to run. Therefore, the message which wakes up the SLIC module from
stop and the CPU from wait mode will be received correctly by the SLIC module. This is because
very little time is required for the CPU to turn the clocks to the SLIC module back on after the
wakeup interrupt occurs.
NOTE
While the SLIC module will correctly receive a message which arrives when
the SLIC module is in stop or wait mode and the MCU is in wait mode, if the
user enters this mode while a message is being received, the data in the
message will become corrupted. This is due to the steps required for the
SLIC module to resume operation upon exiting stop or wait mode, and its
subsequent resynchronization with the LIN bus.
14.5.8 Normal and Emulation Mode Operation
The SLIC module operates in the same manner in all normal and emulation modes. All SLIC module
registers can be read and written except those that are reserved, unimplemented, or write once. The user
must be careful not to unintentionally write a register when using 16-bit writes to avoid unexpected SLIC
module behavior.
14.5.9 Special Mode Operation
Some aspects of SLIC module operation can be modified in special test mode. This mode is reserved for
internal use only.
14.5.10 Low-Power Options
The SLIC module can save power in disabled, wait, and stop modes. A complete description of what the
SLIC module does while in a low-power mode can be found in 14.5 Modes of Operation.
14.6 SLIC During Break Interrupts
The BCFE bit in the BSCR register has no affect on the SLIC module. Therefore the SLIC modules status
bits cannot be protected during break.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
I/O Signals
14.7 I/O Signals
The SLIC module can share its two pins with the general-purpose I/O pins. See Figure 14-1 for the port
pins that are shared.
14.7.1 SLCTX — SLIC Transmit Pin
The SLCTX pin serves as the serial output of the SLIC module.
14.7.2 SLCRX — SLIC Receive Pin
The SLCRX pin serves as the serial input of the SLIC module. This input feeds directly into the digital
receive filter block which filters out noise glitches from the incoming data stream.
14.8 Registers
14.8.1 SLIC Control Register 1
SLIC control register 1 (SLCC1) contains bits used to control various basic features of the SLIC module,
including features used for initialization and at runtime.
Bit 7
0
6
0
5
INITREQ
1
4
0
3
2
1
IMSG
0
Bit 0
SLCIE
0
Read:
Write:
Reset:
WAKETX TXABRT
0
0
0
0
0
= Unimplemented
Figure 14-4. SLIC Control Register 1 (SLCC1)
INITREQ —Initialization Request
Requesting initialization mode by setting this bit will place the SLIC module into its initialized state
immediately. If transmission or reception of data is in progress, the transaction will be terminated
immediately upon entry into initialization mode (signified by INITACK being set to 1). To return to
normal SLIC operation after the SLIC has been initialized (the INITACK is high), the INITREQ must be
cleared by software.
1 = Request for SLIC to be put into reset state immediately
0 = Normal operation
WAKETX — Transmit Wakeup Symbol
This bit allows the user to transmit a wakeup symbol on the LIN bus. When set, this sends a wakeup
symbol, as defined in the LIN specification a single time, then resets to 0. This bit will read 1 while the
wakeup symbol is being transmitted on the bus. This bit will be automatically cleared when the wakeup
symbol is complete.
1 = Send wakeup symbol on LIN bus
0 = Normal operation
TXABRT — Transmit Abort Message
1 = Transmitter aborts current transmission at next byte boundary; TXABRT resets to 0 after the
transmission is successfully aborted
0 = Normal operation
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Slave LIN Interface Controller (SLIC) Module
IMSG — SLIC Ignore Message Bit
IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC module after the next
BREAK/SYNC symbol pair is validated. After it is set, IMSG will not keep data from being written to the
receive data buffer, which means that the buffers cannot be assumed to contain known valid message
data until the next receive buffer full interrupt. IMSG must not be used in BTM mode.
1 = SLIC to ignore data field of message, SLIC interrupts are suppressed until the next message
header arrives
0 = Normal operation
SLCIE — SLIC Interrupt Enable
1 = SLIC interrupt sources are enabled
0 = SLIC interrupt sources are disabled
14.8.2 SLIC Control Register 2
SLIC control register 2 (SLCC2) contains bits used to control various features of the SLIC module.
Bit 7
0
6
0
5
0
4
0
3
SLCWCM
0
2
BTM
0
1
0
Bit 0
SLCE
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 14-5. SLIC Control Register 2 (SLCC2)
SLCWCM — SLIC Wait Clock Mode
This bit can only be written once out of reset state.
1 = SLIC clocks stop when the CPU is placed into wait mode
0 = SLIC clocks continue to run when the CPU is placed into wait mode so that the SLIC can receive
messages and wakeup the CPU.
BTM — UART Byte Transfer Mode
Byte transmit mode bypasses the normal LIN message framing and checksum monitoring and allows
the user to send and receive single bytes in a method similar to a half-duplex UART. When enabled,
this mode reads the bit time register (SLCBT) value and assumes this is the value corresponding to
the number of SLIC clock counts for one bit time to establish the desired UART bit rate. The user
software must initialize this register prior to sending or receiving data, based on the input clock
selection, prescaler stage choice, and desired bit rate.
BTM forces the data length in SLCDLC to one byte (DLC = 0x00) and disables the checksum circuitry
so that CHKMOD has no effect. Refer to 14.9.15 Byte Transfer Mode Operation for more detailed
information about how to use this mode. BTM sets up the SLIC module to send and receive one byte
at a time, with 8-bit data, no parity, and one stop bit (8-N-1). This is the most commonly used setup for
UART communications and should work for most applications. This is fixed in the SLIC and is not
configurable.
1 = UART byte transfer mode enabled
0 = UART byte transfer mode disabled
SLCE — SLIC Module Enable
1 = SLIC module enabled
0 = SLIC module disabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Registers
NOTE
To guarantee timing, the user must ensure that the SLIC clock used allows
the proper communications timing tolerances and therefore internal
oscillator circuits might not be appropriate for use with BTM mode.
14.8.3 SLIC Status Register
SLIC status register (SLCS) contains bits used to monitor the status of the SLIC module.
Bit 7
Read: SLCACT
Write:
6
0
5
4
0
3
0
2
0
1
0
Bit 0
SLCF
0
INITACK
Reset:
0
0
1
0
0
0
0
= Unimplemented
Figure 14-6. SLIC Status Register (SLCS)
SLCACT — SLIC Active (Oscillator Trim Blocking Semaphore)
SLCACT is used to indicate if it is safe to trim the oscillator based upon current SLIC activity in LIN
mode. This bit indicates that the SLIC module might be currently receiving a message header,
synchronization byte, ID byte, or sending or receiving data bytes. This bit is read-only.
1 = SLIC module activity (not safe to trim oscillator)
SLCACT is automatically set to 1 if a falling edge is seen on the SLCRX pin and has
successfully been passed through the digital RX filter. This edge is the potential beginning of a
LIN message frame.
0 = SLIC module not active (safe to trim oscillator)
SLCACT is cleared by the SLIC module only upon assertion of the RX Message Buffer Full
Checksum OK (SLCSV = $10) or the TX Message Buffer Empty Checksum Transmitted
(SLCSV = $08) interrupt sources.
NOTE
SLCACT may not be clear during all idle times of the bus. For example, if
IMSG was used to ignore the data interrupts of an extended message
frame, SLCACT will remain set until another LIN message is received and
either the RX Message Buffer Full Checksum OK (SLCSV = $10) or the TX
Message Buffer Empty Checksum Transmitted (SLCSV = $08) interrupt
sources are asserted and cleared. When clear, SLCACT always indicates
times when the SLIC module is not active, but it is possible for the SLIC
module to be not active with SLCACT set. SLCACT has no meaning in BTM
mode.
INITACK — Initialization Mode Acknowledge
INITACK indicates whether the SLIC module is in the reset mode as a result of writing INITREQ in
SLCC1. While in the reset state the SLIC module clocks are stopped. Clearing the INITREQ allows the
SLIC to proceed and enter SLIC run mode (if SLCE is set). The module will clear INITACK after the
module has left reset mode and the SLIC will seek the next LIN header. This bit is read-only.
1 = SLIC module is in reset state
0 = Normal operation
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
141
Slave LIN Interface Controller (SLIC) Module
SLCF — SLIC Interrupt Flag
The SLCF interrupt flag indicates if a SLIC module interrupt is pending. If set, the SLCSV is then used
to determine what interrupt is pending. This flag is cleared by writing a 1 to the bit. If additional interrupt
sources are pending, the bit will be automatically set to 1 again by the SLIC.
1 = SLIC interrupt pending
0 = No SLIC interrupt pending
14.8.4 SLIC Prescaler Register
SLIC prescaler register (SLCP) is used to configure the delay of the digital receive filter circuit, and hence
the width of noise pulse which is blocked by the filter. The SLIC clock is used to drive the digital receive
circuit. Variations on the input clock will affect filter performance proportionally, so if internal oscillators
are used, worst case oscillator frequencies must be accounted for when determining prescaler settings
to ensure that the frequency of the SLIC clock always remains between 2 MHz and 8 MHz.
Bit 7
RXFP1
1
6
RXFP0
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 14-7. SLIC Prescale Register (SLCP)
Table 14-1. Digital Receive Filter Clock Prescaler
Maximum Filter Delay (in µs)
Digital RX Filter
RXFP[1:0]
Clock Prescaler
(Divide by)
SLIC Clock (in MHz)
2
3.2
5
4
4
6
6.4
2.5
5
8
$00
$01
$10
$11
1
8
2.67
5.33
8
2
4
6
8
2
3 (default)
4
16
24
32
10
15
20
8
12
16
7.5
10
10.67
RXFP[1:0] — Receive Filter Prescaler
These bits configure the effective filter width for the digital receive filter circuit. The RXFP bits control
the maximum number of SLIC clock counts required for the filter to change state, which determines
the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be
rejected by the filter and ignored as noise. For this reason, the user must choose the prescaler value
appropriately to ensure that all valid message traffic is able to pass the filter for the desired bit rate. For
more details about setting up the digital receive filter, please refer to 14.9.17 Digital Receive Filter.
The frequency of the SLIC clock must be between 2 MHz and 8 MHz, factoring in worst case possible
numbers due to untrimmed process variations, as well as temperature and voltage variations in oscillator
frequency. This will guarantee greater than 1.5% accuracy for all LIN messages from 1–20 kbps. The
faster this input clock is, the greater the resulting accuracy and the higher the possible bit rates at which
the SLIC can send and receive. In LIN systems, the bit rates will not exceed 20 kbps; however, the SLIC
module is capable of much higher speeds without any configuration changes, for cases such as
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
142
Freescale Semiconductor
Registers
high-speed downloads for reprogramming of FLASH memory or diagnostics in a test environment where
radiated emissions requirements are not as stringent. In these situations, the user may choose to run
faster than the 20 kbps limit which is imposed by the LIN specification for EMC reasons. Details of how
to calculate maximum bit rates and operate the SLIC above 20 kbps are detailed in 14.9.14 High-Speed
LIN Operation. Refer to 14.9.6 SLIC Module Initialization Procedure for more information on when to set
up this register.
14.8.5 SLIC Bit Time Registers
NOTE
In this subsection, the SLIC bit time registers are collectively referred to as
SLCBT.
In LIN operating mode (BTM = 0), the SLCBT is updated by the SLIC upon reception of a LIN break-synch
combination and provides the number of SLIC clock counts that equal one LIN bit time to the user
software. This value can be used by the software to calculate the clock drift in the oscillator as an offset
to a known count value (based on nominal oscillator frequency and LIN bus speed). The user software
can then trim the oscillator to compensate for clock drift. Refer to 14.9.16 Oscillator Trimming with SLIC
for more information on this procedure. The user cannot read the bit time value from SLCBTH and
SLCBTL any time after the identifier byte is received until the beginning of the next LIN message frame
on the bus. The beginning of this message frame activity will be indicated by SLCACT.
When in byte transfer mode (BTM = 1), the SLCBT must be written by the user to set the length of one
bit at the desired bit rate in SLIC clock counts. The user software must initialize this number prior to
sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate.
This setting is similar to choosing an input capture or output compare value for a timer. The closest even
value must be chosen for this value, as BT0 will be forced to 0 by the SLIC module and any odd value will
always be reduced to the next lowest even integer value. For example, a write of value 51 (0x33) will be
forced to value of 50 and read back as 0x32. A write to both registers is required to update the bit time
value.
NOTE
The SLIC bit time will not be updated until a write of the SLCBTL has
occurred.
Bit 7
0
6
0
5
0
4
BT12
0
3
BT11
0
2
BT10
0
1
BT9
0
Bit 0
BT8
0
Read:
Write:
Reset:
0
0
0
= Unimplemented
Figure 14-8. SLIC Bit Time Register High (SLCBTH)
Bit 7
BT7
0
6
BT6
0
5
BT5
0
4
BT4
0
3
BT3
0
2
BT2
0
1
BT1
0
Bit 0
0
Read:
Write:
Reset:
0
= Unimplemented
Figure 14-9. SLIC Bit Time Register Low (SLCBTL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
143
Slave LIN Interface Controller (SLIC) Module
BT — Bit Time Value
BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of
the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to 14.9.16
Oscillator Trimming with SLIC.
BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details
of the use of the SLCBT registers in BTM mode, refer to 14.9.15 Byte Transfer Mode Operation.
NOTE
Do not write to unimplemented bits as unexpected operation may occur.
14.8.6 SLIC State Vector Register
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
Bit 7
0
6
0
5
4
3
2
1
0
Bit 0
0
Read:
Write:
Reset:
I3
I2
I1
I0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-10. SLIC State Vector Register (SLCSV)
READ: any time
WRITE: ignored
I[3:0] — Interrupt State Vector (Bits 5–2)
These bits indicate the source of the interrupt request that is currently pending.
14.8.6.1 LIN Mode Operation
Table 14-2 shows the possible values for the possible sources for a SLIC interrupt while in LIN mode
operation (BTM = 0).
Table 14-2. Interrupt Sources Summary (BTM = 0)
SLCSV
$00
I3
0
I2
0
I1
0
I0
0
Interrupt Source
No Interrupts Pending
No-Bus-Activity
Priority
0 (Lowest)
1
$04
0
0
0
1
TX Message Buffer Empty
Checksum Transmitted
$08
$0C
$10
0
0
0
0
0
1
1
1
0
0
1
0
2
3
4
TX Message Buffer Empty
RX Message Buffer Full
Checksum OK
RX Data Buffer Full
No Errors
$14
$18
0
0
1
1
0
1
1
0
5
6
Bit-Error
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
144
Registers
Table 14-2. Interrupt Sources Summary (BTM = 0) (Continued)
SLCSV
$1C
$20
I3
0
1
1
1
1
1
1
1
1
I2
1
0
0
0
0
1
1
1
1
I1
1
0
0
1
1
0
0
1
1
I0
1
0
1
0
1
0
1
0
1
Interrupt Source
Receiver Buffer Overrun
Reserved
Priority
7
8
$24
Checksum Error
9
$28
Byte Framing Error
Identifier Received Successfully
Identifier Parity Error
Inconsistent-Synch-Field-Error
Reserved
10
$2C
$30
11
12
$34
13
14
$38
$3C
Wakeup
15 (Highest)
•
•
No Interrupts Pending
This value indicates that all pending interrupt sources have been serviced. In polling mode, the
SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate
an interrupt of the CPU, regardless of state of SLCIE.
No Bus Activity (LIN specified error)
The No-Bus-Activity condition occurs if no valid SYNCH BREAK FIELD or BYTE FIELD was
received for more than 223 SLIC clock counts since the reception of the last valid message. For
example, with 6.4 MHz SLIC clock frequency, a No-Bus-Activity interrupt will occur about 1.31
seconds after the bus begins to idle.
•
•
•
TX Message Buffer Empty — Checksum Transmitted
When the entire LIN message frame has been transmitted successfully, complete with the
appropriately selected checksum byte, this interrupt source is asserted. This source is used for all
standard LIN message frames and the final set of bytes with extended LIN message frames.
TX Message Buffer Empty
This interrupt source indicates that all 8 bytes in the LIN message buffer have been transmitted
with no checksum appended. This source is used for intermediate sets of 8 bytes in extended LIN
message frames.
RX Message Buffer Full — Checksum OK
When the entire LIN message frame has been received successfully, complete with the
appropriately selected checksum byte, and the checksum calculates correctly, this interrupt source
is asserted. This source is used for all standard LIN message frames and the final set of bytes with
extended LIN message frames. To clear this source, SLCD0 must be read first.
RX Data Buffer Full — No Errors
This interrupt source indicates that 8 bytes have been received with no checksum byte and are
waiting in the LIN message buffer. This source is used for intermediate sets of 8 bytes in extended
LIN message frames. To clear this source, SLCD0 must be read first.
Bit Error
•
•
A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at
that bit time, when the bit value that is monitored is different from the bit value that is sent. The
SLIC will terminate the data transmission upon detection of a bit error, according to the LIN
specification. Bit errors are not checked when the LIN bus is running at high speed due to the
effects of physical layer round trip delay. Bit errors are fully checked at all LIN 2.0 compliant speeds
of 20 kbps and below.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Slave LIN Interface Controller (SLIC) Module
•
•
•
Receiver Buffer Overrun Error
This error is an indication that the receive buffer has not been emptied and additional bytes have
been received, resulting in lost data. Because this interrupt is higher priority than the receive buffer
full interrupts, it will appear first when an overflow condition occurs. There will, however, be a
pending receive interrupt which must also be cleared after the buffer overrun flag is cleared.
Checksum Error (LIN specified error)
The checksum error occurs when the calculated checksum value does not match the expected
value. If this error is encountered, it is important to verify that the correct checksum calculation
method was employed for this message frame. Refer to the LIN specification for more details on
the calculations.
Byte Framing Error
This error comes from the standard UART definition for byte encoding and occurs when the STOP
bit is sampled and reads back as a 0. STOP should always read as 1. In LIN mode (BTM=0), if a
byte framing error occurs in an identifier byte of a LIN header the user must set and then clear
CHKMOD to ensure that the checksum calculation is reset. Failure to do so can result in an
improperly calculated enhanced checksum for the subsequent LIN frame. Because any byte
framing error indicates a corrupted byte, the best practice is to always toggle CHKMOD in the case
of a byte framing error.
NOTE
A byte framing error can also be an indication that the number of data bytes
received in a LIN message frame does not match the value written to the
SLCDLC register. See 14.9.7 Handling LIN Message Headers for more
details.
•
•
Identifier Received Successfully
This interrupt source indicates that a LIN identifier byte has been received with correct parity and
is waiting in the LIN identifier buffer (SLCID). Upon reading this interrupt source from SLCSV, the
user can then decode the identifier in software to determine the nature of the LIN message frame.
To clear this source, SLCID must be read.
Identifier-Parity-Error
A parity error in the identifier (i.e., corrupted identifier) will be flagged. Typical LIN slave
applications do not distinguish between an unknown but valid identifier, and a corrupted identifier.
However, it is mandatory for all slave nodes to evaluate in case of a known identifier all eight bits
of the ID-Field and distinguish between a known and a corrupted identifier. The received identifier
value is reported in SLCID so that the user software can choose to acknowledge or ignore the
parity error message.
•
•
Inconsistent-Synch-Field-Error
An Inconsistent-Synch-Field-Error must be detected if a slave detects the edges of the SYNCH
FIELD outside the given tolerance.
Wakeup
The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC
stop mode.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Registers
14.8.6.2 Byte Transfer Mode Operation
When byte transfer mode is enabled (BTM = 1), many of the interrupt sources for the SLCSV no longer
apply, as they are specific to LIN operations. Table 14-3 shows those interrupt sources which are
applicable to BTM operations. The value of the SLCSV for each interrupt source remains the same, as
well as the priority of the interrupt source.
I
Table 14-3. Interrupt Sources Summary (BTM = 1)
SLCSV
$00
I3
0
I2
0
I1
0
I0
0
Interrupt Source
No Interrupts Pending
TX Message Buffer Empty
Priority
0 (Lowest)
3
$0C
0
0
1
1
RX Data Buffer Full
No Errors
$14
0
1
0
1
5
$18
$1C
$28
$38
$3C
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
0
1
Bit-Error
Receiver Buffer Overrun
Byte Framing Error
Reserved
6
7
10
14
Wakeup
15 (Highest)
•
No Interrupts Pending
This value indicates that all pending interrupt sources have been serviced. In polling mode, the
SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate
an interrupt of the CPU, regardless of state of SLCIE.
•
•
•
•
TX Message Buffer Empty
In byte transfer mode, this interrupt source indicates that the byte in the SLCID has been
transmitted.
RX Data Buffer Full — No Errors
This interrupt source indicates that a byte has been received and is waiting in SLCID. To clear this
source, SLCID must be read first.
Bit-Error
A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR must be detected at
that bit time, when the bit value that is monitored is different from the bit value that is sent.
Receiver Buffer Overrun Error
This error is an indication that the receive buffer has not been emptied and additional byte(s) have
been received, resulting in lost data. Because this interrupt is higher priority than the receive buffer
full interrupts, it will appear first when an overflow condition occurs. There will, however, be a
pending receive interrupt which must also be cleared after the buffer overrun flag is cleared.
Byte Framing Error
This error comes from the standard UART definition for byte encoding and occurs when STOP is
sampled and reads back as a 0. STOP should always read as 1.
Wakeup
•
•
The wakeup interrupt source indicates that the SLIC module has entered SLIC run mode from SLIC
wait mode.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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147
Slave LIN Interface Controller (SLIC) Module
14.8.7 SLIC Data Length Code Register
The SLIC data length code register (SLCDLC) is the primary functional control register for the SLIC
module during normal LIN operations. It contains the data length code of the message buffer, indicating
how many bytes of data are to be sent or received, as well as the checksum mode control and transmit
enabling bit.
Bit 7
TXGO
0
6
CHKMOD
0
5
DLC5
0
4
DLC4
0
3
DLC3
0
2
DLC2
0
1
DLC1
0
Bit 0
DLC0
0
Read:
Write:
Reset:
Figure 14-11. SLIC Data Length Code Register (SLCDLC)
TXGO — SLIC Transmit Go
This bit controls whether the SLIC module is sending or receiving data bytes. This bit is automatically
reset to 0 after a transmit operation is complete or an error is encountered and transmission has been
aborted.
1 = Initiate SLIC transmit
The SLIC assumes the user has loaded the proper data into the message buffer and will begin
transmitting the number of bytes indicated in the SLCDLC bits. If the number of bytes is greater
than 8, the first 8 bytes will be transmitted and an interrupt will be triggered (if unmasked) for
the user to enter the next bytes of the message. If the number of bytes is 8 or fewer, the SLIC
will transmit the appropriate number of bytes and automatically append the checksum to the
transmission.
0 = SLIC receive data
CHKMOD — LIN Checksum Mode
CHKMOD is used to decide what checksum method to use for this message frame. Resets after error
code or message frame complete. CHKMOD must be written (if desired) only after the reception of an
identifier and before the reception or transmission of data bytes. Writing this bit to a one clears the
current checksum calculation. The one exception is when a byte framing error is detected and the
checksum calculation should be reset. (See Byte Framing Error description in section 14.8.6.1 LIN
Mode Operation.)
1 = Checksum calculated without the identifier byte (LIN spec <= 1.3)
0 = Checksum calculated with the identifier byte included
(SAE J2602/LIN 2.0)
DLC — Data Length Control Bits
The value of the bits indicate the number of data bytes in message. Values $00–$07 are for “normal”
LIN messaging. Values $08–$3F are for “extended” LIN messaging.
Table 14-4. Data Length Control
DLC[5:0]
$00
Message Data Length (Number of Bytes)
1
2
$01
$02
3
...
...
62
63
64
$3D
$3E
$3F
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
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Registers
14.8.8 SLIC Identifier and Data Registers
The SLIC identifier (SLCID) and eight data registers (SLCD7–SLCD0) comprise the transmit and receive
buffer and are used to read/write the identifier and message buffer 8 data bytes. In BTM mode (BTM = 1),
only SLCID is used to send and receive bytes, as only one byte is handled at any one time. The number
of bytes to be read from or written to these registers is determined by the user software and written to
SLCDLC. To obtain proper data, reads and writes to these registers must be made based on the proper
length corresponding to a particular message. It is the responsibility of the user software to keep track of
this value to prevent data corruption. For example, it is possible to read data from locations in the
message buffer which contain erroneous or old data if the user software reads more data registers than
were updated by the incoming message, as indicated in SLCDLC.
NOTE
An incorrect length value written to SLCDLC can result in the user software
misreading or miswriting data in the message buffer. An incorrect length
value might also result in SLIC error messages. For example, if a 4-byte
message is to be received, but the user software incorrectly reports a
3-byte length to the DLC, the SLIC will assume the 4th data byte is actually
a checksum value and attempt to validate it as such. If this value doesn’t
match the calculated value, an incorrect checksum error will occur. If it does
happen to match the expected value, then the message would be received
as a 3-byte message with valid checksum. Either case is incorrect behavior
for the application and can be avoided by ensuring that the correct length
code is used for each identifier.
The first data byte received after the LIN identifier in a LIN message frame will be loaded into SLCD0. The
next byte (if applicable) will be loaded into SLCD1, and so forth.
.
Bit 7
R7
T7
0
6
R6
T6
0
5
R5
T5
0
4
R4
T4
0
3
R3
T3
0
2
R2
T2
0
1
R1
T1
0
Bit 0
R0
T0
0
Read:
Write:
Reset:
Figure 14-12. SLIC Identifier Register (SLCID)
The SLIC identifier register is used to capture the incoming LIN identifier and when the SLCSV value
indicates that the identifier has been received successfully, this register contains the received identifier
value. If the incoming identifier contained a parity error, this register value will not contain valid data.
In byte transfer mode (BTM = 1), this register is used for sending and receiving each byte of data. When
transmitting bytes, the data is loaded into this register, then TXGO in SLCDLC is set to initiate the
transmission. When receiving bytes, they are read from this register only.
Bit 7
R7
T7
0
6
R6
T6
0
5
R5
T5
0
4
R4
T4
0
3
R3
T3
0
2
R2
T2
0
1
R1
T1
0
Bit 0
R0
T0
0
Read:
Write:
Reset:
Figure 14-13. SLIC Data Register x (SLCD7–SLCD0)
R — Read SLC Receive Data
T — Write SLC Transmit Data
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
149
Slave LIN Interface Controller (SLIC) Module
14.9 Initialization/Application Information
The LIN specification defines a standard LIN “MESSAGE FRAME” as the basic format for transferring
data across a LIN network. A standard MESSAGE FRAME is composed as shown in Figure 14-14 (shown
with 8 data bytes).
LIN transmits all data, identifier, and checksum characters as standard UART characters with eight data
bits, no parity, and one stop bit. Therefore, each byte has a length of 10 bits, including the start and stop
bits. The data bits are transmitted least significant bit (LSB) first.
HEADER
DATA
0x55
SYNCH
BREAK
SYNCH
BYTE
IDENT
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
DATA
FIELD
CHECKSUM
FIELD
0
1
2
3
4
5
6
7
13 OR MORE BITS (LIN 1.3)
Figure 14-14. Typical LIN MESSAGE FRAME
14.9.1 LIN Message Frame Header
The HEADER section of all LIN messages is transmitted by the master node in the network and contains
synchronization data, as well as the identifier to define what information is to be contained in the message
frame. Formally, the header is comprised of three parts:
1. SYNCH BREAK
2. SYNCH BYTE (0x55)
3. IDENTIFIER FIELD
The first two components are present to allow the LIN slave nodes to recognize the beginning of the
message frame and derive the bit rate of the master module.
The SYNCH BREAK allows the slave to see the beginning of a message frame on the bus. The SLIC
module can receive a standard 10-bit break character for the SYNCH BREAK, or any break symbol 10 or
more bit times in length. This encompasses the LIN requirement of 13 or more bits of length for the
SYNCH BREAK character.
The SYNCH BYTE is always a 0x55 data byte, providing five falling edges for the slave to derive the bit
rate of the master node.
The identifier byte indicates to the slave what is the nature of the data in the message frame. This data
might be supplied from either the master node or the slave node, as determined at system design time.
The slave node must read this identifier, check for parity errors, and determine whether it is to send or
receive data in the data field.
More information on the HEADER is contained in 14.9.7.1 LIN Message Headers.
14.9.2 LIN Data Field
The data field is comprised of standard bytes (eight data bits, no parity, one stop bit) of data, from 0–8
bytes for normal LIN frames and greater than eight bytes for extended LIN frames. The SLIC module will
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either transmit or receive these bytes, depending upon the user code interpretation of the identifier byte.
Data is always transmitted into the data field least significant byte (LSB) first.
The SLIC module can automatically handle up to 64 bytes in extended LIN message frames without
significantly changing program execution.
14.9.3 LIN Checksum Field
The checksum field is a data integrity measure for LIN message frames, used to signal errors in data
consistency. The LIN 1.3 checksum calculation only covers the data field, but the SLIC module also
supports an enhanced checksum calculation which also includes the identifier field. For more information
on the checksum calculation, refer to 14.9.13 LIN Data Integrity Checking Methods.
14.9.4 SLIC Module Constraints
In designing a practical module, certain reasonable constraints must be placed on the LIN message traffic
which are not necessarily explicitly specified in the LIN specification. The SLIC module presumes that:
•
Timeout for no-bus-activity = 1 second.
14.9.5 SLCSV Interrupt Handling
Each change of state of the SLIC module is encoded in the SLIC state vector register (SLCSV). This is
an efficient method of handling state changes, indicating to the user not only the current status of the SLIC
module, but each state change will also generate an interrupt (if SLIC interrupts are enabled). For more
detailed information on the SLCSV, please refer to 14.8.6 SLIC State Vector Register.
In the software diagrams in the following subsections, when an interrupt is shown, the first step must
always be reading SLCSV to determine what is the current status of the SLIC module. Likewise, when the
diagrams indicate to “EXIT ISR”, the final step to exiting the interrupt service routine is to clear the SLCF
interrupt flag. This can only be done if the SLCSV has first been read, and in the case that data has been
received (such as an ID byte or command message data) the SLCD has been read at least one time.
After SLCSV is read, it will switch to the next pending state, so the user must be sure it is copied only once
into a software variable at the beginning of the interrupt service routine to avoid inadvertently clearing a
pending interrupt source. Additional decisions based on this value must be made from the software
variable, rather than from the SLCSV itself.
After exiting the ISR, normal application code may resume. If the diagram indicates to “RETURN TO
IDLE,” it indicates that all processing for the current message frame has been completed. If an error was
detected and the corresponding error code loaded into the SLCSV, any pending data in the data buffer
will be flushed out and the SLIC returned to its idle state, seeking out the next message frame header.
14.9.6 SLIC Module Initialization Procedure
14.9.6.1 LIN Mode Initialization
The SLIC module does not require very much initialization, due to its self-synchronizing design. Because
no prior knowledge of the bit rate is required to synchronize to the LIN bus, no programming of bit rate is
required.
At initialization time, the user must configure:
•
•
SLIC prescale register (SLIC digital receive filter adjustment).
Wait clock mode operation.
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The SLIC clock is the same as the CPU bus clock. The module is designed to provide better than 1% bit
rate accuracy at the lowest value of the SLIC clock frequency and the accuracy improves as the SLIC
clock frequency is increased. For this reason, it is advantageous to choose the fastest SLIC clock which
is still within the acceptable operating range of the SLIC. Because the SLIC may be used with MCUs with
internal oscillators, the tolerance of the oscillator must be taken into account to ensure that SLIC clock
frequency does not exceed the bounds of the SLIC clock operating range. This is especially important if
the user wishes to use the oscillator untrimmed, where process variations might result in MCU frequency
offsets of 25%.
The acceptable range of SLIC clock frequencies is 2–8 MHz to guarantee LIN operations with greater than
1.5% accuracy across the 1–20 kbps range of LIN bit rates. The user must ensure that the fastest possible
SLIC clock frequency never exceeds 8 MHz or that the slowest possible SLIC clock never falls below 2
MHz under worst case conditions. This would include, for example, oscillator frequency variations due to
untrimmed oscillator tolerance, temperature variation, or supply voltage variation.
To initialize the SLIC module into LIN operating mode, the user must perform the following steps prior to
needing to receive any LIN message traffic. These steps assume the MCU has been reset either by a
power-on reset (POR) or any other MCU reset mechanism.
The steps for SLIC Initialization for LIN operation are:
1. Write SLCC1 to clear INITREQ.
2. When INITACK = 0, write SLCC1 & SLCC2 with desired values for:
a. SLCWCM — Wait clock mode (default = leaving SLIC clock running when in CPU wait).
3. Write SLCP to set up prescalers for:
a. RXFP — Digital receive filter clock prescaler (default = SLIC divided by 3).
4. Enable the SLIC module by writing SLCC2:
a. SLCE = 1 to place SLIC module into run mode.
b. BTM = 0 to disable byte transfer mode (default).
5. Write SLCC1 to enable SLIC interrupts (if desired).
14.9.6.2 Byte Transfer Mode Initialization
Bit rate synchronization is handled automatically in LIN mode, using the synchronization data contained
in each LIN message to derive the desired bit rate. In byte transfer mode (BTM = 1); however, the user
must set up the bit rate for communications using the clock selection, prescaler, and SLCBT.
More information on byte transfer mode is described in 14.9.15 Byte Transfer Mode Operation, including
the performance parameters on recommended maximum speeds, bit time resolution, and oscillator
tolerance requirements.
After the desired settings of prescalers and bit time are determined, the SLIC Initialization for BTM
operation is virtually identical to that of LIN operation.
The steps are:
1. Write SLCC1 to clear INITREQ.
2. When INITACK = 0, write SLCC2 with desired values for:
a. SLCWCM — Wait clock mode (default = leaving SLIC clock running when in CPU wait).
3. Write SLCICP to set up prescalers for:
a. RXFP — Digital receive filter clock prescaler (default = SLIC divided by 3).
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4. Enable the SLIC module by writing SLCC2:
a. SLCE = 1 to place SLIC module into run mode.
b. BTM = 1 to enable byte transfer mode (default = disabled).
5. Write SLCC1 to enable SLIC interrupts (if desired).
14.9.7 Handling LIN Message Headers
Figure 14-15 shows how the SLIC module deals with incoming LIN message headers.
LIN MESSAGE
HEADER RECEIVED
N
VALID BREAK
AND SYNCH
DATA?
INTERRUPT
READ SLCSV
Y
SLIC UPDATES SLCBT
ID ARRIVING IN RX BUFFER
PROCESS ERROR CODE:
BYTE FRAMING ERROR
INTERRUPT
READ SLCSV
CLEAR SLCF
EXIT ISR
RETURN TO
LIN BUS IDLE
PROCESS ERROR CODE:
IDENTIFIER-PARITY ERROR
BYTE FRAMING ERROR
Y
ERROR CODE
?
N
READ ID FROM SLCID
N
ID FOR THIS
NODE
SET IMSG BIT
?
Y
PROCESS VALID ID
Figure 14-15. Handling LIN Message Headers
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14.9.7.1 LIN Message Headers
All LIN message frame headers are comprised of three components:
•
•
•
The first is the SYNCHRONIZATION BREAK (SYNCH BREAK) symbol, which is a dominant (low)
pulse at least 13 or more bit times long, followed by a recessive (high) synchronization delimiter of
at least one bit time. In LIN 2.0, this is allowed to be 10 or more bit times in length.
The second part is called the SYNCHRONIZATION FIELD (SYNCH FIELD) and is a single byte
with value 0x55. This value was chosen as it is the only one which provides a series of five falling
(recessive to dominant) transitions on the bus.
The third section of the message frame header is the IDENTIFIER FIELD (ID). The identifier is
covered more in 14.9.8 Handling Command Message Frames and 14.9.9 Handling Request LIN
Message Frames.
The SLIC automatically reads the incoming pattern of the SYNCHRONIZATION BREAK and FIELD and
determines the bit rate of the LIN data frame, as well as checking for errors in form and discerning
between a genuine BREAK/FIELD combination and a similar byte pattern somewhere in the data stream.
After the header has been verified to be valid and has been processed, the SLIC module updates the
SLIC bit time register (SLICBT) with the value obtained from the SYNCH FIELD and begins to receive the
ID.
If there are errors in the SYNCH BREAK/FIELD pattern, then an interrupt is generated. If unmasked, it
will trigger an MCU interrupt request and the resulting code in the SLIC state vector register (SLCSV) will
be an “Inconsistent-Synch-Field-Error,” based on the LIN protocol specification.
After the ID for the message frame has been received, an interrupt is generated by the SLIC and will
trigger an MCU interrupt request if unmasked. At this point, it might be possible that the ID was received
with errors such as a parity error (based on the LIN specification) or a byte framing error. If the ID did not
have any errors, it will be copied into the SLCD for the software to read. The SLCSV will indicate the type
error or that the ID was received correctly.
In a LIN system, the meaning and function of all messages, and therefore all message identifiers, is
pre-defined by the system designer. This information can be collected and stored in a standardized format
file, called a Configuration Language Description (CLD) file. In using the SLIC module, it is the
responsibility of the user software to determine the nature of the incoming message, and therefore how
to further handle that message.
The simplest case is when the SLIC receives a message which the user software determines is of no
interest to the application. In other words, the slave node does not need to receive or transmit any data
for this message frame. This might also apply to messages with zero data bytes (which is allowed by the
LIN specification). At this point, the user can set the IMSG control bit, and exit the interrupt service routine
by clearing the SLCIF flag. Because there is no data to be sent or received, the SLIC will not generate
another interrupt until the next message frame header or bus goes idle long enough to trigger a
“No-Bus-Activity” error according to the LIN specification.
NOTE
IMSG will prevent another interrupt from occurring for the current message
frame; however, if data bytes are appearing on the bus they may be
received and copied into the message buffer. This will delete any previous
data which might have been present in the buffer, even though no interrupt
is triggered to indicate the arrival of this data.
At the time the ID is read, the user might also choose to read SLCBT and copy this value out to an
application variable. This data can then be used at a time appropriate to both the application software and
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the LIN communications to adjust the trim of the internal oscillator. This operation must be handled very
carefully to avoid adjusting the base timing of the MCU at the wrong time, adversely affecting the
operation of the SLIC module or of the application itself. More information about this is contained in
14.9.16 Oscillator Trimming with SLIC.
If the user software determines that the ID read out of the SLCD corresponds to a command or request
message for which this node needs to receive or transmit data (respectively), it will then move on to
procedures described in 14.9.8 Handling Command Message Frames and 14.9.9 Handling Request LIN
Message Frames.
For clarification, in this document, “command” messages will refer to any message frame where the SLIC
module is receiving data bytes and “request” messages refer to message frames where the SLIC module
will be expected to transmit data bytes. This is a generic description and should not be confused with the
terminology in the LIN specification. The LIN use of the terms “command” and “request” have the same
basic meaning, but are limited in scope to specific identifier values of 0x3C and 0x3D. In the SLIC module
documentation, these terms have been used to describe these functional types of messages, regardless
of the specific identifier value used.
14.9.7.2 Possible Errors on Message Headers
Possible errors on message headers are:
•
•
Identifier-Parity-Error
Byte Framing Error
14.9.8 Handling Command Message Frames
Figure 14-16 shows how to handle command message frames, where the SLIC module is receiving data
from the master node.
Command message frames refer to LIN messages frames where the master node is “commanding” the
slave node to do something. The implication is that the slave will then be receiving data from the master
for this message frame. This can be a standard LIN message frame of 1–8 data bytes, a reserved LIN
system message (using 0x3C identifier), or an extended command message frame utilizing the reserved
0x3E user defined identifier or perhaps the 0x3F LIN reserved extended identifier. The SLIC module is
capable of handling message frames containing up to 64 bytes of data, while still automatically calculating
and/or verifying the checksum.
14.9.8.1 Standard Command Message Frames
After the application software has read the incoming identifier and determined that it is a valid identifier
which cannot be ignored using IMSG, it must determine if this message frame is a command message
frame or a request message frame. (i.e., should the application receive data from the master or send data
back to the master?)
The first case, shown in Figure 14-16 deals with command messages, where the SLIC will be receiving
data from the master node. If the received identifier corresponds to a standard LIN command frame (i.e.,
1–8 data bytes), the user must then write the number of bytes (determined by the system designer and
directly linked with this particular identifier) corresponding to the length of the message frame into
SLCDLC. The two most significant bits of this register are used for special control bits describing the
nature of this message frame.
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PROCESS
VALID ID
N
PROCESS
REQUEST MESSAGE
COMMAND MESSAGE
?
Y
INITIALIZE SW BYTE COUNT
WRITE SLCDLC FOR THIS ID
0nxx xxxx
(TXGO = 0)
(CHKMOD = n)
Y
EXTENDED FRAME
?
N
WRITE SLCDLC FOR THIS ID
EXIT ISR
0n00 0xxx
(TXGO = 0)
(CHKMOD = n)
INTERRUPT
READ SLCSV
CLEAR SLCF
EXIT ISR
PROCESS ERROR CODE:
BYTE FRAMING ERROR
NO-BUS-ACTIVITY
Y
ERROR CODE
?
INTERRUPT
READ SLCSV
CLEAR SLCF
RECEIVE BUFFER OVERRUN
N
PROCESS ERROR CODE:
BYTE FRAMING ERROR
CHECKSUM-ERROR
NO-BUS-ACTIVITY
EXIT ISR
RETURN TO IDLE
1. EMPTY RX BUFFER
Y
2. DECREMENT SW BYTE COUNT BY 8
ERROR CODE
?
RECEIVE BUFFER OVERRUN
N
LAST FRAME
N
(SW BYTE COUNT £8)
EXIT ISR
RETURN TO IDLE
EMPTY RX BUFFER
?
Y
Figure 14-16. Handling Command Messages (Data Receive)
The SLIC transmit go (TXGO) bit should be 0 for command frames, indicating to the SLIC that data is
coming from the master. The checksum mode control (CHKMOD) bit allows the user to select which
method of checksum calculation is desired for this message frame. The LIN 1.3 checksum does not
include the identifier byte in the calculation, while the SAE version does include this byte. Because the
identifier is already received by the SLIC by this time, the default is to include it in the calculation. If a LIN
1.3 checksum is desired, a 1 in CHKMOD will reset the checksum circuitry to begin calculating the
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checksum on the first data byte. Using CHKMOD in this way allows the SLIC to receive messages with
either method of data consistency check and change on a frame-by-frame basis. If a system uses both
types of data consistency checking methods, the software must simply change the setting of this bit based
on the identifier of each message. If the network only uses one type of check, CHKMOD can be set as a
constant value in the user’s code. If CHKMOD is not written on each frame, care must be taken not to
accidentally modify the bit when writing the data length and TXGO bits. This is especially true if using C
code without carefully inspecting the output of the compiler and assembler.
The control bits and data length code are contained in one register, allowing the user to maximize the
efficiency of the identifier processing by writing a single byte value to indicate the nature of the message
frame. This allows very efficient identifier processing code, which is important in a command frame, as
the master node can be sending data immediately following the identifier byte which might be as little as
one byte in length. The SLIC module uses a separate internal storage area for the incoming data bytes,
so there is no danger of losing incoming data, but the user should spend as little time as possible within
the ISR to ensure that the application or other ISRs are able to use the majority of the CPU bandwidth.
The identifier must be processed in a maximum of 2 byte times on the LIN bus to ensure that the ISR
completes before the checksum would be received for the shortest possible message. This should be
easily achievable, as the only operations required are to read SLCID and look up the checksum method,
data length, and command/request state of that identifier, then write that value to the SLCDLC. This can
be easily streamlined in code with a lookup table of identifiers and corresponding SLCDLC bytes.
NOTE
Once the ID is decoded for a message header and a length code written to
SLCDLC, the SLIC is expecting that number of bytes to be received. If the
SLIC module doesn't receive the number of bytes indicated in the SLCDLC
register, it will continue to look for data bytes. If another message header
begins, a byte framing error will trigger on the break symbol of that second
message. The second message will still properly generate an ID received
interrupt, but the byte framing error prior to this is an indication to the
application that the previous message was not properly handled and should
be discarded.
14.9.8.2 Extended Command Message Frames
Handling of extended frames is very similar to handling of standard frames, providing that the length is
less than or equal to 64 bytes. Because the SLIC module can only receive 8 bytes at a time, the receive
buffer must be emptied periodically for long message frames. This is not standard LIN operation, and is
likely only to be used for downloading calibration data or reprogramming FLASH devices in a factory or
service facility, so the added steps required for processing are not as critical to performance. During these
types of operations, the application code is likely very limited in scope and special adjustments can be
made to compensate for added message processing time.
For extended command frames, the data length is still written one time at the time the identifier is
decoded, along with the TXGO and CHKMOD bits. When this is done, a software counter must also be
initialized to keep track of how many bytes are expected to be received in the message frame. The ISR
completes, clearing the SLCF flag, and resumes application execution. The SLIC will generate an
interrupt, if unmasked, after 8 bytes are received or an error is detected. At this interrupt, the SLCSV will
indicate an error condition (in case of byte framing error, idle bus) or that the receive buffer is full. If the
data is successfully received, the user must then empty the buffer by reading SLCD7-SLCD0 and then
subtract 8 from the software byte count. When this software counter reaches 8 or fewer, the remaining
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data bytes will fit in the buffer and only one interrupt should occur. At this time, the final interrupt may be
handled normally, continuing to use the software counter to read the proper number of bytes from the
appropriate SLCD registers.
NOTE
Do not write SLCDLC more than one time per LIN message frame. The
SLIC tracks the number of sent or received bytes based on the value written
to this register at the beginning of the data field and rewriting this register
will corrupt the checksum calculation and cause unpredictable behavior in
the SLIC module. The application software must track the number of sent
or received bytes to know what the current byte count in the SLIC is. If
programming in C, make sure to use the VOLATILE modifier on this
variable (or make it a global variable) to ensure that it keeps its value
between interrupts.
14.9.8.3 Possible Errors on Command Message Data
Possible errors on command message data are:
•
•
•
•
Byte Framing Error
Checksum-Error (LIN specified error)
No-Bus-Activity (LIN specified error)
Receiver Buffer Overrun Error
14.9.9 Handling Request LIN Message Frames
Figure 14-17 shows how to handle request message frames, where the SLIC module is sending data to
the master node.
Request message frames refer to LIN messages frames where the master node is “requesting” the slave
node to supply information. The implication is that the slave will then be transmitting data to the master
for this message frame. This can be a standard LIN message frame of 1–8 data bytes, a reserved LIN
system message (using 0x3D identifier), or an extended request message frame utilizing the reserved
0x3E identifier or perhaps the 0x3F LIN reserved extended identifier. The SLIC module is capable of
handling request message frames containing up to 64 bytes of data, while still automatically calculating
and/or verifying the checksum.
14.9.9.1 Standard Request Message Frames
Dealing with request messages with the SLIC is very similar to dealing with command messages, with
one important difference. Because the SLIC is now to be transmitting data in the LIN message frame, the
user software must load the data to be transmitted into the message buffer prior to initiating the
transmission. This means an extra step is taken inside the interrupt service routine after the identifier has
been decoded and is determined to be an ID for a request message frame.
Figure 14-17 deals with request messages, where the SLIC will be transmitting data to the master node.
If the received identifier corresponds to a standard LIN command frame (i.e., 1-8 data bytes), the
message processing is very simple. The user must load the data to be transmitted into the transmit buffer
by writing it to the SLCD registers. The first byte to be transmitted on the LIN bus must be loaded into
SLCD0, then SLCD1 for the second byte, etc. After all of the bytes to be transmitted are loaded in this
way, a single write to SLCDLC will allow the user to encode the number of data bytes to be transmitted
(1–8 bytes for standard request frames), set the proper checksum calculation method for the data
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(CHKMOD), as well as signal the SLIC that the buffer is ready by writing a 1 to TXGO. TXGO will remain
set to 1 until the buffer is sent successfully or an error is encountered, signaling to the application code
that the buffer is in process of transmitting. In cases of 1–8 data bytes only being sent (standard LIN
request frames), the SLIC automatically calculates and transmits the checksum byte at the end of the
message frame. The user can exit the ISR after SLCDLC has been written and the SLCF flag has been
cleared.
PROCESS
REQUEST MESSAGE
Y
1. CLEAR SLCF
2. INITIALIZE SW BYTE COUNT
EXTENDED FRAME
?
3. LOAD FIRST 8 DATA BYTES
4. WRITE SLCDLC FOR THIS ID
1nxx xxxx
(TXGO = 1)
N
(CHKMOD = n)
1. CLEAR SLCF
2. LOAD DATA INTO MESSAGE BUFFER
3. WRITE SLCDLC FOR THIS ID
1n00 0xxx
(TXGO = 1)
(CHKMOD = n)
EXIT ISR
EXIT ISR
INTERRUPT
READ SLCSV
CLEAR SLCF
INTERRUPT
READ SLCSV
CLEAR SLCF
PROCESS ERROR CODE:
BYTE FRAMING ERROR
BIT-ERROR
Y
ERROR CODE
PROCESS ERROR CODE:
BYTE FRAMING ERROR
BIT-ERROR
?
Y
ERROR CODE
N
CHECKSUM-ERROR
?
EXIT ISR
RETURN TO IDLE
DECREMENT SW BYTE COUNT BY 8
N
EXIT ISR
RETURN TO IDLE
TRANSMIT COMPLETE
N
LAST FRAME
(SW BYTE COUNT £8)
?
Y
1. LOAD NEXT 8 BYTES TO TRANSMIT
2. WRITE TXGO BIT TO START TRANSMIT(1)
1. LOAD LAST (£8) BYTES TO TRANSMIT
2. WRITE TXGO BIT TO START TRANSMIT(1)
Note 1. When writing TXGO bit only, ensure that CHKMOD and data length values are not accidentally modified.
Figure 14-17. Handling Request LIN Message Frames
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The next SLIC interrupt which occurs, if unmasked, will indicate the end of the request message frame
and will either indicate that the frame was properly transmitted or that an error was encountered during
transmission. Refer to 14.9.9.4 Possible Errors on Request Message Data for more detailed explanation
of these possible errors. This interrupt also signals to the application that the message frame is complete
and all data bytes and the checksum value have been properly transmitted onto the bus.
The SLIC module cannot begin to transmit the data until the user writes a 1 to TXGO, indicating that data
is ready. If the user writes TXGO without loading data into the transmit buffer, whatever data is in storage
will be transmitted, where the number of bytes transmitted is based on the data length value in the data
length register. Similarly, if the user writes the wrong value for the number of data bytes to transmit, the
SLIC will transmit that number of bytes, potentially transmitting garbage data onto the bus. The checksum
calculation is performed based on the data transmitted, and will therefore still be calculated.
The identifier must be processed, data must be loaded into the transmit buffer, and the SLCDLC value
written to initiate data transmission in a certain amount of time, based on the LIN specification. If the user
waits too long to start transmission, the master node will observe an idle bus and trigger a Slave Not
Responding error condition. The same error can be triggered if the transmission begins too late and does
not complete before the message frame times out. Refer to the LIN specification for more details on timing
constraints and requirements for LIN slave devices. This is especially important when dealing with
extended request frames, when the data must be loaded in 8 byte sections (maximum) to be transmitted
at each interrupt.
14.9.9.2 Extended Request Message Frames
Handling of extended frames is very similar to handling of standard frames, providing that the length is
less than or equal to 64 bytes. Because the SLIC module can only transmit 8 bytes at a time, the transmit
buffer must be loaded periodically for extended message frames. This is not standard LIN operation, and
is likely only to be used for special cases, so the added steps required for processing should not be as
critical to performance. During these types of operations, the application code is likely very limited in
scope and special adjustments can be made to compensate for added message processing time.
When handling extended request frames, it is important to clear the SLCF flag first, before loading any
data or writing TXGO. The data length is still written only one time, at the time the identifier is decoded,
along with the TXGO and CHKMOD bits, after the first 8 data bytes are loaded into the transmit buffer.
When this is done, a software counter must also be initialized to keep track of how many bytes are to be
transmitted in the message frame. The SLIC will generate an interrupt, if unmasked, after 8 bytes are
transmitted or an error is detected. At this interrupt, the SLCSV will indicate an error condition (in case of
byte framing error or bit error) or that the transmit buffer is empty. If the data is transmitted successfully,
the user must then clear the SLCF flag, subtract 8 from the software byte count, load the next 8 bytes into
the SLCD registers, and write a 1 to TXGO to tell the SLIC that the buffers are loaded and transmission
can commence. When this software counter reaches 8 or fewer, the remaining data bytes will fit in the
transmit buffer and the SLIC will automatically append the checksum value to the frame after the last byte
is sent.
NOTE
Do not write the CHKMOD or data length values in SLCDLC more than one
time per message frame. The SLIC tracks the number of sent or received
bytes based on the value written to this register at the beginning of the data
field and rewriting this register will corrupt the checksum calculation and
cause unpredictable behavior in the SLIC module. The application software
must track the number of sent or received bytes to know what the current
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byte count in the SLIC is. If programming in C, make sure to use the
STATIC modifier on this variable (or make it a global variable) to ensure
that it keeps its value between interrupts.
14.9.9.3 Transmit Abort
The transmit abort bit (TXABRT) in SLCC1 allows the user to cease transmission of data on the next byte
boundary. When this bit is set to 1, it will finish transmitting the byte currently being transmitted, then
cease transmission. After the transmission is successfully aborted, TXABRT will automatically be reset
by the SLIC to 0. If the SLIC is not in process of transmitting at the time TXABRT is written to 1, there is
no effect and TXABRT will read back as 0.
14.9.9.4 Possible Errors on Request Message Data
Possible errors on request message data are:
•
•
•
Byte Framing Error
Checksum-Error (LIN specified error)
Bit-Error
14.9.10 Handling IMSG to Minimize Interrupts
The IMSG feature is designed to minimize the number of interrupts required to maintain LIN
communications. On a network with many slave nodes, it is very likely that a particular slave will observe
messages which are not intended for that node. When the SLIC module detects any message header, it
synchronizes to that message frame and bit rate, then interrupts the CPU after the identifier byte has been
successfully received and parity checked. At this time, if the software determines that the message may
be ignored, IMSG may be set to indicate to the module that the data field of the message frame is to be
ignored and no additional interrupts should be generated until the next valid message header is received.
The bit is automatically reset to 0 after the current message frame is complete and the LIN bus returns to
idle state. This reduces the load on the CPU and allows the application software to immediately begin
performing any operations which might otherwise not be allowed while receiving messaging.
NOTE
IMSG will prevent another interrupt from occurring for the current message
frame, however if data bytes are appearing on the bus they may be
received and copied into the message buffer. This will delete any previous
data which might have been present in the buffer, even though no interrupt
is triggered to indicate the arrival of this data.
14.9.11 Sleep and Wakeup Operation
The SLIC module itself has no special sleep mode, but does support low-power modes and wake-up on
network activity. For low-power operations, the user must select whether or not to allow the SLIC clock to
continue operating when the MCU issues a wait instruction through the SLC wait clock mode (SLCWCM)
bit in SLCC1. If SLCWCM = 1, the SLIC will enter SLIC STOP mode when the MCU executes a WAIT
instruction. If SLCWCM = 0, the SLIC will enter SLIC WAIT mode when the MCU executes a WAIT
instruction. For more information on these modes, as well as wakeup options from these modes, please
refer to 14.5 Modes of Operation.
When network activity occurs, the SLIC module will wake the MCU out of stop or wait mode, and return
the SLIC module to SLIC run mode. If the SLIC was in SLIC wait mode, normal SLIC interrupt processing
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Slave LIN Interface Controller (SLIC) Module
will resume. If the SLIC was in SLIC stop mode, SLCSV will indicate wakeup as the interrupt source so
that the user knows that the SLIC module brought the MCU out of stop or wait.
In a LIN system, a system message is generally sent to all nodes to indicate that they are to enter
low-power network sleep mode. After a node enters sleep mode, it waits for outside events, such as
switch or sensor inputs or network traffic to bring it out of network sleep mode. If the node using the SLIC
module is awakened by a source other than network traffic, such as a switch input, the LIN specification
requires this node to issue a wake-up signal to the rest of the network. The SLIC module supports this
feature using WAKETX in SLCC2. The user software may set this bit and one LIN wake-up signal is
immediately transmitted on the bus, then the bit is automatically cleared by the SLIC module. If another
wake-up signal is required to be sent, the user must set WAKETX again.
In a LIN system, the LIN physical interface can often also provide an output to the IRQ pin to provide a
wake-up mechanism on network activity. The physical layer might also control voltage regulation supply
to the MCU, cutting power to the MCU when the physical layer is placed in its low-power mode. The user
must take care to ensure that the interaction between the physical layer, IRQ pin, SLIC transmit and
receive pins, and power supply regulator is fully understood and designed to ensure proper operation.
14.9.12 Polling Operation
It is possible to operate the SLIC module in polling mode, if desired. The primary difference is that the
SLIC interrupt request should not be enabled (SLCIE = 0). The SLCSV will update and operate properly
and interrupt requests will be indicated with the SLCF flag, which can be polled to determine status
changes in the SLIC module. It is required that the polling rate be fast enough to ensure that SLIC status
changes be recognized and processed in time to ensure that all application timings can be met.
14.9.13 LIN Data Integrity Checking Methods
The SLIC module supports two different LIN-based data integrity options:
•
•
The first option supports LIN 1.3 and older methods of checksum calculations.
The second option supports an optional additional enhanced checksum calculation which has
greater data integrity coverage.
The LIN 1.3 and earlier specifications transmit a checksum byte in the “CHECKSUM FIELD” of the LIN
message frame. This CHECKSUM FIELD contains the inverted modulo-256 sum over all data bytes. The
sum is calculated by an “ADD with Carry” where the carry bit of each addition is added to the least
significant bit (LSB) of its resulting sum. This guarantees security also for the MSBs of the data bytes. The
sum of modulo-256 sum over all data bytes and the checksum byte must be ’0xFF’.
An optional checksum calculation can also be performed on a LIN data frame which is very similar to the
LIN 1.3 calculation, but with one important distinction. This enhanced calculation simply includes the
identifier field as the first value in the calculation, whereas the LIN 1.3 calculation begins with the least
significant byte of the data field (which is the first byte to be transmitted on the bus). This enhanced
calculation further ensures that the identifier field is correct and ties the identifier and data together under
a common calculation, ensuring greater reliability.
In the SLIC module, either checksum calculation can be performed on any given message frame by
simply writing or clearing CHKMOD in SLCDLC, as desired, when the identifier for the message frame is
decoded. The appropriate calculation for each message frame should be decided at system design time
and documented in the LIN description file, indicating to the user which calculation to use for a particular
identifier.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Initialization/Application Information
14.9.14 High-Speed LIN Operation
High-speed LIN operation does not necessarily require any reconfiguration of the SLIC module,
depending upon what maximum LIN bit rate is desired. Several factors affect the performance of the SLIC
module at LIN speeds higher than 20 kbps, all of which are functions of the speed of the SLIC clock and
the prescaler of the digital filter. The tightest constraint comes from the need to maintain 1.5% accuracy
with the master node timing. This requires that the SLIC module be able to sample the incoming data
stream accurately enough to guarantee that accuracy. Table 14-5 shows the maximum LIN bit rates
allowable to maintain this accuracy.
Table 14-5. Maximum LIN Bit Rates for High-Speed Operation
Maximum LIN Bit Rate
for 1ꢀ SLIC Accuracy
(Bits / Second)
Maximum LIN Bit Rate
for 1.5ꢀ SLIC Accuracy
(Bits / Second)
SLIC Clock (MHz)
8
80,000
64,000
48,000
40,000
32,000
24,000
20,000
120,000
96,000
72,000
60,000
48,000
36,000
30,000
6.4
4.8
4
3.2
2.4
2
The above numbers assume a perfect input waveforms into the SLCRX pin, where 1 and 0 bits are of
equal length and are exactly the correct length for the appropriate speed. Factors such as physical layer
wave shaping and ground shift can affect the symmetry of these waveforms, causing bits to appear
shortened or lengthened as seen by the SLIC module. The user must take these factors into account and
base the maximum speed upon the shortest possible bit time that the SLIC module may observe, factoring
in all physical layer effects. On some LIN physical layer devices it is possible to turn off wave shaping
circuitry for high-speed operation, removing this portion of the physical layer error.
The digital receive filter can also affect high speed operation if it is set too low and begins to filter out valid
message traffic. Under ideal conditions, this will not happen, as the digital filter maximum speeds
allowable are higher than the speeds allowed for 1.5% accuracy. If the digital receive filter prescaler is
set to divide- by-4; however, the filter delay is very close to the 1.5% accuracy maximum bit time.
For example, with a SLIC clock of 4 MHz, the SLIC module is capable of maintaining 1.5% accuracy up
to 60,000 bps. If the digital receive filter prescaler is set to divide-by-4, this means that the filter will only
pass message traffic which is 62,500 bps or slower under ideal circumstances. This is only a difference
of 2,500 bps (4.17% of the nominal valid message traffic speed). In this case, the user must ensure that
with all errors accounted for, no bit will appear shorter than 16 µs
(1 bit at 62,500 bps) or the filter will block that bit. This is far too narrow a margin for safe design practices.
The better solution would be to reduce the filter prescaler, increasing the gap between the filter cut-off
point and the nominal speed of valid message traffic. Changing the prescaler to divide by 2 in this example
gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than the nominal speed of the LIN bus and
much less likely to interfere with valid message traffic.
To ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that
the filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the
bus. Refer to Table 14-6 for a more complete list of the digital receive filter delays as they relate to the
maximum LIN bus frequency. Table 14-7 repeats much of the data found in Table 14-6; however, the filter
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Slave LIN Interface Controller (SLIC) Module
delay values (cutoff values) are shown in the frequency and time domains. Note that Table 14-7 shows
the filter performance under ideal conditions.
When switching between a low-speed (< 4800 bps) to a high-speed (> 40000 bps) LIN message, the
master node must allow a minimum idle time of eight bit times (of the slowest bit rate) between the
messages. This prevents a valid message at another frequency from being detected as an invalid
message.
Table 14-6. Maximum LIN Bit Rates for High-Speed Operation Due to Digital Receive Filter
Maximum LIN
Bit Rate for 1.5ꢀ
SLIC Accuracy
(for Master-Slave
Communication
(Bits / Second)
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷4
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷3
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷2
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷1
SLIC
Clock
(MHz)
(Bits / Second)
(Bits / Second)
THESE PRESCALERS
NOT RECOMMENDED FOR
HIGH-SPEED LIN OPERATION
(Bits / Second)
(Bits / Second)
DIGITAL RX FILTER
NOT CONSIDERED
8
120,000
96,000
72,000
60,000
48,000
36,000
30,000
120,000(1)
100,000
75,000
62,500
50,000
37,500
31,250
120,000(1)
120,000(1)
100,000
83,333
120,000(1)
120,000(1)
120,000(1)
120,000(1)
100,000
120,000(1)
120,000(1)
120,000(1)
120,000(1)
120,000(1)
120,000(1)
120,000(1)
6.4
4.8
4
3.2
2.4
2
66,667
50,000
75,000
41,667
62,500
1. Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the
TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing
error.
Table 14-7. Digital Receive Filter Absolute Cutoff (Ideal Conditions)
Digital RX Filter
Digital RX Filter
Digital RX Filter
Digital RX Filter
Set to ÷4
Set to ÷3
Set to ÷2
Set to ÷1
SLIC
Clock
(MHz)
Max.
Min Pulse
Max.
Min Pulse
Width
Max.
Min Pulse
Width
Max.
Min Pulse
Width
Bit Rate
(Bits /
Sec)
Width
Allowed
(µs)
Bit Rate
(Bits /
Sec)
Bit Rate
(Bits /
Sec)
Bit Rate
(Bits /
Sec)
Allowed
(µs)
Allowed
(µs)
Allowed
(µs)
8
125,000
100,000
75,000
62,500
50,000
37,500
31,250
8.0
166,667
133,333
100,000
83,333
66,667
50,000
41,667
6.0
7.5
250,000
200,000
150,000
125,000
100,000
75,000
4.0
5.0
500,000
400,000
300,000
250,000
200,000
150,000
125,000
2.0
2.5
3.3
4.0
5.0
6.7
8.0
6.4
4.8
4
10.0
13.3
16.0
20.0
26.7
32.0
10.0
12.0
15.0
20.0
24.0
6.7
8.0
3.2
2.4
2
10.0
13.3
16.0
62,500
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
164
Freescale Semiconductor
Initialization/Application Information
14.9.15 Byte Transfer Mode Operation
This subsection describes the operation and limitations of the optional UART-like byte transfer mode
(BTM). This mode allows sending and receiving individual bytes, but changes the behavior of the SLCBT
registers (now read/write registers) and locks the SLCDLC to 1 byte data length. The SLCBT value now
becomes the bit time reference for the SLIC, where the software sets the length of one bit time rather than
the SLIC module itself. This is similar to an input capture/output compare (IC/OC) count in a timer module,
where the count value represents the number of SLIC clock counts in one bit time.
Byte transfer mode assumes that the user has a very stable, precise oscillator, resonator, or clock
reference input into the MCU and is therefore not appropriate for use with internal oscillators. There is no
synchronization method available to the user in this mode and the user must tell the SLIC how many clock
counts comprise a bit time. Figure 14-18, Figure 14-19, Figure 14-20, and Figure 14-21 show calculations
to determine the SLCBT value for different settings.
NOTE
It is possible to use the LIN autobauding circuitry in a non-LIN system to
derive the correct bit timing values if system constraints allow. To do this
the SLIC module must be activated in LIN mode (BTM=0) and receive a
break symbol, 0x55 data byte and one additional data byte (at the desired
BTM speed). Upon receiving this sequence of symbols which appears to be
a LIN header, the SLIC module will assert an ID received successfully
interrupt (SLCSV=0x2C). The value in the SLCBT registers will reflect the
bit rate which the 0x55 data character was received and can be saved to
RAM. The user then switches the SLIC into BTM mode and reloads this
value from RAM and the SLIC will be configured to communicate in BTM
mode at the baud rate which the 0x55 data character was sent.
In the example in Figure 14-18, the user should write 0x16, as a write of 0x15 (decimal value of 21) would
automatically revert to 0x14, resulting in transmitted bit times that are 1.33 SLIC clock periods too short
rather than 0.667 SLIC clock periods too long. The optimal choice, which gives the smallest resolution
error, is the closest even number of SLIC clocks to the exact calculated SLCBT value.
There is a trade-off between maximum bit rate and resolution with the SLIC in BTM mode. Faster SLIC
clock speeds improve resolution, but require higher numbers to be written to the SLCBT registers for a
given desired bit rate. It is up to the user to determine what level of resolution is acceptable for the given
application.
Desired Bit Rate:
57,600 bps
External Crystal Frequency: 4.9152 MHz
1 Second
17.36111 ms
1 Bit
=
=
57,600 Bits
1 Second
4 CGMXCLK Period
1 SLIC Clock Period
813.802 ns
X
X
4,915,200 CGMXCLK Periods
1 SLIC Clock Period
17.36111 ms
1 Bit
1 SLIC Clock Period
813.802 ns
21.33 SLIC Clock Periods
1 Bit
=
Therefore, the closest SLCBT value would be 21 SLIC clocks (SLCBT = 0x0015).
Because you can only use even values in SLCBT, the closest acceptable value is 22 (0x0016).
Figure 14-18. SLCBT Value Calculation Example 1
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Slave LIN Interface Controller (SLIC) Module
Desired Bit Rate:
57,600 bps
External Crystal Frequency: 9.8304 MHz
1 Second
17.36111 ms
1 Bit
=
=
57,600 Bits
1 Second
4 CGMXCLK Period
1 SLIC Clock Period
406.90 ns
X
X
9,830,400 CGMXCLK Periods
1 SLIC Clock Period
17.36111 ms
1 Bit
1 SLIC Clock Period
406.90 ns
42.67 SLIC Clock Periods
1 Bit
=
Therefore, the closest SLCBT value would be 42 SLIC clocks (SLCBT = 0x002A).
Figure 14-19. SLCBT Value Calculation Example 2
Desired Bit Rate:
15,625 bps
External Crystal Frequency: 8.000 MHz
1 Second
64 ms
1 Bit
=
=
15,625 Bits
1 Second
4 CGMXCLK Period
1 SLIC Clock Period
500 ns
X
X
8,000,000 CGMXCLK Periods
1 SLIC Clock Period
64 ms
1 Bit
1 SLIC Clock Period
500 ns
128 SLIC Clock Periods
1 Bit
=
Therefore, the closest SLCBT value would be 128 SLIC clocks (SLCBT = 0x0080).
Figure 14-20. SLCBT Value Calculation Example 3
Desired Bit Rate:
9.615 bps
External Crystal Frequency: 8.000 MHz
1 Second
9,615 Bits
104.004 ms
1 Bit
=
=
1 Second
4 CGMXCLK Period
1 SLIC Clock Period
500 ns
X
X
8,000,000 CGMXCLK Periods
1 SLIC Clock Period
104.004 ms
1 Bit
1 SLIC Clock Period
500 ns
208.008 SLIC Clock Periods
1 Bit
=
Therefore, the closest SLCBT value would be 42 SLIC clocks (SLCBT = 0x00D0).
Figure 14-21. SLCBT Value Calculation Example 4
This resolution affects the sampling accuracy of the SLIC module on receiving bytes, but only as far as
locating the sample point of each bit within a given byte. The best sample point of the bit may be off by
as much as one SLIC clock period from the exact center of the bit, if the proper SLCBT value for the
desired bit rate is an odd number of SLIC clock periods.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Initialization/Application Information
Figure 14-22 shows an example of this error. In this example, the user has additionally chosen an
incorrect value of 30 SLIC clocks for the length of one bit time, and a filter prescaler of 1. This makes little
difference in the receive sampling of this particular bit, as the sample point is still within the bit and the
digital filter will catch any noise pulses shorter than 16 filter clocks long.The ideal value of SLCBT would
be 35 SLIC clocks, but the closest available value is 34, placing the sample point at 17 SLIC clocks into
the bit.
The error in the bit time value chosen by the user in the above example will grow throughout the byte, as
the sample point for the next bit will be only 30 SLIC clock cycles later (1 full bit time at this bit rate setting).
The SLIC resynchronizes upon every falling edge received. In a 0x00 data byte, however, there are no
falling edges after the beginning of the start bit. This means that the accumulated error of the sampling
point over the data byte with these settings could be as high as 30 SLIC clock cycles (10 bits x {2 SLIC
clocks due to user error + 1 SLIC clock resolution error}) placing it at the boundary between the last bit
and the stop bit. This could result in missampling and missing a byte framing error on the last bit on high
speed communications when the SLCBT count is relatively low. A properly chosen SLCBT value would
result in a maximum error of 10 SLIC clock counts over a given byte. This is less than one filter delay time,
and will not cause missampling of any of the bits in that byte. At the falling edge of the next start bit, the
SLIC will resynchronize and any accumulated sampling error returns to 0. The sampling error becomes
even less significant at lower speeds, when higher values of SLCBT are used to define a bit time, as the
worst case bit time resolution error is still only one SLIC clock per bit (or maximum of 10 SLIC clocks per
byte).
UNFILTERED
RX DATA
FILTERED
RX DATA
(³1 PRESCALE)
FILTER CLOCK
(³1 PRESCALE)
16 FILTER CLOCKS
(³1 PRESCALE)
16 FILTER CLOCKS
(³1 PRESCALE)
FILTER REACHES 0XF
AND TOGGLES FILTER OUTPUT
FILTER REACHES 0X0
AND TOGGLES FILTER OUTPUT
FILTER BEGINS
COUNTING DOWN
FILTER BEGINS
COUNTING UP
SLIC CLOCK
15 SLIC CLOCKS
(1/2 OF SLCBT VALUE)
35 SLIC CLOCKS
(ACTUAL FILTERED BIT LENGTH)
IDEAL SLIC SAMPLE POINT (17 SLIC CLOCKS)
SLIC SAMPLE POINT
(BASED ON SLCBT VALUE)
This example assumes a SLCBT value of 30 (0x1E).
Transmitted bits will be sent out as 30 SLIC clock cycles long.
The proper closest SLCBT setting would be 34 (0x22),
which gives the ideal sample point of 17 SLIC clocks and
transmitted bits are 34 SLIC clocks long.
Figure 14-22. BTM Mode Receive Byte Sampling Example
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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167
Slave LIN Interface Controller (SLIC) Module
The error also comes into effect with transmitted bit times. Using the previous example with a SLCBT
value of 34, transmitted bits will appear as 34 SLIC clock periods long. This is one SLIC clock short of the
proper length. Depending on the frequency of the SLIC clock, one period of the SLIC clock might be a
large or a small fraction of one ideal bit time. Raising the frequency of the SLIC clock will reduce this error
relative to the ideal bit time, improving the resolution of the SLIC clock relative to the bit rate of the bus.
In any case, the error is still one SLIC clock cycle. Raising the SLIC clock frequency, however, requires
programming a higher value for SLCBT to maintain the same target bit rate.
Smaller values of SLCBT combined with higher values of the SLIC clock frequency (smaller clock period)
will give faster bit rates, but the SLIC clock period becomes an increasingly significant portion of one bit
time.
Because BTM mode does not perform any synchronization and relies on the accuracy of the data
provided by the user software to set its sample point and generate transmitted bits, the constraint on
maximum speeds is only limited to the limits imposed by the digital filter delay and the SLIC input clock.
Because the digital filter delay cannot be less than 16 SLIC clock cycles, the fastest possible pulse which
would pass the filter is 16 clock periods at 8 MHz, or 500,000 bits/second. The values shown in Table 14-7
are the same values shown in Table 14-8 and indicate the absolute fastest bit rates which could just pass
the minimum digital filter settings (prescaler = divide by 1) under perfect conditions.
Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit
rates. For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the
filter delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits
which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by
the filter without exception. This would translate to 2x to 3x reduction in the maximum speeds shown in
Table 14-7. Recommended maximum bit rates are shown in Table 14-8, and ensure that a single bit time
is at least twice the length of one filter delay value. If system noise is not adequately filtered out it might
be necessary to change the prescaler of the filter and lower the bit rate of the communication. If valid
communications are being absorbed by the filter, corrective action must be taken to ensure that either the
bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset,
asymmetrical rise/fall times, insufficient physical layer supply voltage, etc.).
Table 14-8. Recommended Maximum Bit Rates
for BTM Operation Due to Digital Filter
Maximum BTM
Bit Rate with
Digital RX Filter
Set to ÷4
Maximum BTM
Bit Rate with
Digital RX Filter
Set to ÷3
Maximum BTM
Bit Rate with
Digital RX Filter
Set to ÷2
Maximum BTM
Bit Rate with
Digital RX Filter
Set to ÷1
SLIC
Clock
(MHz)
(Bits / Second)
(Bits / Second)
(Bits / Second)
(Bits / Second)
8
62,500
50,000
37,500
31,250
25,000
18,750
15,625
83,333
66,667
50,000
41,667
33,333
25,000
20,833
120,000(1)
100,000
75,000
62,500
50,000
37,500
31,250
120,000(1)
120,000(1)
120,000(1)
120,000(1)
100,000
6.4
4.8
4
3.2
2.4
2
75,000
62,500
1. Bit rates over 120,000 bits per second are not recommended for BTM communications, as
physical layer delay between the TX and RX pins can cause the stop bit of a byte to be
missampled as the last data bit. This could result in a byte framing error.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Freescale Semiconductor
Initialization/Application Information
14.9.16 Oscillator Trimming with SLIC
SLCACT can be used as an indicator of LIN bus activity. SLCACT tells the user that the SLIC is currently
processing a message header (therefore synchronizing to the bus) or processing a message frame
(including checksum). Therefore, at idle times between message frames or during a message frame
which has been marked as a “don’t care” by writing IMSG, it is possible to trim the oscillator circuit of the
MCU with no impact to the LIN communications.
It is important to note the exact mechanisms with which the SLIC sets and clears SLCACT. Any falling
edge which successfully passes through the digital receive filter will cause SLCACT to become set. This
might even include noise pulses, if they are of sufficient length to pass through the digital RX filter.
Although in these cases SLCACT is becoming set on a noise spike, it is very probable that noise of this
nature will cause other system issues as well such as corruption of the message frame. The software can
then further qualify if it is appropriate to trim the oscillator.
SLCACT will only be cleared by the SLIC upon successful completion of a normal LIN message frame
(see 14.8.3 SLIC Status Register description for more detail). This means that in some cases, if a
message frame terminates with an error condition or some source other than those cited in the SLCACT
bit description, SLCACT might remain set during an otherwise idle bus time. SLCACT will then clear upon
the successful completion of the next LIN message frame.
These mechanisms might result in SLCACT being set when it is safe (from the SLIC module perspective)
to trim the oscillator. However, SLCACT will only be clear when the SLIC considers it safe to trim the
oscillator.
In a particular system, it might also be possible to improve the opportunities for trimming by using system
knowledge and use of IMSG. If a message ID is known to be considered a “don’t care” by this particular
node, it should be safe to trim the oscillator during that message frame (provided that it is safe for the
application software as well). After the software has done an identifier lookup and determined that the ID
corresponds to a “don’t care” message, the software might choose to set IMSG. From that time, the
application software should have at least one byte time of message traffic in which to trim the oscillator
before that ignored message frame expires, regardless of the state of SLCACT. If the length of that
ignored message frame is known, that knowledge might also be used to extend the time of this oscillator
trimming opportunity.
Now that the mechanisms for recognizing when the SLIC module indicates safe oscillator trimming
opportunities are understood, it is important to understand how to derive the information needed to
perform the trimming.
The value in SLCBT will indicate how many SLIC clock cycles comprise one bit time and for any given
LIN bus speed, this will be a fixed value if the oscillator is running at its ideal frequency. It is possible to
use this ideal value combined with the measured value in SLCBT to determine how to adjust the oscillator
of the microcontroller.
The actual oscillator trimming algorithm is very specific to each particular implementation, and
applications might or might not require the oscillator even to be trimmed. The SLIC can maintain
communications even with input oscillator variation of 50% (with 4 MHz nominal, that means that any
input clock into the SLIC from 2 MHz to 6 MHz will still guarantee communications). Because Freescale
internal oscillators are at least within 25% of their nominal value, even when untrimmed, this means that
trimming of the oscillator is not even required for LIN communications. If the application can tolerate the
range of frequencies which might appear within this manufacturing range, then it is not necessary ever to
trim the oscillator. This can be a tremendous advantage to the customer, enabling migration to very
low-cost ROM devices which have no non-volatile memory in which to store the trim value.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
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Slave LIN Interface Controller (SLIC) Module
NOTE
Even though most internal oscillators are within 25% before trimming, they
are stable at some frequency in that range, within at least 5% over the
entire operating voltage and temperature range. The trimming operation
simply eliminates the offset due to factory manufacturing variations to
re-center the base oscillator frequency to the nominal value. Please refer to
the electrical specifications for the oscillator for more specific information,
as exact specifications might differ from module to module.
14.9.17 Digital Receive Filter
The receiver section of the SLIC module includes a digital low-pass filter to remove narrow noise pulses
from the incoming message. block diagram of the digital filter is shown in Figure 14-23.
DIGITAL RX FILTER
PRESCALER (RXFP[1:0])
INPUT
SYNC
4-BIT UP/DOWN COUNTER
RX DATA
FROM
SLCRX PIN
4
EDGE &
COUNT
COMPARATOR
FILTERED
RX DATA OUT
OUT
D
Q
D
Q
UP/DOWN
HOLD
SLIC CLOCK
Figure 14-23. SLIC Module Rx Digital Filter Block Diagram
14.9.17.1 Digital Filter Operation
The clock for the digital filter is provided by the SLIC Interface clock. At each positive edge of the clock
signal, the current state of the receiver input signal from the SLCRX pad is sampled. The SLCRX signal
state is used to determine whether the counter should increment or decrement at the next positive edge
of the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample is low. The
counter will thus progress up towards the highest count value (determined by RXFP bit settings), on
average, the SLCRX signal remains high or progress down towards ‘0’ if, on average, the SLCRX signal
remains low. The final counter value which determines when the filter will change state is generated by
shifting the RXFP value right two positions and bitwise OR-ing the result with the value 0x0F. For
example, a prescale setting of divide by 3 (RXFP = 0x80) would give a count value of 0x2F.
When the counter eventually reaches this value, the digital filter decides that the condition of the SLCRX
signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to become a
logic level 1. Furthermore, the counter is prevented from overflowing and can only be decremented from
this state.
Alternatively, when the counter eventually reaches the value ‘0’, the digital filter decides that the condition
of the SLCRX signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data
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Freescale Semiconductor
Initialization/Application Information
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only
be incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the SLCRX signal.
14.9.17.2 Digital Filter Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the SLCRX signal transitions, then there will be a delay before that transition appears at
the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where
the transition occurs with respect to the sampling points. This ‘filter delay’ is not an issue for SLIC
operation, as there is no need for message arbitration.
The effect of random noise on the SLCRX signal depends on the characteristics of the noise itself. Narrow
noise pulses on the SLCRX signal will be completely ignored if they are shorter than the filter delay. This
provides a degree of low-pass filtering. Figure 14-23 shows the configuration of the digital receive filter
and the consequential effect on the filter delay. This filter delay value indicates that for a particular setup,
only pulses of which are greater than the filter delay will pass the filter.
For example, if the frequency of the SLIC clock (fSLIC) is 3.2 MHz, then the period (tSLIC) is of the SLIC
clock is 313 ns. With the default receive filter prescaler setting of division by 3, the resulting maximum
filter delay in the absence of noise will be 15.00 µs. By simply changing the prescaler of the receive filter,
the user can then select alternatively 5 µs, 10 µs, or 20 µs as a minimum filter delay according to the
systems requirements.
If noise occurs during a symbol transition, the detection of that transition may be delayed by an amount
equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is
truly occurring within the noise.
NOTE
The user must always account for the worst case bit timing of their LIN bus
when configuring the digital receive filter, especially if running at faster
speeds. Ground offset and other physical layer conditions can cause
shortening of bits as seen at the digital receive pin, for example. If these
shortened bit lengths are less than the filter delay, the bits will be
interpreted by the filter as noise and will be blocked, even though the
nominal bit timing might be greater than the filter delay.
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Slave LIN Interface Controller (SLIC) Module
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Chapter 15
Timer Interface Module (TIM)
15.1 Introduction
This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that
provides a timing reference with input capture, output compare, and pulse-width-modulation functions.
The TIM module shares its pins with general-purpose input/output (I/O) port pins. See Figure 15-1 for port
location of these shared pins.
15.2 Features
Features include the following:
•
Two input capture/output compare channels
–
–
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
•
•
Buffered and unbuffered output compare pulse-width modulation (PWM) signal generation
Programmable clock input
–
–
7-frequency internal bus clock prescaler selection
External clock input pin if available, See Figure 15-1
•
•
•
Free-running or modulo up-count operation
Toggle any channel pin on overflow
Counter stop and reset bits
15.3 Functional Description
Figure 15-2 shows the structure of the TIM. The central component of the TIM is the 16-bit counter that
can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference
for the input capture and output compare functions. The counter modulo registers, TMODH:TMODL,
control the modulo value of the counter. Software can read the counter value, TCNTH:TCNTL, at any time
without affecting the counting sequence.
The two TIM channels are programmable independently as input capture or output compare channels.
15.3.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs or the external clock input pin, TCLK if
available. The prescaler generates seven clock rates from the internal bus clock. The prescaler select
bits, PS[2:0], in the TIM status and control register (TSC) select the clock source.
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Timer Interface Module (TIM)
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER FLASH
USER RAM
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
POWER SUPPLY
VSS
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 15-1. Block Diagram Highlighting TIM Block and Pins
15.3.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the counter into
the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can be enabled to generate interrupt requests.
15.3.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can be enabled to generate
interrupt requests.
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Functional Description
TCLK
TCLK
(IF AVAILABLE)
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TCNTH:TCNTL
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
TCH0
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
LOGIC
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
TCH1
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
LOGIC
INTERRUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
Figure 15-2. TIM Block Diagram
15.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 15.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
•
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
•
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
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Timer Interface Module (TIM)
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
15.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
15.3.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 15-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM
to clear the channel pin on output compare if the polarity of the PWM pulse is 1 (ELSxA = 0). Program the
TIM to set the pin if the polarity of the PWM pulse is 0 (ELSxA = 1).
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
POLARITY = 1
(ELSxA = 0)
TCHx
PULSE
WIDTH
POLARITY = 0 TCHx
(ELSxA = 1)
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 15-3. PWM Period and Pulse Width
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Functional Description
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is 000. See 15.8.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
15.3.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 15.3.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written to the timer channel
(TCHxH:TCHxL).
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
•
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
•
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
15.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
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Timer Interface Module (TIM)
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
15.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the counter by setting the TIM stop bit, TSTOP.
b. Reset the counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. See Table 15-2.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See Table 15-2.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control
register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See 15.8.1 TIM Status and Control Register.
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Interrupts
15.4 Interrupts
The following TIM sources can generate interrupt requests:
•
TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register.
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM interrupt requests are controlled by the channel x interrupt
enable bit, CHxIE. Channel x TIM interrupt requests are enabled when CHxIE =1. CHxF and
CHxIE are in the TSCx register.
•
15.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.5.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
15.5.2 Stop Mode
The TIM module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. TIM operation resumes after an external interrupt. If stop mode is exited by
reset, the TIM is reset.
15.6 TIM During Break Interrupts
A break interrupt stops the counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
15.7 I/O Signals
The TIM module can share its pins with the general-purpose I/O pins. See Figure 15-1 for the port pins
that are shared.
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Timer Interface Module (TIM)
15.7.1 TIM Channel I/O Pins (TCH1:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0 can be configured as buffered output compare or buffered PWM pin.
15.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0]. The
minimum TCLK pulse width is specified in the Timer Interface Module Characteristics table in the
Electricals section. The maximum TCLK frequency is the least of 4 MHz or bus frequency ÷ 2.
15.8 Registers
The following registers control and monitor operation of the TIM:
•
•
•
•
•
TIM status and control register (TSC)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
15.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
•
•
•
•
•
Enables TIM overflow interrupts
Flags TIM overflows
Stops the counter
Resets the counter
Prescales the counter clock
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 15-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a
1 to TOF has no effect.
1 = Counter has reached modulo value
0 = Counter has not reached modulo value
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Registers
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the counter until software clears the TSTOP bit.
1 = Counter stopped
0 = Counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode. Also, when the TSTOP bit is set and the timer is
configured for input capture operation, input captures are inhibited until the
TSTOP bit is cleared.
TRST — TIM Reset Bit
Setting this write-only bit resets the counter and the TIM prescaler. Setting TRST has no effect on any
other timer registers. Counting resumes from $0000. TRST is cleared automatically after the counter
is reset and always reads as 0.
1 = Prescaler and counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the counter at a
value of $0000. PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the counter as
Table 15-1 shows.
Table 15-1. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
TCLK (if available)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
15.8.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
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Timer Interface Module (TIM)
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0
0
0
0
0
0
0
0
Figure 15-5. TIM Counter High Register (TCNTH)
Bit 7
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
Reset:
= Unimplemented
Figure 15-6. TIM Counter Low Register (TCNTL)
15.8.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the counter. When the counter reaches
the modulo value, the overflow flag (TOF) becomes set, and the counter resumes counting from $0000
at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until
the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Bit 7
Bit15
1
6
Bit14
1
5
Bit13
1
4
Bit12
1
3
Bit11
1
2
Bit10
1
1
Bit9
1
Bit 0
Bit8
1
Read:
Write:
Reset:
Figure 15-7. TIM Counter Modulo High Register (TMODH)
Bit 7
Bit7
1
6
Bit6
1
5
Bit5
1
4
Bit4
1
3
Bit3
1
2
Bit2
1
1
Bit1
1
Bit 0
Bit0
1
Read:
Write:
Reset:
Figure 15-8. TIM Counter Modulo Low Register (TMODL)
NOTE
Reset the counter before writing to the TIM counter modulo registers.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
182
Freescale Semiconductor
Registers
15.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
•
•
•
•
•
•
•
•
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Bit 7
CH0F
0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read:
Write:
Reset:
0
Figure 15-9. TIM Channel 0 Status and Control Register (TSC0)
Bit 7
CH1F
0
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read:
Write:
Reset:
CH1IE
0
0
0
= Unimplemented
Figure 15-10. TIM Channel 1 Status and Control Register (TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM interrupt service requests on channel x.
1 = Channel x interrupt requests enabled
0 = Channel x interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TSC0.
Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to
general-purpose I/O.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
183
Timer Interface Module (TIM)
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See Table 15-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 15-2).
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Table 15-2. Mode, Edge, and Level Selection
MSxB
MSxA
ELSxB
ELSxA
Mode
Configuration
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
X
X
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
X
X
X
0
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
Output preset
Input capture
Toggle output on compare
Output compare
or PWM
Clear output on compare
Set output on compare
Toggle output on compare
Buffered output
compare or
buffered PWM
Clear output on compare
Set output on compare
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 15-2 shows how ELSxB and ELSxA work.
NOTE
After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
184
Freescale Semiconductor
Registers
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 15-11 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 15-11. CHxMAX Latency
15.8.5 TIM Channel Registers
These read/write registers contain the captured counter value of the input capture function or the output
compare value of the output compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after reset
Figure 15-12. TIM Channel x Register High (TCHxH)
Bit 7
Bit 7
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Indeterminate after reset
Figure 15-13. TIM Channel Register Low (TCHxL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
185
Timer Interface Module (TIM)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
186
Chapter 16
Development Support
16.1 Introduction
This section describes the break module, the monitor module, and the monitor mode entry methods.
16.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
•
•
•
•
Accessible input/output (I/O) registers during the break Interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
16.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
•
A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
•
Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 16-2 shows the structure of the break module.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
187
Development Support
PTA0/AD0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2/TCLK
PTA3/RST/KBI3
INTERNAL OSC
INTERNAL CLOCK SOURCE
4, 8, 12.8, or 25.6 MHz
KEYBOARD INTERRUPT
MODULE
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
EXTERNAL INTERRUPT
MODULE
M68HC08 CPU
PTB0/TCH0
PTB1
AUTO WAKEUP
MODULE
PTB2/AD4
PTB3/AD5
PTB4/SLCRX
PTB5/SLCTX
PTB6
LOW-VOLTAGE
INHIBIT
2-CHANNEL 16-BIT
TIMER MODULE
PTB7
COP
MODULE
MC68HC908QL4
4096 BYTES
MC68HC908QL4
128 BYTES
USER RAM
USER FLASH
6-CHANNEL
10-BIT ADC
SLAVE LIN INTERFACE
CONTROLLER
VDD
VSS
POWER SUPPLY
DEVELOPMENT SUPPORT
MONITOR ROM
BREAK MODULE
RST, IRQ: Pins have internal pull up device
All port pins have programmable pull up device (pullup/down on port A)
PTA[0:5]: Higher current sink and source capability
Figure 16-1. Block Diagram Highlighting BRK and MON Blocks
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
188
Break Module (BRK)
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
CONTROL
BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 16-2. Break Module Block Diagram
When the internal address bus matches the value written in the break address registers or when software
writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by:
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is:
•
•
•
When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
16.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 13.8.2 Break Flag Control Register and the Break Interrupts subsection
for each module.
16.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
189
Development Support
16.2.2 Break Module Registers
These registers control and monitor operation of the break module:
•
•
•
•
•
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
16.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 16-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit
7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Break address match
0 = No break address match
16.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
Bit 7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 16-4. Break Address Register High (BRKH)
Bit 7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
Bit 0
Bit 0
0
Read:
Write:
Reset:
Figure 16-5. Break Address Register Low (BRKL)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
190
Freescale Semiconductor
Break Module (BRK)
16.2.2.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the
MCU is in a state of break interrupt with monitor mode.
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
BDCOP
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt
16.2.2.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SBSW
Note(1)
0
R
R
R
R
R
R
R
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 16-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
16.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU
is in a break state.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
R
0
= Reserved
R
Figure 16-8. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
191
Development Support
16.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the
break module will remain enabled in wait and stop modes. However, since the internal address bus does
not increment in these modes, a break interrupt will never be triggered.
16.3 Monitor Module (MON)
The monitor module allows debugging and programming of the microcontroller unit (MCU) through a
single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher
test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware
requirements for in-circuit programming.
Features include:
•
•
•
•
•
•
•
•
•
•
Normal user-mode pin functionality
One pin dedicated to serial communication between MCU and host computer
Standard non-return-to-zero (NRZ) communication with host computer
Standard communication baud rate (7200 @ 2-MHz bus frequency)
Execution of code in random-access memory (RAM) or FLASH
FLASH memory security feature(1)
FLASH memory programming interface
Use of external 9.8304 MHz crystal or clock to generate internal frequency of 2.4576 MHz
Simple internal oscillator mode of operation (no external clock or high voltage)
Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
•
Normal monitor mode entry if VTST is applied to IRQ
16.3.1 Functional Description
Figure 16-9 shows a simplified diagram of monitor mode entry.
The monitor module receives and executes commands from a host computer. Figure 16-10, Figure 16-11,
and Figure 16-12 show example circuits used to enter monitor mode and communicate with a host
computer via a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
code downloaded into RAM by a host computer while most MCU pins retain normal operating mode
functions. All communication between the host computer and the MCU is through the PTA0 pin. A
level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used
in a wired-OR configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at 9600 baud in monitor mode by using
the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz). Since this feature is enabled only
when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value
is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must
remain low during this monitor session in order to maintain communication.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
192
Freescale Semiconductor
Monitor Module (MON)
POR RESET
YES
NO
IRQ = VTST
?
CONDITIONS
FROM Table 16-1
PTA0 = 1,
PTA1 = 1, AND
PTA4 = 0?
PTA0 = 1,
RESET VECTOR
BLANK?
NO
NO
YES
YES
FORCED
MONITOR MODE
NORMAL
USER MODE
NORMAL
MONITOR MODE
INVALID
USER MODE
HOST SENDS
8 SECURITY BYTES
YES
IS RESET
POR?
NO
ARE ALL
SECURITY BYTES
CORRECT?
YES
NO
ENABLE FLASH
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING
AND FLASH
PROGRAMMING
(IF FLASH
IS ENABLED)
EXECUTE
MONITOR CODE
NO
YES
DOES RESET
OCCUR?
Figure 16-9. Simplified Monitor Mode Entry Flowchart
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
193
Development Support
VDD
VDD
10 kΩ*
VDD
RST (PTA3)
0.1 µF
9.8304 MHz CLOCK
VTST
MAX232
VDD
OSC1 (PTA5)
1
16
15
2
C1+
+
+
+
VDD
1 µF
1 µF
3
4
C1–
C2+
1 µF
+
1 kΩ
10 kΩ*
10 kΩ*
PTA1
V+
V–
IRQ (PTA2)
VDD
1 µF
6
5
9.1 V
C2–
1 µF
10 kΩ
+
PTA4
74HC125
6
DB9
5
10
9
2
7
8
PTA0
74HC125
3
2
4
3
5
VSS
1
* Value not critical
Figure 16-10. Monitor Mode Circuit (External Clock, with High Voltage)
VDD
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
VDD
1
16
15
2
9.8304 MHz CLOCK
C1+
OSC1 (PTA5)
+
+
+
1 µF
1 µF
3
4
1 µF
C1–
C2+
+
PTA1
PTA4
N.C.
N.C.
10 kΩ*
V+
V–
VDD
IRQ (PTA2)
1 µF
6
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
2
7
8
6
PTA0
74HC125
3
4
3
5
2
VSS
1
Figure 16-11. Monitor Mode Circuit (External Clock, No High Voltage)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
194
Freescale Semiconductor
Monitor Module (MON)
VDD
N.C.
N.C.
RST (PTA3)
VDD
0.1 µF
MAX232
VDD
OSC1 (PTA5)
IRQ (PTA2)
1
16
15
2
C1+
+
+
+
1 µF
1 µF
PTA1
PTA4
N.C.
N.C.
3
4
1 µF
C1–
C2+
+
10 kΩ*
VDD
V+
V–
1 µF
6
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
2
7
8
6
PTA0
VSS
74HC125
3
2
4
3
5
1
* Value not critical
Figure 16-12. Monitor Mode Circuit (Internal Clock, No High Voltage)
Table 16-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
•
•
•
If $FFFE and $FFFF do not contain $FF (programmed state):
–
–
The external clock is 9.8304 MHz
IRQ = VTST
If $FFFE and $FFFF contain $FF (erased state):
–
–
The external clock is 9.8304 MHz
IRQ = VDD (this can be implemented through the internal IRQ pullup)
If $FFFE and $FFFF contain $FF (erased state):
IRQ = VSS (internal oscillator is selected, no external clock required)
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
195
Development Support
Table 16-1. Monitor Mode Signal Requirements and Options
Serial
Communi-
cation
Mode
Selection
Communication
Speed
IRQ
Mode
RST Reset
(PTA3) Vector
COP
Comments
(PTA2)
External
Clock Frequency Rate
Bus
Baud
PTA0
PTA1 PTA4
Normal
VTST
9.8304
MHz
2.4576
MHz
Provide external
clock at OSC1.
VDD
X
1
1
0
Disabled
9600
Monitor
$FFFF
(blank)
9.8304
MHz
2.4576
MHz
Provide external
clock at OSC1.
VDD
X
X
X
1
1
X
X
X
X
X
X
Disabled
Disabled
Enabled
9600
9600
X
Forced
Monitor
$FFFF
(blank)
3.2 MHz
(Trimmed)
Internal clock is
active.
VSS
X
X
Not
$FFFF
User
X
X
X
MON08
Function
[Pin No.]
VTST
[6]
RST
[4]
COM
[8]
MOD0 MOD1
[12] [10]
OSC1
[13]
—
—
—
—
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256 and baud rate using internal oscillator is bus frequency / 333.
3. External clock is a 9.8304 MHz oscillator on OSC1.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
NC
NC
NC
NC
1
3
5
7
9
2
4
GND
RST
IRQ
6
8
PTA0
PTA4
PTA1
NC
10
12
14
16
NC 11
OSC1 13
VDD
15
NC
.
16.3.1.1 Normal Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is
applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in
monitor mode, but the pin functions will be determined by the settings in the configuration registers (see
Chapter 5 Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and
BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register.
If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
196
Freescale Semiconductor
Monitor Module (MON)
16.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions,
(PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit
programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset
vector has been programmed, the traditional method of applying a voltage,
VTST, to IRQ must be used to enter monitor mode.
If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled
regardless of the state of IRQ.
If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal
circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors
are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high
voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at
its default frequency.
If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will
operate as a serial communication port and OSC1 input respectively (refer to Figure 16-11). That will
allow the clock to be driven from an external source through OSC1 pin.
If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as
serial communication port. Refer to Figure 16-12.
Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the
Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is
enabled, regardless of the settings in the configuration register. See Chapter 5 Configuration Register
(CONFIG).
The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will
automatically force the MCU to come back to the forced monitor mode.
16.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE
Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST (when RST pin
available) low will not exit monitor mode in this situation.
Table 16-2 summarizes the differences between user mode and monitor mode regarding vectors.
Table 16-2. Mode Differences
Functions
Modes
User
Reset
Vector High
Reset
Vector Low
Break
Vector High
Break
Vector Low
SWI
Vector High
SWI
Vector Low
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
Monitor
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
197
Development Support
16.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
NEXT
START
BIT
START
BIT
BIT 6
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 7
Figure 16-13. Monitor Data Format
16.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
MISSING STOP BIT
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 16-14. Break Transaction
16.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in Table 16-1.
Table 16-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
16.3.1.7 Commands
The monitor ROM firmware uses these commands:
•
•
•
•
•
•
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
198
Freescale Semiconductor
Monitor Module (MON)
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
4
4
1
1
4
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 16-15. Read Transaction
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
WRITE
3
3
1
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, approximately 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 16-16. Write Transaction
A brief description of each monitor mode command is given in Table 16-3 through Table 16-8.
Table 16-3. READ (Read Memory) Command
Description Read byte from memory
Operand 2-byte address in high-byte:low-byte order
Data Returned Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO MONITOR
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
199
Development Support
Table 16-4. WRITE (Write Memory) Command
Description Write byte to memory
Operand 2-byte address in high-byte:low-byte order; low byte followed by data byte
Data Returned None
Opcode $49
Command Sequence
FROM HOST
ADDRESS
HIGH
ADDRESS ADDRESS
HIGH LOW
ADDRESS
LOW
DATA
DATA
WRITE
WRITE
ECHO
Table 16-5. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand None
Data Returned Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
Table 16-6. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand Single data byte
Data Returned None
Opcode $19
Command Sequence
FROM HOST
DATA
DATA
IWRITE
ECHO
IWRITE
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full
64-Kbyte memory map.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
200
Freescale Semiconductor
Monitor Module (MON)
Table 16-7. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Returns incremented stack pointer value (SP + 1) in high-byte:low-byte
order
Data Returned
Opcode $0C
Command Sequence
FROM HOST
SP
HIGH
SP
LOW
READSP
ECHO
READSP
RETURN
Table 16-8. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand None
Data Returned None
Opcode $28
Command Sequence
FROM HOST
RUN
ECHO
RUN
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command
tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program. The READSP command returns
the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at
addresses SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
CONDITION CODE REGISTER
ACCUMULATOR
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 7
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
Figure 16-17. Stack Pointer at Monitor Mode Entry
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
201
Development Support
16.3.2 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6–$FFFD blank. For security reasons, program
locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTA0. If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. See Figure 16-18.
Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
VDD
4096 + 32 BUSCLKX4 CYCLES
RST
FROM HOST
PA0
5
1
1
4
1
4
2
1
FROM MCU
Notes:
1 = Echo delay, approximately 2 bit times
2 = Data return delay, approximately 2 bit times
4 = Wait 1 bit time before sending next byte
5 = Wait until the monitor ROM runs
Figure 16-18. Monitor Mode Entry Timing
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
202
Freescale Semiconductor
Chapter 17
Electrical Specifications
17.1 Introduction
This section contains electrical and timing specifications.
17.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without
permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 17.5 5-V DC Electrical Characteristics and 17.8 3.3-V DC Electrical
Characteristics for guaranteed operating conditions.
Characteristic(1)
Symbol
VDD
Value
–0.3 to +6.0
VSS –0.3 to VDD +0.3
VSS –0.3 to +9.1
15
Unit
V
Supply voltage
Input voltage
VIN
V
Mode entry voltage, IRQ pin
VTST
V
Maximum current per pin excluding PTA0–PTA5, VDD, and VSS
Maximum current for pins PTA0–PTA5
Storage temperature
I
mA
mA
°C
mA
mA
I
PTA0—IPTA5
TSTG
IMVSS
IMVDD
±25
–55 to +150
100
Maximum current out of VSS
Maximum current into VDD
100
1. Voltages references to VSS
.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
203
Electrical Specifications
17.3 Functional Operating Range
Temperature
Code
Characteristic
Symbol
Value
Unit
– 40 to +125
– 40 to +105
–40 to +85
M
V
C
TA
Operating temperature range
Operating voltage range
°C
(TL to TH)
VDD
3.0 to 5.5
V
—
17.4 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
16-pin SOIC
θJA
90
°C/W
16-pin TSSOP
133
I/O pin power dissipation
Power dissipation(1)
PI/O
PD
User determined
PD = (IDD x VDD
+ PI/O = K/(TJ + 273°C)
W
W
)
PD x (TA + 273°C)
+ PD2 x θJA
Constant(2)
K
W/°C
Average junction temperature
TJ
TA + (PD x θJA)
°C
°C
Maximum junction temperature
TJM
150
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ
can be determined for any value of TA.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
204
Freescale Semiconductor
5-V DC Electrical Characteristics
17.5 5-V DC Electrical Characteristics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
V
Output high voltage
I
Load = –2.0 mA, all I/O pins
ILoad = –10.0 mA, all I/O pins
Load = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only
VDD–0.4
VDD–1.5
DD–0.8
—
—
—
—
—
—
VOH
I
V
Maximum combined IOH (all I/O pins)
IOHT
—
—
50
mA
V
Output low voltage
ILoad = 1.6 mA, all I/O pins
ILoad = 10.0 mA, all I/O pins
ILoad = 15.0 mA, PTA0, PTA1, PTA3–PTA5 only
—
—
—
—
—
—
0.4
1.5
0.8
VOL
Maximum combined IOL (all I/O pins)
IOHL
VIH
—
—
—
50
mA
V
Input high voltage
PTA0–PTA5, PTB0–PTB7
0.7 x VDD
VSS
VDD
Input low voltage
PTA0–PTA5, PTB0–PTB7
VIL
—
0.3 x VDD
V
Input hysteresis(3)
VHYS
IINJ
IINJTOT
IIL
0.06 x VDD
—
—
—
+2
V
DC injection current, all ports(4)
Total dc current injection (sum of all I/O)(4)
Ports Hi-Z leakage current
–2
–25
–1
mA
mA
µA
—
+25
+1
±0.1
Capacitance
CIN
—
—
8
pF
Ports (as input)(3)
POR rearm voltage
VPOR
RPOR
VTST
750
0.035
—
—
—
—
—
mV
V/ms
V
POR rise time ramp rate(3)(5)
Monitor mode entry voltage (3)
VDD + 2.5
9.1
Pullup resistors(6)
PTA0–PTA5, PTB0–PTB7
RPU
RPD
16
16
26
26
36
36
kΩ
kΩ
Pulldown resistors(7)
PTA0–PTA5
Low-voltage inhibit reset, trip falling voltage
Low-voltage inhibit reset, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
VTRIPF
VTRIPR
VHYS
3.90
4.00
—
4.20
4.30
100
4.50
4.60
—
V
V
mV
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Values are based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
6. RPU is measured at VDD = 5.0 V. Pullup resistors only available when PTAPUEx is enabled with KBIPx = 0.
7. RPD is measured at VDD = 5.0 V, Pulldown resistors only available when PTAPUEx is enabled with KBIPx =1.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
205
Electrical Specifications
17.6 Typical 5-V Output Drive Characteristics
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5V PTA
5V PTB
0
-5
-10
-15
-20
-25
-30
IOH (mA )
Figure 17-1. Typical 5-Volt Output High Voltage
versus Output High Current (25°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5V PTA
5V PTB
0
5
10
15
20
25
30
IOL (mA )
Figure 17-2. Typical 5-Volt Output Low Voltage
versus Output Low Current (25°C)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
206
5-V Control Timing
17.7 5-V Control Timing
Characteristic(1)
Internal operating frequency
Internal clock period (1/fOP
Symbol
Min
Max
Unit
fOP
—
8
MHz
(fBUS
)
)
tcyc
125
100
—
—
—
—
ns
ns
RST input pulse width low(2)
tRL
IRQ interrupt pulse width low (edge-triggered)(2)
IRQ interrupt pulse period(2)
tILIH
tILIL
100
ns
Note(3)
tcyc
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. Values are based on characterization results, not tested in production.
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc
.
tRL
RST
tILIL
tILIH
IRQ
Figure 17-3. RST and IRQ Timing
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
207
Electrical Specifications
17.8 3.3-V DC Electrical Characteristics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
V
Output high voltage
ILoad = –0.6 mA, all I/O pins
Load = –4.0 mA, all I/O pins
ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only
Maximum combined IOH (all I/O pins)
Output low voltage
Load = 0.5 mA, all I/O pins
ILoad = 6.0 mA, all I/O pins
ILoad = 10.0 mA, PTA0, PTA1, PTA3–PTA5 only
VDD–0.3
VDD–1.0
VDD–0.8
—
—
—
—
—
—
VOH
IOHT
VOL
I
—
—
50
mA
V
I
—
—
—
—
—
—
0.3
1.0
0.8
Maximum combined IOL (all I/O pins)
IOHL
VIH
—
—
—
50
mA
V
Input high voltage
PTA0–PTA5, PTB0–PTB7
0.7 x VDD
VDD
Input low voltage
PTA0–PTA5, PTB0–PTB7
VIL
VSS
—
0.3 x VDD
V
Input hysteresis(3)
VHYS
IINJ
IINJTOT
IIL
0.06 x VDD
—
—
—
+2
V
DC injection current, all ports(4)
Total dc current injection (sum of all I/O)(4)
Ports Hi-Z leakage current
–2
–25
–1
mA
mA
µA
—
+25
+1
±0.1
Capacitance
CIN
—
—
8
pF
Ports (as input)(3)
POR rearm voltage
VPOR
RPOR
VTST
0.75
0.035
—
—
—
—
—
V
V/ms
V
POR rise time ramp rate(3)(5)
Monitor mode entry voltage (3)
VDD + 2.5
VDD + 4.0
Pullup resistors(6)
PTA0–PTA5, PTB0–PTB7
RPU
RPD
16
16
26
26
36
36
kΩ
kΩ
Pulldown resistors(7)
PTA0–PTA5
Low-voltage inhibit reset, trip falling voltage
Low-voltage inhibit reset, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
VTRIPF
VTRIPR
VHYS
2.65
2.75
—
2.8
2.9
3.0
3.10
—
V
V
100
mV
1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Values are based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
5. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
DD is reached.
V
6. RPU is measured at VDD = 3.3 V. Pullup resistors only available when PTAPUEx is enabled with KBIPx = 0.
7. RPD is measured at VDD = 3.3 V, Pulldown resistors only available when PTAPUEx is enabled with KBIPx =1.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
208
Freescale Semiconductor
Typical 3.3-V Output Drive Characteristics
17.9 Typical 3.3-V Output Drive Characteristics
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.3V PTA
3.3V PTB
0
-5
-10
-15
-20
-25
IOH (mA)
Figure 17-4. Typical 3.3-Volt Output High Voltage
versus Output High Current (25°C)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.3V PTA
3.3V PTB
0
5
10
15
20
25
IOL (mA)
Figure 17-5. Typical 3.3-Volt Output Low Voltage
versus Output Low Current (25°C)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
209
Electrical Specifications
17.10 3.3-V Control Timing
Characteristic(1)
Symbol
fOP (fBus
tcyc
Min
—
Max
4
Unit
MHz
ns
Internal operating frequency
)
Internal clock period (1/fOP
)
250
—
—
—
—
RST input pulse width low(2)
tRL
200
ns
IRQ interrupt pulse width low (edge-triggered)(2)
IRQ interrupt pulse period(2)
tILIH
200
ns
tILIL
Note(3)
tcyc
1. VDD = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Values are based on characterization results, not tested in production.
3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc
.
tRL
RST
tILIL
tILIH
IRQ
Figure 17-6. RST and IRQ Timing
17.11 Oscillator Characteristics
Characteristic
Internal oscillator frequency(1)
Symbol
Min
Typ
Max
Unit
ICFS1:ICFS0 = 00
ICFS1:ICFS0 = 01
ICFS1:ICFS0 = 10 (not allowed if VDD <3.0V)
ICFS1:ICFS0 = 11 (not allowed if VDD < 4.5V)
—
—
—
—
4
8
12.8
25.6
—
—
—
—
fINTCLK
MHz
Deviation from trimmed Internal oscillator (2)(3)
4, 8, 12.8, 25.6MHz, fixed voltage, fixed temp
—
± 0.4
—
4, 8, 12.8MHz, VDD ± 10%, 0 to 70°C
4, 8, 12.8MHz, VDD ± 10%, –40 to 85°C
4, 8, 12.8MHz, VDD ± 10%, –40 to 105°C
4, 8, 12.8MHz, VDD ± 10%, –40 to 125°C
—
—
—
—
± 2
—
—
—
—
± 5
± 5
± 5
ACCINT
%
25.6MHz, VDD ± 10%, 0 to 70°C
25.6MHz, VDD ± 10%, –40 to 85°C
25.6MHz, VDD ± 10%, –40 to 105°C
25.6MHz, VDD ± 10%, –40 to 125°C
—
—
—
—
± 5
—
—
—
—
± 10
± 10
± 10
Table continued on next page
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
210
Oscillator Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
External RC oscillator frequency, RCCLK (1)(2)
VDD ≥ 3.0 V
VDD < 3.0 V
fRCCLK
2
2
—
—
10
8.4
MHz
External clock reference frequencyy(1)(4)(5)
VDD ≥ 4.5V
VDD ≥ 3.0V
VDD < 3.0V
—
—
—
dc
dc
dc
32
16
8.4
fOSCXCLK
MHz
—
RC oscillator external resistor
VDD = 5 V
VDD = 3 V
REXT
See Figure 17-7
See Figure 17-8
Crystal frequency, XTALCLK(1)(6)(7)
ECFS1:ECFS0 = 00 ( VDD ≥ 4.5 V)
ECFS1:ECFS0 = 00 (not allowed if VDD < 3.0V)
ECFS1:ECFS0 = 01
8
8
1
—
—
—
—
32
16
8
MHz
MHz
MHz
kHz
fOSCXCLK
ECFS1:ECFS0 = 10
30
100
ECFS1:ECFS0 = 00 (8)
Feedback bias resistor
Crystal load capacitance(9)
Crystal capacitors(9)
RB
CL
C1,C2
—
—
—
1
20
—
—
—
MΩ
pF
pF
(2 x CL) – 5pF
ECFS1:ECFS0 = 01(8)
Crystal series damping resistor
fOSCXCLK = 1 MHz
fOSCXCLK = 4 MHz
fOSCXCLK = 8 MHz
Feedback bias resistor
Crystal load capacitance(9)
Crystal capacitors(9)
RS
—
—
—
—
—
—
20
10
0
5
18
—
—
—
—
—
—
kΩ
kΩ
kΩ
MΩ
pF
RB
CL
C1,C2
(2 x CL) –10 pF
pF
AWU Module: Internal RC oscillator frequency
fINTRC
—
32
—
kHz
1. Bus frequency, fOP, is oscillator frequency divided by 4.
2. Deviation values assumes trimming @25°C and midpoint of voltage range, for example 5.0 V for 5 V ± 10%,
3.3 V for 3.3 V ± 10%.
3. Values are based on characterization results, not tested in production.
4. No more than 10% duty cycle deviation from 50%.
5. When external oscillator clock is greater than 1MHz, ECFS1:ECFS0 must be 00 or 01
6. Use fundamental mode only, do not use overtone crystals or overtone ceramic resonators
7. Due to variations in electrical properties of external components such as, ESR and Load Capacitance, operation above
16 MHz is not guaranteed for all crystals or ceramic resonators. Operation above 16 MHz requires that a Negative
Resistance Margin (NRM) characterization and component optimization be performed by the crystal or ceramic resonator
vendor for every different type of crystal or ceramic resonator which will be used. This characterization and optimization
must be performed at the extremes of voltage and temperature which will be applied to the microcontroller in the
application. The NRM must meet or exceed 10x the maximum ESR of the crystal or ceramic resonator for acceptable
performance.
8. Do not use damping resistor when ECFS1:ECFS0 = 00, 10 or 11
9. Consult crystal vendor data sheet.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
211
Electrical Specifications
12
10
8
5V 25 oC
6
4
2
0
0
10
20
30
ext (k ohms)
40
50
60
R
Figure 17-7. RC versus Frequency (5 Volts @ 25°C)
12
10
8
3.3V 25 oC
6
4
2
0
0
10
20
30
ext (k ohms)
40
50
60
R
Figure 17-8. RC versus Frequency (3.3 Volts @ 25°C)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
212
Freescale Semiconductor
Supply Current Characteristics
17.12 Supply Current Characteristics
Bus
Frequency
(MHz)
Characteristic(1)
Typ(2)
Voltage
Symbol
Max
Unit
5.0
3.3
3.2
3.2
7.25
3.2
8.5
4.5
Run mode VDD supply current(3)
Wait mode VDD supply current(4)
RIDD
WIDD
mA
mA
5.0
3.3
3.2
3.2
1.25
0.80
1.8
1.2
Stop mode VDD supply current(5)
–40 to 85°C
–40 to 105°C
–40 to 125°C
25°C with auto wake-up enabled
Incremental current with LVI enabled at 25°C
Stop mode VDD supply current(4)
–40 to 85°C
–40 to 105°C
–40 to 125°C
0.26
—
—
12
125
1
2
5
—
—
µA
µA
µA
µA
µA
5.0
3.3
SIDD
0.23
—
—
2
100
0.5
1
4
—
—
µA
µA
µA
µA
µA
25°C with auto wake-up enabled
Incremental current with LVI enabled at 25°C
1. VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurement at 25°C only.
3. Run (operating) IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs
and tied to 0.2 V from rail.
4. Wait IDD measured using trimmed internal oscillator, ADC off, all modules enabled. All pins configured as inputs and tied
to 0.2 V from rail.
5. Stop IDD measured with all pins configured as inputs and tied to 0.2 V from rail.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
213
Electrical Specifications
15
14
13
12
11
10
9
Internal OSC (No A/D,SLIC)
Internal OSC all Modules enabled
Ex ternal Reference (No A/D, SLIC)
Ex ternal Reference All modules enabled
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
Freq.
Figure 17-9. Typical 5-Volt Run Current versus Bus Frequency (25°C)
4
Internal OSC (No A/D,SLIC)
3
Internal OSC all Modules enabled
2
Ex ternal Reference (No A/D, SLIC)
1
Ex ternal Reference All modules enabled
0
0
1
2
3
4
5
6
7
Freq.
Figure 17-10. Typical 3.3-Volt Run Current versus Bus Frequency (25°C)
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
214
Freescale Semiconductor
ADC10 Characteristics
17.13 ADC10 Characteristics
Typ(1)
—
Characteristic
Supply voltage
Conditions
Absolute
Symbol
Min
3.0
—
Max
5.5
—
Unit
Comment
VDD
V
Supply Current
ADLPC = 1
ADLSMP = 1
ADCO = 1
VDD < 3.6 V (3.3 V Typ)
55
(2)
IDD
µA
VDD < 5.5 V (5.0 V Typ)
—
—
—
—
—
—
—
75
—
—
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
V
DD < 3.6 V (3.3 V Typ)
VDD < 5.5 V (5.0 V Typ)
DD < 3.6 V (3.3 V Typ)
120
175
140
180
340
440
(2)
IDD
µA
µA
—
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
V
—
(2)
IDD
VDD < 5.5 V (5.0 V Typ)
VDD < 3.6 V (3.3 V Typ)
—
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
—
(2)
IDD
µA
VDD < 5.5 V (5.0 V Typ)
615
High speed (ADLPC = 0)
0.40(3)
0.40(3)
19
—
—
19
39
16
36
4
2.00
1.00
21
ADC internal clock
fADCK
tADC
tADC
tADS
MHz
tADCK = 1/fADCK
Low power (ADLPC = 1)
Conversion time (4)
10-bit Mode
tADCK
cycles
Short sample (ADLSMP = 0)
Long sample (ADLSMP = 1)
Short sample (ADLSMP = 0)
Long sample (ADLSMP = 1)
Short sample (ADLSMP = 0)
Long sample (ADLSMP = 1)
39
41
Conversion time (4)
8-bit Mode
tADCK
cycles
16
18
36
38
4
4
tADCK
cycles
Sample time
24
24
—
7
24
Input voltage
VADIN
CADIN
RADIN
VSS
—
VDD
10
V
Input capacitance
Input impedance
pF
kΩ
Not tested
Not tested
—
5
15
External to
MCU
Analog source impedance
Ideal resolution (1 LSB)
RAS
—
—
10
kΩ
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
1.758
5
5.371
21.48
±2.5
±1.0
—
RES
mV
V
REFH/2N
7.031
20
0
0
0
0
±1.5
±0.7
±0.5
±0.3
Includes
quantization
Total unadjusted error
Differential non-linearity
ETUE
DNL
LSB
LSB
—
Monotonicity and no-missing-codes guaranteed
— Continued on next page
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
215
Electrical Specifications
Typ(1)
±0.5
±0.3
±0.5
±0.3
±0.5
±0.3
—
Characteristic
Conditions
10-bit mode
Symbol
Min
0
Max
—
Unit
Comment
Integral non-linearity
INL
LSB
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
0
—
0
—
Zero-scale error
Full-scale error
Quantization error
EZS
EFS
EQ
LSB
LSB
LSB
VADIN = VSS
0
—
0
—
VADIN = VDD
0
—
—
—
0
±0.5
±0.5
±5
8-bit mode is
not truncated
—
Pad leakage(5)
* RAS
±0.2
±0.1
1.245
Input leakage error
EIL
LSB
V
0
±1.2
1.32
Bandgap voltage input(6)
VBG
1.17
1. Typical values assume VDD = 5.0 V, temperature = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Incremental IDD added to MCU mode current.
3. Values are based on characterization results, not tested in production.
4. Reference the ADC module specification for more information on calculating conversion times.
5. Based on typical input pad leakage current.
6. LVI must be enabled, (LVIPWRD = 0, in CONFIG1). Voltage input to ADCH4:0 = $1A, an ADC conversion on this channel
allows user to determine supply voltage.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
216
Freescale Semiconductor
Timer Interface Module Characteristics
17.14 Timer Interface Module Characteristics
Characteristic
Timer input capture pulse width(1)
Symbol
TH, tTL
tTLTL
tTCL, tTCH
Min
2
Max
—
Unit
tcyc
tcyc
ns
t
Timer input capture period
Note(2)
—
Timer input clock pulse width(1)
tcyc + 5
—
1. Values are based on characterization results, not tested in production.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc
.
tTLTL
tTH
INPUT CAPTURE
RISING EDGE
tTLTL
tTL
INPUT CAPTURE
FALLING EDGE
tTLTL
tTH
tTL
INPUT CAPTURE
BOTH EDGES
tTCH
TCLK
tTCL
Figure 17-11. Input Capture Timing
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
217
Electrical Specifications
17.15 Memory Characteristics
Characteristic
RAM data retention voltage (1)
Symbol
VRDR
Min
1.3
1
Typ
—
Max
—
Unit
V
FLASH program bus clock frequency
—
—
—
MHz
V
FLASH PGM/ERASE supply voltage (VDD
FLASH read bus clock frequency
)
VPGM/ERASE
2.7
0
—
5.5
8 M
(2)
fRead
—
Hz
FLASH page erase time
<1 K cycles
>1 K cycles
tErase
0.9
3.6
1
4
1.1
5.5
ms
FLASH mass erase time
tMErase
tNVS
4
10
5
—
—
—
—
—
—
—
40
—
4
ms
µs
FLASH PGM/ERASE to HVEN setup time
FLASH high-voltage hold time
tNVH
—
µs
FLASH high-voltage hold time (mass erase)
FLASH program hold time
tNVHL
tPGS
100
5
—
µs
—
µs
FLASH program time
tPROG
30
1
—
µs
(3)
FLASH return to read time
tRCV
—
µs
(4)
FLASH cumulative program hv period
FLASH endurance(5)
tHV
—
10 k
15
—
ms
—
—
100 k
100
—
—
Cycles
Years
FLASH data retention time(6)
1. Values are based on characterization results, not tested in production.
2. fRead is defined as the frequency range for which the FLASH memory can be read.
3. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
4. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) ≤ tHV maximum.
5. Typical endurance was evaluated for this product family. For additional information on how Freescale Semiconductor
defines Typical Endurance, please refer to Engineering Bulletin EB619.
6. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines Typical Data
Retention, please refer to Engineering Bulletin EB618.
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
218
Freescale Semiconductor
Chapter 18
Ordering Information and Mechanical Specifications
18.1 Introduction
This section provides ordering information for the MC68HC908QL4, MC68HC908QL3, and
MC68HC908QL2 along with the dimensions for:
•
•
16-pin small outline integrated circuit (SOIC) package
16-pin thin shrink small outline package (TSSOP)
The following figures show the latest package drawings at the time of this publication. To make sure that
you have the latest package specifications, contact your local Freescale Sales Office.
18.2 MC Order Numbers
Table 18-1. MC Order Numbers
MC Order Number
MC908QL4
ADC
Yes
No
FLASH Memory
4096 bytes
Package
16-pins
SOIC,
MC908QL3
4096 bytes
and TSSOP
MC908QL2
Yes
2048 bytes
Temperature and package designators:
C = –40°C to +85°C
V = –40°C to +105°C
M = –40°C to +125°C
DW = Small outline integrated circuit package (SOIC)
DT = Thin shrink small outline package (TSSOP)
M C 9 0 8 Q L X X X X
FAMILY
PACKAGE DESIGNATOR
TEMPERATURE RANGE
Figure 18-1. Device Numbering System
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
219
Ordering Information and Mechanical Specifications
18.3 16-Pin Small Outline Integrated Circuit Package (Case #751G)
A
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
q
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESSOFTHEBDIMENSIONATMAXIMUM
MATERIAL CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
A
M
S
S
0.25
T A
B
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
0.25
0.40
0
0.75
1.00
7
SEATING
PLANE
14X
e
°
°
C
T
18.4 16-Pin Thin Shrink Small Outline Package (Case #948F)
16X KREF
M
S
S
0.10 (0.004) T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEADFLASHORPROTRUSIONSHALL
NOT EXCEED
S
0.15 (0.006) T U
K
K1
16
9
2X L/2
J1
B
-U-
SECTION N-N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOTINCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
M
-V-
N
F
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
---
0.05
0.50
0.65 BSC
0.18
0.09
5.10 0.193 0.200
4.50 0.169 0.177
DETAIL E
1.20
--- 0.047
0.15 0.002 0.006
0.75 0.020 0.030
-W-
C
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
J1 0.09
0.19
H
DETAIL E
SEATING
PLANE
K
-T-
D
G
K1 0.19
L
6.40 BSC
0.252 BSC
M
0
8
0
8
°
°
°
°
MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
220
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© Freescale Semiconductor, Inc. 2004. All rights reserved.
LDCForFreescaleSemiconductor@hibbertgroup.com
MC68HC908QL4
Rev. 4, 12/2004
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