MC9328MXLVM20R2 [MOTOROLA]
RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA256, 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-256;
| 型号： | MC9328MXLVM20R2 |
| 厂家： | 
MOTOROLA |
| 描述： | RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA256, 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-256 时钟 外围集成电路 |
| 文件： | 总82页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MC9328MXL/D
Rev. 3.1, 6/2003
MC9328MXL
i.MX Integrated Portable
System Processor
Contents
1 Introduction
1 Introduction . . . . . . . . . . . 1
2 Signals and
Connections. . . . . . . . . . 4
3 Specifications . . . . . . . . 10
4 Pin-Out and Package
The i.MX family builds on the DragonBall family of application processors which have
demonstrated leadership in the portable handheld market. Continuing this legacy, the i.MX
(Media Extensions) series provides a leap in performance with an ARM9™ microprocessor
core and highly integrated system functions. The i.MX products specifically address the
requirements of the personal, portable product market by providing intelligent integrated
peripherals, an advanced processor core, and power management capabilities.
Information. . . . . . . . . . 78
The new MC9328MXL features the advanced and power-efficient ARM920T™ core that
operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller,
USB support, and an MMC/SD host controller, support a suite of peripherals to enhance any
product seeking to provide a rich multimedia experience. It is packaged in either a 256-pin
Mold Array Process-Ball Grid Array (MAPBGA) or 225-pin PBGA package. Figure 1 shows
the functional block diagram of the MC9328MXL.
Standard
System I/O
System Control
Power
Control
CGM
(PLLx2)
JTAG/ICE
Bootstrap
GPIO
PWM
Connectivity
MC9328MXL
CPU Complex
ARM9TDMI™
MMC/SD
Timer 1 & 2
RTC
Memory Stick®
Host Controller
Watchdog
SPI 1 and
SPI 2
I Cache
D Cache
Multimedia
UART 1
UART 2
Multimedia
Accelerator
Interrupt
Controller
AIPI 1
AIPI 2
VMMU
Video Port
2
SSI/I S
DMAC
Bus
Human Interface
2
I C
(11 Chnl)
Control
LCD Controller
EIM &
SDRAMC
USB Device
Figure 1. MC9328MXL Functional Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change
without notice. © Motorola, Inc., 2003. All rights reserved.
Introduction
1.1 Conventions
This document uses the following conventions:
•
•
•
•
•
•
•
•
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
A signal is an electronic construct whose state conveys or changes in state convey information.
A pin is an external physical connection. The same pin can be used to connect a number of signals.
Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
•
•
•
LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x
are hexadecimal.
1.2 Features
To support a wide variety of applications, the MC9328MXL offers a robust array of features, including the
following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM920T™ Microprocessor Core
AHB to IP Bus Interfaces (AIPIs)
External Interface Module (EIM)
SDRAM Controller (SDRAMC)
DPLL Clock and Power Control Module
Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2)
Two Serial Peripheral Interfaces (SPI1 and SPI2)
Two General-Purpose 32-bit Counters/Timers
Watchdog Timer
Real-Time Clock/Sampling Timer (RTC)
LCD Controller (LCDC)
Pulse-Width Modulation (PWM) Module
Universal Serial Bus (USB) Device
Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
Memory Stick® Host Controller (MSHC)
2
MC9328MXL Advance Information
MOTOROLA
Introduction
•
•
Direct Memory Access Controller (DMAC)
Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module
•
•
•
•
•
•
•
•
•
Inter-IC (I2C) Bus Module
Video Port
General-Purpose I/O (GPIO) Ports
Bootstrap Mode
Multimedia Accelerator (MMA)
Power Management Features
Operating Voltage Range: 1.7 V to 1.98 V core, 1.7 V to 3.3V I/O
256-pin MAPBGA Package
225-pin MAPBGA Package
1.3 Target Applications
The MC9328MXL is targeted for advanced information appliances, smart phones, Web browsers, digital
MP3 audio players, handheld computers, and messaging applications.
1.4 Product Documentation
The following documents are required for a complete description of the MC9328MXL and are necessary to
design properly with the device. Especially for those not familiar with the ARM920T processor or
previous DragonBall products, the following documents are helpful when used in conjunction with this
document.
ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100)
ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029)
ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C)
EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E)
MC9328MXL Product Brief (order number MC9328MXLP/D)
MC9328MXL Reference Manual (order number MC9328MXLRM/D)
The Motorola manuals are available on the Motorola Semiconductors Web site at
http://www.motorola.com/semiconductors. These documents may be downloaded directly from the
Motorola Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from
http://www.arm.com.
MOTOROLA
MC9328MXL Advance Information
3
Signals and Connections
1.5 Ordering Information
Table 1 provides ordering information for both the 256-lead mold array process ball grid array
(MAPBGA) package and the 225-lead BGA package.
Table 1. MC9328MXL Ordering Information
Package Type
Frequency
Temperature
Solderball Type
Order Number
MC9328MXLVH15
MC9328MXLVM15
MC9328MXLDVH15
MC9328MXLDVM15
MC9328MXLCVH15
MC9328MXLCVM15
MC9328MXLVH20
MC9328MXLVM20
MC9328MXLDVH20
MC9328MXLDVM20
MC9328MXLVF15
MC9328MXLVP15
MC9328MXLDVF15
MC9328MXLDVP15
MC9328MXLCVF15
MC9328MXLCVP15
MC9328MXLVF20
MC9328MXLVP20
MC9328MXLDVF20
MC9328MXLDVP20
0OC to 70OC
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
-30OC to 70OC
-40OC to 85OC
0OC to 70OC
150 MHz
256-lead MAPBGA
200 MHz
150 MHz
200 MHz
-30OC to 70OC
0OC to 70OC
-30OC to 70OC
-40OC to 85OC
0OC to 70OC
225-lead MAPBGA
-30OC to 70OC
2 Signals and Connections
Table 2 identifies and describes the MC9328MXL signals that are assigned to package pins. The signals
are grouped by the internal module that they are connected to.
Table 2. MC9328MXL Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip-Select (EIM)
A[24:0]
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24].
D[31:0]
EB0
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MC9328MXL Advance Information
MOTOROLA
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
EB1
EB2
EB3
OE
Byte Strobe—Active low external enable byte signal that controls D [23:16].
Byte Strobe—Active low external enable byte signal that controls D [15:8].
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0].
Memory Output Enable—Active low output enables external data bus.
Chip-Select—The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are
selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is
selected.
CS [5:0]
ECB
Active low input signal sent by a flash device to the EIM whenever the flash device must
terminate an on-going burst sequence and initiate a new (long first access) burst
sequence.
Active low signal sent by a flash device causing the external burst device to latch the
starting burst address.
LBA
Clock signal sent to external synchronous memories (such as burst flash) during burst
mode.
BCLK
RW signal—Indicates whether external access is a read (high) or write (low) cycle. Used
as a WE input signal by external DRAM.
RW
DTACK
DTACK signal— The external input data acknowledge signal. When using the external
DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus
error when a bus cycle is not terminated by the external DTACK signal after 1022 clock
counts have elapsed.
Bootstrap
System Boot Mode Select—The operational system boot mode of the MC9328MXL upon
system reset is determined by the settings of these pins.
BOOT [3:0]
SDRAM Controller
SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals
A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in
SDRAM/SyncFlash cycles.
SDBA [4:0]
SDIBA [3:0]
SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address
signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in
SDRAM/SyncFlash cycles.
MA [11:10]
MA [9:0]
DQM [3:0]
CSD0
SDRAM address signals
SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0]
are selected on SDRAM/SyncFlash cycles.
SDRAM data enable
SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These
two signals are selectable by programming the system control register.
SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two
signals are selectable by programming the system control register. By default, CSD1 is
selected, so it can be used as SyncFlash boot chip-select by properly configuring BOOT
[3:0] input pins.
CSD1
RAS
SDRAM/SyncFlash Row Address Select signal
MOTOROLA
MC9328MXL Advance Information
5
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
CAS
SDRAM/SyncFlash Column Address Select signal
SDRAM/SyncFlash Write Enable signal
SDRAM/SyncFlash Clock Enable 0
SDRAM/SyncFlash Clock Enable 1
SDRAM/SyncFlash Clock
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
SyncFlash Reset
Clocks and Resets
Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator
circuit is shut down.
EXTAL16M
XTAL16M
EXTAL32K
XTAL32K
CLKO
Crystal output
32 kHz crystal input
32 kHz crystal output
Clock Out signal selected from internal clock signals.
Master Reset—External active low Schmitt trigger input signal. When this signal goes
active, all modules (except the reset module and the clock control module) are reset.
RESET_IN
RESET_OUT
POR
Reset Out—Internal active low output signal from the Watchdog Timer module and is
asserted from the following sources: Power-on reset, External reset (RESET_IN), and
Watchdog time-out.
Power On Reset—Internal active high Schmitt trigger input signal. The POR signal is
normally generated by an external RC circuit designed to detect a power-up event.
JTAG
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG
controller.
TRST
TDO
TDI
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
TCK
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the
rising edge of TCK.
TMS
DMA
Big Endian—Input signal that determines the configuration of the external chip-select
space. If it is driven logic-high at reset, the external chip-select space will be configured to
little endian. If it is driven logic-low at reset, the external chip-select space will be
configured to big endian.
BIG_ENDIAN
DMA_REQ
External DMA request pin.
6
MC9328MXL Advance Information
MOTOROLA
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Function/Notes
Signal Name
ETM
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM
mode.
ETMTRACESYNC
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM
mode.
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are
selected in ETM mode.
ETMPIPESTAT [2:0]
ETMTRACEPKT [7:0]
ETM packet signals which are multiplexed with ECB, LBA, BCLK, PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
FLM/VSYNC
LP/HSYNC
LSCLK
Line pulse or H sync
Shift clock
ACD/OE
CONTRAST
SPL_SPR
PS
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel
dedicated signal).
CLS
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SPI 1 and 2
Master Out/Slave In
SPI1_MOSI
SPI1_MISO
SPI1_SS
Slave In/Master Out
Slave Select (Selectable polarity)
Serial Clock
SPI1_SCLK
SPI1_SPI_RDY
Serial Data Ready
MOTOROLA
MC9328MXL Advance Information
7
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
Function/Notes
SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows up as
a primary or alternative signal in the signal multiplex scheme table. Please refer to the
SPI and GPIO chapters in the MC9328MXL Reference Manual for information about how
to bring this signal to the assigned pin.
SPI2_TXD
SPI2 Master RxData Input—This signal is multiplexed with a GPI/O pin yet shows up as a
primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI
and GPIO chapters in the MC9328MXL Reference Manual for information about how to
bring this signal to the assigned pin.
SPI2_RXD
SPI2_SS
SPI2 Slave Select—This signal is multiplexed with a GPI/O pin yet shows up as a primary
or alternative signal in the signal multiplex scheme table. Please refer to the SPI and
GPIO chapters in the MC9328MXL Reference Manual for information about how to bring
this signal to the assigned pin.
SPI2 Serial Clock—This signal is multiplexed with a GPI/O pin yet shows up as a primary
or alternative signal in the signal multiplex scheme table. Please refer to the SPI and
GPIO chapters in the MC9328MXL Reference Manual for information about how to bring
this signal to the assigned pin.
SPI2_SCLK
General Purpose Timers
Timer Input Capture or Timer Input Clock—The signal on this input is applied to both
timers simultaneously.
TIN
TMR2OUT
Timer 2 Output
USB Device
USBD_VMO
USBD_VPO
USBD_VM
USB Minus Output
USB Plus Output
USB Minus Input
USB Plus Input
USBD_VP
USBD_SUSPND
USBD_RCV
USBD_OE
USB Suspend Output
USB Receive Data
USB OE
USBD_AFE
USB Analog Front End Enable
Secure Digital Interface
SD Command—If the system designer does not wish to make use of the internal pull-up,
via the Pull-up enable register, a 4.7K–69K external pull up resistor must be added.
SD_CMD
SD_CLK
MMC Output Clock
Data—If the system designer does not wish to make use of the internal pull-up, via the
Pull-up enable register, a 50K–69K external pull up resistor must be added.
SD_DAT [3:0]
Memory Stick Interface
MS_BS
Memory Stick Bus State (Output)—Serial bus control signal
Memory Stick Serial Data (Input/Output)
MS_SDIO
MS_SCLKO
Memory Stick Serial Clock (Input)—Serial protocol clock source for SCLK Divider
8
MC9328MXL Advance Information
MOTOROLA
Signals and Connections
Table 2. MC9328MXL Signal Descriptions (Continued)
Signal Name
MS_SCLKI
Function/Notes
Memory Stick External Clock (Output)—Test clock input pin for SCLK divider. This pin is
only for test purposes, not for use in application mode.
MS_PI0
MS_PI1
General purpose Input0—Can be used for Memory Stick Insertion/Extraction detect
General purpose Input1—Can be used for Memory Stick Insertion/Extraction detect
UARTs – IrDA/Auto-Bauding
Receive Data
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
UART2_RXD
UART2_TXD
UART2_RTS
UART2_CTS
UART2_DSR
UART2_RI
Transmit Data
Request to Send
Clear to Send
Receive Data
Transmit Data
Request to Send
Clear to Send
Data Set Ready
Ring Indicator
UART2_DCD
UART2_DTR
Data Carrier Detect
Data Terminal Ready
Serial Audio Port – SSI (configurable to I2S protocol)
Transmit Data
SSI_TXDAT
SSI_RXDAT
SSI_TXCLK
SSI_RXCLK
SSI_TXFS
Receive Data
Transmit Serial Clock
Receive Serial Clock
Transmit Frame Sync
Receive Frame Sync
SSI_RXFS
I2C
I2C_SCL
I2C_SDA
I2C Clock
I2C Data
PWM
PWMO
PWM Output
Digital Supply Pins
NVDD
NVSS
Digital Supply for the I/O pins
Digital Ground for the I/O pins
MOTOROLA
MC9328MXL Advance Information
9
Specifications
Signal Name
Table 2. MC9328MXL Signal Descriptions (Continued)
Function/Notes
Supply Pins – Analog Modules
AVDD
AVSS
Supply for analog blocks
Quiet ground for analog blocks
Internal Power Supply
QVDD
QVSS
Power supply pins for silicon internal circuitry
Ground pins for silicon internal circuitry
Substrate Supply Pins
SVDD
SGND
Supply routed through substrate of package; not to be bonded
Ground routed through substrate of package; not to be bonded
3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MXL processor.
3.1 Maximum Ratings
Table 3 provides information on maximum ratings.
Table 3. Maximum Ratings
Rating
Symbol
Vdd
Minimum
Maximum
Unit
Supply voltage
-0.3
0
3.3
70
V
°C
TA
Maximum operating temperature range
Storage temperature
Test
-55
150
°C
8001
13002
Power Consumption
Pmax
mW
1. A typical application with 30 pads simultaneously switching assumes the GPIO toggling and instruction
fetches from the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
2. A worst-case application with 70 pads simultaneously switching assumes the GPIO toggling and
instruction fetches from the ARM core-that is, 32x GPIO, 30x Data bus, 8x Address bus. These
calculations are based on the core running its heaviest OS application at 200MHz, and where the whole
image is running out of SDRAM. QVDD at 2.0V, NVDD and AVDD at 3.3V, therefore, 180mA is the worst
measurement recorded in the factory environment, max 5mA is consumed for OSC pads, with each toggle
GPIO consuming 4mA.
10
MC9328MXL Advance Information
MOTOROLA
Specifications
3.2 Recommended Operating Range
Table 4 provides the recommended operating ranges for the supply voltages. The MC9328MXL has
multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal
logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS
provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a
system.
Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter
the AVDD pins from other VDD pins.
For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4.
Table 4. Recommended Operating Range
Rating
Symbol
Minimum Maximum Unit
I/O supply voltage (if using MSHC, SPI, BTA, USBd, LCD and CSI
which are only 3 V interfaces)
NVDD
2.70
3.30
V
NVDD
QVDD
QVDD
AVDD
I/O supply voltage (if not using the peripherals listed above)
Internal supply voltage (Core = 150 MHz)
Internal supply voltage (Core = 200 MHz)
Analog supply voltage
1.70
1.70
1.80
1.70
3.30
1.90
2.00
3.30
V
V
V
V
3.3 DC Electrical Characteristics
Table 5 contains both maximum and minimum DC characteristics of the MC9328MXL.
Table 5. Maximum and Minimum DC Characteristics
Numberor
Symbol
Parameter
Minimum
Typical
Maximum Unit
Full running operating current at 1.8V for QVDD,
3.3V for NVDD/AVDD (Core = 96 MHz, System =
96 MHz, MPEG4 decoding playback from external
memory card to both external SSI audio decoder
and TFT display panel, and OS with MMU
enabled memory system is running on external
SDRAM).
QVDD at 1.8v
= 120mA;
NVDD+AVDD
at 3.0v =
Iop
—
—
mA
30mA
Standby current (Core = 150 MHz, QVDD = 1.8V,
Sidd1
Sidd2
Sidd3
Sidd4
—
—
—
—
25
45
35
60
—
—
—
—
µA
µA
µA
µA
temp = 25°C)
Standby current (Core = 150 MHz, QVDD = 1.8V,
temp = 55°C)
Standby current (Core = 150 MHz, QVDD = 2.0V,
temp = 25°C)
Standby current (Core = 150 MHz, QVDD = 2.0V,
temp = 55°C)
V
0.7V
DD
Input high voltage
Input low voltage
—
—
Vdd+0.2
0.4
V
V
IH
V
—
IL
MOTOROLA
MC9328MXL Advance Information
11
Specifications
Table 5. Maximum and Minimum DC Characteristics (Continued)
Numberor
Symbol
Parameter
Minimum
Typical
Maximum Unit
V
0.7V
DD
Output high voltage (I
= 2.0 mA)
—
—
Vdd
0.4
V
V
V
V
V
OH
OH
V
Output low voltage (I = -2.5 mA)
OL
—
—
OL
Vit+
Vit-
Positive input threshold voltage, Vi =Vih
Negative input threshold voltage, Vi =Vil
Hysteresis (Vit+ − Vit-) = Vih
—
1.126
—
0.640
—
—
Vhys
0.3
—
Input low leakage current
I
—
—
—
—
—
—
—
±1
±1
4.0
—
µA
µA
IL
(V = GND, no pull-up or pull-down)
IN
Input high leakage current
I
IH
(V = V , no pull-up or pull-down)
IN
DD
Output high current
(V = 0.8VDD, VDD = 1.8V)
I
—
mA
mA
µA
OH
OH
Output low current
I
−4.0
—
OL
(V = 0.4V, VDD = 1.8V)
OL
Output leakage current
I
±5
OZ
(V = V , output is tri-stated)
out
DD
C
i
Input capacitance
—
—
—
—
5
5
pF
pF
C
o
Output capacitance
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an
operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All
timing is measured at 30 pF loading.
Table 6. Tristate Signal Timing
Pin
Parameter
Minimum Maximum Unit
TRISTATE Time from TRISTATE activate until I/O becomes Hi-Z
–
20.8
ns
Table 7. 32k/16M Oscillator Signal Timing
Parameter
Minimum
RMS
Maximum
Unit
EXTAL32k input jitter(peak to peak)
EXTAL32k startup time
–
5
–
20
–
ns
800
ms
12
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 7. 32k/16M Oscillator Signal Timing (Continued)
Parameter
Minimum
RMS
Maximum
Unit
EXTAL16M input jitter(peak to peak)
EXTAL16M startup time
–
TBD
–
TBD
–
–
–
TBD
3.5 Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
•
•
•
32-bit data field
7-bit address field
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 8 on page 13 for the ETM9 timing
parameters used in Figure 2.
2a
1
2b
3a
TRACECLK
3b
TRACECLK
(Half-Rate Clocking Mode)
Output Trace Port
Valid Data
Valid Data
4a
Figure 2. Trace Port Timing Diagram
Table 8. Trace Port Timing Diagram Parameter Table
1.8V 0.10V 3.0V 0.30V
4b
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
Clock high time
Clock low time
Clock rise time
0
1.3
3
85
—
—
4
0
2
100
—
—
3
MHz
ns
2a
2b
3a
2
ns
—
—
ns
MOTOROLA
MC9328MXL Advance Information
13
Specifications
Table 8. Trace Port Timing Diagram Parameter Table (Continued)
1.8V 0.10V 3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3b
4a
Clock fall time
—
3
—
2
3
ns
ns
ns
Output hold time
2.28
3.42
—
—
—
—
4b
Output setup time
3
14
MC9328MXL Advance Information
MOTOROLA
Specifications
3.6 DPLL Timing Specifications
Parameters of the DPLL are given in Table 9. In this table, Tref is a reference clock period after the
pre-divider and Tdck is the output double clock period.
Table 9. DPLL Specifications
Parameter
Test Conditions
Vcc = 1.8V
Minimum
Typical Maximum
Unit
Reference clock freq range
5
—
—
100
30
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
Vcc = 1.8V
5
MHz
Double clock freq range
Pre-divider factor (PD)
80
1
—
—
220
16
MHz
—
—
Includes both integer
and fractional parts
Total multiplication factor (MF)
MF integer part
5
5
0
—
—
—
15
15
—
—
—
—
Should be less than the
denominator
MF numerator
1022
MF denominator
—
—
1
—
—
1023
—
Pre-multiplier lock-in time
—
312.5
µsec
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
Freq lock-in time after
full reset
280
Tref
250
220
300
270
(56 µs)
FOL mode for non-integer MF
(does not include pre-multi lock-in
time)
Freq lock-in time after
partial reset
250
Tref
(50 µs)
Phase lock-in time after
full reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
350
Tref
Tref
300
270
—
400
370
0.01
(70 µs)
Phase lock-in time after
partial reset
FPL mode and integer MF (does
not include pre-multi lock-in time)
320
(64 µs)
0.005
2•Tdck
Freq jitter (p-p)
—
(0.01%)
1.0
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
—
1.7
—
1.5
2.5
4
ns
V
(10%)
Power supply voltage
Power dissipation
—
—
—
FOL mode, integer MF,
mW
fdck = 200 MHz, Vcc = 1.8V
MOTOROLA
MC9328MXL Advance Information
15
Specifications
3.7 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4. Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent
forward biasing.
90% AVDD
1
10% AVDD
POR
Could be adjusted due to 32kHz
Crystal start-up time
2
RESET_POR
Exact 300ms
3
7 cycles @ CLK32
RESET_DRAM
4
14 cycles @ CLK32
HRESET
RESET_OUT
CLK32
HCLK
Figure 3. Timing Relationship with POR
16
MC9328MXL Advance Information
MOTOROLA
Specifications
5
RESET_IN
14 cycles @ CLK32
HRESET
4
RESET_OUT
6
CLK32
HCLK
Figure 4. Timing Relationship with RESET_IN
Table 10. Reset Module Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Ref
No.
Parameter
Unit
Min
Max
Min
Max
1
2
Width of input POWER_ON_RESET
800
—
800
—
ms
ms
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
7
300
7
300
7
300
7
Cycles of
CLK32
3
4
5
6
7K to 32K-cycle stretcher for SDRAM reset
14K to 32K-cycle stretcher for internal system reset
HRESERT and output reset at pin RESET_OUT
Cycles of
CLK32
14
4
14
—
4
14
4
14
—
4
Cycles of
CLK32
Width of external hard-reset RESET_IN
4K to 32K-cycle qualifier
Cycles of
CLK32
4
4
MOTOROLA
MC9328MXL Advance Information
17
Specifications
3.8 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the MC9328MXL,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 11 on page 19 defines the parameters of signals.
(HCLK) Bus Clock
1a
2a
3a
1b
2b
3b
Address
Chip-select
Read (Write)
4a
5a
4b
5b
OE (rising edge)
4c
5c
4d
OE (falling edge)
EB (rising edge)
EB (falling edge)
5d
6b
6a
6a
LBA (negated falling edge)
LBA (negated rising edge)
6c
7a
7b
Burst Clock (rising edge)
7c
7d
Burst Clock (falling edge)
Read Data
8b
9a
9a
8a
9b
Write Data (negated falling)
9c
Write Data (negated rising)
10a
10a
DTACK_B
Figure 5. EIM Bus Timing Diagram
18
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 11. EIM Bus Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Typical Max
Ref No.
Parameter
Unit
Min
Typical Max
Min
1a
1b
2a
2b
3a
3b
4a
4b
4c
4d
5a
5b
5c
5d
6a
6b
6c
7a
7b
7c
7d
8a
8b
9a
9b
9c
10a
Clock fall to address valid
2.48
1.55
2.69
1.55
1.35
1.86
2.32
2.11
2.38
2.17
1.91
1.81
1.97
1.76
2.07
1.97
1.91
1.61
1.61
1.55
1.55
5.54
0
3.31
2.48
3.31
2.48
2.79
2.59
2.62
2.52
2.69
2.59
2.52
2.42
2.59
2.48
2.79
2.79
2.62
2.62
2.62
2.48
2.59
—
9.11
5.69
7.87
6.31
6.52
6.11
6.85
6.55
7.04
6.73
5.54
5.24
5.69
5.38
6.73
6.83
6.45
5.64
5.84
5.59
5.80
—
2.4
1.5
2.6
1.5
1.3
1.8
2.3
2.1
2.3
2.1
1.9
1.8
1.9
1.7
2.0
1.9
1.9
1.6
1.6
1.5
1.5
5.5
0
3.2
2.4
3.2
2.4
2.7
2.5
2.6
2.5
2.6
2.5
2.5
2.4
2.5
2.4
2.7
2.7
2.6
2.6
2.6
2.4
2.5
—
8.8
5.5
7.6
6.1
6.3
5.9
6.8
6.5
6.8
6.5
5.5
5.2
5.5
5.2
6.5
6.6
6.4
5.6
5.8
5.4
5.6
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock fall to address invalid
Clock fall to chip-select valid
Clock fall to chip-select invalid
Clock fall to Read (Write) Valid
Clock fall to Read (Write) Invalid
Clock1 rise to Output Enable Valid
Clock1 rise to Output Enable Invalid
Clock1 fall to Output Enable Valid
Clock1 fall to Output Enable Invalid
Clock1 rise to Enable Bytes Valid
Clock1 rise to Enable Bytes Invalid
Clock1 fall to Enable Bytes Valid
Clock1 fall to Enable Bytes Invalid
Clock1 fall to Load Burst Address Valid
Clock1 fall to Load Burst Address Invalid
Clock1 rise to Load Burst Address Invalid
Clock1 rise to Burst Clock rise
Clock1rise to Burst Clock fall
Clock1 fall to Burst Clock rise
Clock1 fall to Burst Clock fall
Read Data setup time
Read Data hold time
—
—
—
—
Clock1 rise to Write Data Valid
Clock1 fall to Write Data Invalid
Clock1 rise to Write Data Invalid
DTACK setup time
1.81
1.45
1.63
2.52
2.72
2.48
—
6.85
5.69
—
1.8
1.4
1.62
2.5
2.7
2.4
—
6.8
5.5
—
—
—
—
—
1. Clock refers to the system clock signal, HCLK, generated from the System PLL
MOTOROLA
MC9328MXL Advance Information
19
Specifications
3.8.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only CS5 group is
designed to support DTACK signal function when using the external DTACK signal for data
acknowledgement.
3.8.2 DTACK Signal Timing
Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for
this figure are found in Table 12.
HCLK
CS5
3
RW
1
5
OE
4
EXT_DTACK
2
INT_DTACK
Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0
Table 12. Access Cycle Timing Parameters
1.8V 0.10V
3.0V 0.30V
Ref
No.
Characteristic
Unit
Min
Max
Min
Max
1
2
3
4
CS5 asserted to OE asserted
—
0
T
—
T
ns
ns
ns
ns
ns
External DTACK input setup from CS5
asserted
—
—
0
3T
0
—
—
CS5 pulse width
3T
0
External DTACK input hold after CS5 is
negated
1.5T
4.5
1.5T
4
5
OE negated after CS5 is negated
0
0
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
20
MC9328MXL Advance Information
MOTOROLA
Specifications
HCLK
CS5
RW
OE
1
EXT_DTACK (WAIT)
INT_DTACK
Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1
Table 13. Access Cycle Timing Parameters
1.8V 0.10V
Min Max
3.0V 0.30V
Ref
No.
Characteristic
Unit
Min
Max
External DTACK input setup from CS5
asserted
1
0
–
0
—
ns
Note:
1. n is the number of wait states in the current memory access cycle. The max n is 1022.
2. T is the system clock period (system clock is 96 MHz).
3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
MOTOROLA
MC9328MXL Advance Information
21
Specifications
3.8.3 EIM External Bus Timing
The timing diagrams in this section show the timing of accesses to memory or a peripheral.
hclk
hsel_weim_cs[0]
htrans
hwrite
Seq/Nonseq
Read
haddr
hready
V1
weim_hrdata
weim_hready
Last Valid Data
V1
weim_bclk
weim_addr
Last Valid Address
V1
weim_cs
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
V1
Figure 8. WSC = 1, A.HALF/E.HALF
22
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data (V1)
Unknown
weim_hrdata
Last Valid Data
weim_hready
weim_bclk
weim_addr
Last Valid Address
V1
weim_cs[0]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
Last Valid Data
Write Data (V1)
Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
MOTOROLA
MC9328MXL Advance Information
23
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[0]
weim_r/w
weim_lba
weim_oe
Read
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF
24
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[0]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[0]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
1/2 Half Word
2/2 Half Word
Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
25
Specifications
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Read
Address V1 + 2
weim_cs[3]
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF
26
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[3]
htrans
Nonseq
hwrite
Write
V1
haddr
hready
Last Valid
Data
hwdata
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[3]
weim_r/w
weim_lba
weim_oe
Write
weim_eb
weim_data_out]
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
27
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Read
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF
28
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
hwrite
haddr
Write
V1
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr Last Valid Addr
weim_cs[2]
Address V1
Address V1 + 2
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Last Valid Data
1/2 Half Word
2/2 Half Word
Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
29
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Read
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF
30
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
hwrite
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Read
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
1/2 Half Word
2/2 Half Word
Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
31
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
Unknown
weim_hrdata
weim_hready
weim_bclk
weim_addr Last Valid Addr
weim_cs[2]
Address V1
Address V1 + 2
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
1/2 Half Word
2/2 Half Word
Last Valid Data
Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
32
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (V1 Word)
Last Valid Data
Unknown
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb
Write
weim_data_out
1/2 Half Word
2/2 Half Word
Last Valid Data
Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
33
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Last Valid Data
Write Data
Read Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
weim_cs[2]
weim_r/w
weim_lba
Read
Write
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
34
MC9328MXL Advance Information
MOTOROLA
Specifications
Read
Idle
Write
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Write Data
weim_hrdata
weim_hready
Last Valid Data
Read Data
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
Write
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
MOTOROLA
MC9328MXL Advance Information
35
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Write
V1
hwrite
haddr
hready
hwdata
Last Valid
Data
Write Data (Word)
Last Valid Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V1 + 2
weim_cs
weim_r/w
Write
weim_lba
weim_oe
weim_eb
weim_data_out
Write Data (1/2 Half Word)
Write Data (2/2 Half Word)
Last Valid Data
Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
36
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
weim_hrdata
weim_hready
Last Valid Data
Last Valid Data
Write Data
Read Data
weim_bclk
weim_addr Last Valid Addr
weim_cs[4]
Address V1
Address V8
weim_r/w
Read
Write
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
Read Data
weim_data_in
weim_data_out
Last Valid Data
Write Data
Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF
MOTOROLA
MC9328MXL Advance Information
37
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle
Seq
Read
V2
hwrite
haddr
hready
weim_hrdata
weim_hready
Last Valid Data
Read Data (V1)
Read Data (V2)
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V2
CNC
weim_cs[4]
weim_r/w
weim_lba
Read
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
Read Data
(V1)
Read Data
(V2)
weim_data_in
Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
38
MC9328MXL Advance Information
MOTOROLA
Specifications
hclk
hsel_weim_cs[4]
htrans
Nonseq
Read
V1
Idle
Nonseq
Write
V8
hwrite
haddr
hready
hwdata
Last Valid Data
Last Valid Data
Write Data
Read Data
weim_hrdata
weim_hready
weim_bclk
weim_addr
Last Valid Addr
Address V1
Address V8
CNC
weim_cs[4]
weim_r/w
Read
Write
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_data_in
weim_data_out
Read Data
Last Valid Data
Write Data
Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
MOTOROLA
MC9328MXL Advance Information
39
Specifications
hclk
hsel_weim_cs[2]
htrans
Idle
Nonseq
Read
V1
Nonseq
Read
V5
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
weim_addr]
Last Valid Addr
Address V1
Read
Address V5
weim_cs[2]
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V2 Word
V6 Word
V1 Word
V5 Word
Figure 26. WSC = 3, SYNC = 1, A.HALF/E.HALF
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MC9328MXL Advance Information
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Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Read
V1
Idle
Seq
Read
V2
Seq
Read
V3
Seq
Read
V4
hwrite
haddr
hready
weim_hrdata
weim_hready
weim_bclk
Last Valid Data
V1 Word
V2 Word
V3 Word
V4 Word
weim_addr
Last Valid Addr
Address V1
weim_cs[2]
weim_r/w
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 Word
V2 Word
V3 Word
V4 Word
Figure 27. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
MOTOROLA
MC9328MXL Advance Information
41
Specifications
hclk
hsel_weim_cs[2]
htrans
Nonseq
Seq
Idle
hwrite
Read
V1
Read
V2
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
weim_addr
weim_cs[2]
weim_r/w
Last Valid Addr
Address V1
Address V2
Read
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 28. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
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MOTOROLA
Specifications
hclk
hsel_weim_cs[2]
Non
seq
Seq
Read
V2
Idle
htrans
hwrite
Read
V1
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
Last Valid
Addr
Address V1
weim_addr
weim_cs[2]
Read
weim_r/w
weim_lba
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 29. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
MOTOROLA
MC9328MXL Advance Information
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Specifications
hclk
hsel_weim_cs[2]
htrans
Non
seq
Seq
Idle
hwrite
Read
V1
Read
V2
haddr
hready
weim_hrdata
Last Valid Data
V1 Word
V2 Word
weim_hready
weim_bclk
weim_addr
weim_cs[2]
Last Valid
Addr
Address V1
weim_r/w
weim_lba
Read
weim_oe
weim_eb (EBC=0)
weim_eb (EBC=1)
weim_ecb
weim_data_in
V1 1/2
V1 2/2
V2 1/2
V2 2/2
Figure 30. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
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Specifications
3.9 SPI Timing Diagrams
To utilize the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as
a master, two control signals are used for data transfer rate control: the SS signal (output) and the
SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2
Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for
either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1
Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as
well as to increment the data FIFO. Figure 31 through Figure 35 show the timing relationship of the master
SPI using different triggering mechanisms.
.
2
5
3
SS
1
4
SPIRDY
SCLK, MOSI, MISO
Figure 31. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 32. Master SPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 33. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 34. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
MOTOROLA
MC9328MXL Advance Information
45
Specifications
SS (input)
6
7
SCLK, MOSI, MISO
Figure 35. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 14. Timing Parameter Table for Figure 31 through Figure 35
1.8V 0.10V
3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
2T 1
2T1
1
2
SPI_RDY to SS output low
—
—
—
—
ns
ns
SS output low to first SCLK
edge
3 • Tsclk 2
2 • Tsclk
0
3 • Tsclk2
2 • Tsclk
0
Last SCLK edge to SS output
high
3
4
5
—
—
—
—
—
—
ns
ns
ns
SS output high to SPI_RDY
low
Tsclk +
WAIT 3
Tsclk +
WAIT3
SS output pulse width
SS input low to first SCLK
edge
6
7
T
T
—
—
T
T
—
—
ns
ns
SS input pulse width
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.
3.10 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
LD[15:0]
1
Figure 36. SCLK to LD Timing Diagram
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MC9328MXL Advance Information
MOTOROLA
Specifications
Table 15. LCDC SCLK Timing Parameter Table
1.8V 0.10V 3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
SCLK to LD valid
—
2
—
2
ns
Non-display region
T3
Display region
T1
T4
VSYN
T2
HSYN
OE
Line Y
Line 1
Line Y
LD[15:0]
T6
T7
T5
XMAX
HSYN
SCLK
OE
T8
(1,1)
(1,2)
LD[15:0]
VSYN
(1,X)
T9
T10
Figure 37. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Table 16. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing
Symbol
Description
Minimum
Corresponding Register Value
Unit
T5+T6
+T7+T9
T1
End of OE to beginning of VSYN
(VWAIT1·T2)+T5+T6+T7+T9
Ts
T2
T3
T4
T5
T6
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
VWIDTH·(T2)
Ts
Ts
Ts
Ts
Ts
VSYN pulse width
T2
2
End of VSYN to beginning of OE
HSYN pulse width
VWAIT2·(T2)
1
HWIDTH+1
End of HSYN to beginning to T9
1
HWAIT2+1
MOTOROLA
MC9328MXL Advance Information
47
Specifications
Symbol
Table 16. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Description
Minimum
Corresponding Register Value
Unit
T7
T8
End of OE to beginning of HSYN
SCLK to valid LD data
1
HWAIT1+1
3
Ts
ns
-3
End of HSYN idle2 to VSYN edge
(for non-display region)
T9
T9
2
1
1
2
2
1
1
2
Ts
Ts
Ts
Ts
End of HSYN idle2 to VSYN edge
(for Display region)
VSYN to OE active (Sharp = 0)
when VWAIT2 = 0
T10
T10
VSYN to OE active (Sharp = 1)
when VWAIT2 = 0
Note:
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 37, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 37, SCLK
is always active.
•
•
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
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Specifications
3.11 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
3a
1
2
4b
3b
Bus Clock
4a
5b
5a
Valid Data
CMD_DAT Input
Valid Data
7
CMD_DAT Output
Valid Data
Valid Data
6a
6b
Figure 38. Chip-Select Read Cycle Timing Diagram
Table 17. SDHC Bus Timing Parameter Table
1.8V 0.10V
3.0 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
CLK frequency at Data transfer
Mode (PP)1—10/30 cards
1
2
0
0
25/5
0
0
25/5
MHz
kHz
CLK frequency at Identification
Mode2
400
400
3a
3b
Clock high time1—10/30 cards
Clock low time1—10/30 cards
6/33
—
—
10/50
10/50
—
—
ns
ns
15/75
10/50
4a
4b
Clock fall time1—10/30 cards
Clock rise time1—10/30 cards
—
—
—
—
10/50
10/50
ns
ns
(5.00)3
14/67
(6.67)3
5a
5b
6a
6b
7
Input hold time3—10/30 cards
Input setup time3—10/30 cards
Output hold time3—10/30 cards
Output setup time3—10/30 cards
Output delay time3
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
0
—
—
—
—
16
5/5
5/5
5/5
5/5
0
—
—
—
—
14
ns
ns
ns
ns
ns
1. CL ≤ 100 pF / 250 pF (10/30 cards)
2. CL ≤ 250 pF (21 cards)
3. CL ≤ 25 pF (1 card)
MOTOROLA
MC9328MXL Advance Information
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Specifications
3.11.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 39. The symbols for Figure 39 through Figure 43
are defined in Table 18.
Table 18. State Signal Parameters for Figure 39 through Figure 43
Card Active
Definition
Host Active
Definition
Symbol
Symbol
Z
High impedance state
Data bits
S
Start bit (0)
Transmitter bit
(Host = 1, Card = 0)
D
T
*
Repetition
P
E
One-cycle pull-up (1)
End bit (1)
CRC
Cyclic redundancy check bits (7 bits)
N
ID cycles
Host Command
CID/OCR
Content
CMD
CMD
Content
CRC
******
ST
E Z
Z S T
Z Z Z
Identification Timing
N
CR cycles
Host Command
CID/OCR
Content
******
Content
Z Z Z
CRC
ST
E Z
Z S T
SET_RCA Timing
Figure 39. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 40, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC
.
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MC9328MXL Advance Information
MOTOROLA
Specifications
NCR cycles
Host Command
Response
Content
CRC
E Z Z Z
CMD
Content
CRC
******
ST
E Z Z P
P S T
Command response timing (data transfer mode)
NRC cycles
Response
Content
Host Command
Content
CMD
******
CRC
CRC
E Z Z Z
ST
E Z
Z S T
Timing response end to next CMD start (data transfer mode)
NCC cycles
Host Command
Host Command
Content
CRC
E Z Z Z
CMD
Content
CRC
E Z
******
ST
Z S T
Timing of command sequences (all modes)
Figure 40. Timing Diagrams at Data Transfer Mode
Figure 41 on page 52 shows basic read operation timing. In a read operation, the sequence starts with a
single block read command (which specifies the start address in the argument field). The response is sent
on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC
,
beginning from the last bit of the read command. If the system is in multiple block read mode, the card
sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command.
The data stops two clock cycles after the end bit of the stop command.
MOTOROLA
MC9328MXL Advance Information
51
Specifications
NCR cycles
Host Command
Response
Content
CRC
E Z
CMD
DAT
Content
CRC
******
******
ST
E Z Z P
P S T
Z****Z
*****
Z Z P
P S DDDD
Read Data
Timing of single block read
NAC cycles
NCR cycles
Host Command
Response
Content
CRC
E Z
CMD
ST
Content
CRC
******
E Z Z P
Z Z P
P S T
DAT
Z****Z
******
*****
Read Data
*****
*****
Read Data
P S DDDD
P
P S DDDD
NAC cycles
NAC cycles
Timing of multiple block read
NCR cycles
Host Command
Response
CMD
Content
CRC
******
Content
CRC
E Z
ST
E Z Z P
P S T
NST
DAT
*****
*****
DDDD
DDDD E Z Z Z
Timing of stop command
(CMD12, data transfer mode)
Valid Read Data
Figure 41. Timing Diagrams at Data Read
Figure 42 shows the basic write operation timing. As with the read operation, after the card response, the
data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check
for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If
there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC
status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple
block mode, with the flow terminated by a stop transmission command.
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MC9328MXL Advance Information
MOTOROLA
Specifications
Figure 42. Timing Diagrams at Data Write
MOTOROLA
MC9328MXL Advance Information
53
Specifications
The stop transmission command may occur when the card is in different states. Figure 43 shows the
different scenarios on the bus.
Figure 43. Stop Transmission During Different Scenarios
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MC9328MXL Advance Information
MOTOROLA
Specifications
Table 19. Timing Values for Figure 39 through Figure 43
Symbol Minimum Maximum Unit
Parameter
Parameter
MMC/SD bus clock, CLK
(All values are referred to
minimum (VIH) and
maximum (VIL)
MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum
(VIL)
Clock
cycles
Command response cycle
NCR
NID
2
5
2
8
8
2
2
64
Command response cycle
Identification response
cycle
Clock
cycles
Identification response
cycle
5
Clock
cycles
Access time delay cycle
Command read cycle
NAC
NRC
NCC
NWR
NST
TAAC + NSAC
Access time delay cycle
Command read cycle
Clock
cycles
—
—
—
2
Command-command
cycle
Clock
cycles
Command-command cycle
Command write cycle
Stop transmission cycle
Clock
cycles
Command write cycle
Stop transmission cycle
Clock
cycles
TAAC: Data read access
time -1 defined in CSD
register bit[119:112]
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register
bit[111:104]
NSAC: Data read access
time -2 in CLK cycles
(NSAC·100) defined in
CSD register bit[111:104]
3.11.2 SDIO-IRQ and ReadWait Service Handling
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt
Period" during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
MOTOROLA
MC9328MXL Advance Information
55
Specifications
CMD
ST
Content
CRC
Response
******
S
E Z Z P S
E Z Z Z
Z Z Z
DAT[1]
Interrupt Period
IRQ
IRQ
Block Data
Block Data
S
E
E
For 4-bit
L H
DAT[1]
Interrupt Period
For 1-bit
Figure 44. SDIO IRQ Timing Diagram
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the
clock running, and allows the user to submit commands as normal. After all commands are submitted, the
user can switch back to the data transfer operation and all counter and status values are resumed as access
continues.
CMD
******
CMD52 CRC
******
P S T
E Z Z Z
DAT[1]
Block Data
Block Data
S
S
E Z Z L H
S
E
E
For 4-bit
DAT[2]
Block Data
Block Data
E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S
For 4-bit
Figure 45. SDIO ReadWait Timing Diagram
3.12 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
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MC9328MXL Advance Information
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Specifications
2
3
5
1
4
MS_SCLKI
6
8
7
MS_SCLKO
MS_BS
9
10
11
12
11
12
MS_SDIO(output)
14
13
MS_SDIO (input)
(RED bit = 0)
15
16
MS_SDIO (input)
(RED bit = 1)
Figure 46. MSHC Signal Timing Diagram
Table 20. MSHC Signal Timing Parameter Table
Parameter
3.0 0.3V
Minimum Maximum
Ref
No.
Unit
1
2
3
4
5
6
7
8
9
MS_SCLKI frequency
—
20
20
—
—
—
20
15
—
25
—
—
3
MHz
ns
MS_SCLKI high pulse width
MS_SCLKI low pulse width
MS_SCLKI rise time
ns
ns
MS_SCLKI fall time
3
ns
MS_SCLKO frequency1
MS_SCLKO high pulse width1
MS_SCLKO low pulse width1
MS_SCLKO rise time1
25
—
—
5
MHz
ns
ns
ns
MOTOROLA
MC9328MXL Advance Information
57
Specifications
Table 20. MSHC Signal Timing Parameter Table (Continued)
3.0 0.3V
Minimum Maximum
Ref
No.
Parameter
Unit
10
11
12
13
14
15
16
MS_SCLKO fall time1
MS_BS delay time1
—
—
—
18
0
5
3
ns
ns
ns
ns
ns
ns
ns
MS_SDIO output delay time1,2
3
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4
—
—
—
—
23
0
1. Loading capacitor condition is less than or equal to 30pF.
2. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the
MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick
SDIO pin when the pin direction changes.
3. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
4. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
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MOTOROLA
Specifications
3.13 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 47 and the parameters are listed in Table 21.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 47. PWM Output Timing Diagram
Table 21. PWM Output Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency1
Clock high time1
Clock low time1
0
87
—
0
5/10
5/10
—
100
—
MHz
ns
2a
2b
3a
3b
4a
4b
3.3
7.5
—
—
—
ns
Clock fall time1
5
5/10
5/10
—
ns
Clock rise time1
—
6.67
—
—
ns
Output delay time1
Output setup time1
5.7
5.7
5
ns
—
5
—
ns
1. CL of PWMO = 30 pF
3.14 SDRAM Controller
A write to an address within the memory region initiates the program sequence. The first command issued
to the SyncFlash is Load Command Register. The value in A [7:0] determines which operation the
command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank
and other address lines are driven with the address to be programmed. The next command is Active which
registers the row address and confirms the bank address. The third command supplies the column address,
re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes,
therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash
is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register
operation. The bank and other address lines are driven to the selected address. The second command is
MOTOROLA
MC9328MXL Advance Information
59
Specifications
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
1
SDCLK
2
3S
3
CS
RAS
CAS
3H
3H
3S
3S
3H
3
S
3H
4H
WE
ADDR
DQ
4S
ROW/BA
COL/BA
8
5
6
Data
7
3S
DQM
3H
Note: CKE is high during the read/write cycle.
Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 22. SDRAM Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Ref
Parameter
Unit
No.
Minimum Maximum Minimum Maximum
1
2
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
2.67
6
—
—
—
—
4
4
—
—
—
—
ns
ns
ns
ns
3
11.4
3.42
10
3
3S
CS, RAS, CAS, WE, DQM setup time
60
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 22. SDRAM Timing Parameter Table (Continued)
3.0V 0.30V
Minimum Maximum Minimum Maximum
1.8V 0.10V
Ref
No.
Parameter
Unit
3H
4S
4H
5
CS, RAS, CAS, WE, DQM hold time
Address setup time
2.28
3.42
2.28
—
—
—
2
3
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
—
2
SDRAM access time (CL = 3)
SDRAM access time (CL = 2)
SDRAM access time (CL = 1)
Data out hold time
6.84
6.84
22
—
—
—
2.5
—
—
—
5
—
6
5
—
22
—
6
6
2.85
—
—
7
Data out high-impedance time (CL = 3)
Data out high-impedance time (CL = 2)
Data out high-impedance time (CL = 1)
6.84
6.84
22
7
—
6
7
—
22
1
1
8
Active to read/write command period (RC = 1)
—
—
ns
tRCD
tRCD
1. tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MXL reference manual.
MOTOROLA
MC9328MXL Advance Information
61
Specifications
SDCLK
1
3
2
CS
RAS
CAS
6
WE
ADDR
DQ
4
5
7
/ BA
ROW/BA
COL/BA
DATA
8
9
DQM
Figure 49. SDRAM/SyncFlash Write Cycle Timing Diagram
Table 23. SDRAM Write Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Address setup time
2.67
6
—
—
—
—
—
4
4
—
—
—
—
—
ns
ns
ns
ns
ns
11.4
3.42
2.28
10
3
Address hold time
2
2
2
6
7
Precharge cycle period1
—
—
—
—
ns
ns
tRP
tRP
2
2
Active to read/write command delay
tRCD
tRCD
62
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 23. SDRAM Write Timing Parameter Table (Continued)
1.8V 0.10V 3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
8
9
Data setup time
Data hold time
4.0
—
—
2
2
—
ns
ns
2.28
—
1. Precharge cycle timing is included in the write timing diagram.
2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference
manual.
SDCLK
1
3
2
CS
RAS
CAS
6
7
7
WE
ADDR
DQ
4
5
BA
ROW/BA
DQM
Figure 50. SDRAM Refresh Timing Diagram
Table 24. SDRAM Refresh Timing Parameter Table
3.0V 0.30V
1.8V 0.10V
Ref
Parameter
Unit
No.
Minimum
Maximum
Minimum
Maximum
1
2
SDRAM clock high-level width
SDRAM clock low-level width
2.67
6
—
—
4
4
—
—
ns
ns
MOTOROLA
MC9328MXL Advance Information
63
Specifications
Table 24. SDRAM Refresh Timing Parameter Table (Continued)
1.8V 0.10V 3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
3
4
5
SDRAM clock cycle time
Address setup time
Address hold time
11.4
3.42
2.28
—
—
—
10
3
—
—
—
ns
ns
ns
2
1
1
6
7
Precharge cycle period
—
—
—
—
ns
ns
tRP
tRP
1
1
Auto precharge command period
tRC
tRC
1. tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference
manual.
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
BA
DQM
CKE
Figure 51. SDRAM Self-Refresh Cycle Timing Diagram
64
MC9328MXL Advance Information
MOTOROLA
Specifications
3.15 USB Device Port
Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous
transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is
identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section
covers the transfer modes and how they work from the ground up.
Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same
packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved
in the form of packets, however, because isochronous pipes are given a fixed portion of the USB
bandwidth at all times, there is no end-of-transfer.
USBD_AFE
(Output)
t VMO_ROE
4
t ROE_VPO
1
USBD_ROE
(Output)
6
3
tPERIOD
tVPO_ROE
USBD_VPO
(Output)
USBD_VMO
(Output)
tROE_VMO
tFEOPT
USBD_SUSPND
(Output)
2
5
USBD_RCV
(Input)
USBD_VP
(Input)
USBD_VM
(Input)
Figure 52. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX)
Table 25. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
1.8V 0.10V
3.0V 0.30V
Ref No.
Parameter
Unit
Minimum Maximum Minimum Maximum
tROE_VPO; USBD_ROE active to
USBD_VPO low
1
2
3
83.14
81.55
83.54
83.47
81.98
83.80
83.14
81.55
83.54
83.47
81.98
83.80
ns
ns
ns
tROE_VMO; USBD_ROE active to
USBD_VMO high
tVPO_ROE; USBD_VPO high to
USBD_ROE deactivated
MOTOROLA
MC9328MXL Advance Information
65
Specifications
Table 25. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
3.0V 0.30V
Minimum Maximum Minimum Maximum
1.8V 0.10V
Ref No.
Parameter
Unit
t
VMO_ROE; USBD_VMO low to
4
248.90
249.13
248.90
249.13
ns
USBD_ROE deactivated (includes SE0)
5
6
tFEOPT; SE0 interval of EOP
160.00
11.97
175.00
12.03
160.00
11.97
175.00
12.03
ns
t
PERIOD; Data transfer rate
Mb/s
USBD_AFE
(Output)
USBD_ROE
(Output)
USBD_VPO
(Output)
USBD_VMO
(Output)
USBD_SUSPND
(Output)
USBD_RCV
(Input)
1
tFEOPR
USBD_VP
(Input)
USBD_VM
(Input)
Figure 53. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX)
Table 26. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX)
1.8V 0.10V 3.0V 0.30V
Ref No.
Parameter
Unit
Minimum
82
Maximum
Minimum
82
Maximum
1
tFEOPR; Receiver SE0 interval of EOP
—
—
ns
66
MC9328MXL Advance Information
MOTOROLA
Specifications
3.16 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
5
3
4
SCL
2
6
1
2
Figure 54. Definition of Bus Timing for I C
2
Table 27. I C Bus Timing Parameter Table
1.8V 0.10V
3.0V 0.30V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
1
2
3
4
5
6
Hold time (repeated) START condition
Data hold time
182
0
—
171
—
160
0
—
150
—
ns
ns
ns
ns
ns
ns
Data setup time
11.4
80
10
HIGH period of the SCL clock
LOW period of the SCL clock
Setup time for STOP condition
—
120
320
160
—
480
182.4
—
—
—
—
3.17 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In
gated clock mode, the clock functions only during transmission. The internal and external clock timing
diagrams are shown in Figure 56 through Figure 58 on page 69.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
MOTOROLA
MC9328MXL Advance Information
67
Specifications
1
STCK Output
4
2
STFS (bl) Output
STFS (wl) Output
6
8
12
10
11
32
STXD Output
SRXD Input
31
Note: SRXD input in synchronous mode only.
Figure 55. SSI Transmitter Internal Clock Timing Diagram
1
SRCK Output
3
5
SRFS (bl) Output
SRFS (wl) Output
7
9
13
14
SRXD Input
Figure 56. SSI Receiver Internal Clock Timing Diagram
68
MC9328MXL Advance Information
MOTOROLA
Specifications
15
16
17
STCK Input
18
20
STFS (bl) Input
STFS (wl) Input
24
22
28
27
34
26
STXD Output
SRXD Input
33
Note: SRXD Input in Synchronous mode only
Figure 57. SSI Transmitter External Clock Timing Diagram
15
16
17
SRCK Input
19
21
SRFS (bl) Input
SRFS (wl) Input
25
23
30
29
SRXD Input
Figure 58. SSI Receiver External Clock Timing Diagram
Table 28. SSI (Port C Primary Function) Timing Parameter Table
1.8V 0.10V
Minimum Maximum
Internal Clock Operation1 (Port C Primary Function2)
3.0V 0.30V
Ref No.
Parameter
Unit
Minimum Maximum
1
2
3
STCK/SRCK clock period1
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
95
1.5
-1.2
—
4.5
-1.7
83.3
1.3
—
ns
ns
ns
3.9
-1.1
-1.5
MOTOROLA
MC9328MXL Advance Information
69
Specifications
Table 28. SSI (Port C Primary Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.0V 0.30V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
4
5
6
7
8
9
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
2.5
0.1
4.3
-0.8
4.45
-1.5
4.33
-0.8
2.2
0.1
1.3
-1.1
2.2
0.1
3.8
-0.8
3.9
ns
ns
ns
ns
ns
ns
1.48
-1.1
2.51
0.1
-1.5
3.8
-0.8
STCK high to STXD valid from high
impedance
10
14.25
15.73
12.5
13.8
ns
11a
11b
12
STCK high to STXD high
0.91
0.57
12.88
21.1
0
3.08
3.19
13.57
—
0.8
0.5
11.3
18.5
0
2.7
2.8
11.9
—
ns
ns
ns
ns
ns
STCK high to STXD low
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
13
14
—
—
External Clock Operation (Port C Primary Function2)
15
16
17
18
19
20
21
22
23
24
25
STCK/SRCK clock period1
92.8
27.1
61.1
—
—
81.4
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK/SRCK clock high period
STCK/SRCK clock low period
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
—
40.7
—
—
40.7
0
—
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
—
0
—
0
—
0
—
0
—
0
—
0
—
0
STCK high to STXD valid from high
impedance
26
18.01
28.16
15.8
24.7
ns
27a
27b
STCK high to STXD high
STCK high to STXD low
8.98
9.12
18.13
18.24
7.0
8.0
15.9
16.0
ns
ns
70
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 28. SSI (Port C Primary Function) Timing Parameter Table (Continued)
3.0V 0.30V
1.8V 0.10V
Ref No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
28
29
30
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hole time after SRCK low
18.47
1.14
0
28.5
—
16.2
1.0
0
25.0
—
ns
ns
ns
—
—
Synchronous Internal Clock Operation (Port C Primary Function2)
31
32
SRXD setup before STCK falling
SRXD hold after STCK falling
15.4
0
—
—
13.5
0
—
—
ns
ns
Synchronous External Clock Operation (Port C Primary Function2)
33
34
SRXD setup before STCK falling
SRXD hold after STCK falling
1.14
0
—
—
1.0
0
—
—
ns
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as input, the SSI module selects the input based on status of the FMCR register bits in the
Clock controller module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
Table 29. SSI (Port B Alternate Function) Timing Parameter Table
1.8V 0.10V
Minimum Maximum
Internal Clock Operation1 (Port B Alternate Function2)
3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum Maximum
1
2
3
4
5
6
7
8
STCK/SRCK clock period1
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
95
—
83.3
1.5
—
ns
ns
ns
ns
ns
ns
ns
ns
1.7
4.8
4.2
1.0
4.6
2.0
4.2
1.0
4.6
-0.1
3.08
1.25
1.71
-0.1
3.08
1.0
-0.1
2.7
5.24
2.28
4.79
1.0
1.1
1.5
-0.1
2.7
5.24
MOTOROLA
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71
Specifications
Table 29. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
1.8V 0.10V 3.0V 0.30V
Ref
No.
Parameter
Unit
Minimum
Maximum
Minimum
Maximum
9
SRCK high to SRFS (wl) low3
1.25
2.28
1.1
2.0
ns
ns
STCK high to STXD valid from high
impedance
10
14.93
16.19
13.1
14.2
11a STCK high to STXD high
11b STCK high to STXD low
1.25
2.51
12.43
20
3.42
3.99
14.59
—
1.1
2.2
10.9
17.5
0
3.0
3.5
12.8
—
ns
ns
ns
ns
ns
12
13
14
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
0
—
—
External Clock Operation (Port B Alternate Function2)
15
16
17
18
19
20
21
22
23
24
25
STCK/SRCK clock period1
92.8
27.1
61.1
—
—
81.4
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STCK/SRCK clock high period
STCK/SRCK clock low period
STCK high to STFS (bl) high3
SRCK high to SRFS (bl) high3
STCK high to STFS (bl) low3
SRCK high to SRFS (bl) low3
STCK high to STFS (wl) high3
SRCK high to SRFS (wl) high3
STCK high to STFS (wl) low3
SRCK high to SRFS (wl) low3
—
40.7
—
—
40.7
0
—
92.8
92.8
92.8
92.8
92.8
92.8
92.8
92.8
81.4
81.4
81.4
81.4
81.4
81.4
81.4
81.4
—
0
—
0
—
0
—
0
—
0
—
0
—
0
STCK high to STXD valid from high
impedance
26
18.9
29.07
16.6
25.5
ns
27a STCK high to STXD high
27b STCK high to STXD low
9.23
10.60
17.90
1.14
0
20.75
21.32
29.75
—
8.1
9.3
15.7
1.0
0
18.2
18.7
26.1
—
ns
ns
ns
ns
ns
28
29
30
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hold time after SRCK low
—
—
Synchronous Internal Clock Operation (Port B Alternate Function2)
72
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 29. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
3.0V 0.30V
Minimum Maximum
1.8V 0.10V
Ref
No.
Parameter
Unit
Minimum
Maximum
31
32
SRXD setup before STCK falling
SRXD hold after STCK falling
18.81
0
—
—
16.5
0
—
ns
ns
—
Synchronous External Clock Operation (Port B Alternate Function2)
33
34
SRXD setup before STCK falling
SRXD hold after STCK falling
1.14
0
—
—
1.0
0
—
—
ns
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a
non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
2. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad
261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they
can be viewed both at Port C primary function and Port B alternate function. When SSI signals are
configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller
module (CRM). By default, the input are selected from Port C primary function.
3. bl = bit length; wl = word length.
MOTOROLA
MC9328MXL Advance Information
73
Specifications
3.18 CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing, a
control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive
FIFO, and a 16 × 32 statistic data FIFO.
3.18.1 Gated Clock Mode
Figure 59 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 60 on page 74 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 30 on page 75.
1
VSYNC
7
HSYNC
5
6
2
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 59. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
PIXCLK
6
5
2
Valid Data
Valid Data
Valid Data
DATA[7:0]
3
4
Figure 60. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
74
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 30. Gated Clock Mode Timing Parameters
Ref No.
Parameter
Min
Max
Unit
1
2
3
4
5
6
7
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
180
-
-
ns
ns
1
1
-
ns
csi_d hold time
1
-
ns
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
-
ns
-
ns
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MOTOROLA
MC9328MXL Advance Information
75
Specifications
3.18.2 Non-Gated Clock Mode
Figure 61 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 62 on page 76 shows the timing
diagram when the CMOS sensor output data is configured for positive edge and the CSI is programmed to
received data in negative edge. The parameters for the timing diagrams are listed in Table 31 on page 76.
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7:0]
2
3
Figure 61. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
6
4
5
PIXCLK
Valid Data
Valid Data
Valid Data
DATA[7..0]
2
3
Figure 62. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 31. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Min
Max
Unit
1
csi_vsync to csi_pixclk
180
-
ns
76
MC9328MXL Advance Information
MOTOROLA
Specifications
Table 31. Non-Gated Clock Mode Parameters (Continued)
Ref No.
Parameter
csi_d setup time
Min
Max
Unit
2
3
4
5
6
1
1
-
-
ns
ns
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
10.42
10.42
0
-
ns
-
ns
48
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MOTOROLA
MC9328MXL Advance Information
77
4 Pin-Out and Package Information
Table 32 illustrates the package pin assignments for the 256-pin MAPBGA package.
Table 32. MC9328MXL 256 MAPBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
NVSS1
DAT3
CLK
NVSS4
USBD_
AFE
NVDD4
NVSS3
UART1_
RTS
UART1_
RXD
NVDD3
N.C.
N.C.
QVDD4
N.C.
N.C.
N.C.
A24
A23
DAT1
D31
CMD
SSI1_RXDAT
SSI1_RXCLK
USBD_
ROE
USBD_VP
SSI0_
RXCLK
SSI0_
TXCLK
SPI1_
SCLK
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
QVSS4
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DAT0
USBD_
RCV
UART2_
CTS
UART2_
RXD
SSI0_
RXFS
UART1_
TXD
D
E
F
A22
A20
A18
A15
D30
A21
D27
A17
D29
D28
D25
D24
SSI1_RXFS
D26
USBD_
SUSPND
USBD_
VPO
USBD_
VMO
SSI0_
RXDAT
SPI1_
SPI_RDY
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
CLS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DAT2
A16
USBD_VM
UART2_
RTS
SSI0_
TXDAT
SPI1_SS
A19
SSI1_
TXFS
UART2_
TXD
SSI0_
TXFS
SPI1_
MISO
REV
N.C.
N.C.
LSCLK
VSYNC
SPL_SPR
LD1
G
D23
D21
SSI1_
TXDAT
SSI1_
TXCLK
UART1_
CTS
SPI1_
MOSI
CONTRAST
OE_ACD
HSYNC
H
J
A13
A12
A10
A8
D22
A11
D16
A7
A14
D18
A9
D20
D19
D17
D15
A6
NVDD1
NVDD1
NVDD1
D14
NVDD1
NVDD1
NVSS1
NVDD1
NVSS1
NVSS1
NVSS1
NVSS1
NVSS1
RW
QVSS1
NVDD1
NVDD1
CAS
QVDD1
NVSS2
NVDD2
TCK
PS
NVSS2
NVDD2
TIN
LD0
LD6
LD2
LD7
LD4
LD8
LD5
LD11
LD9
LD3
QVDD3
TOUT2
CSI_D2
CSI_D6
QVSS3
LD15
K
L
LD10
PWMO
LD12
LD13
CSI_D0
LD14
D13
D11
CSI_MCLK
CSI_D4
CSI_D1
CSI_VSYNC
CSI_D3
CSI_D5
M
A5
D12
SDCLK
MA10
RAS
RESET_IN
BIG_ENDI
AN
CSI_
HSYNC
N
A4
EB1
D10
D7
A0
D4
PA17
D1
DQM1
RESET_SF
RESET_
OUT
BOOT2
CSI_
PIXCLK
CSI_D7
TMS
TDI
P
R
T
A3
EB2
D9
EB3
A2
EB0
A1
CS3
CS4
CS5
D6
D8
ECB
D5
D2
D3
DQM3
D0
SDCKE1
DQM0
BOOT3
SDCKE0
CLKO
BOOT0
POR
TRST
BOOT1
I2C_CLK
TDO
I2C_DATA
QVDD2
XTAL32K
EXTAL32K
QVSS2
LBA
CS0
BCLK
MA11
NVSS1
OE
CS2
CS1
DQM2
SDWE
AVDD1
TRISTATE
EXTAL16M
XTAL16M
Table 33 illustrates the package pin assignments for the 225-pin PBGA package.
Table 33. MC9328MXL 225 PBGA Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SSI1_
RXCLK
SSI1_
TXCLK
USBD_
ROE
USBD_
SUSPND
SSI0_
RXFS
SSI0_
TXCLK
SPI1_
SCLK
A
B
C
D
E
CMD
USBD_VM
SPI1_RDY
REV
PS
LD2
LD4
LD5
SSI1_
RXDAT
USBD_
AFE
USBD_
VMO
SSI0_
RXDAT
UART1_
TXD
SPL_
SPR
DAT3
D31
A23
CLK
DAT0
A24
USBD_RCV
DAT2
SPI1_SS
LSCLK
LD0
LD8
LD3
LD9
LD11
TIN
LD6
LD7
NVDD2
LD13
SSI1_
RXFS
SSI1_
TXFS
USBD_
VPO
UART2_
RXD
SSI0_
TXFS
UART1_
RTS
CONTRAST VSYNC
LD12
SSI1_
TXDAT
UART2_
TXD
SPI1_
HSYNC
MOSI
DAT1
D30
NVDD1
NVDD1
USBD_VP
QVSS
QVDD4
NVDD3
LD1
TOUT2
CSI_D0
UART2_
RTS
UART1_
RXD
UART1_
CTS
SPI1_
MISO
OE_
ACD
CSI_
MCLK
A21
A22
D29
LD10
LD14
UART2_
CTS
SSI0_
RXCLK
SSI0_
TXDAT
F
G
H
A20
A17
A15
A19
A18
A16
D28
D26
D23
D27
D25
D24
NVDD1
NVDD1
D22
NVDD1
NVSS
NVSS
CLS
QVDD3
LD15
CSI_D2
CSI_HSYNC
I2C_DATA
CSI_D4
CSI_D5
TMS
NVDD4
NVSS
NVSS
NVSS
NVSS
NVSS
QVSS
NVDD2
PWMO CSI_D3
CSI_D7
CSI_
CSI_D1
CSI_
PIXCLK
VSYNC
I2C_
TCK
CLK
J
A14
A13
A12
A11
D21
D20
D19
NVDD1
NVDD1
NVSS
NVSS
NVSS
QVSS
QVDD1
NVDD1
NVSS
NVSS
CSI_D6
D1
TDO_B
BOOT1
BOOT0
BIG_
ENDIAN
RESET_
OUT_B
K
CS2_B
BOOT2
TDI
XTAL32K
L
M
N
P
R
A10
D16
A8
A9
D15
A7
D17
D13
D18
D10
NVDD1
EB3_B
D9
NVDD1
NVDD1
D8
CS5_B
CS4_B
CS3_B
D6
D2
ECB_B
BCLK
PA17
MA10
D4
NVSS
RW_B
D0
NVSS
NVSS
DQM2
DQM1
D3
POR
BOOT3
DQM0
RAS_B
DQM3
QVSS
QVDD2
SDCKE0
SDCKE1
CAS_B
XTAL16M
RESET_IN_B
TRISTATE
CLKO
EXTAL32K
EXTAL16M
TRST_B
CS1_B
CS0_B
D5
D12
EB0_B
A3
D14
A6
A5
A4
A2
A1
MA11
LBA_B
RESETSF_B
AVDD1
D11
EB1_B
EB2_B
OE_B
D7
A0
SDCLK
SDWE_B
Pin-Out and Package Information
4.1 MAPBGA 256 Package Dimensions
Figure 63 illustrates the 256 MAPBGA 14 mm × 14 mm × 1.30 mm package, which has 0.8 mm spacing
between the pads. The device designator for the MAPBGA package is VH.
Case Outline 1367
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
Figure 63. MC9328MXL 256 MAPBGA Mechanical Drawing
80
MC9328MXL Advance Information
MOTOROLA
Pin-Out and Package Information
4.2 PBGA 225 Package Dimensions
Figure 64 illustrates the 225 PBGA 13 mm × 13 mm × 0.8 mm package.
Case Outline 1304B
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
Figure 64. MC9328MXL 225 PBGA Mechanical Drawing
MOTOROLA
MC9328MXL Advance Information
81
Information in this document is provided solely to enable system and software implementers to
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MC9328MXL/D
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