MC9S12E [MOTOROLA]
MC9S12E-Family Device User Guide V01.04; MC9S12E ，家庭设备用户手册V01.04
| 型号： | MC9S12E |
| 厂家： | 
MOTOROLA |
| 描述： | MC9S12E-Family Device User Guide V01.04 |
| 文件： | 总156页 (文件大小：2949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DOCUMENT NUMBER
9S12E128DGV1/D
Freescale Semiconductor, Inc.
MC9S12E-Family
Device User Guide
V01.04
Original Release Date: 4 APR 2003
Revised: 04 NOV 2003
Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and
Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
©Motorola, Inc., 2003
1
For More Information On This Product,
Go to: www.freescale.com
DOCUMENT NUMBER
9S12E128DGV1/D
Freescale Semiconductor, Inc.
Revision History
Version Revision
Author
Description of Changes
Number
01.00
Date
04.APR.03
24.JUN.03
9.OCT.03
Original Version.
01.01
01.02
Minor typo corrections.
MC9S12E32 added.
Added Colpitts and Pierce connections to 2.3.8.
Updated input capacitance.
Updated Table A-8.
Changed pin name ROMONE to ROMCTL.
Added S12 LRAE to Flash section.
01.03
01.04
31.OCT.03
04.NOV.03
Added EXTAL VIH and VIL min/max values and hysteresis value to
Oscillator Characteristics.
New wording on NVM Reliability.
Updated PCB layouts.
Changed PP6 to PK7 on Table 4-1.
Updated DAC Supply min voltage and Operating frequency.
Added Non-multiplexed Address and Chip Select external bus
timing.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components
in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part. Motorola and
Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
©Motorola, Inc., 2003
2
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Section 2 Signal Description
2.1
2.2
2.3
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . 80
PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 80
PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 80
PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.11 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output. . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.12 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB) . . . . . . . 83
2.3.13 PE2 / R/W — Port E I/O Pin 2 / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.14 PE1 / IRQ — Port E input Pin 1 / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . . 84
2.3.15 PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin . . . . . . . . . . . . . 84
2.3.16 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.17 PK6 / XCS — Port K I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.18 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.19 PAD[15:0] / AN[15:0] / KWAD[15:0] — Port AD I/O Pins [15:0]. . . . . . . . . . . . . . 85
2.3.20 PM7 / SCL — Port M I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Device User Guide — 9S12E128DGV1/D V01.04
2.3.21 PM6 / SDA — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.22 PM5 / TXD2 — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.23 PM4 / RXD2 — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.24 PM3 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.25 PM1 / DAO1 — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.26 PM0 / DAO2 — Port M I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.27 PP[5:0] / PW0[5:0] — Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.28 PQ[6:4] / IS[2:0] — Port Q I/O Pins [6:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.29 PQ[3:0] / FAULT[3:0] — Port Q I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.30 PS7 / SS — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.31 PS6 / SCK — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.32 PS5 / MOSI — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.33 PS4 / MISO — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.34 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.35 PS2 / RXD1 — Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.36 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.37 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.38 PT[7:4] / IOC1[7:4]— Port T I/O Pins [7:4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.39 PT[3:0] / IOC0[7:4]— Port T I/O Pins [3:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.40 PU[7:6] — Port U I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.41 PU[5:4] / PW1[5:4] — Port U I/O Pins [5:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.42 PU[3:0] / IOC2[7:4]/PW1[3:0] — Port U I/O Pins [3:0] . . . . . . . . . . . . . . . . . . . . . 88
2.4
2.4.1
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 89
VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage Regulator
2.4.2
89
2.4.3
2.4.4
2.4.5
2.4.6
VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic . . . . . . . . . 89
VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 89
VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 89
VDDPLL, VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . 89
Section 3 System Clock Description
Section 4 Modes of Operation
4.1
4.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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Device User Guide — 9S12E128DGV1/D V01.04
4.3
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
Section 5 Resets and Interrupts
5.1
5.2
5.3
5.3.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Section 6 HCS12 Core Block Description
6.1
6.2
6.3
6.4
6.5
6.6
CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
HCS12 Background Debug Module (BDM) Block Description . . . . . . . . . . . . . . . . . 97
HCS12 Debug (DBG) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 97
HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . 98
Section 7 Analog to Digital Converter (ATD) Block Description
Section 8 Clock Reset Generator (CRG) Block Description
8.1
8.1.1
Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Section 9 Digital to Analog Converter (DAC) Block Description
Section 10 Flash EEPROM Block Description
Section 11 IIC Block Description
Section 12 Oscillator (OSC) Block Description
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Device User Guide — 9S12E128DGV1/D V01.04
Section 13 Port Integration Module (PIM) Block Description
Section 14 Pulse width Modulator with Fault protection (PMF) Block Descrip-
tion
Section 15 Pulse Width Modulator (PWM) Block Description
Section 16 Serial Communications Interface (SCI) Block Description
Section 17 Serial Peripheral Interface (SPI) Block Description
Section 18 Timer (TIM) Block Description
Section 19 Voltage Regulator (VREG) Block Description
19.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
19.2 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Section 20 Printed Circuit Board Layout Proposals
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
A.1.6
A.1.7
A.1.8
A.1.9
Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Appendix B Electrical Specifications
B.1 Voltage Regulator (VREG_3V3) Operating Characteristics . . . . . . . . . . . . . . . . . . 117
B.2 Chip Power-up and LVI/LVR graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . 118
B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
B.3.1
Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Device User Guide — 9S12E128DGV1/D V01.04
B.3.2
Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
B.4 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
B.4.1
B.4.2
B.4.3
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
B.5 Flash NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
B.5.1
B.5.2
NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
B.6 SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
B.6.1
B.6.2
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
B.7 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
B.7.1
B.7.2
B.7.3
B.7.4
B.7.5
ATD Operating Characteristics - 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
ATD Operating Characteristics - 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ATD accuracy - 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ATD accuracy - 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
B.8 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B.8.1 DAC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Appendix C External Bus Timing
Appendix D Package Information
D.1 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
D.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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List of Figures
Figure 0-1 Order Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 1-1 MC9S12E-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 1-2 MC9S12E256 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 23
Figure 1-3 MC9S12E128 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 24
Figure 1-4 MC9S12E64 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 1-5 MC9S12E32 User configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-1 Pin assignments 112 LQFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 76
Figure 2-2 Pin assignments in 80 QFP for MC9S12E-Family. . . . . . . . . . . . . . . . . . . . . 77
Figure 2-3 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 2-4 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 20-1 Recommended PCB Layout (112 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 20-2 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . 118
Figure B-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure B-3 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure B-4 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure B-5 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure B-6 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure B-7 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure B-8 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure C-1 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 153
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List of Tables
Table 0-1 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 0-2 Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 0-3 Package Option Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 0-4 List of MC9S12E-Family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-2 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 1-3 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 2-2 MC9S12E-Family Power and Ground Connection Summary . . . . . . . . . . . . . 90
Table 3-1 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 5-2 Reset Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 20-1 Recommended decoupling capacitor choice. . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-7 Preliminary 3.3V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table A-8 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 20-2 VREG_3V3 - Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table B-1 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table B-2 Startup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table B-3 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table B-4 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table B-5 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table B-6 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table B-7 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table B-8 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table B-9 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Table B-10 5V ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table B-11 3.3V ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table B-12 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table B-14 3.3V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table B-13 5V ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table B-15 DAC Electrical Characteristics (Operating) . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table B-16 DAC Timing/Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table C-1 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . . 149
Table C-2 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . . 151
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Device User Guide — 9S12E128DGV1/D V01.04
Preface
The Device User Guide provides information about the MC9S12E-Family devices made up of standard
HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A
complete set of device manuals also includes all the individual Block Guides of the implemented modules.
In a effort to reduce redundancy, all module specific information is located only in the respective Block
Guide. If applicable, special implementation details of the module are given in the block description
sections of this document.
See Table 0-1 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-1 Document References
E256
E128, E64
Version
E32
Document Order
Number
Block Guide
Version
Version
CPU12 Reference Manual
HCS12 Background Debug (BDM)
HCS12 Debug (DBG)
V02
V04
V01
V01
V03
V04
V04
V04
V01
V01
N/A
N/A
V02
V02
V01
V02
V01
V04
V03
V01
V02
V02
V04
V01
V01
V03
V04
V02
V04
V01
N/A
V01
N/A
V02
V02
V01
V02
V01
V03
V03
V01
V02
V02
V04
V01
V01
V03
V04
V04
V04
V01
N/A
N/A
V02
V02
V02
V01
V02
V01
V04
V03
V01
V02
S12CPUV2/D
S12BDMV4/D
S12DBGV1/D
S12INTV1/D
S12MEBIV3/D
S12MMCV4/D
HCS12 Interrupt (INT)
HCS12 Multiplexed Expanded Bus Interface (MEBI)
HCS12 Module Mapping Control (MMC)
Analog to Digital Converter: 10-Bit, 16 Channels (ATD_10B16C)
Clock and Reset Generator (CRG)
S12ATD10B16CVx/D1
S12CRGV4/D
Digital to Analog Converter: 8-Bit, 1 Channel (DAC_8B1C)
256Kbyte Flash EEPROM (FTS256K2)
128Kbyte Flash EEPROM (FTS128K1)
32Kbyte Flash EEPROM (FTS32K)
S12DAC8B1CV1/D
S12FTS256K2V1/D
S12FTS128K1V1/D
S12FTS32KV2/D
S12IICV2/D
Inter IC Bus (IIC)
Oscillator (OSC)
S12OSCV2/D
Port Integration Module (PIM_9E128)
Pulse Modulator with Fault Protection: 15-Bit, 6 Channels (PMF_15B6C)
Pulse Width Modulator: 8-Bit, 6 Channels (PWM_8B6C)
Serial Communications Interface (SCI)
Serial Peripheral Interface (SPI)
S12PIM9E128V1/D
S12PMF15B6CV2/D
S12PWM8B6CV1/D
S12SCIVy/D2
S12SPIV3/D
S12TIM16B4CV1/D
S12VREG3V3V2/D
Timer: 16-Bit, 4 Channels (TIM_16B4C)
Voltage Regulator (VREG_3V3)
NOTES:
1. x in S12ATD10B16CVx/D is 2 for E64 and E128, and 4 for E32 and E256.
2. y in S12SCIVy/D is 3 for E64 and E128, and 4 for E32 and E256.
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Device User Guide — 9S12E128DGV1/D V01.04
Part Number
Figure 0-1 provides an ordering number example.
MC9S12 E128 C FU
Package Options
FC = 64QFN
Package Option
Temperature Option
FU = 80QFP
PV = 112LQFP
Temperature Options
C = -40°C to 85°C
V = -40°C to 105°C
M = -40°C to 125°C
Device Title
Controller Family
Figure 0-1 Order Part Number Coding
Table 0-2 lists the part number coding based on the package and temperature.
Table 0-2 Part Number Coding
Part Number
MC9S12E256CFU
MC9S12E256CPV
MC9S12E256MFU
MC9S12E256MPV
MC9S12E128CFU
MC9S12E128CPV
MC9S12E128MFU
MC9S12E128MPV
MC9S12E64CFU
MC9S12E64CPV
MC9S12E64MFU
MC9S12E64MPV
MC9S12E32CFU
MC9S12E32MFU
Temp.
Package
80QFP
112LQFP
80QFP
Description
MC9S12E256
MC9S12E256
MC9S12E256
MC9S12E256
MC9S12E128
MC9S12E128
MC9S12E128
MC9S12E128
MC9S12E64
MC9S12E64
MC9S12E64
MC9S12E64
MC9S12E32
MC9S12E32
-40°C, 85°C
-40°C, 85°C
-40°C, 125°C
-40°C, 125°C 112LQFP
-40°C, 85°C
-40°C, 85°C
-40°C, 125°C
80QFP
112LQFP
80QFP
-40°C, 125°C 112LQFP
-40°C, 85°C
-40°C, 85°C
-40°C, 125°C
-40°C, 125°C 112LQFP
-40°C, 85°C
80QFP
112LQFP
80QFP
80QFP
80QFP
-40°C, 125°C
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Device User Guide — 9S12E128DGV1/D V01.04
Table 0-3 summarizes the package option and size configuration.
Table 0-3 Package Option Summary
1
Temp.
2
Package
Device
Part Number
Flash
256K
128K
64K
RAM
16K
8K
I/O
Options
M, C
80QFP MC9S12E256
112LQFP MC9S12E256
80QFP MC9S12E128
112LQFP MC9S12E128
80QFP
112LQFP MC9S12E64
MC9S12E256
MC9S12E256
MC9S12E128
MC9S12E128
MC9S12E64
MC9S12E64
MC9S12E32
MC9S12E32
60
92
60
92
60
92
44
60
M, C
M, C
M, C
M, C
M, C
M, C
M, C
MC9S12E64
4K
64QFN
80QFP
MC9S12E32
MC9S12E32
32K
2K
NOTES:
1. C: TA = 85¯C, f = 25MHz. M: TA= 125¯C, f = 25MHz
2. I/O is the sum of ports capable to act as digital input or output.
Table 0-4 List of MC9S12E-Family members
Device Flash RAM Package MEBI TIM
SCI
SPI
IIC
A/D
D/A PWM PMF KWU I/O
112 LQFP
80 QFP
1
0
1
0
1
0
0
92
E256
256K
16K
12
3
1
1
16
2
6
6
16
60
92
60
92
60
60
112 LQFP
80 QFP
E128
128K
8K
12
3
1
1
16
2
6
6
16
112 LQFP
80 QFP
80 QFP
E64
E32
64K
32K
4K
2K
12
8
3
2
1
1
1
1
16
16
2
2
6
0
6
6
16
16
• Pin out explanations:
— TIM is the number of channels.
— A/D is the number of A/D channels.
— D/A is the number of D/A channels.
— PWM is the number of channels.
— PMF is the number of channels.
— KWU is the number of key wake up interrupt pins.
— I/O is the sum of ports capable to act as digital input or output.
112 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, K = 8, M = 7, P = 6, Q = 7,
S = 8, T = 8, U = 8, AD = 16.
18 inputs provide Interrupt capability (AD = 16, IRQ, XIRQ)
80 Pin Packages:
E = 2 + 2 input only, M = 7, P = 6, Q = 7,
S = 8, T = 8, U = 4, AD = 16.
18 inputs provide Interrupt capability (AD = 16, IRQ, XIRQ)
— Versions with 3 SCI modules will have SCI0, SCI1 and SCI2.
— Versions with 2 SCI modules will have SCI0 and SCI1.
— Versions with 3 TIM modules will have TIM0, TIM1 and TIM2.
— Versions with 2 TIM modules will have TIM0 and TIM1.
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Section 1 Introduction
1.1 Overview
The MC9S12E-Family is a 112/80 pin low cost general purpose MCU family. All members of the
MC9S12E-Family are comprised of standard on-chip peripherals including a 16-bit central processing unit
(HCS12 CPU), up to 256K bytes of Flash EEPROM, up to 16K bytes of RAM, three asynchronous serial
communications interface modules (SCI), a serial peripheral interface (SPI), an Inter-IC Bus (IIC), three
4-channel 16-bit timer modules (TIM), a 6-channel 15-bit Pulse Modulator with Fault protection module
(PMF), a 6-channel 8-bit Pulse Width Modulator (PWM), a 16-channel 10-bit analog-to-digital converter
(ADC), and two 1-channel 8-bit digital-to-analog converters (DAC). The MC9S12E-Family has full 16-bit
data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available on each module, 16
dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. Furthermore,
an on chip bandgap based voltage regulator (VREG) generates the internal digital supply voltage of 2.5V
(VDD) from a 3.135V to 5.5V external supply range.
1.2 Features
•
16-bit HCS12 CORE
– HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
– Module Mapping Control (MMC)
– Interrupt Control (INT)
– Background Debug Module (BDM)
– Debugger (DBG12) including breakpoints and change-of-flow trace buffer
– Multiplexed External Bus Interface (MEBI)
Wake-Up interrupt inputs
– Up to 16 port bits available for wake up interrupt function with digital filtering
Memory options
•
•
– 32K, 64K, 128K or 256K Byte Flash EEPROM
– 2K, 4K, 8K or 16K Byte RAM
•
Two 1-channel Digital-to-Analog Converters (DAC)
– 8-bit resolution
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Device User Guide — 9S12E128DGV1/D V01.04
•
Analog-to-Digital Converter (ADC)
– 16-channel module with 10-bit resolution
– External conversion trigger capability
Three 4-channel Timers (TIM)
•
– Programmable input capture or output compare channels
– Simple PWM mode
– Counter Modulo Reset
– External Event Counting
– Gated Time Accumulation
•
•
6 PWM channels (PWM)
– Programmable period and duty cycle
– 8-bit 6-channel or 16-bit 3-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
6-channel Pulse width Modulator with Fault protection (PMF)
– Three independent 15-bit counters with synchronous mode
– Complementary channel operation
– Edge and center aligned PWM signals
– Programmable dead time insertion
– Integral reload rates from 1 to 16
– Four fault protection shut down input pins
– Three current sense input pins
•
•
Serial interfaces
– Three asynchronous serial communication interfaces (SCI)
– Synchronous serial peripheral interface (SPI)
– Inter-IC Bus (IIC)
Clock and Reset Generator (CRG)
– Windowed COP watchdog
– Real Time interrupt
– Clock Monitor
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– Pierce or low current Colpitts oscillator
– Phase-locked loop clock frequency multiplier
– Self Clock mode in absence of external clock
– Low power 0.5 to 16Mhz crystal oscillator reference clock
Operating frequency
– 50MHz equivalent to 25MHz Bus Speed
Internal 2.5V Regulator
•
•
– Input voltage range from 3.135V to 5.5V
– Low power mode capability
– Includes low voltage reset (LVR) circuitry
– Includes low voltage interrupt (LVI) circuitry
112-Pin LQFP or 80-Pin QFP package
•
•
– Up to 90 I/O lines with 5V input and drive capability (112 pin package)
– Up to two dedicated 5V input only lines (IRQ and XIRQ)
– Sixteen 3.3V/5V A/D converter inputs
Development Support.
TM
– Single-wire background debug mode
– On-chip hardware breakpoints
– Enhanced debug features
1.3 Modes of Operation
User modes (Expanded modes are only available in the 112 pin package version)
•
Normal modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
Special Operating Modes
•
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
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Device User Guide — 9S12E128DGV1/D V01.04
•
Low power modes
– Stop Mode
– Pseudo Stop Mode
– Wait Mode
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1.4 Block Diagram
Figure 1-1 MC9S12E-Family Block Diagram
PW00
PP0
PP1
PP2
PP3
32K - 256K Byte Flash EEPROM
PW01
PW02
PW03
PW04
PW05
2K -16K Byte RAM
Voltage Regulator
PP4
PP5
VDDR
VSSR
PMF
FAULT0
FAULT1
FAULT2
FAULT3
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
BKGD
MODC/TAGHI
CPU12
Single-wire Background
Debug Module
Periodic Interrupt
COP Watchdog
Clock Monitor
Debugger(DBG12)
Breakpoints
IS0
IS1
IS2
XFC
Clock and
EXTAL
XTAL
RESET
PQ6
CRG
Reset
Generation
RXD0
TXD0
RXD1
TXD1
MISO
MOSI
SCK
PS0
PS1
SCI0
SCI1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
XIRQ
IRQ
PS2
PS3
PS4
PS5
PS6
PS7
R/W
System
LSTRB/TAGLO
Integration
Module
(SIM)
SPI
ECLK
MODA/IPIPE0
SS
MODB/IPIPE1
NOACC/XCLKS
IOC04
IOC05
IOC06
IOC07
IOC14
IOC15
IOC16
IOC17
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PU0
PU1
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
TIM0
TIM1
XADDR19
XCS
ECS
PW10
TEST
PW11
PW12
PW13
PW14
PW15
MUX
PU2
PU3
PU4
PU5
PWM
Multiplexed Address/Data Bus
PU6
IOC24
IOC25
IOC26
IOC27
PU7
DDRA
PTA
DDRB
PTB
TIM2
KWAD0
KWAD1
KWAD2
KWAD3
KWAD4
KWAD5
KWAD6
KWAD7
KWAD8
KWAD9
KWAD10
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PAD8
PAD9
PAD10
AN0
AN1
AN2
AN3
AN4
ADC
AN5
AN6
Multiplexed
Wide Bus
AN7
AN8
AN9
ADC/DAC 3.3V/5V
Voltage Reference
Multiplexed
Narrow Bus
AN10
AN11
AN12
AN13
AN14
AN15
KWAD11
KWAD12
PAD11
PAD12
VRH
VRL
KWAD13
PAD13
PAD14
I/O Driver 3.3V/5V
Voltage Regulator 3.3V/5V
VDDA
VSSA
KWAD14
VDDR
VSSR
VDDX
KWAD15
DAO0
PAD15
VSSX
DAC0
DAC1
PM0
PM1
PLL 2.5V
VDDPLL
VSSPLL
Internal Logic 2.5V
VDD1,2
DAO1
PM3
PM4
PM5
PM6
PM7
VSS1,2
RXD2
TXD2
SDA
SCI2
IIC
Signals shown in Bold are not available on the 80 Pin Package
SCL
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1.5 Device Memory Map
Table 1-1 shows the device register map of the MC9S12E-Family after reset. The following figures (,
Figure 1-3, and Figure 1-4) illustrate the full device memory map with Flash and RAM.
Table 1-1 Device Register Map Overview
Address
$000 - $017
$018
Module
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Size
24
1
$019
Voltage Regulator (VREG)
1
$01A - $01B
$01C - $01F
$020 - $02F
$030 - $033
$034 - $03F
$040 - $06F
$070 - $07F
$080 - $0AF
$0B0 - $0C7
$0C8 - $0CF
$0D0 - $0D7
$0D8 - $0DF
$0E0 - $0E7
$0E8 - $0EF
$0F0 - $0F3
$0F4 - $0F7
$0F8 - $0FF
$100- $10F
$110 - $13F
$140 - $16F
$170 - $17F
$180 - $1AF
$1B0 - $1DF
$1E0 - $1FF
$200 - $23F
$240 - $27F
$280 - $3FF
Device ID register (PARTID)
CORE (MEMSIZ, IRQ, HPRIO)
CORE (DBG)
2
4
16
4
12
48
16
48
24
8
8
8
8
8
4
4
8
16
48
48
16
48
48
32
64
64
384
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Standard Timer 16-bit 4 channels (TIM0)
Reserved
Analog to Digital Converter 10-bit 16 channels (ATD)
Reserved
Serial Communications Interface 0 (SCI0)
Serial Communications Interface 1 (SCI1)
Serial Peripheral Interface (SPI)
Inter IC Bus
Serial Communications Interface 2 (SCI2)
Digital to Analog Converter 8-bit 1-channel (DAC0)
Digital to Analog Converter 8-bit 1-channel (DAC1)
Reserved
Flash Control Register
Reserved
Standard Timer 16-bit 4 channels (TIM1)
Reserved
Standard Timer 16-bit 4 channels (TIM2)
Reserved
Pulse Width Modulator 8-bit 6 channels (PWM)
Pulse Width Modulator with Fault 15-bit 6 channels (PMF)
Port Integration Module (PIM)
Reserved
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$4000
$8000
$C000
$4000
16K Bytes RAM
Mappable to any 16K Boundary
$7FFF
$8000
16K Page Window
sixteen * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
$FFFF
VECTORS
VECTORS
NORMAL
EXPANDED
SPECIAL
SINGLE CHIP
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $3FFF: 16K RAM (only 15K RAM visible $0400 - $3FFF)
Figure 1-2 MC9S12E256 User Configurable Memory Map
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$2000
$4000
$2000
$3FFF
$4000
8K Bytes RAM
Mappable to any 8K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
$C000
16K Page Window
eight * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
$FFFF
VECTORS
VECTORS
NORMAL
EXPANDED
SPECIAL
SINGLE CHIP
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $1FFF: 8K RAM (only 7K RAM visible $0400 - $1FFF)
Figure 1-3 MC9S12E128 User Configurable Memory Map
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$3000
$4000
$3000
$3FFF
$4000
4K Bytes RAM
Mappable to any 4K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
$C000
16K Page Window
four * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
$FFFF
VECTORS
VECTORS
NORMAL
EXPANDED
SPECIAL
SINGLE CHIP
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $0FFF: 4K RAM (only 3K RAM visible $0400 - $0FFF)
Figure 1-4 MC9S12E64 User Configurable Memory Map
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$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
$0000
$0400
$3000
$4000
$3700
$3FFF
$4000
2K Bytes RAM
Mappable to any 2K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
$7FFF
$8000
$8000
$C000
16K Page Window
two * 16K Flash EEPROM Pages
EXT
$BFFF
$C000
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$FFFF
$FF00
BDM
(If Active)
$FF00
$FFFF
VECTORS
$FFFF
VECTORS
VECTORS
NORMAL
EXPANDED
SPECIAL
SINGLE CHIP
SINGLE CHIP
The figure shows a useful map, which is not the map out of reset. After reset the map is:
$0000 - $03FF: Register Space
$0000 - $07FF: 2K RAM (only 1K RAM visible $0400 - $07FF)
Figure 1-5 MC9S12E32 User configurable Memory Map
1.6 Detailed Register Map
The detailed register map of the MC9S12E-Family is listed in address order below. For detailed
information about register function please refer to the appropriate block guide.
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$0000 - $000F
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
PORTA
PORTB
DDRA
Write
:
Read
:
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
Write
:
Read
:
Write
:
Read
:
DDRB
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write
:
Read
:
Reserved
Reserved
Reserved
Reserved
PORTE
DDRE
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
0
0
:
Write
:
Read
Bit 1
0
Bit 0
0
:
Bit 7
Bit 7
6
5
5
4
4
3
3
2
Write
:
Read
:
6
0
Bit 2
Write
:
Read
0
0
:
Write
:
NOACC
E
PEAR
PIPOE NECLK LSTRE RDWE
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$0000 - $000F
MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Read
0
0
0
0
0
0
:
$000B
$000C
$000D
$000E
MODE
PUCR
MODC MODB MODA
IVIS
0
EMK
EME
Write
:
Read
0
0
0
0
0
0
0
0
:
PUPKE
PUPEE
PUPBE PUPAE
Write
:
Read
0
0
0
:
RDRIV
EBICTL
RDPK
0
RDPE
0
RDPB
0
RDPA
Write
:
Read
:
ESTR
0
Write
:
Read
0
0
0
:
Write
:
$000F Reserved
$0010 - $0014
MMC map 1 of 4 (HCS12 Module Mapping Control)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
Read
:
RAMHA
L
$0010
$0011
$0012
$0013
$0014
INITRM
INITRG
INITEE
MISC
RAM15 RAM14 RAM13 RAM12 RAM11
Write
:
Read
0
0
0
0
0
0
:
REG14 REG13 REG12 REG11
Write
:
Read
:
EE15
0
EE14
0
EE13
0
EE12
0
EE11
EEON
Write
:
Read
:
EXSTR1 EXSTR0 ROMHM ROMON
Write
:
Read
Bit 7
6
5
4
3
2
1
Bit 0
:
Write
:
MTST0
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$0015 - $0016
INT map 1 of 2 (HCS12 Interrupt)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
$0015
ITCR
WRINT ADR3
ADR2
ADR1
ADR0
Write
:
Read
:
Write
:
$0016
ITEST
INTE
INTC
INTA
INT8
INT6
INT4
INT2
INT0
$0017 - $0017
MMC map 2 of 4 (HCS12 Module Mapping Control)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
Write
:
$0017
MTST1
$0018 - $0018
Miscellaneous Peripherals (Device User Guide)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read
0
0
0
0
0
0
0
:
Write
:
$0018
Reserved
$0019 - $0019
VREG3V3 (Voltage Regulator)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
LVIE
Bit 0
LVIF
Read
0
0
0
0
LVDS
:
Write
:
$0019 VREGCTRL
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$001A - $001B
Miscellaneous Peripherals (Device User Guide)
Addres
Name
s
Bit 7
ID15
Bit 6
ID14
Bit 5
ID13
Bit 4
ID12
Bit 3
ID11
Bit 2
ID10
Bit 1
ID9
Bit 0
ID8
Read
:
$001A PARTIDH
Write
:
Read
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
:
Write
:
$001B
PARTIDL
$001C - $001D
User Guide)
MMC map 3 of 4 (HCS12 Module Mapping Control, Device
Addres
s
Name
Bit 7
Bit 6
0
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
Read
eep_sw eep_sw
ram_sw ram_sw ram_sw
reg_sw0
:
Write
:
1
0
0
0
2
0
1
0
$001C MEMSIZ0
$001D MEMSIZ1
Read rom_sw rom_sw
pag_sw pag_sw
0
:
Write
:
1
0
1
0
$001E - $001E
MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Addres
Name
s
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
Write
:
$001E
INTCR
IRQE
IRQEN
$001F - $001F
INT map 2 of 2 (HCS12 Interrupt)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read
:
Write
:
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
$001F
HPRIO
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$0020 - $002F
DBG (including BKP) map 1of 1 (HCS12 Debug)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
Bit 0
DBGC1
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
read
write
DBGEN
AF
ARM
BF
TRGSEL BEGIN DBGBRK
CAPMOD
$0020
-
CF
0
DBGSC
TRG
$0021
-
DBGTBH
Bit 15
Bit 14
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
$0022
-
DBGTBL
Bit 7
TBF
Bit 6
0
$0023
-
DBGCNT
CNT
EXTCMP
$0024
-
DBGCCX
$0025
PAGSEL
-
DBGCCH
$0026
Bit 15
Bit 7
14
6
13
5
12
4
11
10
2
9
1
Bit 8
Bit 0
RWC
DBGCCL
$0027
3
-
DBGC2
$0028
BKABEN
FULL
BDM
TAGAB BKCEN
TAGC
RWCEN
RWBEN
BKPCT0
DBGC3
BKPCT1
$0029
BKAMBH BKAMBL BKBMBH BKBMBL RWAEN
PAGSEL
Bit 15
RWA
RWB
DBGCAX
BKP0X
EXTCMP
$002A
DBGCAH
$002B
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
BKP0H
DBGCAL
$002C
Bit 7
BKP0L
DBGCBX
$002D
PAGSEL
EXTCMP
BKP1X
DBGCBH
$002E
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
BKP1H
DBGCBL
$002F
BKP1L
$0030 - $0031
MMC map 4 of 4 (HCS12 Module Mapping Control)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
PIX5
0
Bit 4
PIX4
0
Bit 3
PIX3
0
Bit 2
PIX2
0
Bit 1
PIX1
0
Bit 0
PIX0
0
Read
:
$0030
PPAGE
Write
:
Read
0
0
:
Write
:
$0031
Reserved
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$0032 - $0033
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
Addres
Name
s
Bit 7
ECS
Bit 6
XCS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
XAB19
XAB18
XAB17
XAB16
XAB15
XAB14
$0032
PORTK
Write
:
Read
:
Write
:
$0033
DDRK
Bit 7
6
5
4
3
2
1
Bit 0
$0034 - $003F
CRG (Clock and Reset Generator)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
SYN5
0
Bit 4
SYN4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
SYNR
SYN3
SYN2
SYN1
SYN0
Write
:
Read
0
0
:
REFDV REFDV REFDV REFDV
REFDV
3
2
1
0
Write
:
Read
TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0
:
CTFLG
TEST ONLY
Write
:
Read
0
0
LOCK TRACK
SCM
0
:
CRGFLG
CRGINT
CLKSEL
PLLCTL
RTICTL
RTIF
RTIE
PROF
0
LOCKIF
LOCKIE
SCMIF
SCMIE
Write
:
Read
0
0
:
Write
:
Read
:
ROAWA
I
COPWA
I
PLLSEL PSTP SYSWAI
PLLWAI CWAI RTIWAI
0
Write
:
Read
:
CME
0
PLLON AUTO
ACQ
PRE
PCE
SCME
RTR0
Write
:
Read
:
Write
:
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
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$0034 - $003F
CRG (Clock and Reset Generator)
Addres
Name
s
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
CR2
0
Bit 1
CR1
Bit 0
CR0
0
Read
:
$003C
$003D
$003E
COPCTL
WCOP RSBCK
Write
:
Read
0
0
:
FORBYP
COPBY
RTIBYP
P
PLLBYP
FCM
TEST ONLY
Write
:
Read
TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0
:
CTCTL
TEST ONLY
Write
:
Read
0
0
6
0
5
0
4
0
3
0
2
0
1
0
:
Write
:
$003F ARMCOP
Bit 7
Bit 0
$0040 - $006F
TIM0 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0040
$0041
$0042
$0043
TIOS
CFORC
OC7M
OC7D
IOS7
IOS6
IOS5
IOS4
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
9
1
0
0
:
Write
FOC7
FOC6
FOC5
FOC4
:
Read
:
OC7M7 OC7M6 OC7M5 OC7M4
OC7D7 OC7D6 OC7D5 OC7D4
Write
:
Read
0
0
0
:
Write
:
Read
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 8
Bit 0
:
$0044 TCNT (hi)
$0045 TCNT (lo)
Write
:
Read
:
Write
:
33
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Device User Guide — 9S12E128DGV1/D V01.04
$0040 - $006F
TIM0 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
TEN
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0046
$0047
$0048
$0049
$004A
TSCR1
TSWAI TSFRZ TFFCA
Write
:
Read
0
0
0
0
:
TTOV
TOV7
TOV6
TOV5
TOV4
Write
:
Read
:
TCTL1
OM7
0
OL7
0
OM6
0
OL6
0
OM5
0
OL5
0
OM4
0
OL4
0
Write
:
Read
:
Reserved
TCTL3
Write
:
Read
:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
:
$004B Reserved
Write
:
Read
:
$004C
$004D
$004E
$004F
$0050
TIE
C7I
TOI
C7F
C6I
0
C5I
0
C4I
0
Write
:
Read
:
TSCR2
TFLG1
TFLG2
Reserved
TCRE
0
PR2
0
PR1
0
PR0
0
Write
:
Read
:
C6F
0
C5F
0
C4F
0
Write
:
Read
0
0
0
0
0
0
0
0
:
TOF
0
Write
:
Read
0
0
0
:
Write
:
34
For More Information On This Product,
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Device User Guide — 9S12E128DGV1/D V01.04
$0040 - $006F
TIM0 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0051
$0052
$0053
$0054
$0055
$0056
$0057
$0058
$0059
$005A
$005B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TC4 (hi)
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
Bit 8
Bit 0
Bit 8
Bit 0
Write
:
Read
:
TC4 (lo)
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
TC5 (hi)
Write
:
Read
:
Write
:
TC5 (lo)
35
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Device User Guide — 9S12E128DGV1/D V01.04
$0040 - $006F
TIM0 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit 8
Read
:
Bit 15
$005C
$005D
$005E
$005F
$0060
$0061
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
Write
:
Read
:
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
Bit 0
Bit 8
Bit 0
PAI
Write
:
Read
:
Bit 15
9
1
Write
:
Read
:
Bit 7
0
Write
:
Read
:
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
PAOVF
9
Write
:
Read
0
0
0
:
PAFLG
PAIF
Bit 8
Write
:
Read
:
Bit 15
14
13
12
11
10
$0062 PACNT (hi)
$0063 PACNT (lo)
Write
:
Read
:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write
:
Read
:
$0064
$0065
$0066
Reserved
Reserved
Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
36
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0040 - $006F
TIM0 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0067
$0068
$0069
Reserved
Reserved
Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
$006A Reserved
$006B Reserved
$006C Reserved
$006D Reserved
$006E Reserved
$006F Reserved
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
$0070 - $007F
Reserved
Read
0
0
0
0
0
0
0
0
$0070
:
Write
:
-
Reserved
$007F
37
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
1
1
1
1
$0080 ATDCTL0
$0081 ATDCTL1
$0082 ATDCTL2
$0083 ATDCTL3
$0084 ATDCTL4
$0085 ATDCTL5
$0086 ATDSTAT0
WRAP3 WRAP2 WRAP1 WRAP0
Write
:
Read
0
0
0
:
ETRIGS
ETRIGC ETRIGC ETRIGC ETRIGC
2
2
2
2
2
EL
H3
H2
H1
H0
Write
:
Read
ASCIF
:
ETRIGL
E
ADPU
0
AFFC
S8C
AWAI
S4C
ETRIGP ETRIG ASCIE
Write
:
Read
:
S2C
PRS4
MULT
S1C
FIFO
FRZ1
PRS1
FRZ0
PRS0
Write
:
Read
:
SRES8 SMP1
SMP0
SCAN
PRS3
0
PRS2
Write
:
Read
:
DJM
DSGN
0
CC
CB
CA
Write
:
Read
0
0
0
0
CC2
CC1
CC0
:
SCF
0
ETORF FIFOR
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
$0087
Reserved
Write
:
Read
0
0
:
$0088 ATDTEST0
$0089 ATDTEST1
$008A ATDSTAT0
Write
:
Read
0
:
SC
Write
:
Read
CCF15 CCF14 CCF13 CCF12 CCF11 CCF10
CCF9
CCF8
:
Write
:
38
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Device User Guide — 9S12E128DGV1/D V01.04
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
:
$008B ATDSTAT1
$008C ATDDIEN0
$008D ATDDIEN1
$008E PORTAD0
$008F PORTAD1
$0090 ATDDR0H
$0091 ATDDR0L
$0092 ATDDR1H
$0093 ATDDR1L
$0094 ATDDR2H
$0095 ATDDR2L
Write
:
Read
:
IEN15
IEN7
IEN14
IEN6
IEN13
IEN5
IEN12
IEN4
IEN11
IEN3
IEN10
IEN2
IEN9
IEN1
IEN8
Write
:
Read
:
IEN0
Write
:
Read
PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9
PTAD8
:
Write
:
Read
PTAD7
Bit15
Bit7
PTAD6
14
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
Bit8
0
:
Write
:
Read
13
0
12
0
11
0
10
0
9
0
9
0
9
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
:
Write
:
39
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Addres
Name
s
Bit 7
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
Read
Bit15
:
$0096 ATDDR3H
$0097 ATDDR3L
$0098 ATDDR4H
$0099 ATDDR4L
$009A ATDDR5H
$009B ATDDR5L
$009C ATDDR6H
$009D ATDDR6L
$009E ATDDR7H
$009F ATDDR7L
$00A0 ATDDR8H
Write
:
Read
Bit7
Bit15
Bit7
Bit6
14
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
9
0
9
0
9
0
9
0
Bit8
0
:
Write
:
Read
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
13
12
11
10
Bit8
:
Write
:
40
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Device User Guide — 9S12E128DGV1/D V01.04
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Addres
Name
s
Bit 7
Bit7
Bit 6
Bit6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$00A1 ATDDR8L
$00A2 ATDDR9H
$00A3 ATDDR9L
$00A4 ATDDR10H
$00A5 ATDDR10L
$00A6 ATDDR11H
$00A7 ATDDR11L
$00A8 ATDDR12H
$00A9 ATDDR12L
$00AA ATDDR13H
$00AB ATDDR13L
Write
:
Read
Bit15
Bit7
14
Bit6
14
13
0
12
0
11
0
10
0
9
0
9
0
9
0
9
0
9
0
Bit8
0
:
Write
:
Read
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
14
:
Write
:
Read
Bit15
Bit7
13
0
12
0
11
0
10
0
Bit8
0
:
Write
:
Read
Bit6
:
Write
:
41
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Device User Guide — 9S12E128DGV1/D V01.04
$0080 - $00AF
ATD (Analog to Digital Converter 10 Bit 16 Channel)
Addres
Name
s
Bit 7
Bit 6
14
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
Bit8
Read
Bit15
:
$00AC ATDDR14H
$00AD ATDDR14L
$00AE ATDDR15H
Write
:
Read
Bit7
Bit15
Bit7
Bit6
14
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
Bit8
0
:
Write
:
Read
:
Write
:
Read
Bit6
:
Write
:
$00AF ATDDR15L
NOTES:
1. WRAP0-3 bits are available in version V04 of ATD10B16C
2. ETRIGSEL and ETRIGCH0-3 bits are available in version V04 of ATD10B16C
$00B0 - $00C7
Reserved
Read
0
0
0
0
0
0
0
0
$00B0
:
Write
:
-
Reserved
$00C7
$00C8 - $00CF
SCI0 (Asynchronous Serial Interface)
Addres
Name
s
Bit 7
IREN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
$00C8
$00C9
$00CA
SCIBDH
SCIBDL
SCICR1
Write
:
Read
:
SBR7
SBR6
SBR5
RSRC
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
Write
:
Read
:
Write
:
SCISWA
I
LOOPS
WAKE
42
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Device User Guide — 9S12E128DGV1/D V01.04
$00C8 - $00CF
SCI0 (Asynchronous Serial Interface)
Addres
Name
s
Bit 7
TIE
Bit 6
TCIE
TC
Bit 5
RIE
Bit 4
ILIE
Bit 3
TE
Bit 2
RE
Bit 1
RWU
FE
Bit 0
SBK
PF
Read
:
$00CB
$00CC
$00CD
$00CE
SCICR2
SCISR1
SCISR2
SCIDRH
SCIDRL
Write
:
Read
TDRE
RDRF
IDLE
OR
NF
:
Write
:
Read
0
0
0
0
RAF
0
:
1
1
TXPOL RXPOL BRK13 TXDIR
Write
:
Read
R8
0
0
0
0
:
T8
Write
:
Read
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
:
Write
:
$00CF
NOTES:
1. TXPOL and RXPOL bits are available in version V04 of SCI
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface)
Addres
Name
s
Bit 7
IREN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
$00D0
$00D1
$00D2
$00D3
SCIBDH
SCIBDL
SCICR1
SCICR2
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
Write
:
Read
:
SBR7
LOOPS
TIE
SBR6
SBR5
RSRC
RIE
SBR4
M
SBR3
WAKE
TE
SBR2
ILT
SBR1
PE
SBR0
PT
Write
:
Read
:
SCISWA
I
Write
:
Read
:
Write
:
TCIE
ILIE
RE
RWU
SBK
43
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$00D0 - $00D7
SCI1 (Asynchronous Serial Interface)
Read
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
RAF
0
:
$00D4
$00D5
$00D6
SCISR1
SCISR2
SCIDRH
SCIDRL
Write
:
Read
0
0
0
0
:
1
1
TXPOL RXPOL BRK13 TXDIR
Write
:
Read
R8
0
0
0
0
:
T8
Write
:
Read
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
:
Write
:
$00D7
NOTES:
1. TXPOL and RXPOL are available in version V04 of SCI
$00D8 - $00DF
SPI (Serial Peripheral Interface)
Addres
Name
s
Bit 7
SPIE
0
Bit 6
SPE
0
Bit 5
Bit 4
Bit 3
Bit 2
CPHA
0
Bit 1
Bit 0
Read
:
$00D8
$00D9
$00DA
$00DB
SPICR1
SPICR2
SPIBR
SPTIE MSTR
CPOL
SSOE LSBFE
SPISWAI SPC0
Write
:
Read
0
:
MODFE BIDIRO
N
E
Write
:
Read
0
SPIF
0
0
:
SPPR2 SPPR1 SPPR0
SPR2
0
SPR1
0
SPR0
0
Write
:
Read
0
0
SPTEF MODF
0
0
:
SPISR
Write
:
Read
0
0
0
0
0
:
Write
:
$00DC Reserved
44
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$00D8 - $00DF
SPI (Serial Peripheral Interface)
Addres
Name
s
Bit 7
Bit7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit0
0
Read
:
$00DD
SPIDR
6
0
5
0
4
0
3
0
2
0
1
0
Write
:
Read
:
$00DE Reserved
$00DF Reserved
Write
:
Read
0
0
0
0
0
0
0
0
:
Write
:
$00E0 - $00E7
IIC (Inter-IC Bus)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Read
:
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
$00E0
$00E1
$00E2
$00E3
$00E4
IBAD
IBFD
IBCR
IBSR
IBDR
Write
:
Read
:
IBC7
IBC6
IBC5
IBC4
Tx/Rx
IBAL
D4
IBC3
IBC2
IBC1
0
IBC0
Write
:
Read
0
:
IBEN
TCF
IBIE
MS/SL
IBB
TXAK
0
IBSWAI
RXAK
Write
RSTA
SRW
:
Read
IAAS
:
IBIF
D1
Write
:
Read
:
Write
:
D7
D6
D5
D3
D2
D0
45
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Device User Guide — 9S12E128DGV1/D V01.04
$00E0 - $00E7
IIC (Inter-IC Bus)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$00E5 Reserved
$00E6 Reserved
$00E7 Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
$00E8 - $00EF
SCI2 (Asynchronous Serial Interface)
Addres
Name
s
Bit 7
IREN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
$00E8
$00E9
$00EA
$00EB
$00EC
SCIBDH
SCIBDL
SCICR1
SCICR2
SCISR1
Write
:
Read
:
SBR7
SBR6
SBR5
RSRC
SBR4
M
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
Write
:
Read
:
SCISWA
I
LOOPS
WAKE
Write
:
Read
:
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
Write
:
Read
TDRE
RDRF
IDLE
OR
:
Write
:
46
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Device User Guide — 9S12E128DGV1/D V01.04
$00E8 - $00EF
SCI2 (Asynchronous Serial Interface)
Read
0
0
0
RAF
0
:
1
1
$00ED
$00EE
SCISR2
SCIDRH
SCIDRL
TXPOL RXPOL BRK13 TXDIR
Write
:
Read
R8
0
0
0
0
0
:
T8
Write
:
Read
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
:
Write
:
$00EF
NOTES:
1. TXPOL and RXPOL are available in version V04 of SCI
$00F0 - $00F3
DAC0 (Digital-to-Analog Converter)
Addres
Name
s
Bit 7
DACE
0
Bit 6
Bit 5
0
Bit 4
0
Bit 3
DJM
0
Bit 2
Bit 1
Bit 0
Read
DACTE
:
DSGN DACWAI DACOE
$00F0
$00F1
$00F2
$00F3
DACC0
DACC1
DACD
DACD
Write
:
Read
0
0
0
0
0
0
:
Write
:
Read
:
BIT7
BIT7
BIT6
BIT6
BIT5
BIT5
BIT4
BIT4
BIT3
BIT3
BIT2
BIT2
BIT1
BIT1
BIT0
BIT0
Write
:
Read
:
Write
:
47
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Device User Guide — 9S12E128DGV1/D V01.04
$00F4 - $00F7
DAC1 (Digital-to-Analog Converter)
Addres
Name
s
Bit 7
DACE
0
Bit 6
Bit 5
0
Bit 4
0
Bit 3
DJM
0
Bit 2
Bit 1
Bit 0
Read
DACTE
:
DSGN DACWAI DACOE
$00F4
$00F5
$00F6
$00F7
DACC0
DACC1
DACD
DACD
Write
:
Read
0
0
0
0
0
0
:
Write
:
Read
:
BIT7
BIT7
BIT6
BIT6
BIT5
BIT5
BIT4
BIT4
BIT3
BIT3
BIT2
BIT2
BIT1
BIT1
BIT0
BIT0
Write
:
Read
:
Write
:
$00F8 - $00FF
Reserved
Read
0
0
0
0
0
0
0
0
$00F8
:
Write
:
-
Reserved
$00FF
$0100 - $010F
Flash Control Register
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
FDIVLD
:
Write
:
$0100
$0101
$0102
FCLKDIV
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
Read KEYEN
NV6
0
NV5
0
NV4
0
NV3
0
NV2
0
SEC1
0
SEC0
0
:
1
FSEC
Write
:
Read
0
:
Write
:
Reserved for
Factory Test
48
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Device User Guide — 9S12E128DGV1/D V01.04
$0100 - $010F
Flash Control Register
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
KEYAC
C
$0103
$0104
$0105
$0106
$0107
$0108
$0109
$010A
$010B
FCNFG
FPROT
FSTAT
CBEIE
CCIE
Write
:
Read
:
FPOPE
N
NV6
FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0
Write
:
Read
CCIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
ACCER
R
CBEIF
0
PVIOL
BLANK
Write
:
Read
0
0
0
0
0
0
0
:
FCMD
CMDB6 CMDB5
CMDB2
0
CMDB0
0
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Reserved for
Factory Test
Write
:
Read
0
0
0
0
0
0
0
0
0
0
:
Reserved for
Factory Test
Write
:
Read
:
Reserved for
Factory Test
Write
:
Read
:
Reserved for
Factory Test
Write
:
Read
:
Reserved for
Factory Test
Write
:
Read
:
Write
:
$010C Reserved
49
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Device User Guide — 9S12E128DGV1/D V01.04
$0100 - $010F
Flash Control Register
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$010D Reserved
$010E Reserved
$010F Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
$0110 - $013F
Reserved
Read
0
0
0
0
0
0
0
0
$0110
:
Write
:
-
Reserved
$013F
$0140 - $016F
TIM1 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0140
$0141
$0142
$0143
TIOS
CFORC
OC7M
OC7D
IOS7
IOS6
IOS5
IOS4
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
9
0
0
:
Write
FOC7
FOC6
FOC5
FOC4
:
Read
:
OC7M7 OC7M6 OC7M5 OC7M4
OC7D7 OC7D6 OC7D5 OC7D4
Write
:
Read
0
0
0
:
Write
:
Read
Bit 15
14
13
12
11
10
Bit 8
:
Write
:
$0144 TCNT (hi)
50
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Device User Guide — 9S12E128DGV1/D V01.04
$0140 - $016F
TIM1 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
$0145 TCNT (lo)
Write
:
Read
0
0
0
0
0
0
0
0
:
$0146
$0147
$0148
$0149
$014A
TSCR1
TTOV
TEN
TSWAI TSFRZ TFFCA
Write
:
Read
:
TOV7
TOV6
TOV5
TOV4
Write
:
Read
:
TCTL1
OM7
0
OL7
0
OM6
0
OL6
0
OM5
0
OL5
0
OM4
0
OL4
0
Write
:
Read
:
Reserved
TCTL3
Write
:
Read
:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
:
$014B Reserved
Write
:
Read
:
$014C
$014D
$014E
$014F
TIE
C7I
TOI
C6I
0
C5I
0
C4I
0
Write
:
Read
:
TSCR2
TFLG1
TFLG2
TCRE
0
PR2
0
PR1
0
PR0
0
Write
:
Read
:
C7F
TOF
C6F
0
C5F
0
C4F
0
Write
:
Read
0
0
0
0
:
Write
:
51
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$0140 - $016F
TIM1 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0150
$0151
$0152
$0153
$0154
$0155
$0156
$0157
$0158
$0159
$015A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TC4 (hi)
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
Bit 8
Bit 0
Bit 8
Write
:
Read
:
TC4 (lo)
Write
:
Read
:
Write
:
Bit 15
14
13
12
11
10
TC5 (hi)
52
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Device User Guide — 9S12E128DGV1/D V01.04
$0140 - $016F
TIM1 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
$015B
$015C
$015D
$015E
$015F
$0160
$0161
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
TC7 (lo)
PACTL
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
PAI
Write
:
Read
:
1
Write
:
Read
:
Bit 15
14
6
13
5
12
4
11
3
10
2
9
1
Write
:
Read
:
Bit 7
0
Write
:
Read
:
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
PAOVF
9
Write
:
Read
0
0
0
:
PAFLG
PAIF
Bit 8
Write
:
Read
:
$0162 PACNT (hi)
$0163 PACNT (lo)
Bit 15
14
13
12
11
10
Write
:
Read
:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write
:
Read
:
$0164
$0165
Reserved
Reserved
Write
:
Read
0
0
0
0
0
0
0
0
:
Write
:
53
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Device User Guide — 9S12E128DGV1/D V01.04
$0140 - $016F
TIM1 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0166
$0167
$0168
$0169
Reserved
Reserved
Reserved
Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
$016A Reserved
$016B Reserved
$016C Reserved
$016D Reserved
$016E Reserved
$016F Reserved
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
54
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$0170 - $017F
Reserved
Read
0
0
0
0
0
0
0
0
$0110
:
Write
:
-
Reserved
$013F
$0180 - $01AF
TIM2 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0180
$0181
$0182
$0183
TIOS
CFORC
OC7M
OC7D
IOS7
IOS6
IOS5
IOS4
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
:
Write
FOC7
FOC6
FOC5
FOC4
:
Read
:
OC7M7 OC7M6 OC7M5 OC7M4
OC7D7 OC7D6 OC7D5 OC7D4
Write
:
Read
0
0
0
:
Write
:
Read
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Bit 8
Bit 0
0
:
$0184 TCNT (hi)
$0185 TCNT (lo)
Write
:
Read
:
Write
:
Read
0
0
:
$0186
$0187
$0188
TSCR1
TTOV
TEN
TOV7
OM7
TSWAI TSFRZ TFFCA
Write
:
Read
0
0
0
:
TOV6
OL7
TOV5
OM6
TOV4
OL6
Write
:
Read
:
Write
:
TCTL1
OM5
OL5
OM4
OL4
55
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$0180 - $01AF
TIM2 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0189
Reserved
Write
:
Read
:
$018A
TCTL3
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
:
$018B Reserved
Write
:
Read
:
$018C
$018D
$018E
$018F
$0190
$0191
$0192
$0193
TIE
C7I
TOI
C7F
C6I
0
C5I
0
C4I
0
Write
:
Read
:
TSCR2
TCRE
0
PR2
0
PR1
0
PR0
0
Write
:
Read
:
TFLG1
C6F
0
C5F
0
C4F
0
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
TFLG2
TOF
0
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
:
Reserved
Reserved
Reserved
Reserved
Write
:
Read
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
56
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$0180 - $01AF
TIM2 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0194
$0195
$0196
$0197
$0198
$0199
$015A
$019B
$019C
$019D
$019E
Reserved
Reserved
Reserved
Reserved
TC4 (hi)
TC4 (lo)
TC5 (hi)
TC5 (lo)
TC6 (hi)
TC6 (lo)
TC7 (hi)
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
9
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Write
:
Read
:
Write
:
Read
:
Write
:
Bit 15
14
13
12
11
10
57
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$0180 - $01AF
TIM2 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
Bit 7
0
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
$019F
$01A0
$01A1
TC7 (lo)
PACTL
PAFLG
Write
:
Read
:
PAEN
0
PAMOD PEDGE
CLK1
0
CLK0
0
PAOVI
PAOVF
9
PAI
PAIF
Bit 8
Write
:
Read
0
0
0
:
Write
:
Read
:
Bit 15
14
13
12
11
10
$01A2 PACNT (hi)
$01A3 PACNT (lo)
$01A4 Reserved
$01A5 Reserved
$01A6 Reserved
$01A7 Reserved
$01A8 Reserved
$01A9 Reserved
Write
:
Read
:
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write
:
Read
:
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
58
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0180 - $01AF
TIM2 (Timer 16 Bit 4 Channels)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$01AA Reserved
$01AB Reserved
$01AC Reserved
$01AD Reserved
$01AE Reserved
$01AF Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
$01B0 - $01DF
Reserved
Read
0
0
0
0
0
0
0
0
$01B0
:
Write
:
-
Reserved
$01DF
59
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$01E0 - $01FF
PWM (Pulse Width Modulator)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
$01E0
PWME
PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
Write
:
Read
0
0
0
0
0
0
0
0
0
:
$01E1 PWMPOL
$01E2 PWMCLK
$01E3 PWMPRCLK
$01E4 PWMCAE
$01E5 PWMCTL
Write
:
Read
:
PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
0
Write
:
Read
:
PCKB2 PCKB1 PCKB0
PCKA2 PCKA1 PCKA0
Write
:
Read
0
:
CAE5
CAE4
CAE3
CAE2
CAE1
0
CAE0
0
Write
:
Read
:
CON45 CON23 CON01 PSWAI PFRZ
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
PWMTST
$01E6
Test Only
Write
:
Read
:
$01E7 PWMPRSC
$01E8 PWMSCLA
$01E9 PWMSCLB
$01EA PWMSCNTA
Write
:
Read
:
Bit 7
6
5
4
3
2
1
Bit 0
Write
:
Read
:
Bit 7
0
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Write
:
Read
0
:
Write
:
60
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$01E0 - $01FF
PWM (Pulse Width Modulator)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$01EB PWMSCNTB
$01EC PWMCNT0
$01ED PWMCNT1
$01EE PWMCNT2
$01EF PWMCNT3
$01F0 PWMCNT4
$01F1 PWMCNT5
$01F2 PWMPER0
$01F3 PWMPER1
$01F4 PWMPER2
$01F5 PWMPER3
Write
:
Read
Bit 7
0
6
0
6
0
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
2
0
2
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit 0
0
:
Write
:
Read
Bit 7
0
Bit 0
0
:
Write
:
Read
Bit 7
0
Bit 0
0
:
Write
:
Read
Bit 7
0
Bit 0
0
:
Write
:
Read
Bit 7
0
Bit 0
0
:
Write
:
Read
Bit 7
0
Bit 0
0
:
Write
:
Read
:
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
61
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$01E0 - $01FF
PWM (Pulse Width Modulator)
Addres
Name
s
Bit 7
Bit 7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
Bit 0
Read
:
$01F6 PWMPER4
$01F7 PWMPER5
$01F8 PWMDTY0
$01F9 PWMDTY1
$01FA PWMDTY2
$01FB PWMDTY3
$01FC PWMDTY4
$01FD PWMDTY5
$01FE PWMSDN
$01FF Reserved
Write
:
Read
:
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
6
6
6
6
6
6
6
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
5
0
3
0
Write
:
Read
PWM5I
N
:
PWM5I
NL
PWM5E
NA
PWMIF PWMIE
PWMLV
L
Write
PWMRSTR
T
:
Read
0
0
0
0
0
0
0
0
:
Write
:
62
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
Bit 6
MTG
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
WP
EDGEC EDGEB EDGEA INDEPC INDEPB INDEPA
$0200 PMFCFG0
$0201 PMFCFG1
$0202 PMFCFG2
$0203 PMFCFG3
$0204 PMFFCTL
$0205 PMFFPIN
$0206 PMFFSTA
$0207 PMFQSMP
$0208 PMFDMPA
$0209 PMFDMPB
$020A PMFDMPC
Write
:
Read
:
BOTNEGC
TOPNEGC
BOTNEGB
TOPNEGB BOTNEGA TOPNEGA
ENHA
Write
:
Read
0
0
:
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
Write
:
Read
0
:
PMFWAI PMFFRZ
VLMODE
SWAPC SWAPB SWAPA
Write
:
Read
:
FMODE3
FIE3
FMODE2
FIE2
FMODE1
FIE1
FMODE0
FIE0
Write
:
Read
0
0
0
0
:
FPINE3
FFLAG3
FPINE2
FFLAG2
FPINE1
FFLAG1
FPINE0
FFLAG0
Write
:
Read
0
0
0
0
:
Write
:
Read
:
QSMP3
QSMP2
QSMP1
QSMP0
Write
:
Read
:
DMP13
DMP33
DMP53
DMP12
DMP32
DMP52
DMP11
DMP31
DMP51
DMP10
DMP30
DMP50
DMP03
DMP23
DMP43
DMP02
DMP22
DMP42
DMP01
DMP21
DMP41
DMP00
DMP20
DMP40
Write
:
Read
:
Write
:
Read
:
Write
:
63
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$020B Reserved
$020C PMFOUTC
$020D PMFOUTB
$020E PMFDTMS
$020F PMFCCTL
$0210 PMFVAL0
$0211 PMFVAL0
$0212 PMFVAL1
$0213 PMFVAL1
$0214 PMFVAL2
$0215 PMFVAL2
Write
:
Read
0
0
0
0
0
0
0
0
:
OUTCTL OUTCTL OUTCTL OUTCTL OUTCTL OUTCTL
5
4
3
2
1
0
Write
:
Read
:
OUT5
DT5
OUT4
DT4
OUT3
DT3
OUT2
DT2
OUT1
DT1
OUT0
DT0
Write
:
Read
:
Write
:
Read
0
:
ISENS
IPOLC
IPOLB
IPOLA
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
1
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Write
:
Read
:
Write
:
Read
:
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
Write
:
Read
:
Write
:
64
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
Bit 15
14
13
12
11
10
9
Bit 8
$0216 PMFVAL3
$0217 PMFVAL3
$0218 PMFVAL4
$0219 PMFVAL4
$021A PMFVAL5
$021B PMFVAL5
$021C Reserved
$021D Reserved
$021E Reserved
$021F Reserved
$0220 PMFENCA
Write
:
Read
:
Bit 7
Bit 15
Bit 7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
Bit 0
Bit 8
Bit 0
Bit 8
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Bit 15
14
13
12
11
10
Write
:
Read
:
Bit 7
6
5
4
3
2
1
Bit 0
Write
:
Read
0
0
0
0
0
0
0
0
:
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
PWMENA
PWMRIEA
LDOKA
65
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
LDFQA
HALFA
PRSCA
PWMRFA
$0221 PMFFQCA
$0222 PMFCNTA
$0223 PMFCNTA
$0224 PMFMODA
$0225 PMFMODA
$0226 PMFDTMA
$0227 PMFDTMA
$0228 PMFENCB
$0229 PMFFQCB
$022A PMFCNTB
$022B PMFCNTB
Write
:
Read
0
:
Bit 14
6
13
5
12
4
11
3
10
2
9
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Write
:
Read
:
Bit 7
1
Write
:
Read
0
:
Bit 14
13
12
11
10
2
9
Write
:
Read
:
Bit 7
6
5
4
3
1
Write
:
Read
0
0
0
0
:
Bit 11
10
9
1
Write
:
Read
:
Bit 7
6
5
4
3
2
Write
:
Read
0
0
0
0
0
:
PW-
MENB
PWM-
RIEB
LDOKB
Write
:
Read
:
LDFQB
HALFB
PRSCB
PWMRFB
Bit 8
Write
:
Read
0
:
Bit 14
6
13
5
12
4
11
3
10
2
9
1
Write
:
Read
:
Write
:
Bit 7
Bit 0
66
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
:
Bit 14
13
12
11
10
9
Bit 8
$022C PMFMODB
$022D PMFMODB
$022E PMFDTMB
$022F PMFDTMB
$0230 PMFENCC
$0231 PMFFQCC
$0232 PMFCNTC
$0233 PMFCNTC
$0234 PMFMODC
$0235 PMFMODC
$0236 PMFDTMC
Write
:
Read
:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Bit 0
Write
:
Read
0
0
0
0
:
Bit 11
10
9
1
Write
:
Read
:
Bit 7
6
5
4
3
2
Write
:
Read
0
0
0
0
0
:
PW-
MENC
PWM-
RIEC
LDOKC
Write
:
Read
:
LDFQC
HALFC
PRSCC
PWMRFC
Bit 8
Write
:
Read
0
:
Bit 14
6
13
5
12
4
11
3
10
2
9
1
9
1
9
Write
:
Read
:
Bit 7
Bit 0
Write
:
Read
0
:
Bit 14
13
12
11
10
2
Bit 8
Write
:
Read
:
Bit 7
6
5
4
3
Bit 0
Write
:
Read
0
0
0
0
:
Write
:
Bit 11
10
Bit 8
67
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0200 - $023F
PMF (Pulse width Modulator with Fault protection)
Addres
Name
s
Bit 7
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0
0
Read
:
6
5
4
3
2
1
$0237 PMFDTMC
Write
:
Read
0
0
0
0
0
0
:
$0238
$0239
Reserved
Reserved
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
$023A Reserved
$023B Reserved
$023C Reserved
$023D Reserved
$023E Reserved
$023F Reserved
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
68
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0240 - $027F
PIM (Port Interface Module)
Read
:
$0240
$0241
$0242
$0243
$0244
$0245
$0246
$0247
$0248
$0249
$024A
$024B
PTT
PTIT
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
Write
:
Read
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
:
Write
:
Read
:
DDRT
RDRT
PERT
PPST
Reserved
Reserved
PTS
DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Write
:
Read
:
Write
:
Read
:
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
Write
:
Read
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
:
PTIS
Write
:
Read
:
DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
DDRS
RDRS
Write
:
Read
:
Write
:
69
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0240 - $027F
PIM (Port Interface Module)
Read
:
PERS7
PPSS7
PERS6
PPSS6
PERS5
PPSS5
PERS4
PPSS4
PERS3
PPSS3
PERS2
PPSS2
PERS1
PPSS1
PERS0
PPSS0
$024C
$024D
$024E
PERS
PPSS
Write
:
Read
:
Write
:
Read
:
WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
WOMS
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
$024F Reserved
Write
:
Read
:
PTM7
PTM6
PTM5
PTM4
PTM3
PTM1
PTIM1
PTM0
PTIM0
$0250
$0251
$0252
$0253
$0254
$0255
$0256
$0257
PTM
PTIM
Write
:
Read
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
:
Write
:
Read
:
DDRM
RDRM
PERM
PPSM
DDRM7 DDRM6 DDRM5 DDRM4 DDRM3
RDRM7 RDRM6 RDRM5 RDRM4 RDRM3
PERM7 PERM6 PERM5 PERM4 PERM3
PPSM7 PPSM6 PPSM5 PPSM4 PPSM3
DDRM1 DDRM0
RDRM1 RDRM0
PERM1 PERM0
PPSM1 PPSM0
Write
:
Read
:
Write
:
Read
:
Write
:
Read
:
Write
:
Read
0
0
0
:
WOMM7 WOMM6 WOMM5 WOMM4
WOMM
Reserved
Write
:
Read
0
0
0
0
0
0
0
:
Write
:
70
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Freescale Semiconductor, Inc.
Device User Guide — 9S12E128DGV1/D V01.04
$0240 - $027F
PIM (Port Interface Module)
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
$0258
$0259
$025A
$025B
$025C
$025D
PTP
PTIP
Write
:
Read
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
:
Write
:
Read
:
DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
DDRP
RDRP
PERP
PPSP
Write
:
Read
:
Write
:
Read
:
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
Write
:
Read
:
PPSP5
0
PPSP4
0
PPSP3
0
PPSP2
0
PPSP1
0
PPSP0
0
Write
:
Read
:
$025E Reserved
$025F Reserved
Write
:
Read
0
0
0
0
0
0
:
Write
:
Read
:
PTQ6
PTQ5
PTQ4
PTQ3
PTQ2
PTQ1
PTQ0
$0260
$0261
$0262
$0263
PTQ
PTIQ
Write
:
Read
PTIQ6
PTIQ5
PTIQ4
PTIQ3
PTIQ2
PTIQ1
PTIQ0
:
Write
:
Read
:
DDRQ
RDRQ
DDRQ6 DDRQ5 DDRQ4 DDRQ3 DDRQ2 DDRQ1 DDRQ0
RDRQ6 RDRQ5 RDRQ4 RDRQ3 RDRQ2 RDRQ1 RDRQ0
Write
:
Read
:
Write
:
71
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$0240 - $027F
PIM (Port Interface Module)
Read
0
:
PERQ
PPSQ
PERQ6 PERQ5 PERQ4 PERQ3 PERQ2 PERQ1 PERQ0
$0264
$0265
$0266
$0267
$0268
$0269
$026A
$026B
$026C
$026D
$026E
Write
:
Read
0
0
0
:
PPSQ6 PPSQ5 PPSQ4 PPSQ3 PPSQ2 PPSQ1 PPSQ0
Write
:
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
Reserved
Reserved
PTU
Write
:
Read
:
Write
:
Read
:
PTU7
PTU6
PTU5
PTU4
PTU3
PTU2
PTU1
PTU0
Write
:
Read
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
:
PTIU
Write
:
Read
:
DDRU
DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
RDRU7 RDRU6 RDRU5 RDRU4 RDRU3 RDRU2 RDRU1 RDRU0
PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0
Write
:
Read
:
RDRU
Write
:
Read
:
PERU
Write
:
Read
:
PPSU
PPSU7
0
PPSU6
0
PPSU5
0
PPSU4
0
PPSU3
PPSU2
PPSU1
PPSU0
Write
:
Read
:
MODRR
MODRR3 MODRR2 MODRR1 MODRR0
Write
:
Read
0
0
0
0
0
0
0
0
:
Write
:
$026F Reserved
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$0240 - $027F
PIM (Port Interface Module)
Read
:
PTAD(H)
PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9
PTAD8
PTAD0
$0270
$0271
$0272
Write
:
Read
:
PTAD(L)
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
Write
:
Read
PTIAD15 PTIAD14 PTIAD13 PTIAD12 PTIAD11 PTIAD10 PTIAD9 PTIAD8
PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0
:
PTIAD(H)
Write
:
Read
:
$0273
$0274
$0275
PTIAD(L)
DDRAD(H)
DDRAD(L)
Write
:
Read:
DDRAD15
DDRAD14
DDRAD13
DDRAD12
DDRAD11
DDRAD10
DDRAD9
DDRAD8
Write:
Read
:
DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
Write
:
Read
:
RDRAD15
RDRAD14
RDRAD13
RDRAD12
RDRAD11
RDRAD10
RDRAD9
RDRAD8
RDRAD(H)
RDRAD(L)
PERAD(H)
$0276
$0277
$0278
Write
:
Read
:
RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Write
:
Read
:
PERAD15
PERAD14
PERAD13
PERAD12
PERAD11
PERAD10
PERAD9
PERAD8
Write
:
Read
:
PERAD(L)
PPSAD(H)
PPSAD(L)
PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0
$0279
$027A
$027B
Write
:
Read:
Write:
Read
:
PPSAD15
PPSAD14
PPSAD13
PPSAD12
PPSAD11
PPSAD10
PPSAD9
PPSAD8
PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0
PIEAD15 PIEAD14 PIEAD13 PIEAD12 PIEAD11 PIEAD10 PIEAD9 PIEAD8
Write
:
Read
:
PIEAD(H)
$027C
Write
:
73
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$0240 - $027F
PIM (Port Interface Module)
Read
:
PIEAD(L)
PIEAD7 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0
$027D
$027E
$027F
Write
:
Read
:
PIFAD(H)
PIFAD(L)
PIFAD15 PIFAD14 PIFAD13 PIFAD12 PIFAD11 PIFAD10 PIFAD9 PIFAD8
PIFAD7 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0
Write
:
Read
:
Write
:
$0280 - $03FF
Reserved space
Addres
Name
s
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Read
:
$0280
Reserved
- $2FF
Write
:
Read
0
0
0
0
0
0
0
0
$0300
:
Write
:
Unimplement
-
ed
$03FF
1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after
reset. The read-only value is a unique part ID for each revision of the chip. Table 1-2 shows the assigned
part ID numbers.
Table 1-2 Assigned Part ID Numbers
1
Device
Mask Set Number
Part ID
$5000
$5102
$5200
$5300
MC9S12E256
MC9S12E128
MC9S12E64
MC9S12E32
TBD
2L15P
2L15P
TBD
NOTES:
1. The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-8: Minor family identifier
Bit 7-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revision
74
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Device User Guide — 9S12E128DGV1/D V01.04
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C
and $001D after reset). Table 1-3 shows the read-only values of these registers. Refer to HCS12 Module
Mapping Control (MMC) Block Guide for further details.
Table 1-3 Memory size registers
Device
Register name
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
MEMSIZ0
MEMSIZ1
Value
$00
$80
$03
$80
$03
$80
$07
$81
MC9S12E32
MC9S12E32
MC9S12E64
MC9S12E64
MC9S12E128
MC9S12E128
MC9S12E256
MC9S12E256
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Device User Guide — 9S12E128DGV1/D V01.04
Section 2 Signal Description
2.1 Device Pinout
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PM3
RXD2/PM4
1
VRH
2
VDDA
TXD2/PM5
3
PAD07/AN07/KWAD07
PAD06/AN06/KWAD06
PAD05/AN05/KWAD05
PAD04/AN04/KWAD04
PAD03/AN03/KWAD03
PAD02/AN02/KWAD02
PAD01/AN01/KWAD01
PAD00/AN00/KWAD00
PA7/ADDR15/DATA15
PA6/ADDR14/DATA14
PA5/ADDR13/DATA13
PA4/ADDR12/DATA12
VSS2
SDA/PM6
SCL/PM7
4
5
FAULT0/PQ0
FAULT1/PQ1
FAULT2/PQ2
FAULT3/PQ3
ADDR0/DATA0/PB0
ADDR1/DATA1/PB1
ADDR2/DATA2/PB2
ADDR3/DATA3/PB3
VDDX
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MC9S12E-Family
VSSX
112LQFP
ADDR4/DATA4/PB4
ADDR5/DATA5/PB5
ADDR6/DATA6/PB6
ADDR7/DATA7/PB7
IS0/PQ4
VDD2
PA3/ADDR11/DATA11
PA2/ADDR10/DATA10
PA1/ADDR9/DATA9
PA0/ADDR8/DATA8
PS7/SS
IS1/PQ5
IS2/PQ6
PS6/SCK
MODC/TAGHI/BKGD
IOC04/PT0
PS5/MOSI
PS4/MISO
IOC05/PT1
PS3/TXD1
IOC06/PT2
PS2/RXD1
IOC07/PT3
PS1/TXD0
IOC14/PT4
PS0/RXD0
Signals shown in Bold are not available on the 80 Pin Package
Figure 2-1 Pin assignments 112 LQFP for MC9S12E-Family
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Device User Guide — 9S12E128DGV1/D V01.04
PM3
RXD2/PM4
TXD2/PM5
SDA/PM6
1
VRH
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2
VDDA
3
PAD07/AN07/KWAD07
PAD06/AN06/KWAD06
PAD05/AN05/KWAD05
PAD04/AN04/KWAD04
PAD03/AN03/KWAD03
PAD02/AN02/KWAD02
PAD01/AN01/KWAD01
PAD00/AN00/KWAD00
VSS2
4
SCL/PM7
5
FAULT0/PQ0
FAULT1/PQ1
FAULT2/PQ2
FAULT3/PQ3
VDDX
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MC9S12E-Family
VSSX
80 QFP
IS0/PQ4
VDD2
IS1/PQ5
PS7/SS
IS2/PQ6
PS6/SCK
MODC/TAGHI/BKGD
IOC04/PT0
IOC05/PT1
IOC06/PT2
IOC07/PT3
IOC14/PT4
PS5/MOSI
PS4/MISO
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
Figure 2-2 Pin assignments in 80 QFP for MC9S12E-Family
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Device User Guide — 9S12E128DGV1/D V01.04
2.2 Signal Properties Summary
Table 2-1 Signal Properties
Internal Pull
Pin Name
Pin Name
Pin Name Power
Resistor
Description
Function 1 Function 2 Function 3 Domain
CTRL Reset State
EXTAL
XTAL
XFC
RESET
BKGD
TEST
—
—
—
—
MODC
VPP
—
—
—
—
TAGHI
—
VDDPLL
VDDPLL
VDDPLL
VDDX
VDDX
NA
NA
NA
NA
None
Up
NA
NA
NA
NA
None
Up
NA
Oscillator pins
PLL loop filter pin
External reset pin
Background debug, mode pin, tag signal high
Test pin only
PERAD/
PPSAD
PAD[15:0]
AN[15:0]
KWAD[15:0}
VDDX
Disabled
Port AD I/O Pins, ATD inputs, keypad Wake-up
ADDR[15:8]/
DATA[15:8]
PA[7:0]
—
VDDX
PUCR
Disabled
Port A I/O pin, multiplexed address/data
ADDR[7:0]/
PB[7:0]
PE7
—
VDDX
VDDX
VDDX
PUCR
Disabled
Port B I/O pin, multiplexed address/data
Port E I/O pin, access, clock select
DATA[7:0]
NOACC
XCLKS
MODB
Input
Input
While RESET is low:
PE6
IPIPE1
Port E I/O pin, pipe status, mode selection
Down
While RESET is low:
Down
PE5
IPIPE0
MODA
VDDX
Port E I/O pin, pipe status, mode selection
Mode Dep1
PE4
ECLK
—
VDDX
PUCR
Port E I/O pin, bus clock output
Mode Dep(1)
PE3
LSTRB
TAGLO
VDDX
PUCR
Port E I/O pin, low strobe, tag signal low
Mode Dep(1)
PE2
PE1
PE0
PK[7]
PK[6]
PK[5:0]
R/W
IRQ
XIRQ
ECS
XCS
—
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
Port E I/O pin, R/W in expanded modes
Port E input, external interrupt pin
Port E input, non-maskable interrupt pin
Port K I/O Pin, Emulation Chip Select
Port K I/O Pin, External Chip Select
Port K I/O Pins, Extended Addresses
Up
Up
Up
Up
Up
—
ROMCTL
—
XADDR[19:14]
—
PERM/
PM7
SCL
—
—
—
—
—
—
—
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Up
Port M I/O Pin, IIC SCL signal
Port M I/O Pin, IIC SDA signal
Port M I/O Pin, SCI2 transmit signal
Port M I/O Pin, SCI2 receive signal
Port M I/O Pin, IIC SDA signal
Port M I/O Pin, DAC1 output
Port M I/O Pin, DAC0 output
Port P I/O Pins, PWM output
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERM/
PPSM
PERP/
PPSP
PM6
SDA
Up
PM5
TXD2
RXD2
—
Up
PM4
Up
PM3
Disabled
Disabled
Disabled
Disabled
PM1
DAO1
DAO0
PW0[5:0]
PM0
PP[5:0]
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Device User Guide — 9S12E128DGV1/D V01.04
Internal Pull
Resistor
CTRL Reset State
Pin Name
Pin Name
Pin Name Power
Description
Function 1 Function 2 Function 3 Domain
PERQ/
Disabled
PPSQ
PERQ/
Disabled
PPSQ
PQ[6:4]
PQ[3:0]
PS7
IS[6:4]
FAULT[3:0]
SS
—
—
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
VDDX
Port Q I/O Pins, IS[6:4] input
Port Q I/O Pins, Fault[3:0] input
Port S I/O Pin, SPI SS signal
Port S I/O Pin, SPI SCK signal
Port S I/O Pin, SPI MOSI signal
Port S I/O Pin, SPI MISO signal
Port S I/O Pin, SCI1 transmit signal
Port S I/O Pin, SCI1 receive signal
Port S I/O Pin, SCI0 transmit signal
Port S I/O Pin, SCI0 receive signal
Port T I/O Pins, timer (TIM1)
PERS/
PPSS
—
Up
PERS/
PPSS
PS6
SCK
—
Up
PERS/
PPSS
PS5
MOSI
—
Up
PERS/
PPSS
PS4
MISO
—
Up
PERS/
PPSS
PS3
TXD1
—
Up
PERS/
PPSS
PS2
RXD1
—
Up
PERS/
PPSS
PS1
TXD0
—
Up
PERS/
PPSS
PS0
RXD0
—
Up
PERT/
Disabled
PPST
PERT/
Disabled
PPST
PERU/
Disabled
PPSU
PERU/
Disabled
PPSU
PT[7:4]
PT[3:0]
PU[7:6]
PU[5:4]
IOC1[7:4]
IOC0[7:4]
—
—
—
Port T I/O Pins, timer (TIM0)
—
Port U I/O Pins
PW1[5:4]
IOC2[7:4]
—
Port U I/O Pins, PWM outputs
Port U I/O Pins, timer (TIM2), PWM outputs
PERU/
Disabled
PPSU
PU[3:0]
PW1[3:0]
NOTES:
1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For example,
in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to the S12
MEBI Block Guide for PEAR register details.
NOTE: Signals shown in bold are not available in the 80 pin package.
NOTE: If the port pins are not bonded out in the chosen package the user should initialize the
registers to be inputs with enabled pull resistance to avoid excess current consumption.
This applies to the following pins:
(80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
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Device User Guide — 9S12E128DGV1/D V01.04
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing The RESET pin includes an internal pull up device.
2.3.3 TEST — Test Pin
The TEST pin is reserved for test and must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See appendix B.4.3.1and the CRG Block Guide for more
detailed information.
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched
to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, when instruction
tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction
word being read into the instruction queue. This pin always has an internal pull up.
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80 pin package
version.
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package
version.
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Device User Guide — 9S12E128DGV1/D V01.04
2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free cycle”. This signal
will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a
crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce
oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If
the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If
the input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is
an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts
oscillator circuit on EXTAL and XTAL.
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Figure 2-3 Colpitts Oscillator Connections (PE7=1)
EXTAL
C
*
DC
C
MCU
XTAL
Crystal or
1
ceramic resonator
C
2
VSSPLL
* Due to the nature of a translated ground Colpitts oscillator a
DC voltage bias is applied to the crystal
.Please contact the crystal manufacturer for crystal DC
Figure 2-4 Pierce Oscillator Connections (PE7=0)
EXTAL
C
1
MCU
RB
Crystal or
ceramic resonator
*
RS
XTAL
C
2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
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Device User Guide — 9S12E128DGV1/D V01.04
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low. PE6 is not available in the 80 pin package version.
2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5
PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active
when RESET is low. PE5 is not available in the 80 pin package version.
2.3.11 PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output
PE4 is a general purpose input or output pin. In Normal Single Chip mode PE4 is configured with an active
pull-up while in reset and immediately out of reset. The pullup can be turned off by clearing PUPEE in the
PUCR register. In all modes except Normal Single Chip Mode, the PE4 pin is initially configured as the
output connection for the internal bus clock(ECLK). ECLK is used as a timing reference and to
demultiplex the address and data in expanded modes. The ECLK frequency is equal to 1/2 the crystal
frequency out of reset. The ECLK output function depends upon the settings of the NECLK bit in the
PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. All clocks,
including the ECLK, are halted when the MCU is in STOP mode. It is possible to configure the MCU to
interface to slow external memory. ECLK can be stretched for such accesses. The PE4 pin is initially
configured as ECLK output with stretch in all expanded modes. Reference the MISC register
(EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the ECLK is available for use
in external select decode logic or as a constant speed clock for use in the external application system.
2.3.12 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 / Low-Byte Strobe (LSTRB)
PE3 can be used as a general-purpose I/O in all modes and is an input with an active pull-up out of reset.
The pullup can be turned off by clearing PUPEE in the PUCR register. PE3 can also be configured as a
Low-Byte Strobe (LSTRB). The LSTRB signal is used in write operations, so external low byte writes will
not be possible until this function is enabled. LSTRB can be enabled by setting the LSTRE bit in the PEAR
register. In Expanded Wide and Emulation Narrow modes, and when BDM tagging is enabled, the LSTRB
function is multiplexed with the TAGLO function. When enabled a logic zero on the TAGLO pin at the
falling edge of ECLK will tag the low byte of an instruction word being read into the instruction queue.
PE3 is not available in the 80 pin package version.
2.3.13 PE2 / R/W — Port E I/O Pin 2 / Read/Write
PE2 can be used as a general-purpose I/O in all modes and is configured an input with an active pull-up
out of reset. The pullup can be turned off by clearing PUPEE in the PUCR register. If the read/write
function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes
will not be possible until the read/write function is enabled. The PE2 pin is not available in the 80 pin
package version.
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2.3.14 PE1 / IRQ — Port E input Pin 1 / Maskable Interrupt Pin
PE1 is always an input and can always be read. The PE1 pin is also the IRQ input used for requesting an
asynchronous interrupt to the MCU. During reset, the I bit in the condition code register (CCR) is set and
any IRQ interrupt is masked until software enables it by clearing the I bit. The IRQ is software
programmable to either falling edge-sensitive triggering or level-sensitive triggering based on the setting
of the IRQE bit in the IRQCR register. The IRQ is always enabled and configured to level-sensitive
triggering out of reset. It can be disabled by clearing IRQEN bit in the IRQCR register. There is an active
pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing
PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ — Port E input Pin 0 / Non Maskable Interrupt Pin
PE0 is always an input and can always be read. The PE0 pin is also the XIRQ input for requesting a
nonmaskable asynchronous interrupt to the MCU. During reset, the X bit in the condition code register
(CCR) is set and any XIRQ interrupt is masked until MCU software enables it by clearing the X bit.
Because the XIRQ input is level sensitive triggered, it can be connected to a multiple-source wired-OR
network. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPEE in the PUCR register.
2.3.16 PK7 / ECS / ROMCTL — Port K I/O Pin 7
PK7 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as the emulation chip select output (ECS). In expanded
modes the PK7 pin can be used to determine the reset state of the ROMON bit in the MISC register. At
the rising edge of RESET, the state of the PK7 pin is latched to the ROMON bit. There is an active pull-up
on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPKE
in the PUCR register. Refer to the HCS12 MEBI Block Guide for further details. PK7 is not available in
the 80 pin package version.
2.3.17 PK6 / XCS — Port K I/O Pin 6
PK6 is a general purpose input or output pin. During MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, this pin is used as an external chip select signal for most external
accesses that are not selected by ECS. There is an active pull-up on this pin while in reset and immediately
out of reset. The pullup can be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12
MEBI Block Guide for further details. PK6 is not available in the 80 pin package version.
2.3.18 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0]
PK[5:0] are general purpose input or output pins. In MCU expanded modes of operation, when the EMK
bit in the MODE register is set to 1, PK[5:0] provide the expanded address XADDR[19:14] for the external
bus. There are active pull-ups on PK[5:0] pins while in reset and immediately out of reset. The pullup can
be turned off by clearing PUPKE in the PUCR register. Refer to the HCS12 MEBI Block Guide for further
details. PK[5:0] are not available in the 80 pin package version.
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2.3.19 PAD[15:0] / AN[15:0] / KWAD[15:0] — Port AD I/O Pins [15:0]
PAD[15:0] are the analog inputs for the analog to digital converter (ADC). They can also be configured
as general purpose digital input or output pin. When enabled as digital inputs or outputs, the PAD[15:0]
can also be configured as Keypad Wake-up pins (KWU) and generate interrupts causing the MCU to exit
STOP or WAIT mode. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the
ATD_10B16C Block Guide for information about pin configurations.
2.3.20 PM7 / SCL — Port M I/O Pin 7
PM7 is a general purpose input or output pin. When the IIC module is enabled it becomes the serial clock
line (SCL) for the IIC module (IIC). While in reset and immediately out of reset the PM7 pin is configured
as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and
the IIC Block Guide for information about pin configurations.
2.3.21 PM6 / SDA — Port M I/O Pin 6
PM6 is a general purpose input or output pin. When the IIC module is enabled it becomes the Serial Data
Line (SDL) for the IIC module (IIC). While in reset and immediately out of reset the PM6 pin is configured
as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and
the IIC Block Guide for information about pin configurations.
2.3.22 PM5 / TXD2 — Port M I/O Pin 5
PM5 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) transmitter
is enabled the PM5 pin is configured as the transmit pin TXD2 of SCI2. While in reset and immediately
out of reset the PM5 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.23 PM4 / RXD2 — Port M I/O Pin 4
PM4 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) receiver is
enabled the PM4 pin is configured as the receive pin RXD2 of SCI2. While in reset and immediately out
of reset the PM4 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.24 PM3 — Port M I/O Pin 3
PM3 is a general purpose input or output pin. While in reset and immediately out of reset the PM3 pin is
configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block
Guide for information about pin configurations.
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2.3.25 PM1 / DAO1 — Port M I/O Pin 1
PM1 is a general purpose input or output pin. When the Digital to Analog module 1 (DAC1) is enabled
the PM1 pin is configured as the analog output DA01 of DAC1. While in reset and immediately out of
reset the PM1 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9E128 Block Guide and the DAC_8B1C Block Guide for information about pin configurations.
2.3.26 PM0 / DAO2 — Port M I/O Pin 0
PM0 is a general purpose input or output pin. When the Digital to Analog module 2 (DAC2) is enabled
the PM0 pin is configured as the analog output DA02 of DAC2. While in reset and immediately out of
reset the PM0 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9E128 Block Guide and the DAC_8B1C Block Guide for information about pin configurations.
2.3.27 PP[5:0] / PW0[5:0] — Port P I/O Pins [5:0]
PP[5:0] are general purpose input or output pins. When the Pulse width Modulator with Fault protection
(PMF) is enabled the PP[5:0] output pins, as a whole or as pairs, can be configured as PW0[5:0] outputs.
While in reset and immediately out of reset the PP[5:0] pins are configured as a high impedance input pins.
Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PMF_15B6C Block Guide
for information about pin configurations.
2.3.28 PQ[6:4] / IS[2:0] — Port Q I/O Pins [6:4]
PQ[6:4] are general purpose input or output pins. When enabled in the Pulse width Modulator with Fault
protection module (PMF), the PQ[6:4] pins become the current status input pins, IS[2:0], for top/bottom
pulse width correction. While in reset and immediately out of reset PP[5:0] pins are configured as a high
impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the
PMF_15B6C Block Guide for information about pin configurations.
2.3.29 PQ[3:0] / FAULT[3:0] — Port Q I/O Pins [3:0]
PQ[3:0] are general purpose input or output pins. When enabled in the Pulse width Modulator with Fault
protection module (PMF), the PQ[3:0] pins become the Fault protection inputs pins, FAULT[3:0], of the
PMF. While in reset and immediately out of reset the PQ[3:0] pins are configured as a high impedance
input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the PMF_15B6C
Block Guide for information about pin configurations.
2.3.30 PS7 / SS — Port S I/O Pin 7
PS7 is a general purpose input or output. When the Serial Peripheral Interface (SPI) is enabled PS7
becomes the slave select pin SS. While in reset and immediately out of reset the PS7 pin is configured as
a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and the
SPI Block Guide for information about pin configurations.
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2.3.31 PS6 / SCK — Port S I/O Pin 6
PS6 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS6
becomes the serial clock pin, SCK. While in reset and immediately out of reset the PS6 pin is configured
as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide and
the SPI Block Guide for information about pin configurations.
2.3.32 PS5 / MOSI — Port S I/O Pin 5
PS5 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS5 is
the master output (during master mode) or slave input (during slave mode) pin. While in reset and
immediately out of reset the PS5 pin is configured as a high impedance input pin Consult the Port
Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin
configurations.
2.3.33 PS4 / MISO — Port S I/O Pin 4
PS4 is a general purpose input or output pin. When the Serial Peripheral Interface (SPI) is enabled PS4 is
the master input (during master mode) or slave output (during slave mode) pin. While in reset and
immediately out of reset the PS4 pin is configured as a high impedance input pin. Consult the Port
Integration Module (PIM) PIM_9E128 Block Guide and the SPI Block Guide for information about pin
configurations.
2.3.34 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general purpose input or output. When the Serial Communications Interface 1 (SCI1) transmitter
is enabled the PS3 pin is configured as the transmit pin, TXD1, of SCI1. While in reset and immediately
out of reset the PS3 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.35 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output. When the Serial Communications Interface 1 (SCI1) receiver is
enabled the PS2 pin is configured as the receive pin RXD1 of SCI1. While in reset and immediately out
of reset the PS2 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.36 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) transmitter
is enabled the PS1 pin is configured as the transmit pin, TXD0, of SCI0. While in reset and immediately
out of reset the PS1 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
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2.3.37 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) receiver is
enabled the PS0 pin is configured as the receive pin RXD0 of SCI0. While in reset and immediately out
of reset the PS0 pin is configured as a high impedance input pin. Consult the Port Integration Module
(PIM) PIM_9E128 Block Guide and the SCI Block Guide for information about pin configurations.
2.3.38 PT[7:4] / IOC1[7:4]— Port T I/O Pins [7:4]
PT[7:4] are general purpose input or output pins. When the Timer system 1 (TIM1) is enabled they can
also be configured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and
immediately out of reset the PT[7:4] pins are configured as a high impedance input pins. Consult the Port
Integration Module (PIM) PIM_9E128 Block Guide and the TIM_16B4C Block Guide for information
about pin configurations.
2.3.39 PT[3:0] / IOC0[7:4]— Port T I/O Pins [3:0]
PT[3:0] are general purpose input or output pins. When the Timer system 0 (TIM0) is enabled they can
also be configured as the TIM0 input capture or output compare pins IOC0[7-4]. While in reset and
immediately out of reset the PT[3:0] pins are configured as a high impedance input pins. Consult the Port
Integration Module (PIM) PIM_9E128 Block Guide and the TIM_16B4C Block Guide for information
about pin configurations.
2.3.40 PU[7:6] — Port U I/O Pins [7:6]
PU[7:6] are general purpose input or output pins. While in reset and immediately out of reset the PU[7:6]
pins are configured as a high impedance input pins. Consult the Port Integration Module (PIM)
PIM_9E128 for information about pin configurations. PU[7:6] are not available in the 80 pin package
version.
2.3.41 PU[5:4] / PW1[5:4] — Port U I/O Pins [5:4]
PU[5:4] are general purpose input or output pins. When the Pulse Width Modulator (PWM) is enabled the
PU[5:4] output pins, individually or as a pair, can be configured as PW1[5:4] outputs. While in reset and
immediately out of reset the PU[5:4] pins are configured as a high impedance input pins. Consult the Port
Integration Module (PIM) PIM_9E128 Block Guide and the PWM_8B6C Block Guide for information
about pin configurations. PU[5:4] are not available in the 80 pin package version.
2.3.42 PU[3:0] / IOC2[7:4]/PW1[3:0] — Port U I/O Pins [3:0]
PU[3:0] are general purpose input or output pins. When the Timer system 2 (TIM2) is enabled they can
also be configured as the TIM2 input capture or output compare pins IOC2[7-4]. When the Pulse Width
Modulator (PWM) is enabled the PU[3:0] output pins, individually or as a pair, can be configured as
PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM
function is selected. While in reset and immediately out of reset the PU[3:0] pins are configured as a high
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impedance input pins. Consult the Port Integration Module (PIM) PIM_9E128 Block Guide, TIM_16B4C
Block Guide, and the PWM_8B6C Block Guide for information about pin configurations.
2.4 Power Supply Pins
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded.
2.4.2 VDDR, VSSR — Power Supply Pins for I/O Drivers & for Internal Voltage
Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Bypass requirements
depend on how heavily the MCU pins are loaded.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Power Supply Pins for Internal Logic
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal
voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned
off, if VDDR is tied to ground.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to
digital converter.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by
the internal voltage regulator.
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Table 2-2 MC9S12E-Family Power and Ground Connection Summary
Nominal
Mnemonic
Description
Voltage
VDD1
VDD2
VSS1
VSS2
2.5 V
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and
bypass the internal voltage regulator.
0V
VDDR
VSSR
VDDX
VSSX
VDDA
3.3/5.0 V
0 V
3.3/5.0 V
0 V
External power and ground, supply to internal voltage regulator.
To disable voltage regulator attach VDDR to VSSR
.
External power and ground, supply to pin drivers.
3.3/5.0 V Operating voltage and ground for the analog-to-digital converter, the
reference for the internal voltage regulator and the digital-to-analog
converters, allows the supply voltage to the A/D to be bypassed
independently.
VSSA
0 V
VRH
VRL
3.3/5.0 V Reference voltage high for the ATD converter, and DAC.
0 V
Reference voltage low for the ATD converter.
VDDPLL
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
VSSPLL
0 V
NOTE: All VSS pins must be connected together in the application. Because fast signal
transitions place high, short-duration current demands on the power supply, use
bypass capacitors with high-frequency characteristics and place them as close to
the MCU as possible. Bypass requirements depend on MCU pin load.
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Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
HCS12 CORE
BDM
CPU
Core Clock
MEBI
INT
MMC
DBG
Flash
RAM
ATD
DAC
IIC
PIM
EXTAL
XTAL
PMF
Bus Clock
OSC
CRG
PWM
Oscillator Clock
SCI0, SCI1, SCI2
SPI
TIM0, TIM1, TIM2
VREG
Figure 3-1 Clock Connections
Table 3-1Clock Selection Based on PE7
PE7 = XCLKS
Description
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
1
0
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Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12E-Family. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
PE5 =
PK7 =
ROMON
Mode Description
MODB
MODA
ROMCTL
Bit
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
0
0
0
X
1
0
1
X
0
1
X
0
1
1
0
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
1
1
1
1
0
1
X
1
0
1
0
1
Normal Expanded Wide, BDM allowed
For further explanation on the modes refer to the HCS12 MEBI Block Guide.
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
Description
Colpitts Oscillator selected
Pierce Oscillator/external clock selected
1
0
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4.3 Security
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
•
•
•
Protection of the contents of FLASH,
Operation in single-chip mode,
Operation from external memory with internal FLASH disabled.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the user downloads a key through the SCI which allows access to a programming routine that
updates parameters.
4.3.1 Securing the Microcontroller
Once the user has programmed the FLASH, the part can be secured by programming the security bits
located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part
and through powering down the part.
The security byte resides in a portion of the Flash array.
Check the Flash Block Guide for more details on the security configuration.
4.3.2 Operation of the Secured Microcontroller
4.3.2.1 Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
4.3.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be
blocked.
4.3.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an
external program in expanded mode.
Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a
program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase
and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but
the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to
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an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.
4.4 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator (CRG) Block Guide.
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active.
For further power consumption the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
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Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. System resets can be generated through external control of the RESET pin, through the clock
and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator
module. Refer to the CRG and VREG Block Guides for detailed information on reset generation.
5.2 Vectors
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
CCR
HPRIO Value
to Elevate
Vector Address
Interrupt Source
Local Enable
Mask
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register None
to determine reset source)
$FFFE, $FFFF
None
–
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFE8 to $FFEF
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
None
None
None
None
X-Bit
I-Bit
COPCTL (CME, FCME)
COP rate select
None
–
–
–
–
–
SWI
XIRQ
IRQ
None
None
INTCR (IRQEN)
CRGINT (RTIE)
$F2
$F0
Real Time Interrupt
I-Bit
Reserved
Standard Timer 0 channel 4
Standard Timer 0 channel 5
Standard Timer 0 channel 6
Standard Timer 0 channel 7
Standard Timer overflow
Pulse accumulator overflow
Pulse accumulator input edge
SPI
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
TIE (C4I)
TIE (C5I)
TIE (C6I)
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
TIE (C7I)
TSCR2 (TOI)
PACTL(PAOVI)
PACTL (PAI)
SPICR1 (SPIE, SPTIE)
SCICR2
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
SCI0
SCI1
SCI2
I-Bit
I-Bit
I-Bit
$D6
$D4
$D2
(TIE, TCIE, RIE, ILIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
SCICR2
(TIE, TCIE, RIE, ILIE)
$FFD0, $FFD1
$FFCE, $FFCF
$FFC8 to $FFCD
$FFC6, $FFC7
$FFC4, $FFC5
ATD
Port AD (KWU)
I-Bit
I-Bit
Reserved
I-Bit
I-Bit
ATDCTL2 (ASCIE)
PTADIF (PTADIE)
$D0
$CE
CRG PLL lock
CRG Self Clock Mode
PLLCR (LOCKIE)
PLLCR (SCMIE)
$C6
$C4
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$FFC2, $FFC3
$FFC0, $FFC1
$FFBA to $FFBF
$FFB8, $FFB9
$FFB6, $FFB7
$FFB4, $FFB5
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
Reserved
I-Bit
IIC Bus
IBCR (IBIE)
$C0
Reserved
I-Bit
I-Bit
FLASH
FCNFG (CCIE, CBEIE)
TIE (C4I)
$B8
$B6
$B4
$B2
$B0
$AE
Standard Timer 1 channel 4
Standard Timer 1 channel 5
Standard Timer 1 channel 6
Standard Timer 1 channel 7
Standard Timer 1 overflow
I-Bit
I-Bit
I-Bit
I-Bit
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOI)
Standard Timer 1 Pulse accumulator
$FFAC, $FFAD
$FFAA, $FFAB
I-Bit
I-Bit
PACTL (PAOVI)
PACTL (PAI)
$AC
$AA
overflow
Standard Timer 1 Pulse accumulator
input edge
$FFA8, $FFA9
$FFA6, $FFA7
$FFA4, $FFA5
$FFA2, $FFA3
$FFA0, $FFA1
$FF9E, $FF9F
Reserved
I-Bit
I-Bit
I-Bit
I-Bit
Standard Timer 2 channel 4
Standard Timer 2 channel 5
Standard Timer 2 channel 6
Standard Timer 2 channel 7
Standard Timer overflow
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
TSCR2 (TOI)
$A6
$A4
$A2
$A0
$9E
I-Bit
Standard Timer 2 Pulse accumulator
$FF9C, $FF9D
$FF9A, $FF9B
I-Bit
I-Bit
PACTL (PAOVI)
PACTL (PAI)
$9C
$9A
overflow
Standard Timer 2 Pulse accumulator
input edge
$FF98, $FF99
$FF96, $FF97
$FF94, $FF95
$FF92, $FF93
$FF90, $FF91
$FF8E, $FF8F
$FF8C, $FF8D
$FF8A, $FF8B
$FF88, $FF89
$FF80 to $FF87
PMF Generator A Reload
PMF Generator B Reload
PMF Generator C Reload
PMF Fault 0
I-Bit
I-Bit
PMFENCA (PWMRIEA)
PMFENCB (PWMRIEB)
$98
$96
$94
$92
$90
$8E
$8C
$8A
$88
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
PMFENCC (PWMRIEC)
PMFFCTL (FIE0)
PMFFCTL (FIE1)
PMFFCTL (FIE2)
PMFFCTL (FIE3)
CTRL0 (LVIE)
PMF Fault 1
PMF Fault 2
PMF Fault 3
VREG LVI
PWM Emergency Shutdown
PWMSDN(PWMIE)
Reserved
5.3 Resets
Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a
system reset are summarized in Table 5-2.
Table 5-2 Reset Summary
Reset
Power-on Reset
External Reset
Low Voltage Reset
Clock Monitor Reset
Priority
Source
CRG Module
RESET pin
VREG Module
CRG Module
Vector
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
1
1
1
2
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Table 5-2 Reset Summary
COP Watchdog Reset
3
CRG Module
$FFFA, $FFFB
5.3.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block Guides for register reset states. Refer to the HCS12 MEBI Block Guide for mode
dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.
Refer to Table 1-1 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information about the Central Processing Unit.
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods.
So 1 cycle is equivalent to 1 Bus Clock period.
6.2 HCS12 Background Debug Module (BDM) Block Description
Consult the HCS12 BDM Block Guide for information about the Background Debug Module.
When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.
6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
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6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module.
Note that V04 of the ATD has an external trigger (ETRIG) function which is tied off and not available for
use.
Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications. 3F.
8.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 9 Digital to Analog Converter (DAC) Block
Description
There are two digital to analog converter modules (DAC0, DAC1). Consult the DAC Block Guide for
information about the DAC Module.
Section 10 Flash EEPROM Block Description
Consult the FTS32K Block Guide for information about the flash module for the MC9S12E32.
Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E64.
Consult the FTS128K1 Block Guide for information about the flash module for the MC9S12E128.
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Consult the FTS256K2 Block Guide for information about the flash module for the MC9S12E256.
The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into
the flash memory of this device during manufacture. This LRAE program will provide greater
programming flexibility to the end users by allowing the device to be programmed directly using SCI after
it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not
required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its
implementation, please see the S12 LREA Application Note (AN2546/D) .
It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE
programmed in the Flash . Exact details of the changeover (ie blank to programmed) for each product will
be communicated in advance via GPCN and will be traceable by the customer via datecode marking on
the device.
Please contact Motorola SPS Sales if you have any additional questions.
Section 11 IIC Block Description
Consult the IIC Block Guide for information about the IIC Module.
Section 12 Oscillator (OSC) Block Description
Consult the OSC Block Guide for information about the Oscillator module.
Section 13 Port Integration Module (PIM) Block Description
Consult the PIM_9E128 Block Guide for information about the Port Integration Module.
Section 14 Pulse width Modulator with Fault protection
(PMF) Block Description
Consult the PMF_15B6C Block Guide for information about the Pulse width Modulator with Fault
protection Module.
Section 15 Pulse Width Modulator (PWM) Block Description
Consult the PWM_8B6C Block Guide for information about the Pulse Width Modulator Module.
Section 16 Serial Communications Interface (SCI) Block
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Description
There are three Serial Communications Interface modules (SCI0, SCI1, SCI2). Consult the SCI Block
Guide for information about the Serial Communications Interface module.
Section 17 Serial Peripheral Interface (SPI) Block
Description
Consult the SPI Block Guide for information about the Serial Peripheral Interface module.
Section 18 Timer (TIM) Block Description
There are three timer modules (TIM0, TIM1, TIM2). Consult the TIM_16B4C Block Guide for
information about the Timer module.
Section 19 Voltage Regulator (VREG) Block Description
Consult the VREG Block Guide for information about the dual output linear voltage regulator.
19.1 VREGEN
On the MC9S12E-Family the regulator enable signal (VREGEN) is not available externally and is
connected internally to VDDR.
19.2 VDD1, VDD2, VSS1, VSS2
In both the 112 pin LQFP and the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V
domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1
and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally. This
allows systems to employ better supply routing and further decoupling.
Section 20 Printed Circuit Board Layout Proposals
The Printed Circuit Board (PCB) must be carefully laid out to ensure proper operation of the voltage
regulator as well as the MCU itself. The following rules must be observed:
•
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
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•
•
•
•
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
VSSPLL must be directly connected to VSSR.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
•
•
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
Table 20-1 Recommended decoupling capacitor choice
Component
Purpose
VDD1 filter cap
VDD2 filter cap (80 QFP only)
VDDA filter cap
VDDR filter cap
VDDPLL filter cap
VDDX filter cap
OSC load cap
Type
Value
100 - 220nF
100 - 220nF
100nF
>=100nF
100nF
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
R1
Q1
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
>=100nF
OSC load cap
PLL loop filter cap
PLL loop filter cap
DC cutoff cap
PLL loop filter res
Quartz
See PLL specification chapter
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Figure 20-1 Recommended PCB Layout (112 LQFP)
NOTE: Oscillator in Colpitts mode.
VSSA
C3
VSS1
VDDA
VDDX
C6
VSS2
C2
VDD2
VSSX
VSSR
VDDR
Q1
VSSPLL
VDDPLL
R1
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Figure 20-2 Recommended PCB Layout (80 QFP)
NOTE: Oscillator in Colpitts mode.
VSSA
C3
VSS1
VDDA
VSS2
VDDX
VSSX
C2
C6
VDD2
VSSR
VDDR
Q1
VSSPLL
R1
VDDPLL
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Appendix A Electrical Characteristics
A.1 General
NOTE: The electrical characteristics given in this section are preliminary and should be
used as a guide only. Values cannot be guaranteed by Motorola and are subject to
change without notice.
NOTE:
The part is specified and tested over the 5V and 3.3V ranges. For the intermediate
range, generally the electrical specifications for the 3.3V range apply, but the part
is not tested in production test in the intermediate range.
This supplement contains the most accurate electrical information for the MC9S12E-Family
microcontroller available at the time of publication. The information should be considered
PRELIMINARY and is subject to change.
This introduction is intended to give an overview on several common topics like power supply, current
injection etc.
A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate.
NOTE: This classification will be added at a later release of the specification
P: Those parameters are guaranteed during production testing on each individual device.
C: Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations. They are regularly verified by production monitors.
T: Those parameters are achieved by design characterization on a small sample size from typical devices.
All values shown in the typical column are within this category.
D: Those parameters are derived mainly from simulations.
A.1.2 Power Supply
The MC9S12E-Family utilizes several pins to supply power to the I/O ports, A/D converter, oscillator,
PLL and internal logic.
The VDDA, VSSA pair supplies the A/D converter and D/A converter.
The VDDX, VSSX pair supplies the I/O pins
The VDDR, VSSR pair supplies the internal voltage regulator.
VDD1, VSS1, VDD2 and VSS2 are the supply pins for the internal logic.
VDDPLL, VSSPLL supply the oscillator and the PLL.
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VSS1 and VSS2 are internally connected by metal.
VDD1 and VDD2 are internally connected by metal.
VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD
protection.
NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5
is used for either VSSA, VSSR and VSSX unless otherwise noted.
IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR
pins.
VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and
VSSPLL.
IDD is used for the sum of the currents flowing into VDD1 and VDD2.
A.1.3 Pins
There are four groups of functional pins.
A.1.3.1 3.3V/5V I/O pins
Those I/O pins have a nominal level of 3.3V or 5V depending on the application operating point. This
group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs.The
internal structure of all those pins is identical, however some of the functionality may be disabled.
A.1.3.2 Analog Reference
This group of pins is comprised of the VRH and VRL pins.
A.1.3.3 Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied
by VDDPLL.
A.1.3.4 TEST
This pin is used for production testing only.
A.1.4 Current Injection
Power supply must maintain regulation within operating V
or V range during instantaneous and
DD
DD5
operating maximum current conditions. If positive injection current (V > V
) is greater than I
, the
DD5
in
DD5
injection current may flow out of VDD5 and could result in external power supply going out of regulation.
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
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A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V
or V
).
SS5
DD5
Table A-1 Absolute Maximum Ratings
Num
Rating
Symbol
VDD5
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
6.5
3.0
3.0
0.3
0.3
6.5
6.5
3.0
10.0
Unit
V
1
2
3
4
5
6
7
8
9
I/O, Regulator and Analog Supply Voltage
Internal Logic Supply Voltage1
VDD
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage difference VDDX to VDDR and VDDA
Voltage difference VSSX to VSSR and VSSA
Digital I/O Input Voltage
V
VDDX
∆
V
VSSX
VIN
VRH, VRL
VILV
V
Analog Reference
V
XFC, EXTAL, XTAL inputs
TEST input
V
VTEST
V
Instantaneous Maximum Current
ID
10
11
12
-25
-25
+25
+25
0
mA
mA
mA
Single pin limit for all digital I/O pins 2
Instantaneous Maximum Current
IDL
Single pin limit for XFC, EXTAL, XTAL3
Instantaneous Maximum Current
Single pin limit for TEST4
IDT
TA
-0.25
13
14
Operating Temperature Range (packaged)
Operating Temperature Range (junction)
Storage Temperature Range
– 40
– 40
– 65
125
140
155
°C
°C
°C
TJ
Tstg
15
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
2. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA
3. These pins are internally clamped to VSSPLL and VDDPLL
.
4. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
1500
100
Unit
Ohm
pF
Series Resistance
R1
C
Storage Capacitance
Human Body
Number of Pulse per pin
positive
-
3
3
-
negative
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Machine
Latch-up
Number of Pulse per pin
positive
-
-
3
3
negative
Minimum input voltage limit
Maximum input voltage limit
-2.5
7.5
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num
C
C
C
C
Rating
Human Body Model (HBM)
Symbol
VHBM
Min
2000
200
Max
Unit
V
1
2
3
-
-
-
VMM
Machine Model (MM)
V
VCDM
Charge Device Model (CDM)
500
V
Latch-up Current at 125°C
positive
ILAT
4
5
C
C
+100
-100
-
-
mA
mA
negative
Latch-up Current at 27°C
positive
negative
ILAT
+200
-200
A.1.7 Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions
apply to all the following data.
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NOTE: Instead of specifying ambient temperature all parameters are specified for the more
meaningful silicon junction temperature. For power dissipation calculations refer
to Section A.1.8 Power Dissipation and Thermal Characteristics.
Table A-4 Operating Conditions
Rating
Symbol
VDD5
Min
3.135
2.35
2.35
-0.1
Typ
Max
5.5
Unit
V
I/O, Regulator and Analog Supply Voltage
3.3/5
Internal Logic Supply Voltage1
VDD
2.5
2.5
0
2.75
2.75
0.1
V
PLL Supply Voltage (1)
VDDPLL
V
∆
Voltage Difference VDDX to VDDA
Voltage Difference VSSX to VSSR and VSSA
Oscillator
V
VDDX
∆
-0.1
0
0.1
V
VSSX
fosc
fbus
TJ
0.5
-
16
MHz
MHz
Bus Frequency2
0.25
-
25
Operating Junction Temperature Range
-40
-
140
°C
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The
given operating range applies when this regulator is disabled and the device is powered from an external source.
2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper opera-
tion.
A.1.8 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded. The average chip-junction temperature (T ) in °C can be
J
obtained from:
T = T + (P • Θ
)
J
A
D
JA
T = Junction Temperature, [°C]
J
T
= Ambient Temperature, [°C]
A
D
P
= Total Chip Power Dissipation, [W]
= Package Thermal Resistance, [°C/W]
Θ
JA
The total power dissipation can be calculated from:
= P
P
+ P
D
INT
IO
P
= Chip Internal Power Dissipation, [W]
INT
Two cases with internal voltage regulator enabled and disabled must be considered:
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1. Internal Voltage Regulator disabled
P
= I
⋅ V
+ I
⋅ V
+ I
⋅ V
INT
DD DD DDPLL DDPLL DDA DDA
2
P
=
R
⋅ I
IO
DSON IO
∑
i
Which is the sum of all output currents on I/O ports associated with VDDX and VDDM.
For R is valid:
DSON
V
OL
R
= ------------ ;for o utpu ts dri ven low
DSON
I
OL
respectively
V
– V
DD5
OH
R
= ----------------------------------- ;f or out put s dr iv en hi gh
DSON
I
OH
2. Internal voltage regulator enabled
P
= I
⋅ V
+ I
⋅ V
INT
DDR DDR DDA DDA
I
is the current shown in Table A-8 and not the overall current flowing into VDDR, which
DDR
additionally contains the current flowing into the external loads with output high.
2
P
=
R
⋅ I
DSON IO
IO
∑
i
Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.
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1
Table A-5 Thermal Package Characteristics
Num
C
Rating
Symbol
Min
Typ
Max
Unit
Thermal Resistance LQFP112, single sided PCB2
°oC/W
θJA
1
T
–
–
54
Thermal Resistance LQFP112, double sided PCB
with 2 internal planes3
oC/W
θJA
2
T
–
–
41
°oC/W
oC/W
oC/W
°oC/W
θJB
θJC
ΨJT
θJA
3
4
5
6
T
T
T
T
Junction to Board LQFP112
–
–
–
–
–
–
–
–
31
11
2
Junction to Case LQFP112
Junction to Package Top LQFP112
Thermal Resistance QFP 80, single sided PCB
51
Thermal Resistance QFP 80, double sided PCB with
2 internal planes
oC/W
θJA
7
T
–
–
41
°oC/W
oC/W
oC/W
θJB
θJC
ΨJT
8
T
T
T
Junction to Board QFP80
Junction to Case QFP80
–
–
–
–
–
–
27
14
3
9
10
Junction to Package Top QFP80
NOTES:
1. The values for thermal resistance are achieved by package simulations
2. PC Board according to EIA/JEDEC Standard 51-3
3. PC Board according to EIA/JEDEC Standard 51-7
A.1.9 I/O Characteristics
This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable,
e.g. not all pins feature pull up/down resistances.
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Table A-6 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
P
T
Rating
Symbol
Min
Typ
Max
-
Unit
V
VIH
0.65*VDD5
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Input Hysteresis
-
1
VIH
VIL
-
-
VDD5 + 0.3
0.35*VDD5
V
P
T
-
-
-
V
2
3
VIL
VSS5 - 0.3
-
V
VHYS
C
250
mV
Input Leakage Current (pins in high ohmic input
mode)1
Iin
4
5
P
C
–2.5
-
-
2.5
-
µA
Vin = VDD5 or VSS5
Output High Voltage (pins in output mode)
VOH
VDD5 – 0.8
V
Partial Drive I
= –2mA
OH
Output High Voltage (pins in output mode)
Full Drive IOH = –10mA
VOH
VOL
VOL
VDD5 – 0.8
6
7
P
C
-
-
-
V
V
Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
-
-
0.8
Output Low Voltage (pins in output mode)
8
9
P
P
C
P
-
-
-
-
0.8
-130
-
V
Full Drive I
= +10mA
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
-
-10
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
10
11
Internal Pull Down Device Current,
tested at VIH Min.
130
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
12
13
C
D
10
-
-
-
µA
Input Capacitance
6
pF
Injection current2
IICS
IICP
14
T
-2.5
-25
-
2.5
25
mA
Single Pin limit
Total Device Limit. Sum of all injected currents
Port AD Interrupt Input Pulse filtered3
Port AD Interrupt Input Pulse passed(3)
tPIGN
tPVAL
15
P
P
3
µs
µs
16
10
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8°C to 12°C in the temperature range from 50°C to 125°C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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Table A-7 Preliminary 3.3V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
P
T
Rating
Symbol
Min
Typ
Max
-
Unit
V
VIH
0.65*VDD5
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Input Hysteresis
-
1
VIH
VIL
-
-
VDD5 + 0.3
0.35*VDD5
V
P
T
-
-
-
V
2
3
VIL
VSS5 - 0.3
-
V
VHYS
C
250
mV
Input Leakage Current (pins in high ohmic input
mode)1
Iin
4
P
–2.5
-
2.5
µA
Vin = VDD5 or VSS5
Output High Voltage (pins in output mode)
VOH
VOH
VOL
VOL
VDD5 – 0.4
5
6
C
P
C
P
P
C
P
-
-
-
-
-
-
-
-
V
V
Partial Drive I
= –0.75mA
OH
Output High Voltage (pins in output mode)
Full Drive I = –4.5mA
VDD5 – 0.4
-
OH
Output Low Voltage (pins in output mode)
Partial Drive I = +0.9mA
7
-
-
0.4
0.4
–60
-
V
OL
Output Low Voltage (pins in output mode)
Full Drive I = +5.5mA
8
V
OL
Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
9
-
µA
µA
µA
Internal Pull Up Device Current,
tested at VIH Min.
10
11
-6
-
Internal Pull Down Device Current,
tested at VIH Min.
60
Internal Pull Down Device Current,
tested at VIL Max.
IPDL
Cin
12
13
C
D
6
-
-
-
µA
Input Capacitance
6
pF
Injection current2
IICS
IICP
14
T
-2.5
-25
-
2.5
25
mA
Single Pin limit
Total Device Limit. Sum of all injected currents
Port AD Interrupt Input Pulse filtered3
Port AD Interrupt Input Pulse passed(3)
tPIGN
tPVAL
15
P
P
3
µs
µs
16
10
NOTES:
1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for
each 8°C to 12°C in the temperature range from 50°C to 125°C.
2. Refer to Section A.1.4 Current Injection, for more details
3. Parameter only applies in STOP or Pseudo STOP mode.
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A.1.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for
the measurements.
A.1.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single
chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.
A.1.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data
and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be
given. A very good estimate is to take the single chip currents and add the currents due to the external
loads.
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Table A-8 Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
IDD5
Min
Typ
Max
Unit
Run supply currents
Single Chip, Internal regulator enabled
1
P
mA
65
Wait Supply current
IDDW
2
3
P
P
All modules enabled
only RTI enabled
40
5
mA
Pseudo Stop Current (RTI and COP enabled) 1, 2
C
C
C
C
C
C
C
570
600
-40°C
27°C
650
70°C
IDDPS
µA
750
85°C
850
105°C
125°C
140°C
1200
1500
Pseudo Stop Current (RTI and COP disabled) (1),(2)
-40°C
C
P
C
C
P
C
P
C
P
370
400
450
550
600
650
800
850
1200
27°C
70°C
85°C
500
IDDPS
4
5
µA
"C" Temp Option 100°C
105°C
1600
2100
5000
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
Stop Current (2)
C
P
C
C
P
C
P
C
P
12
-40°C
30
100
27°C
70°C
100
130
160
200
350
400
600
85°C
IDDS
µA
1200
1700
5000
"C" Temp Option 100°C
105°C
"V" Temp Option 120°C
125°C
"M" Temp Option 140°C
NOTES:
1. PLL off
2. At those low power dissipation levels TJ = TA can be assumed
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Appendix B Electrical Specifications
B.1 Voltage Regulator (VREG_3V3) Operating Characteristics
This section describes the characteristics of the on chip voltage regulator.
Table 20-2 VREG_3V3 - Operating Conditions
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
VVDDR,A
1
P
Input Voltages
3.135
—
5.5
V
Regulator Current
Reduced Power Mode
Shutdown Mode
IREG
2
3
P
P
—
—
20
12
50
40
µA
µA
Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode
2.5
2.35
1.6
—
2.75
2.75
—
V
V
V
VDD
2.5
1
Output Voltage PLL
V
V
V
V
Full Performance Mode
2.5
2.5
2.35
2.0
1.6
—
2.75
2.75
2.75
—
VDDPLL
4
P
Reduced Power Mode2
Reduced Power Mode3
2.5
4
Shutdown Mode
Low Voltage Interrupt5
Assert Level
VLVIA
VLVID
5
5
P
P
C
4.1
4.37
4.52
V
V
4.66
4.77
4.25
Deassert Level
Low Voltage Reset6
Assert Level
Deassert Level
VLVRA
VLVRD
2.25
—
—
—
—
2.55
V
V
Power-on Reset7
Assert Level
Deassert Level
VPORA
VPORD
7
0.97
—
---
---
—
2.05
V
V
NOTES:
1. High Impedance Output
2. Current IDDPLL = 1mA (Colpitts Oscillator)
3. Current IDDPLL = 3mA (Pierce Oscillator)
4. High Impedance Output
5. Monitors VDDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
6. Monitors VDD, active only in Full Performance Mode. VLVRA and VPORD must overlap
7. Monitors VDD. Active in all modes.
NOTE: The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
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B.2 Chip Power-up and LVI/LVR graphical explanation
Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage
reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1.
Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
V
VDDA
VLVID
VLVIA
VDD
VLVRD
VLVRA
VPORD
t
LVI
LVI enabled
LVI disabled due to LVR
POR
LVR
B.3 Output Loads
B.3.1 Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no
external DC loads.
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B.3.2 Capacitive Loads
The capacitive loads are specified in Table B-1. Ceramic capacitors with X7R dielectricum are required.
Table B-1 Voltage Regulator - Capacitive Loads
Num
Characteristic
VDD external capacitive load
VDDPLL external capacitive load
Symbol
CDDext
Min
200
90
Typical
440
Max
12000
5000
Unit
nF
1
2
CDDPLLext
220
nF
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B.4 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
B.4.1 Startup
Table B-2 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table B-2 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
T
Rating
Symbol
VPORR
VPORA
PWRSTL
nRST
Min
Typ
Max
Unit
V
1
2
3
4
5
6
7
8
POR release level
POR assert level
2.07
T
0.97
2
V
tosc
nosc
D
D
D
D
P
P
Reset input pulse width, minimum input time
Startup from Reset
192
20
196
14
PWIRQ
tWRS
Interrupt pulse width, IRQ edge-sensitive mode
Wait recovery startup time
LVR release level
ns
tcyc
VLVRR
VLVRA
2.25
V
V
LVR assert level
2.55
B.4.1.1 POR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
PORA DD
PORR
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
B.4.1.2 LVR
The release level V
and the assert level V
are derived from the V Supply. They are also valid
LVRR
LVRA DD
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
no valid oscillation is detected, the MCU will start using the internal self
CQOUT
clock. The fastest startup time possible is given by n
.
uposc
B.4.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
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B.4.1.4 External Reset
When external reset is asserted for a time greater than PW
the CRG module generates an internal
RSTL
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
B.4.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
B.4.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts
wrs
fetching the interrupt vector.
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B.4.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
or oscillator fail. t
specifies the maximum time before switching to the internal self clock mode after
CQOUT
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
oscillator start-up time t
. The device also features a clock monitor. A Clock Monitor Failure is
UPOSC
asserted if the frequency of the incoming clock signal is below the Assert Frequency f
Table B-3 Oscillator Characteristics
CMFA.
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
fOSC
Min
0.5
Typ
Max
16
Unit
MHz
MHz
µA
1a
1b
2
C Crystal oscillator range (Colpitts)
Crystal oscillator range (Pierce) 1
fOSC
iOSC
C
0.5
40
P Startup Current
100
82
1003
2.5
tUPOSC
tCQOUT
fCMFA
fEXT
3
C Oscillator start-up time (Colpitts)
D Clock Quality check time-out
P Clock Monitor Failure Assert Frequency
ms
s
4
0.45
50
5
100
200
50
KHz
MHz
ns
External square wave input frequency 4
External square wave pulse width low(4)
External square wave pulse width high(4)
External square wave rise time(4)
6
P
D
D
D
D
0.5
9.5
9.5
tEXTL
tEXTH
tEXTR
tEXTF
CIN
7
8
ns
9
1
1
ns
External square wave fall time(4)
10
11
ns
D Input Capacitance (EXTAL, XTAL pins)
7
pF
DC Operating Bias in Colpitts Configuration on
VDCBIAS
12
13
C
1.1
V
EXTAL Pin
EXTAL Pin Input High Voltage(4)
EXTAL Pin Input High Voltage(4)
EXTAL Pin Input Low Voltage(4)
EXTAL Pin Input Low Voltage(4)
EXTAL Pin Input Hysteresis(4)
VIH,EXTAL 0.7*VDDPLL
VIH,EXTAL
P
T
P
T
C
V
V
VDDPLL + 0.3
0.3*VDDPLL
VIL,EXTAL
14
V
VIL,EXTAL VSSPLL - 0.3
VHYS,EXTAL
V
15
250
mV
NOTES:
1. Depending on the crystal a damping series resistor might be necessary
2. fosc = 4MHz, C = 22pF.
3. Maximum value is for extreme cases using high Q, low frequency crystals
4. Only valid if Pierce oscillator/external clock mode is selected
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B.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
B.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C
p
VDDPLL
R
Phase
C
XFC Pin
s
VCO
f
f
vco
f
1
ref
osc
∆
K
K
Φ
V
refdv+1
Detector
f
cmp
Loop Divider
1
1
2
synr+1
Figure B-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table B-4.
1
1
ch
The grey boxes show the calculation for f
= 50MHz and f = 1MHz. E.g., these frequencies are used
ref
VCO
for f
= 4MHz and a 25MHz bus clock.
OSC
The VCO Gain at the desired VCO frequency is approximated by:
(f1 – fvco
)
(60 – 50)
-----------------------
-----------------------
K1 ⋅ 1V
–100
K = K ⋅ e
= -90.48MHz/V
= –100 ⋅ e
V
1
The phase detector relationship is given by:
K = – i ⋅ K
V
= 316.7Hz/Ω
Φ
ch
i is the current in tracking mode.
ch
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The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
C
typical values are 50. ζ = 0.9 ensures a good transient response.
2 ⋅ ζ ⋅ f
f
ref
1
ref
------
f < ------------------------------------------ Þ
→ f < ------------- ;(ζ = 0.9)
C
C
10
4 ⋅ 10
2
π ⋅ ζ + 1 + ζ
fC < 25kHz
And finally the frequency relationship is defined as
f
VCO
n = ------------- = 2 ⋅ (s y n r + 1 )
= 50
f
ref
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f =10kHz:
C
2 ⋅ π ⋅ n ⋅ f
C
= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ
R = ----------------------------
K
Φ
The capacitance C can now be calculated as:
s
2
2 ⋅ ζ
0.516
C
= 5.19nF =~ 4.7nF
Cp = 470pF
---------------------
C =
≈ --------------;(ζ = 0.9)
s
π ⋅ f ⋅ R
f ⋅ R
C
The capacitance C should be chosen in the range of:
p
C ⁄ 20 ≤ C ≤ C ⁄ 10
s
p
s
B.4.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure B-2. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-3.
NOTE: This section is under construction
The basic functionality of the PLL is shown in Figure B-2. With each transition of the clock f , the
cmp
deviation from the reference clock f is measured and input voltage to the VCO is adjusted
ref
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accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure B-3.
1
2
3
N-1
N
0
t
min1
t
nom
t
max1
t
minN
t
maxN
Figure B-3 Jitter Definitions
is at its maximum for one clock period, and decreases towards zero for larger
The relative deviation of t
nom
number of clock periods (N).
Defining the jitter as:
t
(N)
t
(N)
min
max
J(N) = max 1 –
, 1 –
--------------------
---------------------
N ⋅ t
N ⋅ t
nom
nom
For N < 100, the following equation is a good fit for the maximum jitter:
j
1
J(N) =
+ j
2
-------
N
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J(N)
1
5
10
20
N
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table B-4 PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
P
D
Rating
Self Clock Mode frequency
VCO locking range
Symbol
fSCM
Min
1
Typ
Max
5.5
Unit
MHz
MHz
1
2
fVCO
8
50
Lock Detector transition from Acquisition to
Tracking mode
1
|∆trk
|
3
D
3
4
%
(1)
|∆Lock
|∆unl
|
4
5
D
D
Lock Detection
0
1.5
2.5
%
(1)
|
Un-Lock Detection
0.5
%
Lock Detector transition from Tracking to
Acquisition mode
(1)
|∆unt
|
6
D
6
8
%
PLLON Total Stabilization delay (Auto Mode) 2
PLLON Acquisition mode stabilization delay (2)
tstab
tacq
tal
7
C
D
D
D
D
D
D
C
C
0.5
0.3
ms
ms
8
9
PLLON Tracking mode stabilization delay (2)
Fitting parameter VCO loop gain
0.2
ms
K1
f1
10
-100
60
MHz/V
MHz
µA
11
Fitting parameter VCO loop frequency
Charge pump current acquisition mode
Charge pump current tracking mode
| ich
| ich
j1
|
12
38.5
3.5
|
13
µA
Jitter fit parameter 1(2)
Jitter fit parameter 2(2)
14
1.1
%
j2
15
0.13
%
NOTES:
1. % deviation from target frequency
2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs =
10KΩ.
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B.5 Flash NVM
B.5.1 NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum
oscillator frequency f
is required for performing program or erase operations. The NVM modules
NVMOSC
do not have any means to monitor the frequency and will not prevent program or erase operation at
frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at
a lower frequency a full program or erase transition is not assured.
The Flash program and erase operations are timed using a clock derived from the oscillator using the
FCLKDIV register. The frequency of this clock must be set within the limits specified as f
.
NVMOP
The minimum program and erase times shown in Table B-5 are calculated for maximum f
and
NVMOP
maximum f . The maximum times are calculated for minimum f
and a f of 2MHz.
bus
bus
NVMOP
B.5.1.1 Single Word Programming
The programming time for single word programming is dependent on the bus frequency as a well as on
the frequency f¨
and can be calculated according to the following formula.
NVMOP
1
1
---------------------
----------
t
= 9 ⋅
+ 25 ⋅
swpgm
f
f
NVMOP
bus
B.5.1.2 Row Programming
Flash programming where up to 32 words in a row can be programmed consecutively by keeping the
command pipeline filled. The time to program a consecutive word can be calculated as:
1
1
bus
---------------------
----------
t
= 4 ⋅
+ 9 ⋅
bwpgm
f
f
NVMOP
The time to program a whole row is:
t
= t
+ 31 ⋅ t
swpgm bwpgm
brpgm
Row programming is more than 2 times faster than single word programming.
B.5.1.3 Sector Erase
Erasing a 512 byte Flash sector takes:
1
---------------------
t
≈ 4000 ⋅
era
The setup times can be ignored for this operation.
f
NVMOP
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B.5.1.4 Mass Erase
Erasing a NVM block takes:
1
---------------------
t
≈ 20000 ⋅
mass
f
NVMOP
The setup times can be ignored for this operation.
B.5.1.5 Blank Check
The time it takes to perform a blank check on the Flash is dependant on the location of the first non-blank
word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the
command.
t
≈ location ⋅ t
+ 10 ⋅ t
cyc cyc
check
Table B-5 NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
D
D
D
P
D
D
P
P
D
Rating
External Oscillator Clock
Symbol
fNVMOSC
fNVMBUS
fNVMOP
tswpgm
Min
0.5
1
Typ
Max
501
Unit
MHz
MHz
kHz
µs
1
2
Bus frequency for Programming or Erase Operations
Operating Frequency
3
150
200
74.53
313
462
20.42
678.42
204
4
Single Word Programming Time
Flash Burst Programming consecutive word
Flash Burst Programming Time for 32 Words
Sector Erase Time
tbwpgm
tbrpgm
tera
5
µs
1035.53
26.73
1333
6
µs
7
ms
1004
115
tmass
t check
8
Mass Erase Time
ms
327786
tcyc
9
Blank Check Time Flash per block
NOTES:
1. Restrictions for oscillator in crystal mode apply!
2. Minimum Programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequen-
cy fbus
.
3. Maximum Erase and Programming times are achieved under particular combinations of f NVMOP and bus frequency f bus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP
5. Minimum time, if first word in the array is not blank
.
6. Maximum time to complete check on an erased block.
B.5.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
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The failure rates for data retention and program/erase cycling are specified at <2ppm defects over lifetime
at the operating conditions noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE: All values shown in Table B-6 are target values and subject to further extensive
characterization.
Table B-6 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
Data Retention at an average junction temperature of
TJavg = 85°C
tNVMRET
1
C
15
Years
Data Retention at a junction temperature of TJ =
140°C
tNVMRET
nFLPE
2
3
C
C
10
Years
Flash number of Program/Erase cycles
10,000
Cycles
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B.6 SPI Characteristics
This section provides electrical parametrics and ratings for the SPI.
In Table B-7 the measurement conditions are listed.
Table B-7 Measurement Conditions
Description
Value
full drive mode
Unit
—
Drive mode
Load capacitance CLOAD,
on all outputs
Thresholds for delay
measurement points
50
pF
V
(20% / 80%) VDDX
B.6.1 Master Mode
In Figure B-4 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1
(OUTPUT)
2
1
12
12
13
13
3
SCK
4
(CPOL = 0)
(OUTPUT)
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
MSB IN2
10
LSB IN
BIT 6 . . . 1
9
(INPUT)
11
MOSI
MSB OUT2
BIT 6 . . . 1
LSB OUT
(OUTPUT)
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure B-4 SPI Master Timing (CPHA=0)
In Figure B-5 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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SS1
(OUTPUT)
1
12
12
13
13
3
2
SCK
(CPOL = 0)
(OUTPUT)
4
4
SCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
MSB IN2
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
(INPUT)
9
MOSI
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
(OUTPUT)
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure B-5 SPI Master Timing (CPHA=1)
In Table B-8 the timing characteristics for master mode are listed.
Table B-8 SPI Master Mode Timing Characteristics
Num
C
Characteristic
SCK Frequency
Symbol
Unit
Min
1/2048
2
Typ
—
Max
1/2
2048
—
fsck
tsck
tlead
tlag
twsck
tsu
fbus
tbus
tsck
tsck
tsck
ns
1
1
P
P
D
D
D
D
D
D
D
D
D
D
SCK Period
—
2
Enable Lead Time
—
1/2
1/2
1/2
—
3
Enable Lag Time
—
—
4
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
—
5
8
—
thi
6
8
—
—
ns
tvsck
tvss
tho
9
—
—
30
15
—
ns
10
11
12
13
—
—
ns
20
—
—
ns
trfi
—
8
ns
trfo
—
—
8
ns
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B.6.2 Slave Mode
In Figure B-6 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
SS
(INPUT)
1
12
12
13
3
SCK
(CPOL = 0)
(INPUT)
4
4
2
13
11
SCK
(CPOL = 1)
10
(INPUT)
8
7
9
11
MISO
see
SEE
BIT 6 . . . 1
SLAVE LSB OUT
SLAVE MSB
6
(OUTPUT)
note
NOTE
5
MOSI
BIT 6 . . . 1
MSB IN
LSB IN
(INPUT)
NOTE: Not defined!
Figure B-6 SPI Slave Timing (CPHA=0)
In Figure B-7 the timing diagram for slave mode with transmission format CPHA=1 is depicted.
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SS
(INPUT)
3
1
12
12
13
13
2
SCK
(CPOL = 0)
(INPUT)
4
4
SCK
(CPOL = 1)
(INPUT)
11
8
9
MISO
see
BIT 6 . . . 1
SLAVE MSB OUT
SLAVE LSB OUT
LSB IN
note
(OUTPUT)
7
5
6
MOSI
MSB IN
BIT 6 . . . 1
(INPUT)
NOTE: Not defined!
Figure B-7 SPI Slave Timing (CPHA=1)
In Table B-9 the timing characteristics for slave mode are listed.
Table B-9 SPI Slave Mode Timing Characteristics
Num
C
Characteristic
SCK Frequency
Symbol
Unit
Min
DC
4
Typ
—
Max
1/4
fsck
tsck
tlead
tlag
fbus
tbus
tbus
tbus
tbus
ns
1
1
2
3
4
5
6
P
P
D
D
D
D
D
SCK Period
—
∞
Enable Lead Time
4
—
—
—
—
—
—
Enable Lag Time
4
—
twsck
tsu
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
4
—
8
—
thi
8
—
ns
Slave Access Time (time to data
active)
ta
7
D
—
—
20
ns
tdis
8
9
D
D
Slave MISO Disable Time
—
—
—
—
22
ns
ns
1
1
tvsck
Data Valid after SCK Edge
30 + tbus
tvss
tho
trfi
10
11
D
D
D
D
Data Valid after SS fall
—
20
—
—
—
—
—
—
ns
ns
ns
ns
30 + tbus
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
—
8
12
trfo
13
8
NOTES:
1. tbus added due to internal synchronization delay
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B.7 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the
ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.
B.7.1 ATD Operating Characteristics - 5V Range
The Table B-10 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-10 5V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= VDDA <=5V+10%
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1
D
Low
High
VRL
VRH
VSSA
VDDA/2
VDDA
V
V
VDDA/2
Differential Reference Voltage1
2
3
C
VRH-VRL
4.75
0.5
5.0
5.25
2.0
V
D ATD Clock Frequency
f
MHz
ATDCLK
ATD 10-Bit Conversion Period
Clock Cycles2
N
14
7
28
14
7
Cycles
µs
CONV10
CONV10
CONV10
4
D
Conv, Time at 2.0MHz ATD Clock fATDCLK
Conv, Time at 4.0MHz3 ATD Clock fATDCLK
T
T
3.5
µs
ATD 8-Bit Conversion Period
Clock Cycles(1)
5
D
D
N
12
6
26
13
Cycles
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
T
µs
Stop Recovery Time (VDDA=5.0 Volts)
6
7
t
20
µs
SR
P Reference Supply current
I
0.375
mA
REF
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.75V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
3. Reduced accuracy see Table B-13 and Table B-14.
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B.7.2 ATD Operating Characteristics - 3.3V Range
The Table B-11 shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not
drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will
effectively be clipped.
Table B-11 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= VDDA <= 3.3V+10%
Num C
Rating
Symbol
Min
Typ
Max
Unit
Reference Potential
1
D
Low
High
V
RH
V
DDA
V
/2
V
V
RL
SSA
DDA
V
V
/2
V
DDA
2
3
C Differential Reference Voltage
D ATD Clock Frequency
V
-V
3.0
3.3
3.6
V
RH RL
ATDCLK
f
0.5
2.0
MHz
ATD 10-Bit Conversion Period
Clock Cycles1
N
14
7
28
14
7
Cycles
µs
CONV10
CONV10
CONV10
4
D
Conv, Time at 2.0MHz ATD Clock fATDCLK
Conv, Time at 4.0MHz2 ATD Clock fATDCLK
T
T
3.5
µs
ATD 8-Bit Conversion Period
Clock Cycles(1)
5
D
N
12
6
26
13
Cycles
CONV8
CONV8
Conv, Time at 2.0MHz ATD Clock fATDCLK
T
µs
Recovery Time (VDDA=3.3 Volts)
6
7
D
P
t
20
µs
REC
Reference Supply current
I
0.250
mA
REF
NOTES:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see Table B-13 and Table B-14.
B.7.3 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
B.7.3.1 Source Resistance:
Due to the input pin leakage current as specified in Table A-6 and Table A-7in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
S
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
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B.7.3.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage ≤ 1LSB, then the external filter capacitor, C ≥ 1024 * (C - C ).
f
INS
INN
B.7.3.3 Current injection
There are two cases to consider.
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less
than VRL unless the current is higher than specified as disruptive conditions.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy
of the conversion depending on the source resistance.
The additional input voltage error on the converted channel can be calculated as V
= K * R *
S
ERR
I
, with I being the sum of the currents injected into the two pins adjacent to the converted
INJ
INJ
channel.
Table B-12 ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
Rating
Symbol
Min
Typ
Max
Unit
RS
1
C
Max input Source Resistance
-
-
1
KΩ
Total Input Capacitance
Non Sampling
Sampling
CINN
CINS
2
T
10
15
pF
INA
Kp
Kn
3
4
5
C
C
C
Disruptive Analog Input Current
-2.5
2.5
10-4
10-2
mA
A/A
A/A
Coupling Ratio positive current injection
Coupling Ratio negative current injection
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B.7.4 ATD accuracy - 5V Range
Table B-13 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table B-13 5V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV
f
= 2.0MHz
ATDCLK
Num
C
Rating
Symbol
LSB
Min
Typ
5
Max
Unit
mV
1
2
3
4
P 10-Bit Resolution
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
DNL
INL
–1
1
Counts
Counts
Counts
–2.0
-2.5
2.0
2.5
10-Bit Absolute Error1
P
C
AE
10-Bit Absolute Error at fATDCLK= 4MHz
5
AE
LSB
DNL
INL
AE
±7.0
Counts
mV
6
P 8-Bit Resolution
20
7
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.0
-1.5
0.5
1.0
1.5
Counts
Counts
Counts
8
±0.5
±1.0
8-Bit Absolute Error(1)
P
9
NOTES:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.
B.7.5 ATD accuracy - 3.3V Range
Table B-14 specifies the ATD conversion performance excluding any errors due to current injection,
input capacitance and source resistance.
Table B-14 3.3V ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted
VREF = VRH - VRL = 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
f
= 2.0MHz
ATDCLK
Num C
Rating
Symbol
LSB
Min
Typ
3.25
Max
Unit
mV
1
2
3
4
P 10-Bit Resolution
P 10-Bit Differential Nonlinearity
P 10-Bit Integral Nonlinearity
DNL
INL
–1.5
–3.5
-5
1.5
3.5
5
Counts
Counts
Counts
±1.5
±2.5
±7.0
13
10-Bit Absolute Error1
P
C
AE
10-Bit Absolute Error at fATDCLK= 4MHz
5
6
7
8
9
AE
LSB
DNL
INL
AE
Counts
mV
P 8-Bit Resolution
P 8-Bit Differential Nonlinearity
P 8-Bit Integral Nonlinearity
–0.5
–1.5
-2.0
0.5
1.5
2.0
Counts
Counts
Counts
±1.0
±1.5
8-Bit Absolute Error(1)
P
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NOTES:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure B-8.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
V – V
i
i – 1
DNL(i) =
– 1
------------------------
1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
V – V
1LSB
n
0
INL(n) =
DNL(i) =
– n
-------------------
∑
=
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DNL
10-Bit Absolute Error Boundary
LSB
V
V
i
i-1
$3FF
$3FE
$3FD
$3FC
$3FB
$3FA
$3F9
$3F8
$3F7
$3F6
$3F5
$3F4
$3F3
8-Bit Absolute Error Boundary
$FF
$FE
$FD
2
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5
10
15
20
25
30
35
40
50
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin
mV
Figure B-8 ATD Accuracy Definitions
NOTE:Figure B-8 shows only definitions, for specification values refer to Table B-13 and Table
B-14.
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B.8 DAC Characteristics
This section describes the characteristics of the digital to analog converter.
B.8.1 DAC Operating Characteristics
Table B-15 DAC Electrical Characteristics (Operating)
Num
C
D
D
Characteristic
Condition
Symbol
Min
3.135
—
Typ
Max
5.5
Unit
V
VDDA
1
DAC Supply
—
IDDArun
Running
—
3.5
mA
2
3
DAC Supply Current
Reference Potential
Stop
IDDstop
—
—
1.0
mA
D
(low power)
VSSA
VREF
IREF
VSSA
VDDA/2
—
VSSA
VDDA
400
1
D
D
D
D
Low
—
—
—
—
V
V
High
VREF to VSSA
4
5
Reference Supply Current
Input Current, Channel Off1
mA
µA
IOFF
-200
Operating Temperature
Range
0C
6
D
T
-40
—
125
Table B-16 DAC Timing/Performance Characteristics
Num
C
Parameters
Condition
Symbol
Min
Typ
Max
Unit
VDDA = 3.0V
VREF = TBD
fBUS
D
—
—
25
25
DAC Operating
Frequency
1
MHz
VDDA = 5.5V
VREF = TBD
fBUS
D
—
—
2
3
D
D
Integral Non-Linearity
INL
—
—
0.25
0.10
—
—
Count
Count
Differential
Non-Linearity
DNL
4
5
6
7
D
D
P
D
Resolution
RES
TS
—
5
—
—
8
10
1
Bit
µs
Settling Time
Absolute Accuracy
Offset Error
ABSACC
ERR
-1
—
Count
mV
+/-2.5
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Appendix C External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure C-1 with the actual timing
values shown on table Table C-1. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
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Device User Guide — 9S12E128DGV1/D V01.04
Figure C-1 General External Bus Timing
1, 2
3
4
ECLK
PE4
5
9
6
16
10
15
11
Addr/Data
data
data
data
addr
(read)
PA, PB
7
8
12
14
data
13
Addr/Data
addr
(write)
PA, PB
17
19
23
26
18
Non-Multiplexed
Addresses
PK5:0
20
21
22
ECS
PK7
24
27
25
28
R/W
PE2
29
32
LSTRB
PE3
31
34
30
33
NOACC
PE7
35
36
IPIPO0
IPIPO1, PE6,5
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Table C-1 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40°C to +140°C, CLOAD = 50pF
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
D
D
Rating
Frequency of operation (E-clock)
Cycle time
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
25.0
tcyc
2
40
19
19
PWEL
3
Pulse width, E low
ns
Pulse width, E high1
PWEH
tAD
4
ns
5
Address delay time
8
ns
Address valid time to E rise (PWEL–tAD
)
tAV
6
11
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
7
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
ns
8
7
ns
9
2
ns
10
11
12
13
13
0
ns
ns
7
ns
2
12
19
6
ns
Write data setup time(1) (PWEH–tDDW
Address access time(1) (tcyc–tAD–tDSR
E high access time(1) (PWEH–tDSR
Non-multiplexed address delay time
)
14
15
D
D
ns
ns
tACCA
)
tACCE
tNAD
tNAV
tNAH
tCSD
tACCS
tCSH
tCSN
tRWD
tRWV
tRWH
tLSD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
6
Non-muxed address valid to E rise (PWEL–tNAD
Non-multiplexed address hold time
Chip select delay time
)
14
2
16
Chip select access time(1) (tcyc–tCSD–tDSR
Chip select hold time
)
11
2
Chip select negated time
8
Read/write delay time
7
7
7
Read/write valid time to E rise (PWEL–tRWD
)
14
2
Read/write hold time
Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
Low strobe hold time
)
tLSV
14
2
tLSH
tNOD
tNOV
NOACC strobe delay time
NOACC valid time to E rise (PWEL–tNOD
)
14
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Table C-1 Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40°C to +140°C, CLOAD = 50pF
tNOH
tP0D
tP0V
tP1D
tP1V
32
33
34
35
D
D
D
D
D
NOACC hold time
2
2
ns
ns
ns
ns
ns
IPIPO[1:0] delay time
7
IPIPO[1:0] valid time to E rise (PWEL–tP0D
)
11
2
IPIPO[1:0] delay time(1) (PWEH-tP1V
IPIPO[1:0] valid time to E fall
)
25
36
11
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Table C-2 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40°C to +140°C, CLOAD = 50pF
Num
1
C
P
P
D
D
D
D
D
D
D
D
D
D
D
Rating
Frequency of operation (E-clock)
Cycle time
Symbol
fo
Min
0
Typ
Max
Unit
MHz
ns
16.0
tcyc
2
62.5
30
PWEL
3
Pulse width, E low
ns
Pulse width, E high1
PWEH
tAD
4
30
ns
5
Address delay time
16
ns
Address valid time to E rise (PWEL–tAD
)
tAV
6
16
2
ns
tMAH
tAHDS
tDHA
tDSR
tDHR
tDDW
tDHW
tDSW
7
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
ns
8
7
ns
9
2
ns
10
11
12
13
15
0
ns
ns
15
ns
2
ns
Write data setup time(1) (PWEH–tDDW
Address access time(1) (tcyc–tAD–tDSR
E high access time(1) (PWEH–tDSR
Non-multiplexed address delay time
)
14
15
D
D
15
29
15
ns
ns
tACCA
)
tACCE
tNAD
tNAV
tNAH
tCSD
tACCS
tCSH
tCSN
tRWD
tRWV
tRWH
tLSD
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
Non-muxed address valid to E rise (PWEL–tNAD
Non-multiplexed address hold time
Chip select delay time
)
Chip select access time(1) (tcyc–tCSD–tDSR
Chip select hold time
)
Chip select negated time
Read/write delay time
14
14
14
Read/write valid time to E rise (PWEL–tRWD
)
16
2
Read/write hold time
Low strobe delay time
Low strobe valid time to E rise (PWEL–tLSD
)
tLSV
16
2
tLSH
Low strobe hold time
tNOD
tNOV
NOACC strobe delay time
NOACC valid time to E rise (PWEL–tNOD
)
16
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Table C-2 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40°C to +140°C, CLOAD = 50pF
tNOH
tP0D
tP0V
tP1D
tP1V
32
33
34
35
D
D
D
D
D
NOACC hold time
2
2
ns
ns
ns
ns
ns
IPIPO[1:0] delay time
14
25
IPIPO[1:0] valid time to E rise (PWEL–tP0D
)
16
2
IPIPO[1:0] delay time(1) (PWEH-tP1V
IPIPO[1:0] valid time to E fall
)
36
11
NOTES:
1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
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Appendix D Package Information
D.1 80-pin QFP package
L
60
61
41
40
B
P
B
-A-
L
-B-
V
B
-A-,-B-,-D-
DETAIL A
DETAIL A
21
80
F
1
20
-D-
A
M
S
S
S
0.20
H A-B
D
D
0.05 A-B
J
N
S
M
S
0.20
C A-B
M
D
E
DETAIL C
M
S
S
0.20
C
A-B
D
C
DATUM
-H-
PLANE
SECTION B-B
VIEW ROTATED 90
°
-C-
0.10
H
SEATING
PLANE
M
MILLIMETERS
G
DIM MIN
MAX
NOTES:
A
B
C
D
E
F
13.90 14.10
13.90 14.10
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2.15
0.22
2.00
0.22
2.45
0.38
2.40
0.33
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE
U
T
G
H
J
0.65 BSC
---
0.13
0.65
0.25
0.23
0.95
DATUM
-H-
DETERMINED AT DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -C-.
PLANE
R
K
L
12.35 REF
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
M
N
P
Q
R
S
T
5
10
°
°
0.13
0.17
PROTRUSION IS 0.25 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR
THE FOOT.
0.325 BSC
0
7
°
°
K
0.13
0.30
Q
W
16.95 17.45
0.13
---
---
X
U
V
W
X
0
°
DETAIL C
16.95 17.45
0.35
0.45
1.6 REF
Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B)
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D.2 112-pin LQFP package
4X
0.20 T L-M N
4X 28 TIPS
85
0.20 T L-M N
4X
P
J1
J1
PIN 1
112
IDENT
C
1
84
L
VIEW Y
X
108X
G
X=L, M OR N
VIEW Y
V
B
L
M
AA
J
B1
V1
28
57
BASE
F
D
METAL
29
56
M
0.13
T L-M N
N
SECTION J1-J1
A1
S1
ROTATED 90 COUNTERCLOCKWISE
°
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
A
2. DIMENSIONS IN MILLIMETERS.
3. DATUMS L, M AND N TO BE DETERMINED
AT
S
SEATING PLANE, DATUM T.
4. DIMENSIONS S AND V TO BE DETERMINED
AT
SEATING PLANE, DATUM T.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25 PER SIDE.
C2
VIEW AB
θ2
C
0.050
112X
0.10 T
SEATING
MILLIMETERS
PLANE
DIM MIN
MAX
θ3
A
A1
B
20.000 BSC
10.000 BSC
20.000 BSC
10.000 BSC
T
B1
C
---
1.600
C1 0.050 0.150
C2 1.350 1.450
θ
D
E
F
G
J
0.270 0.370
0.450 0.750
0.270 0.330
0.650 BSC
0.090 0.170
0.500 REF
R R2
K
P
0.325 BSC
R1 0.100 0.200
R2 0.100 0.200
0.25
R R1
S
S1
V
22.000 BSC
11.000 BSC
22.000 BSC
11.000 BSC
0.250 REF
1.000 REF
GAGE PLANE
V1
Y
Z
(K)
E
C1
θ1
AA 0.090 0.160
8 °
3 ° 7 °
13 °
11 ° 13 °
0 °
θ
θ1
θ2
θ3
(Y)
(Z)
11 °
VIEW AB
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Device User Guide End Sheet
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