MCC141533AZ_技术文档

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC141532A

MC141533A

LCD Segment / Common Driver

with Controller

CMOS

MC141532A / MC141533A is a CMOS LCD Driver which consists of 4 annun-

ciator outputs and 153 high voltage LCD driving signals (33 commons and 120 seg-

ments). MC141532A is one sided common output while MC141533A is split common

output design. It has parallel interface capability for operating with general MCU. Be-

sides the general LCD driver features, it has an on chip LCD bias Voltage Generator

circuit such that fewer external components are required during application.

TAB

•

Single Supply Operation, 2.4 V - 3.5 V

Operating Temperature Range : -30 to 85°C

Low Current Stand-by Mode (<500nA)

On Chip Bias Voltage Generator

8 Bit Parallel Interface

Graphic Mode Operation

On Chip 120 x 33 Graphic Display Data RAM

120 Segment Drivers, 33 Common Drivers

Selectable 1/16, 1/32, 1/33 Multiplex Ratio

Selectable on Chip Voltage Doubler and Tripler

Selectable 1:5 or 1:7 Bias Ratio

Re-mapping of Row and Column Drivers

Four Stand Alone Annunciator (Static Icon) Driver Circuits

Low Power Icon Mode Driven by Com32 in Special Driving Scheme

Selectable LCD Driving Voltage Temperature Coefficients

16 Level Internal Contrast Control

Die

ORDERING INFORMATION

MC141532AT

MC141532AT2

TAB

MCC141532AZ Gold Bump Die

MCC141533AZ Gold Bump Die

External Contrast Control Provided

Master Clear RAM

Standard TAB, Gold Bump Die

REV 0

1/99

Block Diagram

Annun0 to

Annun3

Com0 to

Com32

BP

Seg0~Seg119

Level

Selector

HV Buffer Cell Level Shifter

Annunciator

Control

Circuit

VLL6

33 Bit

VLL2

VCC

120 Bit Latch

Latch

VR

OSC1

OSC2

Display

Timing

Generator

VF

LCD Driving

C2P

Voltage Generator

C2N

C1P

Tripler,

Doubler,

C1N

DUM2

DUM1

C+

Voltage Regulator,

Voltage Divider,

Contrast Control,

Temperature

GDDRAM

33 X 120 Bits

Compensation

C-

AVDD

AVSS

Command Decoder

DVSS

DVDD

Command Interface

Parallel Interface

RES D/C CS (CLK)

CE

R/W

D0~D7

MC141532A • MC141533A

2

MOTOROLA

MC141532AT PIN ASSIGNMENT

(COPPER VIEW)

MOTOROLA

MC141532A • MC141533A

3

1

241

228

227

1

241

228

227

Ann0

Ann1

Ann2

Ann3

BP

DVdd

RES

DVss

D/C

R/W

Ann0

Ann1

Ann2

Ann3

BP

DVdd

RES

DVss

D/C

R/W

Seg105

Seg104

Seg103

Seg102

Seg101

Seg100

Seg99

Seg98

Seg97

Seg96

Seg95

Seg94

Seg93

Seg92

Seg91

Seg90

Seg89

Seg88

Seg87

Seg86

Seg85

Seg84

Seg83

Seg82

Seg81

Seg80

Seg79

Seg78

Seg77

Seg76

Seg75

Seg74

Seg73

Seg72

Seg71

Seg70

Seg69

Seg68

Seg67

Seg66

Seg65

Seg64

Seg63

Seg62

Seg61

Seg60

Seg59

Seg58

Seg57

Seg56

Seg55

Seg54

Seg53

Seg52

Seg51

Seg50

Seg49

Seg48

Seg47

Seg46

Seg45

Seg44

Seg43

Seg42

Seg41

Seg40

Seg39

Seg38

Seg37

Seg36

Seg35

Seg34

Seg33

Seg32

Seg31

Seg30

Seg29

Seg28

Seg27

Seg26

Seg25

Seg24

Seg23

Seg22

Seg21

Seg20

Seg19

Seg18

Seg17

Seg16

Seg15

Seg14

Seg13

Seg12

Seg11

Seg10

Seg9

Com30

Com31

Com32

Seg119

Seg118

Seg117

Seg116

Seg115

Seg114

Seg113

Seg112

Seg111

Seg110

Seg109

Seg108

Seg107

Seg106

Seg105

Seg104

Seg103

Seg102

Seg101

Seg100

Seg99

Seg98

Seg97

Seg96

Seg95

Seg94

Seg93

Seg92

Seg91

Seg90

Seg89

Seg88

Seg87

Seg86

Seg85

Seg84

Seg83

Seg82

Seg81

Seg80

Seg79

Seg78

Seg77

Seg76

Seg75

Seg74

Seg73

Seg72

Seg71

Seg70

Seg69

Seg68

Seg67

Seg66

Seg65

Seg64

Seg63

Seg62

Seg61

Seg60

Seg59

Seg58

Seg57

Seg56

Seg55

Seg54

Seg53

Seg52

Seg51

Seg50

Seg49

Seg48

Seg47

Seg46

Seg45

Seg44

Seg43

Seg42

Seg41

Seg40

Seg39

Seg38

Seg37

Seg36

Seg35

Seg34

Seg33

Seg32

Seg31

Seg30

Seg29

Seg28

Seg27

Seg26

Seg25

Seg24

Seg23

Seg22

Seg21

Seg20

Seg19

Seg18

Seg17

Seg16

Seg15

Seg14

Seg13

Seg12

Seg11

Seg10

Seg9

Alignment Mark

Co-ordination

CS(CLK)

DVss

D0

CS(CLK)

DVss

D0

X (mm)

Y(mm)

-78

D1

D2

D3

D4

D5

D6

D7

CE

D1

D2

D3

D4

D5

D6

D7

CE

A

B

C

D

E

-2625.2

-2525.2

-2575.2

-2436.8

4360.2

4410.2

4460.2

4421.6

116

22

-26

B

C

B

C

A

F

A

F

DVss

AVdd

C1P

DVss

AVdd

C1P

E

-26

D

F

-78

O₁

G

H

I

-75.8

-186.7

-138.7

-86.7

-186.0

14.0

J

K

L

O₂

d

-72.6

4802.2

4702.2

4866.2

4867.2

4824.8

4674.6

C1N

C2P

C2N

C1N

C2P

C2N

Keep

out

27.4

VLL2

VLL3

DVss

VLL4

VLL5

VLL6

DUM1

DVss

OSC2

DVss

DUM2

DVss

C+

DVss

C-

DVss

VCC

DVss

VF

VLL2

VLL3

DVss

VLL4

VLL5

VLL6

DUM1

DVss

OSC2

DVss

DUM2

DVss

C+

DVss

C-

DVss

VCC

DVss

VF

area

1*

27.4

-72.6

490.6

Keep

out

636.2

area

2*

636.2

490.6

O₁and O₂are the centers of the circu-

lar alignment marks which diameter is

d.

Seg8

Seg7

Seg6

Seg5

Seg4

Seg3

* Areas not shown in the figure also

with gold bumps

DVss

VR

DVss

VR

AVss

OSC1

DVss

Test1

Test2

AVss

OSC1

DVss

Test1

Test2

Seg2

Seg1

Seg0

Com32

Com31

Com30

Com29

Com28

Com27

Com26

Com25

Com24

Com23

Com22

Com21

Com20

Com19

Com18

Com17

Com16

Com15

Com14

Com13

Seg8

Seg7

Seg6

Seg5

Seg4

Seg3

Seg2

Seg1

G

L

H

G

L

H

J

O₂

Y

I

Seg0

K

Com15

Com14

Com13

102

101

102

101

87

88

87

88

X

MC141532A Die Pin Assignment

MC141533A Die Pin Assignment

MC141532A • MC141533A

4

MOTOROLA

This device contains circuitry to protect the inputs

against damage due to high static voltages or electric

fields; however, it is advised that normal precautions to

be taken to avoid application of any voltage higher than

maximum rated voltages to this high impedance circuit.

For proper operation it is recommended that V_inand V_out

be constrained to the range V_SS< or = (V_inor V_out) < or

= V_DD. Reliability of operation is enhanced if unused

input are connected to an appropriate logic voltage level

(e.g., either V_SSor V_DD). Unused outputs must be left

open. This device may be light sensitive. Caution should

be taken to avoid exposure of this device to any light

source during normal operation. This device is not radia-

tion protected.

MAXIMUM RATINGS* (Voltages Referenced to V_SS, T_A=25°C)

Symbol

Parameter

Value

Unit

AV_DD,DV_DD

Supply Voltage

Input Voltage

-0.3 to +4.0

V_SS-0.3 to V_SS+10.5

V_SS-0.3 to V_DD+0.3

25

V

V_CC

V_in

I

V

Current Drain Per Pin Excluding V_DDand V_SS

Operating Temperature

mA

°C

T_A

T_stg

-30 to +85

Storage Temperature Range

-65 to +150

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation

should be restricted to the limits in the Electrical Characteristics tables or Pin Description section.

V_SS= AV_SS= DV_SS(DV_SS= V_SSof Digital circuit, AV_SS= V_SSof Analogue Circuit)

V_DD= AV_DD= DV_DD(DV_DD= V_DDof Digital circuit, AV_DD= V_DDof Analogue Circuit)

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , T =25°C)

SS

A

Symbol

V_DD

Parameter

Test Condition

Min

2.4

Typ

Max

3.5

Unit

V

Supply voltage (Absolute value Referenced to V_SS

)

AV_DD= DV_DD

3.15

Supply Current (Measure with V_DDfixed at 3.15V)

Access Mode Supply Current Drain from Pin AVDD

and DVDD.

I_AC

I_DP1

I_DP2

Internal DC/DC Converter On, Display On, Tripler

Enable, R/W Accessing, T_cyc=1MHz, Osc.

Freq.=50kHz, 1/33 Duty Cycle,1/7 Bias.

Internal DC/DC Converter On, Display On, Tripler

Enable, R/W Halt, Osc. Freq.=50kHz, 1/33 Duty

Cycle,1/7 Bias.

Internal DC/DC Converter On, Display On, Tripler

Enable, R/W Halt, Osc. Freq.=38.4kHz, 1/33 Duty

Cycle,1/7 Bias.

0

200

80

300

150

100

mA

Display Mode Supply Current Drain from Pin AVDD

and DVDD.

Display Mode Supply Current Drain from Pin AVDD

and DVDD

60

I_SB1

I_SB2

Stand-by Mode Supply Current Drain from Pin AVDD Display Off, Oscillator Disabled, R/W Halt

and DVDD

Stand-by Mode Supply Current Drain from Pin AVDD Display Off, Oscillator Enable, R/W Halt, External

0

-

300

2.5

5

500

5

nA

mA

and DVDD.

Stand-by Mode Supply Current Drain from Pin AVDD Display Off, Oscillator Enable, R/W Halt, Internal

and DVDD. Oscillator and Frequency = 50kHz.

Stand-by Mode Supply Current Drain from Pin AVDD Low Power Icon Mode, Oscillator Enable, R/W Halt,

Oscillator and Frequency = 50kHz.

I_SB3

10

25

I_ICON

15

and DVDD

Internal Oscillator and Frequency = 50kHz

VLCD Voltage (Absolute Value Referenced to V_SS

)

V_CC1

V_CC2

V_LCD

LCD Driving Voltage Generator Output Voltage at Pin Display On, Internal DC/DC Converter Enabled, Tri-

-

3*DV_DD

2*DV_DD

-

10.5

7

V

V_CC

.

pler Enable, Osc. Freq. = 50kHz, Regulator Enabled,

Divider Enabled Iout <= 100mA

LCD Driving Voltage Generator Output Voltage at Pin Display On, Internal DC/DC Converter Enabled, Dou-

V_CC

.

bler Enable, Osc. Freq. = 50kHz, Regulator Enabled,

Divider Enabled Iout <= 100mA

LCD Driving Voltage input at pin V_CC

Output Voltage

.

Internal DC/DC Converter Disabled.

5

10.5

V_OH1

V_OL1

Output High Voltage at Pins D0-D7, Annun0-3, BP and I_out=100mA

OSC2.

Output Low Voltage at Pins D0-D7, Annun0-3, BP and I_out=100mA

0.8*V_DD

0

-

V_DD

V

0.2*V_DD

OSC2.

V_R1

V_R2

LCD Driving Voltage Source at Pin VR

Regulator Enabled, I_out=50mA

Regulator Disabled

0

-

V_CC

-

V

Floating

Input Voltage

V_IH1

V_IL1

Input High Voltage at Pins RES, CE, CS, D0-D7, R/W,

D/C, OSC1 and OSC2.

Input Low Voltage at Pins RES, CE, CS, D0-D7, R/W,

D/C, OSC1 and OSC2.

0.8*V_DD

0

-

V_DD

V

0.2*V_DD

MOTOROLA

MC141532A • MC141533A

5

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , DV =2.4-3.15V, T =25°C)

SS

DD

A

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

LCD Display Voltage. (LCD Driving Voltage Output from

Pins VLL6, VLL5, VLL4, VLL3 and VLL2.)

1/5 Bias Ratio, Voltage Divider Enabled, Regulator

Enabled.

V_LL6

V_LL5

V_LL4

V_LL3

V_LL2

-

V_R

-

V

0.8*V_R

0.6*V_R

0.4*V_R

0.2*V_R

V_LL6

V_LL5

V_LL4

DUM2

DUM1

V_LL3

1/7 Bias Ratio, Internal Voltage Divider Enabled,

Regulator Enabled

-

V_R

-

V

6/7*V_R

5/7*V_R

4/7*V_R

3/7*V_R

2/7*V_R

1/7*V_R

V_LL2

V_LL6

V_LL5

V_LL4

V_LL3

V_LL2

External Voltage Generator, Internal Voltage Divider

Disable

0.5V_CC

V_SS

-

V_CC

0.5V_CC

V

V_SS

Output Current

I_OH

I_OL

I_OZ

Output High Current Source from Pins D0-D7,

Annun0-3, BP and OSC2

Output Low Current Drain by Pins D0-D7, Annun0-3, V_out=0.4V.

BP and OSC2

Output Tri-state Current Drain Source at pins D0-D7

and OSC2

V_out=V_DD-0.4V.

100

-

-100

1

mA

-1

I_IL/I_IHInput Current at pins RES, CE, CS, D0-D7, R/W, D/C OSC1

and OSC2.

-1

-

1

mA

Ron

On Resistance

During Display on, 0.1V Apply between Two Termi-

10

kW

Channel Resistance between LCD Driving Signal Pins nals, V_CCwithin Operating Voltage Range.

(SEG and COM) and Driving Voltage Input Pins (V_LL2

to V_LL6).

V_SB

Memory Retention Voltage (DV_DD

)

1.8

-

V

Standby Mode, Retained All Internal Configuration

and RAM Data

C_IN

Input Capacitance

5

7.5

pF

All Control Pins

Temperature Coefficient Compensation

Flat Temperature Coefficient

Temperature Coefficient 1*

Temperature Coefficient 2*

Temperature Coefficient 3*

PTC0

PTC1

PTC2

PTC3

TC1=0, TC2=0, Voltage Regulator Disabled.

TC1=0, TC2=1, Voltage Regulator Enabled.

TC1=1, TC2=0, Voltage Regulator Enabled.

TC1=1, TC2=1, Voltage Regulator Enabled.

-

0.0

-

%

-0.18

-0.22

-0.35

V_CN

Internal Contrast Control

Internal Regulator Enabled, Internal Contrast Control

Enabled.

-

±18

-

%

VR Output Voltage with Internal Contrast Control

Selected. 16 Voltage Levels Controlled by Software.

Each Level is Typical of 2.25% of the Regulator Output

Voltage.

* The formula for the temperature coefficient is:

VR at 50°C - VR at 0°C

1

TC(%)=

X

X100%

50°C - 0°C

VR at 25°C

MC141532A • MC141533A

6

MOTOROLA

ELECTRICAL CHARACTERISTICS (Voltage Referenced to V , AV =DV =2.4 to 3.5V, T =25°C)

SS

DD

A

Total variation of VR DV_RTis affected by the following factors :

Process variation of Regulator DV_R

External V_DDVariation contributed to Regulator DV_VDD

External resistor pair Ra/Rf contributed to Regulator DV_res

2

where DV_RT

=

(DV_R)²+ (DV_V)²+ (DV_res

)

DD

Assume external V_DDvariation is ±6% at 3.15V and 1% variation resistor used at application

TC Level

DV_VDD(%)

DV_R(%)

±2.5

DV_res(%)

±1.414

DV_RT(%)

TC0

TC1

TC2

TC3

±6.0

±4.0

±2.5

±1.4

±6.652

±4.924

±3.805

±3.195

Reference

Generator

AC ELECTRICAL CHARACTERISTICS (T =25°C, Voltage referenced to V , V =2.4 to 3.15V)

A

SS

DD

Symbol Parameter

Oscillation Frequency.

Test Condition

Min

Typ

Max

Unit

Set Clock Frequency to Slow

F_OSC1

F_ANN1

F_FRM1

Oscillation Frequency of Display Timing Generator with

60Hz Frame Frequency.

Annunciator Display (50% duty cycle) from Pins

Annun0-3 and BP

-

38.4

-

kHz

Hz

18.75

LCD Driving Signal Frame Frequency.

Either External Clock Input or Internal Oscillator

Enable, Either 1/32 or 1/16 Duty Cycle, Graphic Dis-

play Mode.

Either External Clock Input or Internal Oscillator

Enable, 1/33 Duty Cycle, Graphic Display Mode.

-

66

64

-

Hz

F_CON1

LCD Driving Signal Frame Frequency.

Oscillation Freq.

Set Clock Frequency to Normal

Fosc₂

F_ANN2

F_FRM2

F_CON2

Oscillation Frequency of Display Timing Generator with

60Hz Frame Frequency.

Annunciator Display Frequency (with 50% duty cycle)

from Pins Annun0-3 and BP

-

50

24.4

65

-

kHz

Hz

LCD driving Signal Frame Frequency.

Either External Clock Input or Internal Oscillator

Enable, Either 1/32 or 1/16 Duty Cycle.

Either External Clock Input or Internal Oscillator

Enable, 1/33 Duty Cycle.

Hz

LCD driving Signal Frame Frequency.

63

Hz

OSC

Internal Oscillation Frequency

Internal Oscillator Enabled. V_DDwithin Operation

Internal OSC Oscillation Frequency with Different Range.

Value of Feedback Resistor.

See Figure 1 for the relationship

Set Clock Frequency to Slow : F_FRM1=F_OSC1/576

Set Clock Frequency to Normal : F_FRM2=F_OSC2/768

MOTOROLA

MC141532A • MC141533A

7

420k

390k

150k

120k

90k

60k

30k

Oscillation

Frequency

(Hz)

100k

500k

1.0M

Resistor Value between OSC1 and OSC2 (W)

Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value

1.5M

2.0M

AC OPERATION CONDITIONS AND CHARATERISTICS

ELECTRICAL CHARACTERISTICS LCD Panel driving signal timing (T =-30 to 85°C, V = 2.4 to 3.5V, V = 0V)

A

DD

SS

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

COMx

SEGy

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

1/F_ANN

BP, Annun0-3

Figure 2. LCD Driving Signal Timing Diagram

MC141532A • MC141533A

8

MOTOROLA

TABLE 2a. Parallel Timing Characteristics (Write Cycle) (T =-30 to 85°C, DV =2.4 to 3.5V, V =0V)

A

DD

SS

Symbol

t_cycle

t_EH

Parameter

Min

600

290

5

Typ

Max

Unit

ns

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

-

ns

t_AS

ns

t_DS

290

20

ns

t_DH

Data Hold Time

ns

t_AH

Address Hold Time

20

ns

CE

t_cycle

CS

t_EH

R/W

t_AH

t_AS

D/C

t_DS

t_DH

D0-D7

Valid Data

Figure 3. Timing Characteristics (Write Cycle)

MOTOROLA

MC141532A • MC141533A

9

TABLE 2b. Parallel Timing Characteristics (Read Cycle) (T =-30 to 85°C, DV =2.4 to 3.5V, V =0V)

A

DD

SS

Symbol

t_cycle

t_EH

Parameter

Min

600

290

5

Typ

Max

Unit

ns

Enable Cycle Time

Enable Pulse Width

Address Setup Time

Data Setup Time

-

ns

t_AS

-

290

-

ns

t_DS

-

ns

t_DH

Data Hold Time

10

20

ns

t_AH

Address Hold Time

-

ns

CE

t_cycle

CS

t_EH

R/W

t_AH

t_AS

D/C

t_DS

t_DH

Valid Data

D0-D7

Figure 4. Timing Characteristics (Read Cycle)

MC141532A • MC141533A

10

MOTOROLA

between these two pins.

PIN DESCRIPTIONS

D/C (Data / Command)

VR and VF

This input pin let the driver distinguish the input at D0-D7 is data or com-

mand. Input High for data while input Low for command.

This is a feedback path for the gain control (external contrast control) of

VLL1 to VLL6. For adjusting the LCD driving voltage, it requires a feed-

back resistor placed between VR and VF, a gain control resistor placed

between VF and AVSS, a 10 mF capacitor placed between VR and AVSS.

(Refer to the Application Circuit)

CS (CLK) (Chip Select / Input Clock)

This pin is normal Low clock input. Data on D0-D7 is latched at the fall-

ing edge of CS.

COM0-COM32 (Row Drivers)

RES (Reset)

These pins provide the row driving signal to LCD panel. Com0-Com31

are used in 32 mux configuration. Com0-Com15 are used in 16 mux and no

row remap configuration while Com16-Com31 are used in 16 mux with row

remap configuration. Com32 is used to drive the non-static icons in 33 Mux.

They output 0V during display off. (Note : The IC facilitates two Com32

pins, which output same signal, for the LCD panel layout flexibility.)

An active Low pulse to this pin reset the internal status of the driver

(same as power on reset). The minimum pulse width is 10 ms.

CE (Chip Enable)

HIGH input to this pin to enable the control pins on the driver.

D0-D7

SEG0-SEG119 (Column Drivers)

These 120 pins provide LCD column driving signal to LCD panel. They

output 0V during display off.

This bi-directional bus is used for data / command transferring.

R/W (Read/Write)

This is an input pin. To read the display data RAM or the internal status

(Busy / Idle), pull this pin High. The R/W input Low indicates a write oper-

ation to the display data RAM or to the internal setup registers.

BP (Annunciator Backplane)

This pin combines with Annun0-Annun3 pins to form annunciator driv-

ing part. When the annunciator circuit is enabled, it will output square wave

of F_ANNnHz. It outputs low when oscillator is disabled.

OSC1 (Oscillator Input)

For internal oscillator mode, this is an input for the internal low power

RC oscillator circuit. In this mode, an external resistor of certain value is

placed between the OSC1 and OSC2 pins for a range of internal operating

frequencies (refer to Figure 1). For external oscillator mode, OSC1 should

be left open.

Annun0 - Annun3 (Annunciator Frontplanes)

These pins are four independent annunciator driving outputs. The

enabled annunciator outputs from its corresponding pin a F_ANNnHz square

wave which is 180 degrees out of phase with BP. Disabled annunciator out-

put from its corresponding pin an square wave in-phase with BP. When

oscillator is disabled, all these pins output 0V.

OSC2 (Oscillator Output / External Oscillator Input)

This is an output for the internal low power RC oscillator circuit. For

external oscillator mode, OSC2 will be an input pin for external clock and

no external resistor is needed.

AVDD and AVSS

AVDD is the positive supply to the noise sensitive circuitry in LCD

Driver and should be at same level as DVDD. AVSS is ground.

VLL6 - VLL2

VCC

Group of voltage level pins for driving the LCD panel. They can either be

connected to external driving circuit for external bias supply or connected

internally to built-in divider circuit. For internal Voltage Divider enabled, a

capacitor to AV_SSis required on each pin.

For using the Internal DC/DC Converter, a 0.1 mF capacitor from this pin

to AVSS is required. It can also be an external bias input pin if Internal DC/

DC Converter is not used. Positive power is supplied to the LCD Driving

Level Selector and HV Buffer Cell with this pin. Normally, this pin is not

intended to be a power supply to other component.

DUM1 and DUM2

If internal Voltage Divider is enabled with 1/7 bias selected, a capacitor

to AV_SSis required on each pin. Otherwise, pull these two pin to AV_SS

DVDD and DVSS

Power is supplied to the digital control circuit and other circuitry in LCD

bias Voltage Generator of the driver using these two pins. DVDD is power

and DVSS is ground.

C1N and C1P

If Internal DC/DC Converter is enabled, a capacitor is required to con-

nect these two pins.

C2N and C2P

If internal Tripler is enabled, a capacitor is required between these two

pins. Otherwise, leave these pin open.

C+ and C-

If internal divider circuit is enabled, a capacitor is required to connect

MOTOROLA

MC141532A • MC141533A

11

OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER

Description of Block Diagram Module

Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or

command.

MPU Parallel Interface

The parallel interface consists of 8 bi-directional data lines (D0-D7), R/

W, and the CS. The R/W input High indicates a read operation from the

Graphic Display Data RAM (GDDRAM). R/W input Low indicates a write

to Display Data RAM or Internal Command Registers depending on the sta-

tus of D/C input. The CS input serves as data latch signal (clock). Refer to

AC operation conditions and characteristics section for Parallel Interface

Timing Description.

Data is directed to this module based upon the input of the D/C pin. If D/

C high, data is written to Graphic Display Data RAM (GDDRAM). D/C low

indicates that the input at D0-D7 is interpreted as a Command.

CE is the master chip selection signal. A High input enable the input lines

ready to sample signals. Reset is of same function as Power ON Reset

(POR). Once RES received the reset pulse, all internal circuitry will back to

its initial status. Refer to Command Description section for more informa-

tion.

Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be

displayed. The size of the RAM is determined by number of row times the

number of column (120x33 = 3960 bits). Figure 5 is a description of the

GDDRAM address map. For mechanical flexibility, re-mapping on both

Segment and Common outputs are provided.

Column address 00H

Column address 77H

(or column address 77H)

(or column address 00H)

Com0

(Com31)

Row 0

LSB

Page 1

MSB

LSB

Page 2

MSB

LSB

Page 3

MSB

LSB

Page 4

MSB

Row 31

Com31

(Com0)

Page 5

Com32

Row 32

LSB

Note : The configuration in parentheses represents the remapping of Row and Columns

Figure 5. Graphic Display Data RAM (GDDRAM) Address Map

MC141532A • MC141533A

12

MOTOROLA

Display Timing Generator

Annunciator Control Circuit

This module is an on chip low power RC oscillator circuitry (Figure 6).

The oscillator frequency can be selected in the range of 15 kHz to 50 kHz by

external resistor. One can enable the circuitry by software command. For

external clock provided, feed the clock to OSC2 and leave OSC1 open.

The LCD waveform of the 4 annunciators and BP are generated by this

module. The 4 independent annunciators are enabled by software com-

mand. Annunciator is also controlled by oscillator circuit too. Annunciator

output waveform shown in Figure 7.

Oscillator enable

Internal Oscillator Selected

enable1

enable2

enable

Buffer

Oscillation Circuit

MC141532A/33

External component

OSC2

OSC1

Feedback for internal oscillator

For external CLK input

Figure 6. Oscillator Circuitry

LCD Driving Voltage Generator

can be varied. Refer to the application circuit for details.

This module generates the LCD voltage needed for display output. It

takes a single supply input and generate necessary bias voltages. It consists

of :

All blocks can be individually turned off if external voltage generator is

employed.

1. Voltage Doubler and Voltage Tripler

33 Bit Latch / 120 Bit Latch

To generate the Vcc voltage. Either Doubler or Tripler can be enabled.

2. Voltage Regulator

Feedback gain control for initial LCD voltage. it can also be used with

external contrast control.

A 153 bit long register which carry the display signal information. First

33 bits are Common driving signals and other 120 bits are Segment driving

signals. Data will be input to the HV-buffer Cell for bumping up to the

required level.

3. Voltage Divider

Divide the LCD display voltage (V_LL2-V_LL6) from the regulator output.

This is a low power consumption circuit which can save the most display

current compare with traditional resistor ladder method.

4. Bias Ratio Selection circuitry

Software control of 1/5 and 1/7 bias ratio to match the characteristic of

LCD panel.

Level Selector

Level Selector is a control of the display synchronization. Display volt-

age can be separated into two sets and used with different cycles. Synchro-

nization is important since it selects the required LCD voltage level to the

HV Buffer Cell for output signal voltage pump.

5. Self adjust temperature compensation circuitry

Provide 4 different compensation grade selections to satisfy the various

liquid crystal temperature grades. The grading can be selected by soft-

ware control.

6. Contrast Control Block

Software control of 16 voltage levels of LCD voltage.

7. External Contrast Control

HV Buffer Cell (Level Shifter)

HV Buffer Cell works as a level shift-er which translates the low voltage

output signal to the required driving voltage. The output is shifted out with

an internal FRM clock which comes from the Display Timing Generator.

The voltage levels are given by the level selector which is synchronized

with the internal M signal.

By adjusting the gain control resistors connected externally, the contrast

LCD Panel Driving Waveform

The following is an example of how the Common and Segment drivers

may be connected to a LCD panel. The waveforms shown in Figure 7a, 7b

and 7c illustrate the desired multiplex scheme.

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

Figure 7a. LCD Display Example “0”

MOTOROLA

MC141532A • MC141533A

13

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

COM0

COM1

SEG0

SEG1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

Figure 7b. LCD Driving Signal from MC141532A/33A

TIME SLOT

1 2 3 4

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com0

“OFF” Pixel

VLL6

VLL5

VLL4

VLL3

VLL2

VLL1

-VLL2

-VLL3

-VLL4

-VLL5

-VLL6

Seg0-Com1

“ON” Pixel

Figure 7c. Effective LCD waveform on LCD pixel

MC141532A • MC141533A

14

MOTOROLA

Command Description

Set Display On/Off (Display Mode / Stand-by Mode)

With bit option = 1 in this command, the Save / Restore Column Address

command saves a copy of the Column Address of GDDRAM. With a bit

option = 0, this command restores the copy obtained from the previous exe-

cution of saving column address. This instruction is very useful for writing

full graphics characters that are larger than 8 pixels vertically.

The Display On command turns the LCD Common and Segment outputs

on and has no effect to the annunciator output. This command causes the

conversion of data in GDDRAM to necessary waveforms on the Common

and Segment driving outputs. The on-chip bias generator is also turned on

by this command. (Note : “Oscillator On” command should be sent before

“Display On” is selected)

Set Column Mapping

This instruction selects the mapping of GDDRAM to Segment drivers for

mechanical flexibility. There are 2 mappings to select:

1. Column 0 - Column 119 of GDDRAM mapped to Seg0-Seg119 respec-

tively;

2. Column 0 - Column 119 of GDDRAM mapped to Seg119-Seg0 respec-

tively.

The Display Off command turns the display off and the states of the LCD

driver are as follow during display off :

1. The Common and Segment outputs are fixed at V_LL1(V_SS).

2. The bias Voltage Generator is turned off.

3. The RAM and content of all registers are retained.

4. IC will accept new commands and data.

The status of the Annunciators and Oscillator are not affected by Display

Off command.

Com32 will not be affected by this command. Detailed information

please refer to section “Display Output Description”.

Set Row Mapping

Set GDDRAM Column Address

This instruction selects the mapping of GDDRAM to Common Drivers

for mechanical flexibility. There are 2 selected mappings:

1. Row 0 - Row 31 of GDDRAM to Com0 - Com31 respectively;

2. Row 0 - Row 31 of GDDRAM to Com31 - Com0 respectively.

Com32 will not be affected by this command. See section “Display Out-

put Description” for related information.

This command positions the address pointer on a column location. The

address can be set to location 00H-77H (120 columns). The column address

will be increased by one automatically after a read or write operation. Refer

to “Address Increment Table” and command “Set GDDRAM Page

Address”.

Set GDDRAM Page Address

Set Annunciator Control Signals

This command positions the row address to 1 of 5 possible positions in

GDDRAM. Refer to figure 5.

This command is used to control the active states of the 4 stand alone

annunciator drivers.

Master Clear GDDRAM

Set Oscillator Disable / Enable

This command is to clear the 480 byte GDDRAM by setting the RAM

data to zero. Issue this command followed by a dummy write command.

The RAM for icon line will not be affected by this command.

This command is used to either disable or enable the Oscillator. For using

internal or external oscillator, this command should be executed. The setting

for this command is not affected by command “Set Display On/Off” and

“Set Annunciator Control Signal”. See command “Set Internal / External

Oscillator” for more information

Master Clear Icons

This command is used to clear the data in page 5 of GDDRAM which

stores the icon line data. Before using this command, set the page address to

Page 5 by the command “Set GDDRAM Page Address”. A dummy write

data is also needed after this “Master Clear Icons” command to make the

clear icon action effective.

Set Internal / External Oscillator

This command is used to select either internal or external oscillator.

When Internal Oscillator is selected, feedback resistor between OSC1 and

OSC2 is needed. For external oscillation circuit, feed clock input signal to

OSC2 and leave OSC1 open.

Set Display with Icon Line

If 1/32 Mux selected, use this command change to 1/33 Mux for using

the Icon LIne. This command can also change Icon Display Mode to Nor-

mal Display Mode (1/32 or 1/33 MUX).

Set Clock Frequency

Use this command to choose from two different oscillation frequency

(50kHz or 38.4kHz) to get the 60 Hz frame frequency. With frequency high,

50 kHz clock frequency is preferred. 38.4kHz clock frequency (low fre-

quency) enable for power saving purpose.

Set Icon Display Mode

This command force the output to the icon display mode. Display on

Row 0 to Row 31 will be disabled.

Set DC/DC Converter On/Off

Use this command selects the Internal DC/DC Converter to generate the

V_CCfrom AV_DD. Disable the Internal DC/DC Converter if external Vcc is

provided.

Set Icon Line / Annunciator Contrast Level

The contrast of the icon line and annunciators in Icon Mode can be set by

this command. There are four levels to select from.

Set Voltage Doubler / Tripler

Set Vertical Scroll Value

Use this command to choose Doubler or Tripler when the Internal DC/

DC Converter is enabled.

This command is used to scroll the screen vertically with scroll value 0 to

31. With scroll value equals to 0, Row 0 of GDDRAM is mapped to Com0

and Row 1 through Row 31 are mapped to Com1 through Com31 respec-

tively. With scroll value equal to 1, Row 1 of GDDRAM is mapped to

Com0, then Row 2 through Row 31 will be mapped to Com1 through

Com30 respectively and Row 0 will be mapped to Com31. Com32 is not

affected by this command.

Set Internal Regulator On/Off

Choose bit option 0 to disable the Internal Regulator. Choose bit option 1

to enable Internal Regulator which consists of the internal contrast control

and temperature compensation circuits.

Set Internal Voltage Divider On/Off

Save / Restore GDDRAM Column Address

If the Internal Voltage Divider is disabled, external bias can be used for

MOTOROLA

MC141532A • MC141533A

15

V_LL6to V_LL2.If the Internal Voltage Divider is enabled, the internal circuit

will automatically select the correct bias level according to the number of

multiplex. Refer to command “Bias Ratio Select”.

Read Contrast Value

This command allows the user to read the current contrast level value.

With R/W input high (READ), D/C input low (COMMAND) and D7 D6

D5 D4 are equal to 0 0 0 1, the value of the internal contrast value can be

read on D0-D3 at the falling edge of CS.

Set Duty Cycle

This command is to select 16 mux or 32 mux display. When 16 mux is

enabled, the unused 16 common outputs will be swinging between VLL2

and VLL5 for dummy scan purpose and doubler will be used.

Set Temperature Coefficient

This command can select 4 different LCD driving voltage temperature

coefficients to match various liquid crystal temperature grades. Those tem-

perature coefficients are specified in Electrical Characteristics Tables.

Set Bias Ratio

This command sets the 1/5 bias or 1/7 bias for the divider output. The

selection should match the characteristic of LCD Panel.

Set I_DDReduction Mode On/Off

By using this command to reduce the display clock frequency by half.

Use in Icon Mode to reduce stand-by current.

Set Internal Contrast Control On/Off

This command is used to turn on or off the intrernal control of delta volt-

age of the bias voltages. With bit option = 1, the software selection for delta

bias voltage control is enabled. With bit option = 0, internal contrast control

is disabled.

Increase / Decrease Contrast Level

If the internal contrast control is enabled, this command is used to

increase or decrease the contrast level within the 16 contrast levels. The

contrast level starts from lowest value after POR.

Set Contrast Level

This command is to select one of the 16 contrast levels when internal

contrast control circuitry is in use.

MC141532A • MC141533A

16

MOTOROLA

COMMAND TABLE

Bit Pattern

Command

Comment

00000X₂X₁X₀

Set GDDRAM Page Address

Set GDDRAM Page Address using X₂X₁X₀as address bits.

X₂X₁X₀=000 : page 1 (POR)

X₂X₁X₀=001 : page 2

X₂X₁X₀=010 : page 3

X₂X₁X₀=011 : page 4

X₂X₁X₀=100 : page 5

000011X₁X₀

Set Icon Line / Annunciator Contrast Level Set one of the 4 available values to the icon and annunciator contrast,

using X₁X₀as data bits.

X₁X₀=00 (Von = 0.87V_DD

X₁X₀=01 (Von = 0.71V_DD

)

X₁X₀=10 (Von = 0.61V_DD) POR

X₁X₀=11 (Von = 0.55V_DD

)

0001X₃X₂X₁X₀

Set Contrast Level

Set one of the 16 available values to the internal contrast register, using

X₃X₂X₁X₀as data bits. The contrast register is reset to 0000 during

POR.

Read Contrast Value

With D/C pin input Low, R/W pin input high, and D7 D6 D5 D4 pins

equal to 0001 at the rising edge of CS, the value of the internal contrast

register will be latched out at D3 D2 D1 D0 pins, i.e. X₃X₂X₁X₀, at the

rising edge of CS.

0010000X₀

0010001X₀

0010010X₀

Set Voltage Doubler / Tripler

Set Column Mapping

Set Row Mapping

X₀=0: Select Voltage Tripler (POR)

X₀=1: Select Voltage Doubler

X₀=0 : Col0 to Seg0 (POR)

X₀=1 : Col0 to Seg119

X₀=0 : Row0 to Com0 (POR)

X₀=1: Row0 to Com31

0010011X₀

0010100X₀

Reserved

Set Display On/Off

X₀=0: display off (POR)

X₀=1: display on

0010101X₀

0010110X₀

Set DC/DC Converter On/Off

Set Internal Regulator On/Off

X₀=0: DC/DC Converter off (POR)

X₀=1: DC/DC Converter on

X₀=0: Internal Regulator off (POR)

X₀=1: Internal Regulator on

When the application employs external contrast control, the internal con-

trast control, temperature compensation and the Regulator must be

enabled.

0010111X₀

0011000X₀

Set Internal Voltage Divider On/Off

Set Internal Contrast Control On/Off

Set Clock Frequency

X₀=0: Internal Voltage Divider off (POR)

X₀=1: Internal Voltage Divider on

When an external bias network is preferred, the voltage divider should

be disabled.

X₀=0: Internal Contrast Control off (POR)

X₀=1: Internal Contrast Control on

Internal contrast circuits can be disabled if external contrast circuits is

preferred.

0011001X₀

0011010X₀

X₀=0 : low frequency (38.4kHz) (POR)

X₀=1 : high frequency (50kHz)

Save/Restore GDDRAM Column Address X₀=0 : restore address

X₀=1 : save address

00110110

00110111

Master Clear GDDRAM

Master Clear Icons

Master clear GDDRAM page 1 to 4

Master Clear of GDDRAM page 5.

GDDRAM page 5 should be selected and dummy write is required

0011100X₀

0011101X₀

Set Bias Ratio

Reserved.

X₀=0: set 1/7 bias (POR)

X₀=1: set 1/5 bias

X₀=0: normal operation (POR)

X₀=1: test mode

(Note: Make sure to set X₀=0 during application)

MOTOROLA

MC141532A • MC141533A

17

Bit Pattern

0011110X₀

Command

Comment

Set Display with Icon Line

X₀=0: set display mode without Icon Line

X₀=1: set display mode with Icon Line

00111110

Set Icon Display Mode

Set Vertical Scroll Value

Power saving icon display mode, Com0 to Com31 will be disabled

010X₄X₃X₂X₁X₀

Use X₄X₃X₂X₁X₀as number of lines to scroll.

Scroll value = 0 upon POR

01100A₁A₀X₀

Set Annunciator Control Signals

A₁A₀=00: select annunciator 1 (POR)

A₁A₀=01: select annunciator 2

A₁A₀=10: select annunciator 3

A₁A₀=11: select annunciator 4

X₀=0: turn selected annunciator off (POR)

X₀=1: turn selected annunciator on

0110100X₀

0110101X₀

011011X₁X₀

Set Duty Cycle

X₀=0: 1/32 duty and tripler enabled (POR)

X₀=1: 1/16 duty and doubler enabled

Set I_DDReduction Mode

Set Temperature Coefficient

X₀=0: Normal Mode

X₀=1: I_DDReduction Mode

X₁X₀=00 : 0.00% (POR)

X₁X₀=01 : -0.18%

X₁X₀=10 : -0.22%

X₁X₀=11 : -0.35%

0111000X₀

Increase / Decrease Contrast Value

X₀=0: Decrease by one level

X₀=1: Increase by one level

(Note: increment/decrement wraps round among the 16 contrast levels.

Start at the lowest level when POR.

0111001X₀

0111010X₀

0111011X₀

Reserved

X₀=0: normal operation (POR)

X₀=1: test mode select

(Note: Make sure to set X₀=0 during application)

0111100X₀

0111101X₀

Reserved

Set Internal / External Oscillator

X₀=0: Internal oscillator (POR)

X₀=1: External oscillator.

Internal oscillator circuit is automatically enabled if resistors are placed

at OSC1 and OSC2. For external oscillator, simply feed clock in OSC2.

0111110X₀

0111111X₀

Reserved

Set Oscillator Disable / Enable

X₀=0: oscillator disable (POR)

X₀=1: oscillator enable.

This is the master control fro oscillator circuitry. This command should

be issued after the “External / Internal Oscillator” command.

1X₆X₅X₄X₃X₂X₁X₀

Set GDDRAM Column Address

Set GDDRAM Column Address.

Use X₆X₅X₄X₃X₂X₁X₀as address bits.

Data Read / Write

To read data from the GDDRAM, input High to R/W pin and D/C pin. Data is valid at the falling edge of CS. And the GDDRAM column address pointer

will be increased by one automatically.

To write data to the GDDRAM, input Low to R/W pin and High to D/C pin. Data is latched at the falling edge of CS. And the GDDRAM column address

pointer will be increased by one automatically.

No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands Required for R/

W Actions on RAM” Table)

MC141532A • MC141533A

18

MOTOROLA

Address Increment Table (Automatic)

D/C

0

R/W

Comment

Address Increment

Remarks

0

1

0

1

Write Command

Read Command

Write Data

No

0

No

*1

*2

1

Yes

1

Read Data

Address Increment is done automatically data read write. The column address pointer of GDDRAM^*3is affected.

Remarks :

*1. Refer to the command “Read Contrast Value”.

*2. If write data is issued after Command Clear RAM, Address increase is not applied.

*3. Column Address will be wrapped round when overflow.

Power Up Sequence (Commands Required)

Command Required

POR Status

Remarks

Set Clock Frequency

Set Oscillator Enable

Set Annunciator Control Signals

Set Duty Cycle

Set Bias Ratio

Set Interna DC/DC Converter On

Set Internal Regulator On

Set Temperature Coefficient

Set Internal Contrast Control On

Increase Contrast Level

Set Internal Voltage Divider On

Set Segment Mapping

Set Common Mapping

Set Vertical Scroll Value

Set Display On

Low

Disable

Annunciator all Off

1/32 duty

1/7 bias

Off

TC=0%

Off

Contrast Level = 0

Off

Seg. 0 = Col. 0

Com. 0 = Row 0

Scroll Value = 0

Off

*1

*1, *3

*1, *2, *3

*1

Remarks :

*1 -- Required only if desired status differ from POR.

*2 -- Effective only if Internal Contrast Control is enabled.

*3 -- Effective only if Regulator is enabled.

Commands Required for Display Mode Setup

Display Mode

Commands Required

Set External / Internal Oscillator,

Set Oscillator Enable,

Set Display On.

(0111101X₀)*

(01111111)*

(00101001)*

Annunciator Display

Set External / Internal Oscillator,

Set Oscillator Enable,

(0111101X₀)*

(01111111)*

Set Annunciator Control Signal.

(01100A₁A₀X₀)*

Standby Mode 1.

Standby Mode 2.

Set Display Off,

Set Oscillator Disable.

(00101000)*

(01111110)*

Set External Oscillator,

Set Annunciator Control Signal,

Set Display Off,

(01111011)*

(01100A₁A₀X₀)*

(00101000)*

(01111111)*

Set Oscillator Enable.

Standby Mode 3.

Set Internal Oscillator,

Set Annunciator Control Signal,

Set Display Off,

(01111010)*

(01100A₁A₀X₀)*

(00101000)*

(01111111)*

Set Oscillator Enable.

Other Related Command with Display Mode : Set Duty Cycle, Set Column Mapping, Set Row Mapping, Set Vertical Scroll Value.

Commands Related to Internal DC/DC Converter :

Set Oscillator Disable / Enable, Set Internal Regulator On/Off, Set Duty Cycle, Set Temperature Coefficient, Set Internal Contrast Control On/Off, Increase /

Decrease Contrast Level, Set Internal Voltage Divider On/Off, Set Bias Ratio, Set Display On/Off, Set Internal / External Oscillator, Set Contrast Level, Set

Voltage Doubler / Tripler, Set 33 Mux Display Mode, Set Icon Display Mode

* No need to resend the command again if it is set previously.

MOTOROLA

MC141532A • MC141533A

19

Commands Required for R/W Actions on RAM

R/W Actions on RAMs

Commands Required

Read/Write Data from/to GDDRAM.

Set GDDRAM Page Address

Set GDDRAM Column Address

Read/Write Data

(000X₄X₃X₂X₁X₀)*

(1X₆X₅X₄X₃X₂X₁X₀)*

(X₇X₆X₅X₄X₃X₂X₁X₀)

Save/Restore GDDRAM Column Address.

Increase GDDRAM Address by One

Master Clear GDDRAM

Save/Restore GDDRAM Column Address.

Dummy Read Data

(0011010X₀)

(X₇X₆X₅X₄X₃X₂X₁X₀)

Master Clear GDDRAM

Dummy Write Data

(00110110)

(X₇X₆X₅X₄X₃X₂X₁X₀)

* No need to resend the command again if it is set previously.

Display Output Description

This is an example of output pattern on the LCD panel. Figure 8b and 8c are data map of GDDRAM and the output pattern on the LCD display with different

command enabled.

COM0

Content of GDDRAM

PAGE 1 Upper Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A

Lower Nibble 5 A 5 A 5 A 5 A 5 A - - - - - - - - - 5 A 5 A 5 A 5 A 5 A

PAGE 2 Upper Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C

Lower Nibble 3 3 C C 3 3 C C 3 3 - - - - - - - - - C C 3 3 C C 3 3 C C

PAGE 3 Upper Nibble 0 0 0 0 F F F F 0 0 - - - - - - - - - F F 0 0 0 0 F F F F

Lower Nibble F F F F 0 0 0 0 F F - - - - - - - - - 0 0 F F F F 0 0 0 0

PAGE 4 Upper Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0

Lower Nibble F F F F F F F F 0 0 - - - - - - - - - F F 0 0 0 0 0 0 0 0

PAGE 5 Upper Nibble 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - 0 0 0 0 0 0 0 0 0 0

Lower Nibble 0 0 0 1 1 1 0 0 0 0 - - - - - - - - - 0 0 0 0 1 1 1 0 0 0

COM31

COM32

Figure 8b

SEG0

SEG119

Figure 8a

Column remap disable

Row re-map disable

Column remap enable

Row re-map disable

Column remap disable

Row re-map enable

Column remap disable

Row re-map disable

Scroll Value = 31

Figure 8c. Examples of LCD display with different command enabled

MC141532A • MC141533A

20

MOTOROLA

MC141532AT TAB PACKAGE DIMENSION (1 OF 2)

To Be Updated

MOTOROLA

MC141532A • MC141533A

21

MC141532AT TAB PACKAGE DIMENSION (2 OF 2)

To Be Updated

MC141532A • MC141533A

22

MOTOROLA

Application Circuit

32/33 MUX Display with Analog Circuitry enabled, Tripler enabled and 1/7 bias

AV_DD

0.1mF

DV_DD

0.1mF

0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF

DVSS DVDD

AVDD AVSS

VLL2 VLL3 DUM2 DUM1 VLL4 VLL5 VLL6 VCC

COM0 to

COM32

RES

D/C

CS

SEG0 to

SEG119

To LCD

Panel

MC141532A/33A

CMOS

MPU/

MCU with

Parallel

Interface

CE

Annun 0-3

and BP

R/W

D0~D7

RAM

OSC2 OSC1 C+

C- VF

VR C2P C2N C1P C1N

760kW

EPROM

1MW

0.1mF

200kW

0.1mF

4.7mF

0.1mF

560pF

Remark :

1. VR and VF can be left open for Regulator Disable.

2. CS pin low at Standby Mode.

MOTOROLA

MC141532A • MC141533A

23

Application Circuit

16 MUX Display with Analog Circuitry enabled, Tripler Disabled and 1/5 bias

AV_DD

0.1mF

DV_DD

0.1mF

0.1mF 0.1mF 0.1mF

DVSS DVDD

AVDD AVSS

VLL2 VLL3 DUM2 DUM1 VLL4 VLL5 VLL6 VCC

COM0 to

COM32

RES

D/C

CS

SEG0 to

SEG119

To LCD

Panel

MC141532A/33A

CMOS

MPU/

MCU with

Parallel

Interface

CE

Annun 0-3

and BP

R/W

D0~D7

RAM

OSC2 OSC1 C+

C- VF

VR C2P C2N C1P C1N

760kW

EPROM

External Clock

0.1mF

200kW

0.1mF

4.7mF

560pF

Remark :

1. VR and VF can be left open for Regulator Disable.

2. CS pin low at Standby Mode.

MC141532A • MC141533A

24

MOTOROLA

Application Circuit

16/32/33 MUX Display with Analog Circuitry disabled

AV_DD

0.1mF

DV_DD

0.1mF

V_CC

DVSS DVDD

AVDD AVSS

VLL2 VLL3 DUM2 DUM1 VLL4 VLL5 VLL6 VCC

COM0 to

COM32

RES

D/C

CS

SEG0 to

SEG119

To LCD

Panel

MC141532A/33A

CMOS

MPU/

MCU with

Parallel

Interface

CE

Annun 0-3

and BP

R/W

D0~D7

RAM

OSC1

C+

C-

VF

VR

C2P

C2N

C1N

OSC2

C1P

EPROM

External Clock

Remark :

1. VR and VF can be left open for Regulator Disable.

2. CS pin low at Standby Mode.

MOTOROLA

MC141532A • MC141533A

25

Die Pad Co-ordinate for MC141532A

Pad

1

2

3

4

5

6

7

Name

Ann0

Ann1

Ann2

Ann3

BP

DVdd

RES

DVss

D/C

Pad

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100 Com11

101 Com12

102 Com13

103 Com14

104 Com15

105 Com16

106 Com17

107 Com18

108 Com19

109 Com20

110 Com21

111 Com22

112 Com23

113 Com24

114 Com25

115 Com26

116 Com27

117 Com28

118 Com29

119 Com30

120 Com31

121 Com32

Name

DVss

C+

DVss

C-

DVss

VCC

DVss

VF

Pad

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Name

Seg0

Seg1

Seg2

Seg3

Seg4

Seg5

Seg6

Seg7

Pad

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222 Seg100

223 Seg101

224 Seg102

225 Seg103

226 Seg104

227 Seg105

228 Seg106

229 Seg107

230 Seg108

231 Seg109

232 Seg110

233 Seg111

234 Seg112

235 Seg113

236 Seg114

237 Seg115

238 Seg116

239 Seg117

240 Seg118

241 Seg119

Name

Seg59

Seg60

Seg61

Seg62

Seg63

Seg64

Seg65

Seg66

Seg67

Seg68

Seg69

Seg70

Seg71

Seg72

Seg73

Seg74

Seg75

Seg76

Seg77

Seg78

Seg79

Seg80

Seg81

Seg82

Seg83

Seg84

Seg85

Seg86

Seg87

Seg88

Seg89

Seg90

Seg91

Seg92

Seg93

Seg94

Seg95

Seg96

Seg97

Seg98

Seg99

X (mm)

-4803.6

-4702.0

-4600.4

-4498.8

-4397.2

-4295.6

-4194.0

-4092.4

-3990.8

-3889.2

Y (mm)

-526.6

-591.8

-530.4

X (mm)

2472.8

2574.4

2676.0

2777.6

2879.2

2980.8

3082.4

3184.0

3285.6

3387.2

3488.8

3590.4

3692.0

3793.6

3869.6

3945.6

4021.6

4097.6

4173.6

4249.6

4325.6

4401.6

4477.6

4553.6

4629.6

4705.6

4835.2

5174.4

4771.2

4695.2

4619.2

4518.0

4442.0

4366.0

4290.0

4214.0

4138.0

4062.0

3986.0

3910.0

3834.0

3758.0

3682.0

3606.0

3530.0

3454.0

3378.0

3302.0

Y (mm)

-530.4

-551.0

-550.6

-497.8

-408.8

-332.8

-256.8

-180.8

-104.8

-28.8

X (mm)

3217.4

3141.4

3065.4

2989.4

2913.4

2837.4

2761.4

2685.4

2609.4

2533.4

2457.4

2381.4

2305.4

2229.4

2153.4

2077.4

2001.4

1925.4

1849.4

1773.4

1697.4

1621.4

1545.4

1469.4

1393.4

1317.4

1241.4

1165.4

1089.4

1013.4

937.4

Y (mm)

492.7

X (mm)

-1266.6

-1342.6

-1418.6

-1494.6

-1570.6

-1646.6

-1722.6

-1798.6

-1874.6

-1950.6

-2026.6

-2102.6

-2178.6

-2254.6

-2330.6

-2406.6

-2482.6

-2558.6

-2634.6

-2710.6

-2786.6

-2862.6

-2938.6

-3014.6

-3090.6

-3166.6

-3242.6

-3318.6

-3394.6

-3470.6

-3546.6

-3622.6

-3698.6

-3774.6

-3850.6

-3926.6

-4002.6

-4078.6

-4154.6

-4230.6

-4306.6

-4382.6

-4458.6

-4534.6

-4619.2

-4695.2

-4771.2

-5174.4

Y (mm)

492.7

516.2

427.2

351.2

275.2

199.2

123.2

47.2

8

9

10

DVss

VR

Seg8

Seg9

R/W

11 CS(CLK) -3787.6

AVss

OSC1

DVss

Test1

Test2

Com32

Com0

Com1

Com2

Com3

Com4

Com5

Com6

Com7

Com8

Com9

Com10

Seg10

Seg11

Seg12

Seg13

Seg14

Seg15

Seg16

Seg17

Seg18

Seg19

Seg20

Seg21

Seg22

Seg23

Seg24

Seg25

Seg26

Seg27

Seg28

Seg29

Seg30

Seg31

Seg32

Seg33

Seg34

Seg35

Seg36

Seg37

Seg38

Seg39

Seg40

Seg41

Seg42

Seg43

Seg44

Seg45

Seg46

Seg47

Seg48

Seg49

Seg50

Seg51

Seg52

Seg53

Seg54

Seg55

Seg56

Seg57

Seg58

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

DVss

D0

D1

D2

D3

D4

D5

D6

D7

-3686.0

-3584.4

-3482.8

-3381.2

-3279.6

-3178.0

-3076.4

-2974.8

-2873.2

-2771.6

-2670.0

-2498.3

-873.6

-797.6

-721.6

-645.6

-569.6

-493.6

-417.6

-341.6

-265.6

-189.6

-113.6

-37.6

CE

DVss

AVdd

C1P

861.4

785.4

709.4

633.4

557.4

481.4

405.4

329.4

253.4

177.4

101.4

25.4

47.2

38.4

114.4

190.4

266.4

342.4

418.4

494.4

644.0

123.2

199.2

275.2

351.2

427.2

516.2

492.7

745.6

847.2

948.8

-50.6

-126.6

-202.6

-278.6

-354.6

-430.6

-506.6

-582.6

-658.6

-734.6

-810.6

-886.6

-962.6

-1038.6

-1114.6

-1190.6

C1N

C2P

1050.4

1152.0

1253.6

1355.2

1456.8

1558.4

1660.0

1761.6

1863.2

1964.8

2066.4

2168.0

2269.6

2371.2

C2N

VLL2

VLL3

DVss

VLL4

VLL5

VLL6

DUM1

DVss

OSC2

DVss

DUM2

-28.8

-104.8

-180.8

-256.8

-332.8

-408.8

-497.8

Gold Bump Size

Die Size

Bump Size X

Bump Size Y

Pad

X (mm)

Y (mm)

1522.0

(mm)

66.5

49.0

66.5

49.0

(mm)

1-23

24-42

43-74

75-85

86

66.5

39.8

66.5

107.0

10881.0

87

No Gold Bump

88

107.0

49.0

74.5

49.0

74.5

107.0

74.5

49.0

89-100

101

102-227

228

107.0

229-240

MC141532A • MC141533A

26

MOTOROLA

Die Pad Co-ordinate for MC141533A

Pad

1

2

3

4

5

6

7

Name

Ann0

Ann1

Ann2

Ann3

BP

DVdd

RES

DVss

D/C

Pad

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

Name

DVss

C+

DVss

C-

DVss

VCC

DVss

VF

Pad

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Name

Seg17

Seg18

Seg19

Seg20

Seg21

Seg22

Seg23

Seg24

Seg25

Seg26

Seg27

Seg28

Seg29

Seg30

Seg31

Seg32

Seg33

Seg34

Seg35

Seg36

Seg37

Seg38

Seg39

Seg40

Seg41

Seg42

Seg43

Seg44

Seg45

Seg46

Seg47

Seg48

Seg49

Seg50

Seg51

Seg52

Seg53

Seg54

Seg55

Seg56

Seg57

Seg58

Seg59

Seg60

Seg61

Seg62

Seg63

Seg64

Seg65

Seg66

Seg67

Seg68

Seg69

Seg70

Seg71

Seg72

Seg73

Seg74

Seg75

Pad

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205 Seg100

206 Seg101

207 Seg102

208 Seg103

209 Seg104

210 Seg105

211 Seg106

212 Seg107

213 Seg108

214 Seg109

215 Seg110

216 Seg111

217 Seg112

218 Seg113

219 Seg114

220 Seg115

221 Seg116

222 Seg117

223 Seg118

224 Seg119

225 Com32

226 Com31

227 Com30

228 Com29

229 Com28

230 Com27

231 Com26

232 Com25

233 Com24

234 Com23

235 Com22

236 Com21

237 Com20

238 Com19

239 Com18

240 Com17

241 Com16

Name

Seg76

Seg77

Seg78

Seg79

Seg80

Seg81

Seg82

Seg83

Seg84

Seg85

Seg86

Seg87

Seg88

Seg89

Seg90

Seg91

Seg92

Seg93

Seg94

Seg95

Seg96

Seg97

Seg98

Seg99

X (mm)

-4803.6

-4702.0

-4600.4

-4498.8

-4397.2

-4295.6

-4194.0

-4092.4

-3990.8

-3889.2

Y (mm)

-526.6

-591.8

-530.4

X (mm)

2472.8

2574.4

2676.0

2777.6

2879.2

2980.8

3082.4

3184.0

3285.6

3387.2

3488.8

3590.4

3692.0

3793.6

3869.6

3945.6

4021.6

4097.6

4173.6

4249.6

4325.6

4401.6

4477.6

4553.6

4629.6

4705.6

4835.2

5174.4

4771.2

4695.2

4619.2

4518.0

4442.0

4366.0

4290.0

4214.0

4138.0

4062.0

3986.0

3910.0

3834.0

3758.0

3682.0

3606.0

3530.0

3454.0

3378.0

3302.0

Y (mm)

-530.4

-551.0

-550.6

-497.8

-408.8

-332.8

-256.8

-180.8

-104.8

-28.8

X (mm)

3217.4

3141.4

3065.4

2989.4

2913.4

2837.4

2761.4

2685.4

2609.4

2533.4

2457.4

2381.4

2305.4

2229.4

2153.4

2077.4

2001.4

1925.4

1849.4

1773.4

1697.4

1621.4

1545.4

1469.4

1393.4

1317.4

1241.4

1165.4

1089.4

1013.4

937.4

Y (mm)

492.7

X (mm)

-1266.6

-1342.6

-1418.6

-1494.6

-1570.6

-1646.6

-1722.6

-1798.6

-1874.6

-1950.6

-2026.6

-2102.6

-2178.6

-2254.6

-2330.6

-2406.6

-2482.6

-2558.6

-2634.6

-2710.6

-2786.6

-2862.6

-2938.6

-3014.6

-3090.6

-3166.6

-3242.6

-3318.6

-3394.6

-3470.6

-3546.6

-3622.6

-3698.6

-3774.6

-3850.6

-3926.6

-4002.6

-4078.6

-4154.6

-4230.6

-4306.6

-4382.6

-4458.6

-4534.6

-4619.2

-4695.2

-4771.2

-5174.4

Y (mm)

492.7

516.2

427.2

351.2

275.2

199.2

123.2

47.2

8

9

10

DVss

VR

R/W

11 CS(CLK) -3787.6

AVss

OSC1

DVss

Test2

Test1

Com32

Com0

Com1

Com2

Com3

Com4

Com5

Com6

Com7

Com8

Com9

Com10

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

DVss

D0

D1

D2

D3

D4

D5

D6

D7

-3686.0

-3584.4

-3482.8

-3381.2

-3279.6

-3178.0

-3076.4

-2974.8

-2873.2

-2771.6

-2670.0

-2498.3

-873.6

-797.6

-721.6

-645.6

-569.6

-493.6

-417.6

-341.6

-265.6

-189.6

-113.6

-37.6

CE

DVss

AVdd

C1P

861.4

785.4

709.4

633.4

557.4

481.4

405.4

329.4

253.4

177.4

101.4

25.4

47.2

38.4

114.4

190.4

266.4

342.4

418.4

494.4

644.0

123.2

199.2

275.2

351.2

427.2

516.2

492.7

100 Com11

101 Com12

102 Com13

103 Com14

104 Com15

745.6

847.2

948.8

-50.6

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

Seg0

Seg1

Seg2

Seg3

Seg4

Seg5

Seg6

Seg7

Seg8

-126.6

-202.6

-278.6

-354.6

-430.6

-506.6

-582.6

-658.6

-734.6

-810.6

-886.6

-962.6

-1038.6

-1114.6

-1190.6

C1N

C2P

1050.4

1152.0

1253.6

1355.2

1456.8

1558.4

1660.0

1761.6

1863.2

1964.8

2066.4

2168.0

2269.6

2371.2

C2N

VLL2

VLL3

DVss

VLL4

VLL5

VLL6

DUM1

DVss

OSC2

DVss

DUM2

Seg9

Seg10

Seg11

Seg12

Seg13

Seg14

Seg15

Seg16

-28.8

-104.8

-180.8

-256.8

-332.8

-408.8

-497.8

Gold Bump Size

Die Size

Bump Size X

Bump Size Y

Pad

X (mm)

Y (mm)

1522.0

(mm)

66.5

49.0

66.5

49.0

(mm)

1-23

24-42

43-74

75-85

86

66.5

39.8

66.5

107.0

10881.0

87

No Gold Bump

88

107.0

49.0

74.5

49.0

74.5

107.0

74.5

49.0

89-100

101

102-227

228

107.0

229-240

MOTOROLA

MC141532A • MC141533A

27

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of

its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and

all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including

“Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of oth-

ers.Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its offices,

employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manu-

facture of the part. Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC141532A/33A


型号：	MCC141533AZ
厂家：	MOTOROLA
描述：	Liquid Crystal Driver, 153-Segment, CMOS, GOLD BUMP, DIE-241 驱动接口集成电路
文件：	总28页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCC141533AZ [MOTOROLA]

相关型号：

MCC141533Z

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