MCF5275CVM166 [MOTOROLA]
MCF5275 Integrated Microprocessor Family Hardware Specification; MCF5275集成的微处理器系列硬件规格
| 型号： | MCF5275CVM166 |
| 厂家： | 
MOTOROLA |
| 描述： | MCF5275 Integrated Microprocessor Family Hardware Specification |
| 文件： | 总76页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCF5275EC/D
Rev. 1.1, 9/2004
Freescale Semiconductor
Hardware Specification
MCF5275 Integrated
Microprocessor Family Hardware
Specification
32-Bit Embedded Controller Division
Table of Contents
The MCF5275 family is a highly integrated
implementation of the ColdFire family of reduced
®
1
2
3
4
5
6
7
8
9
MCF5275 Family Configurations..................... 2
Block Diagram ................................................. 3
Features .......................................................... 5
Signal Descriptions........................................ 17
Chip Configuration......................................... 32
Design Recommendations ............................ 34
Pinout ............................................................ 42
Mechanicals .................................................. 45
Ordering Information ..................................... 47
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275
family includes the MCF5275, MCF5275L, MCF5274
and MCF5274L microprocessors. The differences
between these parts are summarized in Table 1. This
document is written from the perspective of the
MCF5275 and unless otherwise noted, the information
applies also to the MCF5275L, MCF5274 and
MCF5274L.
10 Preliminary Electrical Characteristics............ 47
11 Device/Family Documentation List ................ 74
12 Document Revision History........................... 74
The MCF5275 family delivers a new level of
performance and integration on the popular version 2
ColdFire core with up to 159 (Dhrystone 2.1) MIPS @
166MHz. These highly integrated microprocessors build
upon the widely used peripheral mix on the popular
MCF5272 ColdFire microprocessor (10/100 Mbps
Ethernet MAC and USB device) by adding a second
10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)
and hardware encryption (MCF5275L and MCF5275).
In addition, the MCF5275 family features an Enhanced
Multiply Accumulate Unit (EMAC), large on-chip
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
• Preliminary
MCF5275 Family Configurations
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory
controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file
management, connectivity, data buffering, and user interface, as well as signal processing in a variety of
key markets such as security, imaging, networking, gaming, and medical. This leading package of
integration and high performance allows fast time to market through easy code reuse and extensive third
party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com.
1 MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
5274L
5275L
5274
5275
ColdFire Version 2 Core with EMAC (Enhanced
Multiply-Accumulate Unit)
x
x
x
x
System Clock
up to 166 MHz
up to 159
Performance (Dhrystone 2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
16 Kbytes (configurable)
64 Kbytes
Interrupt Controllers (INTC)
Edge Port Module (EPORT)
External Interface Module (EIM)
4-channel Direct-Memory Access (DMA)
DDR SDRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module (WDT)
4-channel Programmable Interval Timer Module (PIT)
32-bit DMA Timers
2
x
x
x
x
1
x
x
4
x
x
3
x
4
x
x
2
x
x
x
x
1
x
x
4
x
x
3
x
4
x
x
2
x
x
x
x
2
x
x
4
x
x
3
x
4
x
x
2
x
x
x
x
2
x
x
4
x
x
3
x
4
x
x
USB
QSPI
UART(s)
I2C
PWM
General Purpose I/O Module (GPIO)
CIM = Chip Configuration Module + Reset Controller Module
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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2
Preliminary
BlockDiagram
Table 1. MCF5275 Family Configurations
Module
5274L
5275L
5274
5275
Debug BDM
x
x
x
x
x
x
x
x
x
JTAG - IEEE 1149.1 Test Access Port
Hardware Encryption
Package
—
—
x
196
196
256
256
MAPBGA
MAPBGA
MAPBGA MAPBGA
2 Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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3
Preliminary
Block Diagram
DDR
EIM
QSPI
I2C_SDA
I2C_SCL
TXDx
CHIP
SELECTS
(To/From SRAM backdoor)
RXDx
EBI
RTSx
INTC0 INTC1
Arbiter
CTSx
DTOUTx
DTINx
FAST ETHERNET
CONTROLLER
(FEC0)
FEC0
FEC1
USB
(To/From PADI)
(To/From PADI)
UART
0
UART UART
I2C
PWMx
QSPI
FAST ETHERNET
CONTROLLER
(FEC1)
1
2
SDRAMC
D[31:16]
A[23:0]
DTIM
3
DTIM DTIM
DTIM
0
R/
W
1
2
CS[3:0]
(To/From
PADI)
4 CH DMA
DREQ[1:0]
TA
JTAG_EN
TRST
V2 ColdFire CPU
DACK[3:0]
TCLK
JTAG
TAP
TMS
TDI
EMAC
DIV
TDO
TSIZ[1:0]
JTAG_EN
TEA
BS[3:2]
64 Kbytes
SRAM
(To/From
PADI)
16 Kbytes
CACHE
(8Kx16)x4
(1Kx32)x4
4 CH PWM
(To/From PADI)
PORTS
(GPIO)
CIM
(To/From Arbiter backdoor)
Watchdog
Timer
SKHA
RNGA
MDHA
PLL
CLKGEN
PIT0
PIT1
PIT2
PIT3
USB 2.0
(To/From INTC)
Full Speed
(To/From PADI)
Edge
Port
Cryptography
Modules
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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4
Preliminary
Features
3 Features
This document contains information on a new product. Specifications and information herein are subject
to change without notice.
3.1 Feature Overview
•
ColdFire version 2 variable-length RISC processor
— Static operation
— 32-bit address and data path on-chip
— 166/133 MHz processor core and 83/66.5 MHz bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Enhanced multiply accumulate unit (eMAC) for DSP and fast multiply operations
System debug support
•
— Real time trace for determining dynamic execution path while in emulator mode
— Background debug mode (BDM) for debug features while halted
— Real time debug support, with two user visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
•
•
•
On chip memories
— 16 Kbyte cache, configurable as I-cache or I-cache and D-cache
— 64 Kbyte dual-ported SRAM on CPU internal bus with standby power supply support
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
Two Fast Ethernet Media Access Controllers (FEC MAC)
— 10 base T capability, half or full duplex
— 100 base T capability, half or full duplex throughput
— On chip transmit and receive FIFOs
— Built-in DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII)
•
USB Device Module
— Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices
— Full compliance with the Universal Serial Bus Specification, Revision 2.0
— Automatic hardware processing of USB standard device requests
— Supports external USB transceiver
— Protocol control and administration for up to four endpoints (programmable types)
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Preliminary
Features
— One FIFO RAM per endpoint (2-Kbyte total)
— Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus
— Remote wake-up
•
•
Hardware cryptography accelerator (optional)
— Random number generator
— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator
Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
— Serial communication channel
— 16-bit divider for clock generation
— Internal channel control logic
— Interrupt control logic
— Maskable interrupts
— DMA support
— Programmable clock-rate generator
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
— Transmit and receive FIFO buffers
2
•
•
I C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
2
— Fully compatible with industry-standard I C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfer
— Up to four chip selects available
— Master operation
— Programmable master bit rates
— Up to 16 preprogrammed transfers
Four 32-bit Timers with DMA request capability
Pulse width modulation (PWM) unit
— Four identical channels
•
•
•
Software Watchdog Timer
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Preliminary
Features
— 16-bit counter
— Low power mode support
•
Phase Locked Loop (PLL)
— Reference crystal 8 to 25 MHz
— Low power modes supported
— Separate CLKOUT and DDR_CLKOUT signals
Four Programmable Interrupt Timers (PITs)
Interrupt Controllers (x2)
•
•
— Support for 58 independent interrupt sources, organized as follows:
– 51 fully-programmable interrupt sources
– 7 fixed-level external interrupt sources
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
DMA Controller
•
— Four fully programmable channels
— Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability
— Source/destination address pointers that can increment or remain constant
— 24-bit transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Two-bus-clock internal access
— External request pins for each channel
•
External Memory Interface
— External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM,
flash, ROM, etc.)
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 16-bit external bidirectional data bus
— 24-bit address bus
— Eight chip selects
— Byte/write enables
— Ability to boot from external memories that are 8 or 16 bits wide
DDR SDRAM controller
•
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Features
— Supports 16-bit wide memory devices
— Supports Dual Data Rate (DDR) SDRAM.
— Page mode support
— Programmable refresh interval timer.
— Sleep mode and self-refresh.
— Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer.
— Memory sizes from 8 Mbyte to 128 MByte (per chip select)
— 166 MHz data transfer rate (DDR)
— Two independent chip selects
•
•
Reset
— Separate Reset In and Reset Out signals
— Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock)
— Status flag indication of source of last reset
Chip Configurations
— System configuration during reset
— Bus Monitor, Abort Monitor
— Configurable output pad drive strength
— Unique Part Identification and Part Revision Numbers
General Purpose I/O interface
•
•
— Up to 69 bits of general purpose I/O
— Coherent 32-bit control
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
— Unique JTAG Part Identification and Part Revision Numbers
3.2 V2 Core Overview
The ColdFire V2 core is comprised of two separate pipelines that are decoupled by an instruction buffer.
The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and
instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched
instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline
stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX)
performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
V2 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing
capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations,
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Features
with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned
integers as well as signed fractional operands as well as a complete set of instructions to process these data
types. The EMAC provides superb support for execution of DSP operations within the context of a single
processor at a minimal hardware cost.
3.3 Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface
provided on Motorola’s 683xx family of parts.
The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers
(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask
register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through
the dedicated debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address, data, and
PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to
generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug
data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
data, and branch target addresses defining processor activity at the CPU’s clock rate.
3.4 JTAG
The MCF5275 microprocessors support circuit board test strategies based on the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port
(TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass
register, a 326-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the
device’s pins into one shift register. Test logic, implemented using static logic design, is independent of
the device system logic.
The MCF5275 implementation can do the following:
•
•
Perform boundary-scan operations to test circuit board electrical continuity
Sample MCF5275 system pins during operation and transparently shift out the result in the
boundary scan register
•
Bypass the MCF5275 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
•
•
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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9
Preliminary
Features
3.5 On-chip Memories
The 64 Kbyte data RAM and the 16 Kbyte cache RAM for the processors are built using a RAM compiler.
Both RAM blocks connect directly to the RAM controller via a standard single-port synchronous SRAM
interface.
3.5.1 Cache
The 16-Kbyte cache can be configured into one of three possible organizations: a 16-Kbyte instruction
cache, a 16-Kbyte data cache or a split 8-Kbyte instruction/8-Kbyte data cache. The configuration is
software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all
configurations, the cache is a direct-mapped single-cycle memory.
3.5.2 SRAM
The SRAM module provides a general-purpose 64-Kbyte memory implemented as four 16-Kbyte blocks
that the ColdFire core can access in a single cycle. The location of the memory block can be set to any
64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses
or memory-referencing commands from the debug module.
The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FECs.
The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer
schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize
system performance. As an example, system performance can be increased significantly if Ethernet
packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
3.6 Power Management
The MCF5275 family incorporates several low power modes of operation which are entered under
program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit
monitors the input supply and forces an MCU reset as the supply voltage rises.
3.7 Fast Ethernet Controller (FEC)
The MCF5275 family contains up to two 10/100 BaseT fast Ethernet Controllers (FECs). Refer to Table 1
for device configurations.
Each FEC includes these distinctive features:
•
•
•
IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
Built-in FIFO and DMA controller
Support for different Ethernet physical interfaces:
— 100Mbps IEEE 802.3 MII
— 10Mbps IEEE 802.3 MII
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Features
•
•
Support for full-duplex operation (200Mbps throughput) with a minimum system clock of
50MHz
Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of
25MHz
•
•
•
•
IEEE 802.3 full duplex flow control
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
Retransmission from transmit FIFO following a collision (no system bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no system bus utilization)
•
Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
•
•
RMON and IEEE statistics
Interrupts for network activity and error conditions
3.8 Universal Serial Bus (USB)
The USB controller supports device mode data communications with a USB host (typically a PC).
The programmable USB registers allow the user to enable or disable the module, control characteristics of
individual endpoints, and monitor traffic flow through the module without ever seeing the low-level details
of the USB protocol.
The USB module provides the following features to the user:
•
•
•
•
Supports full-speed 12-Mbps USB devices and low-speed 1.5-Mbps devices
Full compliance with the Universal Serial Bus Specification, Revision 2.0
Automatic hardware processing of USB standard device requests
USB device controller with protocol control and administration for up to eight endpoints, 16
interfaces, and 16 configurations. Endpoint types are programmable with support for up to eight
control, interrupt, bulk, or isochronous endpoints
•
•
•
•
Independent interrupts for each endpoint
Supports remote wakeup via a register bit
Detects start-of-frame and missed start-of-frame for isochronous endpoint synchronization
Notification of start-of-frame, reset, suspend, and resume events
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Features
3.9 Cryptography
Some of the MCF5275 family devices incorporate small, fast, and dedicated hardware accelerators for
random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher
functions. This allows for the implementation of common Internet security protocol cryptography
operations with performance well in excess of software-only algorithms. Refer to Table 1 for device
configurations.
3.10 UARTs
The MCF5275 family of microprocessors each contain three (3) UARTs that function independently. Any
of the three UARTs can be clocked by the system bus clock, eliminating the need for an external crystal.
Each UART module contains the following major functional features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Serial communication channel
16-bit divider for clock generation
Internal channel control logic
Interrupt control logic
Maskable interrupts
DMA support
Programmable clock-rate generator
Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
Up to 2 stop bits in 1/16 increments
Error-detection capabilities
Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
Transmit and receive FIFO buffers
UART Modes of Operation:
— Full-duplex
— Auto-echo loopback
— Local loopback
— Remote loopback
3.11 I2C Bus
2
The I C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
2
communications over a short distance between many devices. The flexible I C allows additional devices
to be connected to the bus for expansion and system development.
The I2C includes these distinctive features:
•
Compatibility with I2C bus standard
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Features
•
•
•
•
•
•
•
•
•
•
•
Multiple-master operation
Software programmable for one of 64 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven, byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
DMA support
3.12 QSPI
The queued serial peripheral interface module provides a serial peripheral interface with queued transfer
capability. It allows users to enqueue up to 16 transfers at once, eliminating CPU intervention between
transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.
The QSPI contains the following features:
•
•
•
•
•
•
•
Programmable queue to support up to 16 transfers without user intervention
Supports transfer sizes of 8 to 16 bits in 1-bit increments
Four peripheral chip-select lines
Baud rates from 162.1 Kbps to 20.75 Mbps at 83 MHz
Programmable delays before and after transfers
Programmable clock phase and polarity
Supports wraparound mode for continuous transfers
3.13 DMA Timers (DTIM0-DTIM3)
There are four independent, general purpose 32-bit platform timers (DTIM0, DTIM1, DTIM2, DTIM3)
on the MCF5275 family of microprocessors. The output of an 8-bit prescaler clocks each timer.
Each of the platform timer modules has these distinctive features:
•
•
•
•
•
•
Programmable sources for the clock input, including external clock
Input capture capability with programmable trigger edge on input pin
Output compare with programmable mode for the output pin
Free run and restart modes
Maskable interrupts on input capture or reference compare
DMA support
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Features
Each of the four timer modules has four operating modes:
•
•
•
Capture mode
Output mode
Reference compare mode
3.14 Pulse Width Modulation (PWM) Module
The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having
programmable duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog
converter.
The PWM module has six channels with independent control of left and center aligned outputs on each
channel. The MCF5275 family uses four of these channels namely 0, 1, 2 and 3. The emergency shutdown
functionality (channel 5 only) is not used for the MCF5275 family.
Each of the PWM channels has a programmable period and duty cycle as well as a dedicated counter. A
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
Summary of the main features include:
•
•
•
•
•
Independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective
period is reached (PWM counter reaches zero) or when the channel is disabled.
•
•
•
•
Programmable center or left aligned outputs on individual channels
16-bit PWM resolution available by concatenating 8-bit channels
Four clock sources (A, B, SA and SB) provide for a wide range of frequencies.
Programmable Clock Select Logic
3.15 Software Watchdog Timer (WDT)
The watchdog timer is a 16-bit timer for helping software recover from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software
must periodically restart the countdown.
3.16 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL),
reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
14
Freescale Semiconductor
Preliminary
Features
the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
3.17 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers which support 58 interrupt sources on the MCF5275. Each interrupt
controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique
interrupt vector, and 51 of the 58 sources of a given controller provide a programmable level [1-7] and
priority within the level.
3.18 Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMA) Module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four channels that allow byte, word, or
longword operand transfers. These transfers can be single or dual address to off-chip devices or dual
address to on-chip devices.
The DMA contains the following features:
•
•
•
•
•
•
•
•
•
•
Four fully independent, programmable DMA controller channels/bus modules
Auto-alignment feature for source or destination accesses
Single- and dual-address transfers
Up to four external request pins (DREQ[3:0])
Channel arbitration on transfer boundaries
Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer
Supports continuous-mode and cycle-steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
Provide two clock data transfers
3.19 External Interface Module (EIM)
The external interface module on MCF5275 devices handles the transfer of information between the
internal core and memory, peripherals, or other processing elements in the external address space.
Programmable chip select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select is general purpose;
however, any one of the chip selects can be programmed to provide read and write enable signals suitable
for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is
programmable on all chip selects, and further decoding is available for protection from user mode access
or read-only access.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
15
Preliminary
Features
The key features of the EIM are summarized below:
•
Eight independent, user-programmable chip-select signals (CS[7:0]) that interface with various
memory types and peripherals
•
•
•
Address masking for 64 Kbyte to 4 gigabyte memory block sizes
Programmable wait states and port sizes
External master access to chip selects
3.20 Double Data Rate (DDR) Synchronous DRAM
(SDRAM) Controller
The SDRAMC provides a 16-bit glueless external interface to double-data-rate (DDR) SDRAM memory
devices. It is responsible for providing address, data and control signals for up to two independent
chip-selects.
The SDRAMC includes the following features:
•
•
•
•
•
Supports a glueless interface to DDR SDRAMs
16-bit fixed memory port width
32-bit data bus interface to Coldfire core
16 bytes (8 beat x 16-bit) critical word first burst transfer
Up to 14 row address lines, up to 12 column address lines, maximum of two chip selects. The
maximum row bits plus column bits is 24.
•
•
Supported SDRAM devices include: 8, 16, 32, 64, and 128Mbyte per chip select
Minimum memory configuration of 8 Mbyte—12 bit row address (RA), 8 bit column address
(CA), 2 bit bank address (BA) and one chip select
•
•
•
Supports page mode to maximize the data rate
Supports sleep mode and self-refresh mode
Error detect and parity check are not supported
3.21 Resets
The Reset Controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and then to keep a history of what caused the reset.
The MCF5275 family has six (6) sources of reset:
•
•
•
•
•
•
External
Power On Reset (POR)
Watchdog timer
PLL Loss of Lock
PLL Loss of Clock
Software
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
16
Preliminary
SignalDescriptions
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also
software-readable status flags indicating the cause of the last reset.
3.22 General Purpose I/O
Most peripheral I/O pins on MCF5275 devices are muxed with GPIO, adding flexibility and usability to
all signals on the chip.
4 Signal Descriptions
Table 2 lists the signals for the MCF5275 in functional group order.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. Signal Information and Muxing
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
Reset
RESET
—
—
—
—
—
—
I
1
1
1
1
RSTOUT
O
Clock
EXTAL
XTAL
—
—
—
—
—
—
—
—
—
I
1
1
1
1
1
1
O
O
CLKOUT
Mode Selection
CLKMOD[1:0]
RCON
—
—
—
—
—
—
I
I
2
1
2
1
External Memory Interface and Ports
PADDR[7:5] CS[6:4]
A[23:21]
—
O
3
3
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
17
Preliminary
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
A[20:0]
D[31:16]
BS[3:2]
OE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
I
21
16
2
21
16
2
—
PBS[3:2]
CAS[3:2]
—
PBUSCTL[7]
PBUSCTL[6]
PBUSCTL[5]
PBUSCTL[4]
PBUSCTL[3]
PBUSCTL[2]
PBUSCTL[1]
PBUSCTL[0]
1
1
TA
—
1
1
TEA
DREQ1
—
I
1
0
R/W
O
O
O
O
O
1
1
TSIZ1
TSIZ0
TS
DACK1
DACK0
DACK2
DREQ0
1
1
1
1
1
1
TIP
1
0
Chip Selects
CS[7:1]
CS0
PCS[7:1]
—
—
—
—
—
O
O
7
1
7
1
DDR SDRAM Controller
DDR_CLKOUT
DDR_CLKOUT
SD_CS[1:0]
SD_SRAS
SD_SCAS
SD_WE
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
O
O
I/O
O
I
1
1
2
1
1
1
1
2
1
2
1
1
2
1
1
1
1
2
1
2
—
PSDRAM[7:6]
PSDRAM[5]
PSDRAM[4]
PSDRAM[3]
—
CS[3:2]
—
—
—
SD_A10
—
SD_DQS[1:0]
SD_CKE
PSDRAM[1:0]
PSDRAM[2]
—
—
—
SD_VREF
—
External Interrupts Port
IRQ[7:5]
IRQ[4]
IRQ[3:2]
IRQ1
PIRQ[7:5]
PIRQ[4]
—
DREQ2
DREQ[3:2]
—
—
—
—
—
I
I
I
I
3
1
2
1
3
1
2
1
PIRQ[3:2]
PIRQ[1]
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
18
Preliminary
SignalDescriptions
Table 2. Signal Information and Muxing (continued)
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
FEC0
FEC0_MDIO
FEC0_MDC
FEC0_TXCLK
FEC0_TXEN
FEC0_TXD[0]
FEC0_COL
PFECI2C[5]
PFECI2C[4]
PFEC0H[7]
PFEC0H[6]
PFEC0H[5]
PFEC0H[4]
PFEC0H[3]
PFEC0H[2]
PFEC0H[1]
PFEC0H[0]
I2C_SDA
U2RXD
U2TXD
—
I/O
O
I
1
1
1
1
1
1
1
1
1
1
3
1
3
1
1
1
1
1
1
1
1
1
1
1
3
1
3
1
I2C_SCL
—
—
—
—
—
—
—
—
—
—
—
—
—
I
—
O
I
—
FEC0_RXCLK
FEC0_RXDV
FEC0_RXD[0]
FEC0_CRS
—
I
—
I
—
I
—
I
FEC0_TXD[3:1] PFEC0L[7:5]
FEC0_TXER PFEC0L[4]
FEC0_RXD[3:1] PFEC0L[3:1]
—
O
O
I
—
—
FEC0_RXER
PFEC0L[0]
—
O
FEC1
FEC1_MDIO
FEC1_MDC
FEC1_TXCLK
FEC1_TXEN
FEC1_TXD[0]
FEC1_COL
PFECI2C[3]
PFECI2C[2]
PFEC1H[7]
PFEC1H[6]
PFEC1H[5]
PFEC1H[4]
PFEC1H[3]
PFEC1H[2]
PFEC1H[1]
PFEC1H[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O
O
I
1
1
1
1
1
1
1
1
1
1
3
1
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
O
I
FEC1_RXCLK
FEC1_RXDV
FEC1_RXD[0]
FEC1_CRS
I
I
I
I
FEC1_TXD[3:1] PFEC1L[7:5]
FEC1_TXER PFEC1L[4]
FEC1_RXD[3:1] PFEC1L[3:1]
FEC1_RXER PFEC1L[0]
O
O
I
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
19
Preliminary
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
I2C
I2C_SDA
I2C_SCL
PFECI2C[1]
PFECI2C[0]
U2RXD
U2TXD
—
—
I/O
I/O
1
1
1
1
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
—
—
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
QSPI_CS[3:2]
QSPI_CS1
QSPI_CS0
QSPI_CLK
QSPI_DIN
PQSPI[6:5]
PQSPI[4]
PQSPI[3]
PQSPI[2]
PQSPI[1]
PQSPI[0]
PWM[3:2]
SD_CKE
—
DACK[3:2]
O
O
O
O
I
2
1
1
1
1
1
2
1
1
1
1
1
—
—
—
—
—
I2C_SCL
I2C_SDA
—
QSPI_DOUT
O
UARTs
U0CTS
U0RTS
U0RXD
U0TXD
U1CTS
U1RTS
U1RXD
U1TXD
U2CTS
U2RTS
U2RXD
U2TXD
PUARTL[0]
PUARTL[1]
PUARTL[3]
PUARTL[2]
PUARTL[4]
PUARTL[5]
PUARTL[7]
PUARTL[6]
PUARTH[1]
PUARTH[0]
PUARTH[3]
PUARTH[2]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
O
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
—
—
O
I
—
—
O
I
—
—
O
I
PWM1
PWM0
—
O
I
—
O
USB
USB_SPEED
PUSBH[0]
—
—
I/O
1
1
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
20
Preliminary
SignalDescriptions
Table 2. Signal Information and Muxing (continued)
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
USB_CLK
USB_RN
PUSBL[7]
PUSBL[6]
PUSBL[5]
PUSBL[4]
PUSBL[3]
PUSBL[2]
PUSBL[1]
PUSBL[0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
USB_RP
I
USB_RXD
USB_SUSP
USB_TN
I
O
O
O
O
USB_TP
USB_TXEN
Timers (and PWMs)
DT3IN
DT3OUT
DT2IN
PTIMER[7]
PTIMER[6]
PTIMER[5]
PTIMER[4]
PTIMER[3]
PTIMER[2]
PTIMER[1]
PTIMER[0]
DT3OUT
PWM3
U2RTS
I
O
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
U2CTS
—
DT2OUT
PWM2
DT2OUT
DT1IN
—
O
I
DT1OUT
PWM1
—
DT1OUT
DT0IN
—
O
I
DT0OUT
PWM0
—
DT0OUT
—
O
BDM/JTAG2
DSCLK
PSTCLK
BKPT
—
—
—
—
—
—
—
—
TRST
TCLK
TMS
TDI
TDO
—
—
—
—
—
—
—
—
—
I
O
I
1
1
1
1
1
1
4
4
1
1
1
1
1
1
4
4
DSI
I
DSO
O
I
JTAG_EN
DDATA[3:0]
PST[3:0]
—
O
O
—
Test
TEST
—
—
—
—
—
—
I
I
1
1
1
1
PLL_TEST
Power Supplies
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
21
Preliminary
Signal Descriptions
Table 2. Signal Information and Muxing (continued)
GPIO
Port
Name
Alternate1 Alternate2 Dir.1
VDDPLL
VSSPLL
VDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
1
1
1
1
VSS
OVDD
OVSS
SD_VDD
N1 OTES:
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup
enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR,
PBS, PSDRAM.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO
module is not responsible for assigning these pins.
2
4.1 Reset Signals
Table 3 describes signals that are used to either reset the chip or as a reset indication.
Table 3. Reset Signals
Signal Name
Reset In
Abbreviation
Function
I/O
RESET
Primary reset input to the device. Asserting RESET immediately
resets the CPU and peripherals.
I
Reset Out
RSTOUT
Driven low for 128 CPU clocks when the soft reset bit of the system
configuration register (SCR[SOFTRST]) is set. It is driven low for 32K
CPU clocks when the software watchdog timer times out or when a
low input level is applied to RESET.
O
4.2 PLL and Clock Signals
Table 4 describes signals that are used to support the on-chip clock generation circuitry.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
22
Freescale Semiconductor
Preliminary
SignalDescriptions
I/O
Table 4. PLL and Clock Signals
Function
Signal Name
Abbreviation
External Clock In
EXTAL
Always driven by an external clock input except when used as a
connection to the external crystal when the internal oscillator circuit is
used. The clock source is configured during reset by CLKMOD[1:0].
I
Crystal
XTAL
Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
O
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
4.3 Mode Selection
Table 5 describes signals used in mode selection.
Table 5. Mode Selection Signals
Function
Clock Mode Selection CLKMOD[1:0] Configure the clock mode after reset.
Signal Name
Abbreviation
I/O
I
I
Reset Configuration
RCON
Indicates whether the external D[31:16] pin states affect chip
configuration at reset.
4.4 External Memory Interface Signals
These signals are used for doing transactions on the external bus.
Table 6 describes signals that are used for doing transactions on the external bus.
Table 6. External Memory Interface Signals
Signal Name
Address Bus
Abbreviation
Function
I/O
A[23:0]
The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
O
Data Bus
D[31:16]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
I/O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
23
Preliminary
Signal Descriptions
Table 6. External Memory Interface Signals (continued)
Signal Name
Abbreviation
Function
I/O
Byte Strobes
BS[3:2]
Define the flow of data on the data bus. During SRAM and peripheral
accesses, these output signals indicate that data is to be latched or
driven onto a byte of the data when driven low. The BS[3:2] signals are
asserted only to the memory bytes used during a read or write access.
BS3 controls access to the most significant byte lane of data, and BS2
controls access to the least significant byte lane of data.
O
The BS[3:2] signals are asserted during accesses to on-chip
peripherals but not to on-chip SRAM, or cache. During SDRAM
accesses, these signals act as the CAS[3:2] signals, which indicate a
byte transfers between SDRAM and the chip when driven high.
For SRAM or Flash devices, the BS[3:2] outputs should be connected
to individual byte strobe signals.
For SDRAM devices, the BS[3:2] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM1 with
the MSB, in which case BS3 should be connected to the SDRAM's
DQM1 input.
Output Enable
OE
Indicates when an external device can drive data during external read
cycles.
O
I
Transfer Acknowledge TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
O
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
Bus control output signal indicating bus transfer in progress.
O
O
O
Transfer in Progress
Chip Selects
TIP
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
4.5 DDR SDRAM Controller Signals
Table 7 describes signals that are used for DDR SDRAM accesses.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
24
Preliminary
SignalDescriptions
I/O
Table 7. SDRAM Controller Signals
Signal Name
Abbreviation
Function
SDRAM Clock Out
DDR_CLKOUT This output signal reflects the internal system clock.
O
O
SDRAM Inverted
Clock Out
DDR_CLKOUT This output signal reflects the inverted internal system clock.
SDRAM Synchronous SD_SRAS
Row Address Strobe
SDRAM synchronous row address strobe.
SDRAM synchronous column address strobe.
O
O
SDRAM Synchronous SD_SCAS
Column Address Strobe
SDRAM Write Enable SD_WE
SDRAM write enable.
O
O
O
O
O
SDRAM A10
SD_A10
SDRAM address bit 10 or command.
SDRAM chip select signals.
SDRAM clock enable.
SDRAM Chip Selects
SD_CS[1:0]
SDRAM Clock Enable SD_CKE
SDRAM Data Strobes SD_DQS[3:2] SDRAM byte-lane read/write data strobe signals.
4.6 External Interrupt Signals
Table 8 describes the external interrupt signals.
Table 8. External Interrupt Signals
Signal Name
Abbreviation
Function
I/O
External Interrupts
IRQ[7:1]
External interrupt sources.
I
IRQ[3:2] can also be configured as DMA request signals DREQ[3:2].
IRQ4 can also be configured as DMA request signals DREQ2.
4.7 Fast Ethernet Controller Signals
The following signals are used by the Ethernet modules for data and clock signals.
Table 9. Ethernet Module (FEC) Signals
Signal Name
Abbreviation
Function
I/O
Management Data
FECn_MDIO
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FECn_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
I/O
Management Data
Clock
FECn_MDC
In Ethernet mode, FECn_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FECn_MDIO
signal. Applies to MII mode operation.
O
I
Transmit Clock
FECn_TXCLK Input clock which provides a timing reference for FECn_TXEN,
FECn_TXD[3:0] and FECn_TXER
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
25
Preliminary
Signal Descriptions
Table 9. Ethernet Module (FEC) Signals (continued)
Signal Name
Abbreviation
Function
I/O
Transmit Enable
FECn_TXEN
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first FECn_TXCLK following the final nibble of the frame.
O
Transmit Data 0
FECn_TXD0
FECn_TXD0 is the serial output Ethernet data and is only valid during
the assertion of FECn_TXEN. This signal is used for 10-Mbps
Ethernet data. It is also used for MII mode data in conjunction with
FECn_TXD[3:1].
O
Collision
FECn_COL
Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
I
I
I
Receive Clock
Receive Data Valid
FECn_RXCLK Provides a timing reference for FECn_RXDV, FECn_RXD[3:0], and
FECn_RXER.
FECn_RXDV
Asserting the receive data valid (FECn_RXDV) input indicates that the
PHY has valid nibbles present on the MII. FECn_RXDV should remain
asserted from the first recovered nibble of the frame through to the last
nibble. Assertion of FECn_RXDV must start no later than the SFD and
exclude any EOF.
Receive Data 0
FECn_RXD0
FECn_RXD0 is the Ethernet input data transferred from the PHY to
the media-access controller when FECn_RxDV is asserted. This
signal is used for 10-Mbps Ethernet data. This signal is also used for
MII mode Ethernet data in conjunction with FECn_RXD[3:1].
I
Carrier Receive Sense FECn_CRS
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
I
Transmit Data 1–3
Transmit Error
FECn_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data
and are valid only during assertion of FECn_TXEN in MII mode.
O
O
FECn_TXER
In Ethernet mode, when FECn_TXER is asserted for one or more
clock cycles while FECn_TXEN is also asserted, the PHY sends one
or more illegal symbols. FECn_TXER has no effect at 10 Mbps or
when FECn_TXEN is negated. Applies to MII mode operation.
Receive Data 1–3
Receive Error
FECn_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data
transferred from the PHY to the Media Access Controller when
FECn_RXDV is asserted in MII mode operation.
I
FECn_RXER
In Ethernet mode, FECn_RXER—when asserted with
FECn_RXDV—indicates that the PHY has detected an error in the
current frame. When FECn_RXDV is not asserted FECn_RXER has
no effect. Applies to MII mode operation.
O
4.8 Queued Serial Peripheral Interface (QSPI)
Table 10 describes QSPI signals.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
26
Freescale Semiconductor
Preliminary
SignalDescriptions
I/O
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
Abbreviation Function
Signal Name
QSPI Syncrhonous
Serial Output
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
O
SPI_CLK = fsys/2 ÷ n
SynchronousPeripheral QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
O
Chip Selects
active high or low. QSPI_CS1 can also be configured as SDRAM clock
enable signal SD_CKE.
4.9 I2C I/O SIGNALS
2
Table 11 describes the I C serial interface module signals.
2
Table 11. I C I/O Signals
Signal Name
Serial Clock
Abbreviation
Function
I/O
I2C_SCL
Open-drain clock signal for the for the I2C interface. Either it is driven
by the I2C module when the bus is in the master mode or it becomes
the clock input when the I2C is in the slave mode.
I/O
Serial Data
I2C_SDA
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
4.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Table 12. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
UnTXD
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
O
Receive Serial Data
Input
UnRXD
Receiver serial data inputs for the UART modules. Data received on
this pin is sampled on the rising edge of the serial clock source lsb
first. When the UART clock is stopped for power-down mode, any
transition on this pin restarts it.
I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
27
Preliminary
Signal Descriptions
Signal Name
Table 12. UART Module Signals (continued)
Abbreviation
Function
I/O
Clear-to-Send
UnCTS
UnRTS
Indicate to the UART modules that they can begin data transmission.
I
Request-to-Send
Automatic request-to-send outputs from the UART modules. UnRTS
can also be configured to be asserted and negated as a function of
the RxFIFO level.
O
4.11 USB Signals
Table 13 describes the USB serial interface module signals.
Table 13. USB Module Signals
Signal Name
USB Clock
Abbreviation
Function
I/O
USB_CLK
This 48MHz (or 6MHz) clock is used by the USB module for both
clock recovery and generation of a 12Mhz (or 1.5MHz) internal bit
clock.
I
USB Speed
USB_SPEED Applications which make use of low speed USB signalling must be
able to switch the USB transceiver between low speed and full speed
operations. Software has control of this function by driving the state
of the USB_SPD bit in the USB_CTRL register onto the
USB_SPEED pin.
I/O
USB Received D-
USB Received D+
USB_RN
USB_RP
USB_RXD
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
I
I
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
USB Receive Data
USB Suspended
Input data from the differential input receiver. USB_RXD is the
single-ended data extracted from the USB_RP and USB_RN signals
via a differential input buffer.
I
USB_SUSP After a long period of inactivity (3.0ms minimum), the USB will enter
suspend mode, indicated on the interface by an active state on
USB_SUSP. During this mode, the device is supposed to enter a low
power state while waiting for a wake-up from the USB Host. When
the device enters suspend mode, it asserts the suspend signal which
forces the analog front end into a low power state. When the device
leaves suspend mode, USB_SUSP is deasserted, enabling the
analog front end for normal USB operations.
O
USB Transmitted D-
USB_TN
This signal is one half of the differential NRZI formatted output from
the USB module. It is fed to the transmitted D- input of the analog
front end.
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
28
Preliminary
SignalDescriptions
I/O
Table 13. USB Module Signals (continued)
Abbreviation Function
USB_TP
Signal Name
USB Transmitted D+
This signal is one half of the differential NRZI formatted output from
the module. It is fed to the transmitted D+ input of the analog front
end.
O
USB Transmit Enable
USB_TXEN This signal is an active low output enable for the differential drivers on
the analog front end. When this signal is active, the differential drivers
will drive the USB. When this signal is inactive, the differential drivers
will tristate their outputs.
O
4.12 DMA Timer Signals
Table 14 describes the signals of the four DMA timer modules.
Table 14. DMA Timer Signals
Signal Name
Abbreviation
Function
I/O
DMA Timer 0 Input
DT0IN
Can be programmed to cause events to occur in first platform timer. It
can either clock the event counter or provide a trigger to the timer
value capture logic.
I
DMA Timer 0 Output
DMA Timer 1 Input
DT0OUT
DT1IN
The output from first platform timer.
O
I
Can be programmed to cause events to occur in the second platform
timer. This can either clock the event counter or provide a trigger to the
timer value capture logic.
DMA Timer 1 Output
DMA Timer 2 Input
DT1OUT
DT2IN
The output from the second platform timer.
O
I
Can be programmed to cause events to occur in the third platform
timer. It can either clock the event counter or provide a trigger to the
timer value capture logic.
DMA Timer 2 Output
DMA Timer 3 Input
DT2OUT
DT3IN
The output from the third platform timer.
I
I
Can be programmed as an input that causes events to occur in the
fourth platform timer. This can either clock the event counter or
provide a trigger to the timer value capture logic.
DMA Timer 3 Output
DT3OUT
The output from the fourth platform timer.
O
4.13 Pulse Width Modulator Signals
Table 15 describes the PWM signals. Note that the primary functions of these pins are DMA Timer outputs
(DTnOUT).
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
29
Preliminary
Signal Descriptions
Signal Name
Table 15. PWM Signals
Function
Abbreviation
I/O
PWM Output Channel 0 PWM0
PWM Output Channel 1 PWM1
PWM Output Channel 2 PWM2
PWM Output Channel 3 PWM3
Pulse width modulated output for PWM channel 0.
Pulse width modulated output for PWM channel 1.
Pulse width modulated output for PWM channel 2.
Pulse width modulated output for PWM channel 3.
O
O
O
O
4.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM
logic.
Table 16. Debug Support Signals
Signal Name
Test Reset
Abbreviation
Function
I/O
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
TMS
Used to synchronize the JTAG logic.
I
I
Test Mode Select
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Clocks the serial communication port to the BDM module during
packet transfers.
I
Breakpoint
BKPT
DSI
Used to request a manual breakpoint.
I
I
Development Serial
Input
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
Development Serial
Output
DSO
This internally-registered signal provides serial output communication
for BDM module responses.
O
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
Processor Status
Outputs
PST[3:0]
Indicate core status, as shown in Table 17. Debug mode timing is
synchronous with the processor clock; status is unrelated to the
current bus transfer. The CLKOUT signal can be used by the
development system to know when to sample PST[3:0].
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
30
Preliminary
SignalDescriptions
Table 17. Processor Status
Processor Status
PST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Continue execution
Begin execution of one instruction
Reserved
Entry into user mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch
Reserved
Begin execution of RTE instruction
Begin one-byte transfer on DDATA
Begin two-byte transfer on DDATA
Begin three-byte transfer on DDATA
Begin four-byte transfer on DDATA
Exception processing
Reserved
Processor is stopped
Processor is halted
4.15 Test Signals
Table 18 describes test signals.
Table 18. Test Signals
Function
Signal Name
Abbreviation
I/O
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
I
PLL Test
PLL_TEST
Reserved for factory testing only and should be treated as a
no-connect (NC).
I
4.16 Power and Ground Pins
The pins described in Table 19 provide system power and ground to the chip. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
31
Preliminary
Chip Configuration
Table 19. Power and Ground Pins
Function
Signal Name
Abbreviation
I/O
PLL Analog Supply
VDDPLL,
VSSPLL
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
I
Positive Supply
Positive Supply
Ground
VDDO
VDD
These pins supply positive power to the I/O pads.
These pins supply positive power to the core logic.
This pin is the negative supply (ground) to the chip.
I
I
VSS
5 Chip Configuration
5.1 Device Operating Options
•
Chip operating mode:
— Master mode
•
Boot device/size:
— External device boot
– 32-bit
– 16-bit (Default)
– 8-bit
•
•
Output pad strength:
— Partial drive strength (Default)
— Full drive strength
Clock mode:
— Normal PLL with external crystal
— Normal PLL with external clock
— 1:1 PLL Mode
— External oscillator mode (no PLL)
Chip Select Configuration:
•
— PADDR[7:5] configured as chip select(s) and/or address line(s)
– PADDR[7:5] configured as A23-A21 (default)
– PADDR configured as CS6, PADDR[6:5] as A22-A21
– PADDR[7:6] configured as CS[6:5], PADDR5 as A21
– PADDR[7:5] configured as CS[6:4]
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32
Freescale Semiconductor
Preliminary
ChipConfiguration
5.2 Chip Configuration Pins
Table 20. Configuration Pin Descriptions
Chip Configuration
Function
Pin
Pin State/Meaning
1 disabled
Comments
RCON
Chip configuration
enable
Active low: if asserted, then all
configuration pins must be driven
appropriately for desired operation
0 enabled
D26, D17, D16
Select chip
111 master
operating mode
110 reserved
101 reserved
100 reserved
0xx reserved
D19, D18
D21
Select external boot 00,11 external (32-bit)
device data port size 10 external (8-bit)
01 external (16-bit)
Value read defaults to 32-bit
Select output pad
drive strength
1 Full
0 Partial
CLKMOD1,
CLKMOD0
Select clock mode
00 External clock mode (no VDDPLL must be supplied if a PLL
PLL)
mode is selected
01 1:1 PLL mode
10 Normal PLL with
external clock reference
11 Normal PLL with crystal
clock reference
D25, D24
Select chip select /
address line
00 PADDR[7:5] configured
as A23-A21 (default)
10 PADDR7 configured as
CS6,
PADDR[6:5] as A22-A21
01 PADDR[7:6] configured
as CS[6:5],
PADDR5 as A21
11 PADDR[7:5] configured
as CS[6:4]
JTAG_EN
Selects BDM or
JTAG mode
0 BDM mode
1 JTAG mode
5.3 Chip Configuration Circuit
Figure 2 shows a block diagram of the recommended circuit used to drive the reset configuration values
for the MCF5275.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
33
Preliminary
Design Recommendations
74HC244
MCF5275
D16
D17
Inputs
driven
high or
low as
needed
D18
D19
D21
D24
D25
D26
OE
RSTOUT
RCON
VDD/VSS
CLKMOD0
CLKMOD1
JTAG_EN
Figure 2. MCF5275 Recommended Reset Configuration Circuit
6 Design Recommendations
6.1 Layout
•
•
•
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5275.
See application note AN1259 System Design and Layout Techniques for Noise Reduction in
MCU-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and
board impedance. Add termination (series or therein) to the traces to dampen reflections.
Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do
cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6
mils trace and separation. Clocks get extra separation and more precise balancing.
6.2 Power Supply
•
33uF, 0.1uF and 0.01uF across each power supply
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
34
Freescale Semiconductor
Preliminary
DesignRecommendations
6.3 Decoupling
•
Place the decoupling capacitors as close to the pins as possible, but they can be outside the
footprint of the package.
•
0.1uF and 0.01uF at each supply input
6.4 Buffering
•
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See electricals.
6.5 Pull-up Recommendations
•
Use external pull-up resistors on unused inputs. See pin table.
6.6 Clocking Recommendations
•
Use a multi-layer board with a separate ground plane.
•
Place the crystal and all other associated components as close to the EXTAL and XTAL
(oscillator pins) as possible.
•
•
•
Do not run a high frequency trace around crystal circuit.
Ensure that the ground for the bypass capacitors is connected to a solid ground trace.
Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop
currents in the vicinity of the crystal.
•
•
Tie the ground pin to the most solid ground in the system.
Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.
•
Tie XTAL to ground when an external oscillator is clocking the device.
6.7 Interface Recommendations
6.7.1 DDR SDRAM Controller
6.7.1.1 SDRAM Controller Signals in Synchronous Mode
Table 21 shows the behavior of SDRAM signals in synchronous mode.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
35
Preliminary
Design Recommendations
Signal
Table 21. Synchronous DRAM Signal Connections
Description
SD_SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which
should not be interfaced to the SDRAM SD_SRAS signals.
SD_SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
SD_WE
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0]
Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:2]
Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
DDR_CLKOUT Bus clock output. Connects to the CLK input of SDRAMs.
6.7.1.2 Address Multiplexing
Table 22 shows the generic address multiplexing scheme for SDRAM configurations. All possible address
connection configurations can be derived from this table.
Table 22. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address
Notes Related to Port Sizes
8-bit port only
8- and 16-bit ports only
17
16
15
14
13
12
11
10
9
17
16
15
14
13
12
11
10
9
0
1
2
3
4
5
6
7
8
17
18
17
18
16
17
32-bit port only
16-bit port only or 32-bit port with only 8
column address lines
19
19
18
16-bit port only when at least 9 column
address lines are used
20
21
20
21
19
20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
36
Preliminary
DesignRecommendations
Table 22. Generic Address Multiplexing Scheme (continued)
Address Pin Row Address Column Address Notes Related to Port Sizes
22
23
24
25
22
23
24
25
21
22
23
24
The following tables provide a more comprehensive, step-by-step way to determine the correct address
line connections for interfacing the MCF5275 to SDRAM. To use the tables, find the one that corresponds
to the number of column address lines on the SDRAM and to the port size as seen by the MCF5275, which
is not necessarily the SDRAM port size. For example, if two 8M x 8-bit SDRAMs together form a
8M x 16-bit memory, the port size is 16 bits. Most SDRAMs likely have fewer address lines than are
shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 23. MCF5275 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17 16 15 14 13 12 11 10
9
8
18 19 20 21 22 23 24 25 26 27 28 29 30 31
Column
0
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Pins
Table 24. MCF5275 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17 16 15 14 13 12 11 10
9
8
19 20 21 22 23 24 25 26 27 28 29 30 31
18
Column
0
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Pins
Table 25. MCF5275 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17 16 15 14 13 12 11 10
9
8
19 21 22 23 24 25 26 27 28 29 30 31
18 20
Column
0
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
Pins
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
37
Preliminary
Design Recommendations
Table 26. MCF5275 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17 16 15 14 13 12 11 10
9
8
19 21 23 24 25 26 27 28 29 30 31
18 20 22
Column
0
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Pins
Table 27. MCF5275 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17 16 15 14 13 12 11 10
9
8
19 21 23 25 26 27 28 29 30 31
18 20 22 24
Column
0
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Pins
Table 28. MCF5275 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16 15 14 13 12 11 10
9
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Column
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Pins
Table 29. MCF5275 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16 15 14 13 12 11 10
9
8
18 19 20 21 22 23 24 25 26 27 28 29 30 31
17
Column
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Pins
Table 30. MCF5275 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16 15 14 13 12 11 10
9
8
18 20 21 22 23 24 25 26 27 28 29 30 31
17 19
Column
1
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
Pins
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
38
Freescale Semiconductor
Preliminary
DesignRecommendations
Table 31. MCF5275 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16 15 14 13 12 11 10
9
8
18 20 22 23 24 25 26 27 28 29 30 31
17 19 21
Column
1
2
3
4
5
6
7
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 32. MCF5275 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16 15 14 13 12 11 10
9
8
18 20 22 24 25 26 27 28 29 30 31
17 19 21 23
Column
1
2
3
4
5
6
7
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 33. MCF5275 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A24 A26 A27 A28 A29 A30 A31
Pins
Row
16
1
15
2
14
3
13
4
12
5
11
6
10
7
9
8
18
17
20
19
22
21
24
23
26
25
27
28
29
30
31
Column
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
Table 34. MCF5275 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15 14 13 12 11 10
9
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16
Column
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Pins
Table 35. MCF5275 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15 14 13 12 11 10
9
8
17 19 20 21 22 23 24 25 26 27 28 29 30 31
16 18
Column
2
3
4
5
6
7
SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
Pins
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
39
Preliminary
Design Recommendations
Table 36. MCF5275 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15 14 13 12 11 10
9
8
17 19 21 22 23 24 25 26 27 28 29 30 31
16 18 20
Column
2
3
4
5
6
7
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 37. MCF5275 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15 14 13 12 11 10
9
8
17 19 21 23 24 25 26 27 28 29 30 31
16 18 20 22
Column
2
3
4
5
6
7
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 38. MCF5275 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15
2
14
3
13
4
12
5
11
6
10
7
9
8
17
16
19
18
21
20
23
22
25
24
26
27
28
29
30
31
Column
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
6.7.1.2.1 SDRAM Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To
interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF5275, the connections
would be as shown in Table 39.
Table 39. SDRAM Hardware Connections
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 = CMD
A20
BA0
A21
BA1
A22
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19
Pins
6.7.2 Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 40.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
40
Freescale Semiconductor
Preliminary
DesignRecommendations
Table 40. MII Mode
Signal Description
Transmit clock
MCF5275 Pin
FECn_TXCLK
FECn_TXEN
FECn_TXD[3:0]
FECn_TXER
FECn_COL
Transmit enable
Transmit data
Transmit error
Collision
Carrier sense
Receive clock
Receive enable
Receive data
Receive error
FECn_CRS
FECn_RXCLK
FECn_RXDV
FECn_RXD[3:0]
FECn_RXER
FECn_MDC
Management channel clock
Management channel serial data
FECn_MDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 41.
Table 41. Seven-Wire Mode Configuration
Signal Description
Transmit clock
MCF5275 Pin
FECn_TXCLK
FECn_TXEN
FECn_TXD[0]
FECn_COL
Transmit enable
Transmit data
Collision
Receive clock
FECn_RXCLK
FECn_RXDV
FECn_RXD[0]
FECn_RXER
FECn_CRS
Receive enable
Receive data
Unused, configure as PB14
Unused input, tie to ground
Unused, configure as PB[13:11]
Unused output, ignore
Unused, configure as PB[10:8]
Unused, configure as PB15
Input after reset, connect to ground
FECn_RXD[3:1]
FECn_TXER
FECn_TXD[3:1]
FECn_MDC
FECn_MDIO
Refer to the M5275EVBevaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5275 site by navigating from:
http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx,
MCF5275 and M5275EVB links.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
41
Preliminary
Pinout
6.7.3 BDM
Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for
this board are accessible at the MCF5275 site by navigating from: http://e-www.motorola.com/ following
the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5275 and M5275EVB links.
7 Pinout
7.1 256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by
group and shows which signals are muxed and bonded on each of the device packages.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
42
Freescale Semiconductor
Preliminary
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FEC1_
RXD1
FEC1_
RXDV
FEC1_
CRS
FEC1_
COL
FEC0_
COL
FEC0_
MDIO
SD_
VREF
A
B
C
D
E
F
VSS
U0RXD U1RXD
U0TXD U1TXD
U0CTS U1CTS
VSS
A23
A20
A17
A14
VSS
A
B
C
D
E
F
FEC1_ FEC1_
RXD3 RXD2
FEC1_
RXD0
FEC1_
RXCLK
FEC0_
RXDV
FEC0_
RXCLK
FEC0_
MDC
I2C_
SDA
A22
A21
CS6
A19
A18
CS5
A16
A15
CS4
CS3
A13
A12
A7
A11
A10
A6
A9
A8
FEC1_ FEC1_
TXCLK RXER
FEC0_
TXCLK
FEC0_
RXER
FEC0_
RXD2
FEC0_
RXD0
FEC0_
CRS
I2C_
SCL
FEC1_ FEC1_
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXD3
FEC0_
RXD1
U0RTS
OVDD
OVDD
VSS
VDD
U1RTS
CS7
TSIZ1
A3
TXER
TXEN
FEC1_ FEC1_
TXD3 TXD2
FEC0_
TXD3
NC
VSS
OVDD
VSS
OVDD SD_VDD SD_VDD SD_VDD VSS
A5
A4
FEC1_ FEC1_
TXD0 TXD1
FEC0_
TXD2
FEC0_
TXD1
OVDD
OVDD
OVDD
OVDD SD_VDD SD_VDD VSS SD_VDD CS2
A2
A1
A0
FEC1_ FEC1_
MDIO MDC
FEC0_
TXD0
USB_
SPEED
USB_
CLK
G
H
J
DT0OUT
OVDD
OVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS SD_VDD SD_VDD IRQ7
VSS SD_VDD SD_VDD VDD
TSIZ0
IRQ6
G
H
J
DT1IN DT1OUT DT0IN
NC
DT3IN
VDD
VSS
IRQ4
IRQ5
VSS
OE
DT2IN DT2OUT
SD_WE DT3OUT
SD_VDD SD_VDD
SD_VDD SD_VDD
VSS
VSS
VSS
OVDD OVDD
OVDD OVDD
IRQ2
IRQ3 USB_RP USB_RN
K
L
VSS
IRQ1 USB_TN USB_TP VSSPLL
K
L
SD_
SCAS
SD_
USB_
TXEN
USB_
RXD
SD_CKE
SRAS
TS
SD_VDD
VSS
VSS
SD_VDD SD_VDD OVDD OVDD
VSS
OVDD
NC
TA
EXTAL
USB_
SUSP
PLL_
TEST
M
N
P
R
T
D31 SD_CS1
BS3
D28
D23
D22
SD_DQS3
D20
SD_VDD SD_VDD SD_VDD OVDD OVDD OVDD
VDDPLL XTAL
M
N
P
R
T
QSPI_
CS2
CLK
MOD1
D30
D27
D25
D29
D26
D24
D16
SD_A10
TIP
CS1
R/W
VSS
VDD
TEST DDATA2 DDATA0
RSTOUT RESET
VSS
QSPI_
CS0
CLK
TRST/
TDO/
DSO PSTCLK
TCLK/
D19
SD_DQS2
BS2
RCON U2CTS DDATA3 DDATA1
MOD0 DSCLK
QSPI_ QSPI_ JTAG_
DOUT CS3 EN
TMS/
D18
CS0
U2RTS U2TXD PST2
PST0
TDI/DSI
BKPT
SD_
VREF
DDR_CLK DDR_CLK
OUT
QSPI_ QSPI_ QSPI_
VSS
D21
D17
SD_CS0
TEA
U2RXD PST3
10
PST1 CLKOUT
11 12
VSS
OUT
DIN
CS1
CLK
1
2
3
4
5
6
7
8
9
13
14
15
16
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
43
Preliminary
Pinout
7.2 196 MAPBGA Pinout
Figure 4 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals
by group and shows which signals are muxed and bonded on each of the device packages.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FEC0_
CRS
FEC0_
MDIO
SD_
VREF
A
B
C
D
E
F
NC
U0RXD
U0TXD
U1RXD
I2C_SCL
A23
CS6
CS5
A15
A12
NC
A
B
C
D
E
F
FEC0_
RXD2
FEC0_
RXD1
FEC0_
RXCLK
FEC0_
COL
U0RTS
U1RTS
U0CTS
VDD
I2C_SDA
U1CTS
U1TXD
OVDD
VSS
A22
A21
CS7
A20
A18
A19
A16
A17
CS4
A13
A14
A11
A6
CS3
A10
A9
A8
TSIZ1
CS2
FEC0_
TXCLK
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXDV
FEC0_
MDC
FEC0_
TXD3
FEC0_
TXD0
FEC0_
TXD1
FEC0_
RXD3
FEC0_
RXD0
A7
A5
A2
FEC0_
TXD2
FEC0_
RXER
DT0IN
DT1IN
DT0OUT
DT1OUT
DT3IN
TS
OVDD
OVDD
OVDD
OVDD
VSS
SD_VDD2 SD_VDD2 SD_VDD2
A4
A1
TSIZ0
IRQ7
IRQ5
IRQ3
USB_TN
TA
DT2IN
SD_CAS
SD_CS1
D31
DT2OUT
SD_WE
OE
VSS
VSS
SD_VDD2 SD_VDD2
A3
USB_CLK
VDD
A0
USB_
SPEED
G
H
J
DT3OUT
SD_SRAS
VDD
VSS
VSS
VSS
SD_VDD2
OVDD
IRQ6
USB_RN
IRQ1
G
H
J
SD_VDD1
VSS
VSS
VSS
IRQ4
IRQ2
SD_CKE SD_DQS3
D22
SD_VDD1 SD_VDD1
VSS
VSS
OVDD
OVDD
DDATA0
OVDD
USB_RP USB_TP
TDO/DSO RESET
USB_
TXEN
K
L
BS3
D30
D27
D20
D29
D26
D21
D19
D28
D23
SD_VDD1 SD_VDD1 SD_VDD1
OVDD
PST2
PST1
PST0
OVDD
K
L
QSPI_
DOUT
D25
D24
BS2
SD_CS0
CS0
R/W
RCON
TEST
VDD
QSPI_CLK RSTOUT VSSPLL USB_RXD
QSPI_
CS0
M
N
P
D18
D17
DDATA3
DDATA2
QSPI_DIN CLKMOD1 TDI/DSI
VDDPLL
EXTAL
XTAL
M
N
P
QSPI_
CS2
QSPI_
USB_
SUSP
D16
SD_A10
CLKMOD0 TMS/BKPT
CS1
SD_
VREF
DDR_CLK DDR_CLK
OUT
QSPI_
CS3
TCLK/PST TRST/DSC
NC
SD_DQS2
CS1
PST3
DDATA1 CLKOUT
JTAG_EN
NC
OUT
CLK
LK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 4. MCF5274L and MCF5275L Pinout (196 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
44
Preliminary
Mechanicals
8 Mechanicals
8.1 Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
X
D
M
LASER MARK FOR PIN A1
IDENTIFICATION IN
THIS AREA
5
Y
E
0.30 Z
A2
K
A
A1
256X
4
0.15 Z
Z
DETAIL K
ROTATED 90 CLOCKWISE
°
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
M
0.20
15X e
S
METALIZED MARK FOR
PIN A1 IDENTIFICATION
IN THIS AREA
16151413121110
7 6 5 4 3 2 1
A
B
C
D
E
F
S
15X e
3
G
H
J
256X
b
MILLIMETERS
M
M
0.25
0.10
Z X Y
K
L
M
N
P
R
T
DIM MIN
1.25
A1 0.27
MAX
1.60
0.47
Z
A
A2
b
1.16 REF
0.40
0.60
D
E
e
17.00 BSC
17.00 BSC
1.00 BSC
0.50 BSC
VIEW M-M
S
Figure 5. 256 MAPBGA Package Dimensions
8.2 Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
45
Preliminary
Mechanicals
NOTES:
D
X
Y
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances per
ASME Y14.5M, 1994.
3. Dimension B is measured at the
maximum solder ball diameter, parallel
to datum plane Z.
Laser mark for pin 1
identification in
this area
M
K
4. Datum Z (seating plane) is defined by
the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude
any effect of mark on top surface of
package.
E
Millimeters
DIM
Min Max
A
1.32 1.75
A1 0.27 0.47
A2 1.18 REF
b
D
E
e
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
M
S
0.20
13X e
S
Metalized mark for
pin 1 identification
in this area
14 13 12 11 10
9
6
5
4
3
2
1
A
B
C
D
E
F
5
S
0.30 Z
13X e
A2
A
G
H
J
A1
0.15 Z
4
Z
K
L
M
N
P
Detail K
Rotated 90 Clockwise
°
3
196X
b
View M-m
0.30 Z X Y
0.10 Z
Figure 6. 196 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
46
Freescale Semiconductor
Preliminary
OrderingInformation
9 Ordering Information
Table 42. Orderable Part Numbers
Motorola Part
Number
Description
Speed
Temperature
MCF5274LVM133
MCF5274LVM166
MCF5274VM133
MCF5274VM166
MCF5275LCVM133
MCF5275LCVM166
MCF5275CVM133
MCF5275CVM166
MCF5274L RISC Microprocessor, 196 MAPBGA
MCF5274L RISC Microprocessor, 196 MAPBGA
MCF5274 RISC Microprocessor, 256 MAPBGA
MCF5274 RISC Microprocessor, 256 MAPBGA
MCF5275L RISC Microprocessor, 196 MAPBGA
MCF5275L RISC Microprocessor, 196 MAPBGA
MCF5275 RISC Microprocessor, 256 MAPBGA
MCF5275 RISC Microprocessor, 256 MAPBGA
133MHz
166MHz
133MHz
166MHz
133MHz
166MHz
133MHz
166MHz
0° to +70° C
0° to +70° C
0° to +70° C
0° to +70° C
-40° to +85° C
-40° to +85° C
-40° to +85° C
-40° to +85° C
10 Preliminary Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5275.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
10.1 Maximum Ratings
1, 2
Table 43. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core Supply Voltage
VDD
O VDD
SD VDD
SD VDD
VDDPLL
VIN
– 0.5 to +2.0
– 0.3 to +4.0
– 0.3 to + 2.8
– 0.3 to +4.0
– 0.3 to +4.0
– 0.3 to + 4.0
0 to 3.3
V
V
V
V
V
V
V
V
I/O Pad Supply Voltage (3.3V)
Memory Interface SSTL 2.5V Pad Supply Voltage
Memory Interface SSTL 3.3V Pad Supply Voltage
Clock Synthesizer Supply Voltage
Digital Input Voltage 3
EXTAL pin voltage
VEXTAL
VXTAL
XTAL pin voltage
0 to 3.3
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
47
Preliminary
Preliminary Electrical Characteristics
Table 43. Absolute Maximum Ratings
1, 2
Instantaneous Maximum Current
ID
25
mA
Single pin limit (applies to all pins) 4, 5
Operating Temperature Range (Packaged)
TA
– 40 to 85
°C
(TL - TH)
Storage Temperature Range
Tstg
– 65 to 150
°C
NOTES:
1
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those
listed may affect device reliability or cause permanent damage to the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD).
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use
the larger of the two values.
2
3
4
5
All functional non-supply pins are internally clamped to VSS and O VDD
.
Power supply must maintain regulation within operating O VDD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the
injection current may flow out of O VDD and could result in external power supply going out of
regulation. Insure external O VDD load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must
maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions.
10.2 Thermal Characteristics
Table 44 lists thermal resistance values
Table 44. Thermal characteristics
Characteristic
Junction to ambient, natural convection
Symbol
Value
Unit
256 MBGA
θJMA
261,2
°C/W
Four layer board (2s2p)
Junction to ambient (@200 ft/min)
256 MBGA
θJMA
23
°C/W
Four layer board (2s2p)
Junction to board
256 MBGA
θJB
θJC
Ψjt
Tj
153
104
25
°C/W
°C/W
°C/W
oC
Junction to case
256 MBGA
Junction to top of package
Maximum operating junction temperature
N1 OTES:
Natural convection
256 MBGA
105
θ
JMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Motorola recommends the use of θJmA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
2
3
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
48
Freescale Semiconductor
Preliminary
PreliminaryElectricalCharacteristics
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
4
5
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
(1)
)
TJ = TA + (PD × ΘJMA
Where:
TA
= Ambient Temperature, °C
ΘJMA
PD
= Package Thermal Resistance, Junction-to-Ambient, °C/W
= PINT + PI/O
PINT
PI/O
= IDD × VDD, Watts - Chip Internal Power
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is
neglected) is:
PD = K ÷ (TJ + 273°C)
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at
equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1)
and (2) iteratively for any value of TA.
10.3 ESD Protection
1, 2
Table 45. ESD Protection Characteristics
Characteristics
Symbol
Value
Units
ESD Target for Human Body Model
ESD Target for Machine Model
HBM Circuit Description
HBM
MM
2000
200
1500
100
0
V
V
Rseries
C
ohms
pF
MM Circuit Description
Rseries
C
ohms
pF
200
Number of pulses per pin (HBM)
positive pulses
negative pulses
—
—
—
1
1
Number of pulses per pin (MM)
positive pulses
negative pulses
—
—
—
3
3
Interval of Pulses
N1 OTES:
—
1
sec
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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49
Preliminary
Preliminary Electrical Characteristics
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
10.4 DC Electrical Specifications
1
Table 46. DC Electrical Specifications
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
VDD
O VDD
SD VDD
VIH
1.35
3.0
1.65
V
V
I/O Pad Supply Voltage
3.6
SSTL I/O Pad Supply Voltage
Input High Voltage
2.3
2.7
V
0.7 x O VDD
VSS – 0.3
2.0
3.6
V
Input Low Voltage
VIL
0.35 x O VDD
V
Input High Voltage SSTL 2.5V I/O Pads
Input Low Voltage SSTL 2.5V I/O Pads
Input High Voltage SSTL 3.3V I/O Pads
Input Low Voltage SSTL 3.3V I/O Pads
Input Hysteresis
VIH
2.8
0.8
3.6
0.8
—
V
VIL
– 0.5
V
VIH
2.0
V
VIL
– 0.5
V
VHYS
Iin
0.06 x VDD
–1.0
mV
µA
Input Leakage Current
1.0
Vin = VDD or VSS, Input-only pins
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins
IOZ
VOH
VOL
–1.0
O VDD - 0.5
__
1.0
__
µA
V
Output High Voltage (All input/output and all output pins)
IOH = –2.0 mA
Output Low Voltage (All input/output and all output pins)
IOL = 2.0mA
0.5
V
Weak Internal Pull Up Device Current, tested at VIL Max.2
Input Capacitance 3
IAPU
Cin
-10
- 130
µA
pF
All input-only pins
All input/output (three-state) pins
—
—
7
7
Load Capacitance4
Low Drive Strength
High Drive Strength
pF
CL
25
50
Core Operating Supply Current 5
IDD
Master Mode
WAIT
DOZE
—
—
—
—
175
15
10
mA
mA
mA
µA
STOP
100
I/O Pad Operating Supply Current
Master Mode
Low Power Modes
O IDD
—
—
250
250
mA
µA
3, 6, 7, 8
DC Injection Current
IIC
mA
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
-1.0
-10
1.0
10
N1 OTES:
Refer to Table 47 for additional PLL specifications.
Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
2
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50
Preliminary
PreliminaryElectricalCharacteristics
3
4
This parameter is characterized before qualification rather than 100% tested.
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination.
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching
load.
5
6
7
All functional non-supply pins are internally clamped to VSS and their respective VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at
power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
8
10.5 Oscillator and Phase Lock Loop (PLLMRFM) Electrical
Specifications
1
Table 47. PLL Electrical Specifications
Characteristic
PLL Reference Frequency Range
Symbol
Min
Max
Unit
MHz
Crystal reference
External reference
1:1 Mode (NOTE: fsys/2 = 2 × fref_1:1
fref_crystal
fref_ext
fref_1:1
8
8
24
25
25
83
)
Core frequency
fcore
166
83
83
MHz
MHZ
MHz
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
0
fsys/2
fref / 32
Loss of Reference Frequency 3, 5
Self Clocked Mode Frequency 4, 5
Crystal Start-up Time 5, 6
fLOR
fSCM
tcst
100
TBD
—
1000
TBD
10
kHz
MHz
ms
EXTAL Input High Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VIHEXT
VIHEXT
V
TBD
TBD
TBD
TBD
EXTAL Input Low Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VILEXT
VILEXT
V
TBD
TBD
TBD
TBD
XTAL Output High Voltage
IOH = 1.0 mA
VOH
VOL
V
V
TBD
—
—
XTAL Output Low Voltage
IOL = 1.0 mA
XTAL Load Capacitance7
PLL Lock Time 8
TBD
30
5
pF
tlpll
—
750
µs
Power-up To Lock Time 6, 9
With Crystal Reference
tlplk
—
—
11
750
ms
µs
Without Crystal Reference10
1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11
Duty Cycle of reference 5
tskew
tdc
-1
1
ns
40
60
% fsys/2
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Preliminary
Preliminary Electrical Characteristics
1
Table 47. PLL Electrical Specifications
Characteristic
Frequency un-LOCK Range
Symbol
Min
Max
Unit
fUL
- 3.8
- 1.7
4.1
2.0
% fsys/2
% fsys/2
Frequency LOCK Range
fLCK
Cjitter
CLKOUT Period Jitter, 5, 6, 9,12, 13 Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
—
—
5
.01
% fsys/2
% fsys/2
MHz
Frequency Modulation Range Limit14 15
,
Cmod
fico
0.8
2.2
83
(fsys/2Max must not be exceeded)
ICO Frequency. fico = fref * 2 * (MFD+2)16
48
NOTES:
1
All values given are initial design targets and subject to change.
All internal registers retain data at 0 Hz.
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
2
3
4
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
f
LOR with default MFD/RFD settings.
5
6
7
8
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
9
tlpll = (64 * 4 * 5 + 5 x τ) x T , where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10-6 x 2(MFD + 2)
10
11
12
ref
PLL is operating in 1:1 PLL mode.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
13
14
15
Based on slow system clock of 33MHz maximum frequency.
Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.
Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
fsys/2 = fico / (2 * 2RFD
)
16
10.6 External Interface Timing Characteristics
Table 48 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
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Table 48. Processor Bus Input Timing Specifications
Name
Characteristic1
Symbol
Min
Max Unit
B0
CLKOUT
tCYC
12
—
ns
Control Inputs
B1a
B1b
B2a
B2b
Control input valid to CLKOUT high2
BKPT valid to CLKOUT high3
tCVCH
tBKVCH
tCHCII
9
9
0
0
—
—
—
—
ns
ns
ns
ns
CLKOUT high to control inputs invalid2
CLKOUT high to asynchronous control input BKPT invalid3
tBKNCH
Data Inputs
B4
Data input (D[31:16]) valid to CLKOUT high
CLKOUT high to data input (D[31:16]) invalid
tDIVCH
tCHDII
4
0
—
—
ns
ns
B5
N1 OTES:
Timing specifications have been indicated taking into account the full drive strength for the pads.
TEA and TA pins are being referred to as control inputs.
Refer to figure A-19.
2
3
Timings listed in Table 48 are shown in Figure 7.
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53
Preliminary
Preliminary Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
CLKOUT (83MHz)
TSETUP
THOLD
Invalid
Valid
Invalid
Input Setup And Hold
trise
Vh = VIH
Input Rise Time
Vl = VIL
tfall
Vh = VIH
Vl = VIL
Input Fall Time
CLKOUT
Inputs
B4
B5
Figure 7. General Input Timing Requirements
10.7 Processor Bus Output Timing Specifications
Table 49 lists processor bus output timings.
Table 49. External Bus Output Timing Specifications
Name
Characteristic
Symbol
Min
Max
Unit
Control Outputs
B6a
CLKOUT high to chip selects (CS[7:0]) valid 1
CLKOUT high to byte enables (BS[3:2]) valid2
CLKOUT high to output enable (OE) valid3
CLKOUT high to control output (BS[3:2], OE) invalid
CLKOUT high to chip selects invalid
tCHCV
tCHBV
tCHOV
tCHCOI
tCHCI
—
—
0.5tCYC + 5
0.5tCYC + 5
0.5tCYC + 5
—
ns
ns
ns
ns
ns
B6b
B6c
B7
—
0.5tCYC + 1.5
0.5tCYC + 1.5
B7a
—
Address and Attribute Outputs
B8
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) valid
tCHAV
—
9
ns
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PreliminaryElectricalCharacteristics
Table 49. External Bus Output Timing Specifications (continued)
Name
B9
Characteristic
Symbol
Min
Max
Unit
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) invalid
tCHAI
1.5
—
ns
Data Outputs
B11
B12
B13
CLKOUT high to data output (D[31:16]) valid
CLKOUT high to data output (D[31:16]) invalid
tCHDOV
tCHDOI
—
1.5
—
9
—
9
ns
ns
ns
CLKOUT high to data output (D[31:16]) high impedance tCHDOZ
NOTES:
1
CS transitions after the falling edge of CLKOUT.
BS transitions after the falling edge of CLKOUT.
OE transitions after the falling edge of CLKOUT.
2
3
Read/write bus timings listed in Table 49 are shown in Figure 8, Figure 9, and Figure 10.
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Preliminary
Preliminary Electrical Characteristics
S4
S5
S0
S1
S2
S5
S0
S1
S2
S3
S4
S3
CLKOUT
CSn
B7a
B7a
B6a
B6a
B8
B8
B9
A[23:0]
TSIZ[1:0]
TS
B8
B9
B9
B8
TIP
B9
B8
B6c
B0
B7
OE
B9
(H)
B8
B6b
R/W
B6b
B7
BS[3:2]
B7
B11
B4
B12
B13
D[31:16]
B5
(H)
TA
(H)
TEA
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 49.
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Preliminary
PreliminaryElectricalCharacteristics
S4
S0
S1
S2
S5
S0
S1
S3
CLKOUT
CSn
B6a
B7a
B8
B9
A[23:0]
TSIZ[1:0]
B8
TS
B9
B8
B9
TIP
OE
B6c
B7
B7
(H)
R/W
B6b
BS[3:2]
B5
B4
D[31:16]
TA
B2a
B1a
TEA
(H)
Figure 9. SRAM Read Bus Cycle Terminated by TA
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 49.
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Preliminary
Preliminary Electrical Characteristics
S4
S1
S2
S5
S0
S1
S0
S3
CLKOUT
B6a
CSn
B7a
B8
B9
A[23:0]
TSIZ[1:0]
B8
TS
B9
B8
TIP
B9
B6c
OE
B7
(H)
R/W
B6b
B7
BS[3:2]
D[31:16]
TA
(H)
B1a
TEA
B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
10.8 DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is
available and is user programmable. DDR Clock timing specifications are given in Table 50 and Figure 11.
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Preliminary
PreliminaryElectricalCharacteristics
1
Table 50. DDR Clock Timing Specifications
Symbol
Characteristic
Clock output mid-point voltage
Min
Max
Unit
VMP
VOUT
VID
1.05
-0.3
0.7
1.45
V
V
V
V
Clock output voltage level
SD VDD + 0.3
SD VDD + 0.6
1.45
Clock output differential voltage (peak to peak swing)
Clock crossing point voltage
VIX
1.05
N1 OTES:
SD VDD is nominally 2.5V.
SDCLK
SDCLK
VIX
VMP
VIX
VID
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 51 must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 51. DDR Timing
NUM
Characteristic1
Frequency of operation2
Symbol
Min
Max
Unit
TBD
12
83
TBD
MHz
ns
DD1 Clock Period (DDR_CLKOUT)
DD2 Pulse Width High3
DD3 Pulse Width Low3
tCK
tCKH
tCKl
0.45
0.45
-
0.55
tCK
tCK
ns
0.55
DD4 DDR_CLKOUT high to DDR address, SD_CKE,
SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid
tCMV
0.5 x tCK + 1
DD5 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,
SD_SCAS, SD_SRAS, SD_WE invalid
tCMH
2
-
ns
DD6 Write command to first SD_DQS Latching Transition
DD7 SD_DQS high to Data and DM valid (write) - setup4,5
DD8 SD_DQS high to Data and DM invalid (write) - hold4
DD9 SD_DQS high to Data valid (read) - setup6
tDQSS
tQS
-
1.25
tCK
ns
1.5
-
-
tQH
1
ns
tIS
-
1
ns
DD10 SD_DQS high to Data invalid (read) - hold7
DD11 SD_DQS falling edge to CLKOUT high - setup
DD12 SD_DQS falling edge to CLKOUT high - hold
tIH
0.25 x tCK+ 1
-
ns
tDSS
tDSH
tRPRE
tRPST
tWPRE
tWPST
0.5
0.5
-
ns
-
ns
DD13 DQS input read preamble width (tRPRE
DD14 DQS input read postamble width (tRPST
DD15 DQS output write preamble width (tWPRE
)
0.9
1.1
0.6
—
0.6
tCK
tCK
tCK
tCK
)
0.4
)
0.25
0.4
DD16 DQS output write postamble width (tWPST
)
N1 OTES:
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
2
3
4
tCKH + tCKL must be less than or equal to tCK
.
D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
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Preliminary
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5
The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The
remaining data beats will be valid for each subsequent SD_DQS edge
Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
6
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
7
line becomes invalid.
Figure 13 shows a DDR SDRAM write cycle.
DDR_CLKOUT
VIX
VID
VMP
VIX
DDR_CLKOUT
Figure 12. DDR_CLKOUT and DDR_CLKOUT crossover timing
DD1
DD2
DDR_CLKOUT
DDR_CLKOUT
DD3
DD5
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
ROW
DD4
DD6
A[13:0]
COL
DD7
DM[3:2]
SD_DQS[3:2]
D[31:16]
DD8
DD7
WD1 WD2 WD3 WD4
DD8
Figure 13. DDR Write Timing
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Preliminary
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DD1
DD2
CLKOUT
CLKOUT
DD3
DD5
CL=2
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
ROW
DD4
CL=2.5
A[13:0]
COL
DD9
DQS Read
Postamble
DQS Read
Preamble
SD_DQS[3:2]
D[31:16]
DD10
WD1 WD2 WD3 WD4
DQS Read
Preamble
DQS Read
Postamble
SD_DQS[3:2]
D[31:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
10.9 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in
Table 52 and Figure 15.
Table 52. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1 CLKOUT High to GPIO Output Valid
G2 CLKOUT High to GPIO Output Invalid
G3 GPIO Input Valid to CLKOUT High
G4 CLKOUT High to GPIO Input Invalid
tCHPOV
tCHPOI
tPVCH
tCHPI
-
10
-
ns
ns
ns
ns
1.5
9
-
1.5
-
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Preliminary
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CLKOUT
G2
G1
GPIO Outputs
G3
G4
GPIO Inputs
Figure 15. GPIO Timing
10.10Reset and Configuration Override Timing
Table 53. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
Characteristic
Symbol
Min
Max
Unit
R1 RESET Input valid to CLKOUT High
tRVCH
tCHRI
9
1.5
5
-
ns
ns
R2 CLKOUT High to RESET Input invalid
R3 RESET Input valid Time 2
-
tRIVT
-
tCYC
ns
R4 CLKOUT High to RSTOUT Valid
tCHROV
tROVCV
tCOS
-
10
R5 RSTOUT valid to Config. Overrides valid
R6 Configuration Override Setup Time to RSTOUT invalid
R7 Configuration Override Hold Time after RSTOUT invalid
R8 RSTOUT invalid to Configuration Override High Impedance
0
-
ns
20
0
-
tCYC
ns
tCOH
-
tROICZ
-
1 x tCYC
ns
N1 OTES:
All AC timing is shown with respect to 50% O VDD levels unless otherwise noted.
2
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
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CLKOUT
RESET
R1
R2
R3
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides1:
(RCON, Override pins])
1. Refer to the Coldfire Integration Module (CIM) section for more information.
Figure 16. RESET and Configuration Override Timing
10.11Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
10.11.1MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FECn_RXCLK frequency.
Table 54 lists MII receive channel timings.
Table 54. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FECn_RXD[3:0], FECn_RXDV, FECn_RXER to
FECn_RXCLK setup
5
5
—
ns
ns
M2
M3
M4
FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV,
FECn_RXER hold
—
FECn_RXCLK pulse width high
35%
35%
65%
65%
FECn_RXCLK
period
FECn_RXCLK pulse width low
FECn_RXCLK
period
Figure 17 shows MII receive signal timings listed in Table 54.
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Preliminary Electrical Characteristics
M3
FECn_RXCLK (input)
M4
FECn_RXD[3:0] (inputs)
FECn_RXDV
FECn_RXER
M1
M2
Figure 17. MII Receive Signal Timing Diagram
10.11.2MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
Table 55 lists MII transmit channel timings.
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FECn_TXCLK frequency.
The transmit outputs (FECn_TXD[3:0], FECn_TXEN, FECn_TXER) can be programmed to transition
from either the rising or falling edge of FECn_TXCLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 55. MII transmit channel timings.
Num
Characteristic
Min
Max
Unit
M5
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER invalid
5
—
ns
ns
M6
M7
M8
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER valid
—
25
FECn_TXCLK pulse width high
35%
35%
65%
65%
FECn_TXCLK
period
FECn_TXCLK pulse width low
FECn_TXCLK
period
Figure 18 shows MII transmit signal timings listed in Table 55.
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M7
FECn_TXCLK (input)
M5
M8
FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER
M6
Figure 18. MII Transmit Signal Timing Diagram
10.11.3MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 56 lists MII asynchronous inputs signal timing.
Table 56. MII asynchronous input signal timing
Num
Characteristic
Min
1.5
Max
Unit
M9
FECn_CRS, FECn_COL minimum pulse width
—
FECn_TXCLK
period
Figure 19 shows MII asynchronous input timings listed in Table 56.
FECn_CRS, FECn_COL
M9
Figure 19. MII Async Inputs Timing Diagram
10.11.4MII Serial Management Channel Timing (FECn_MDIO and
FECn_MDC)
Table 57 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 57. MII serial management channel timings.
Num
Characteristic
Min Max
Unit
M10 FECn_MDC falling edge to FECn_MDIO output invalid (minimum
0
—
ns
propagation delay)
M11 FECn_MDC falling edge to FECn_MDIO output valid (max prop delay)
M12 FECn_MDIO (input) to FECn_MDC rising edge setup
M13 FECn_MDIO (input) to FECn_MDC rising edge hold
—
10
0
25
—
—
ns
ns
ns
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Preliminary
Preliminary Electrical Characteristics
Table 57. MII serial management channel timings.
Characteristic Min Max
Num
Unit
M14 FECn_MDC pulse width high
M15 FECn_MDC pulse width low
40% 60% MDC period
40% 60% MDC period
Figure 20 shows MII serial management channel timings listed in Table 57.
M14
M15
FECn_MDC (output)
M10
FECn_MDIO (output)
M11
FECn_MDIO (input)
M12
M13
Figure 20. MII Serial Management Channel Timing Diagram
10.11.5USB Interface AC Timing Specifications
Table 58 lists USB Interface timings.
Table 58. USB Interface timings.
Num
Characteristic
Min
Max
Units
US1
US2
US3
US4
USB_CLK frequency of operation
48
—
—
45
48
2
MHz
ns
USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V)
USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V)
2
ns
USB_CLK duty cycle (at 0.5 x O VDD
)
55
%
Data Inputs
US5
US6
USB_RP, USB_RN, USB_RXD valid to USB_CLK high
USB_CLK high to USB_RP, USB_RN, USB_RXD invalid
Data Outputs
6
6
—
—
ns
ns
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Table 58. USB Interface timings.
Characteristic
Num
Min
Max
Units
US7
US8
USB_CLK high to USB_TP, USB_TN, USB_SUSP valid
USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid
—
3
12
—
ns
ns
Figure 21 shows USB interface timings listed in Table 58.
US1
USB_CLK
US8
US7
USB Outputs
US5
US6
USB Inputs
trise
Vh = VIH
Input Rise Time
Input Fall Time
Vl = VIL
tfall
Vh = VIH
Vl = VIL
Figure 21. USB Signals timing diagram
10.12I2C Input/Output Timing Specifications
2
Table 59 lists specifications for the I C input timing parameters shown in Figure 22.
2
Table 59. I C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I1
I2
I3
I4
I5
2 x tCYC
—
—
1
ns
ns
Clock low period
8 x tCYC
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
Data hold time
—
0
mS
ns
—
1
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
mS
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Preliminary Electrical Characteristics
2
Table 59. I C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I6
I7
I8
I9
Clock high time
Data setup time
4 x tCYC
0
—
—
—
—
ns
ns
ns
ns
Start condition setup time (for repeated start condition only)
Stop condition setup time
2 x tCYC
2 x tCYC
2
Table 60 lists specifications for the I C output timing parameters shown in Figure 22.
2
Table 60. I C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Start condition hold time
Min
Max
Units
I11
6 x tCYC
10 x tCYC
—
—
—
—
ns
ns
µS
I2 1
I3 2
Clock low period
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
I4 1
I5 3
Data hold time
7 x tCYC
—
—
3
ns
ns
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
I6 1
I7 1
I8 1
Clock high time
Data setup time
10 x tCYC
2 x tCYC
—
—
—
ns
ns
ns
Start condition setup time (for repeated start
condition only)
20 x tCYC
I9 1
Stop condition setup time
10 x tCYC
—
ns
N1 OTES:
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 60. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the I2C_SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 60 are minimum values.
2
3
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 59 and Table 60.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
PreliminaryElectricalCharacteristics
I2
I6
I5
SCL
SDA
I3
I1
I4
I8
I9
I7
2
Figure 22. I C Input/Output Timings
10.13DMA Timers Timing Specifications
Table 61 lists timer module AC timings.
Table 61. Timer Module AC Timing Specifications
Name
Characteristic 1
Min
Max
Unit
T1
T2
T0IN / T1IN / T2IN / T3IN cycle time
T0IN / T1IN / T2IN / T3IN pulse width
3 x tCYC
1 x tCYC
—
—
ns
ns
N1 OTES:
All timing references to CLKOUT are given to its rising edge.
10.14QSPI Electrical Specifications
Table 62 lists QSPI timings.
Table 62. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QS2
QS3
QS4
QS5
QSPI_CS[3:0] to QSPI_CLK
1
—
2
510
10
—
tCYC
ns
QSPI_CLK high to QSPI_DOUT valid.
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
QSPI_DIN to QSPI_CLK (Input setup)
QSPI_DIN to QSPI_CLK (Input hold)
ns
9
—
ns
9
—
ns
The values in Table 62 correspond to Figure 23.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
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QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 23. QSPI Timing
10.15JTAG and Boundary Scan Timing
Table 63. JTAG and Boundary Scan Timing
Num
Characteristics1
TCLK Frequency of Operation
Symbol
Min
Max
Unit
J1
J2
fJCYC
tJCYC
DC
1/4
-
fsys/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK Cycle Period
4 x tCYC
J3
TCLK Clock Pulse Width
tJCW
26
0
-
J4
TCLK Rise and Fall Times
tJCRF
3
-
J5
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
TMS, TDI Input Data Hold Time after TCLK Rise
TCLK Low to TDO Data Valid
tBSDST
tBSDHT
tBSDV
4
J6
26
0
-
J7
33
33
-
J8
tBSDZ
0
J9
tTAPBST
tTAPBHT
tTDODV
tTDODZ
tTRSTAT
tTRSTST
4
J10
J11
J12
J13
10
0
-
26
8
-
TCLK Low to TDO High Z
0
TRST Assert Time
100
10
J14
TRST Setup Time (Negation) to TCLK High
-
N1 OTES:
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
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Preliminary
PreliminaryElectricalCharacteristics
J2
J3
J3
VIH
TCLK
(input)
VIL
J4
J4
Figure 24. Test Clock Input Timing
TCLK
VIL
VIH
J5
J6
Data Inputs
Input Data Valid
J7
J8
Data Outputs
Output Data Valid
Data Outputs
Data Outputs
J7
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
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Preliminary
Preliminary Electrical Characteristics
TCLK
VIL
VIH
J9
Input Data Valid
J10
TDI
TMS
J11
TDO
Output Data Valid
J12
J11
TDO
TDO
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
TRST
14
13
Figure 27. TRST Timing
10.16Debug AC Timing Specifications
Table 64 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 64. Debug AC Timing Specification
166 MHz
Num
Characteristic
Units
Min
Max
D0
PSTCLK cycle time
0.5
tCYC
ns
D1
PST, DDATA to CLKOUT setup
CLKOUT to PST, DDATA hold
DSI-to-DSCLK setup
4
D2
1.5
ns
D3
1 x tCYC
4 x tCYC
ns
D4 1
DSCLK-to-DSO hold
ns
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Preliminary
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Table 64. Debug AC Timing Specification
166 MHz
Units
Num
Characteristic
Min
Max
D5
DSCLK cycle time
5 x tCYC
4
ns
ns
ns
ns
D6
D7
D8
BKPT input data setup time to CLKOUT Rise
BKPT input data hold time to CLKOUT Rise
CLKOUT high to BKPT high Z
1.5
0.0
10.0
NOTES:
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input
relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 64.
CLKOUT
D1
D2
PST[3:0]
DDATA[3:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 64.
CLKOUT
D5
DSCLK
D3
DSI
Current
Past
Next
D4
DSO
Current
Figure 29. BDM Serial Port AC Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Device/Family Documentation List
11 Device/Family Documentation List
Table 65. MCF5275 Documentation
Motorola
Document
Number
Title
Revision
Status
MCF5275EC/D MCF5275 RISC Microprocessor Hardware Specifications
0
0
0
0
0
This Document
In Process
Available
MCF5275RM/D
MCF5275PB/D
MCF5275FS
MCF5275 Reference Manual
MCF5275 Product Brief
MCF5275 Fact Sheet
In Process
Available
CFPRODFACT/D
The ColdFire Family of 32-Bit Microprocessors Family
Overview and Technology Roadmap
MCF5XXXWP
MCF5XXXWP WHITE PAPER: Motorola ColdFire VL
RISC Processors
0
Available
MAPBGAPP
CFPRM/D
MAPBGA 4-Layer example
0
2
Available
Available
ColdFire Family Programmer's Reference Manual
12 Document Revision History
Table 66 provides a revision history for this hardware specification.
Table 66. Document Revision History
Rev. No.
Substantive Change(s)
1.1
Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.
1
0
Added Figure 6
Initial release.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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DocumentRevisionHistory
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MCF5275EC/D
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• Preliminary
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