MCF5307 [MOTOROLA]
UART MODULE; UART模块
MOTOROLA 
MCF5307
UART MODULE
5307 UART Module
1- 1
®
Motorola ColdFire
UART INTERFACE
OVERVIEW
• TWO INDEPENDENT, FULL DUPLEX ASYNCHRONOUS/SYNCHRONOUS RECEIVER/
TRANSMITTER CHANNELS
• INDEPENDENTLY PROGRAMMABLE BAUD RATE GENERATOR FOR EACH
RECEIVER AND TRANSMITTER DERIVABLE FROM SYSTEM CLOCK
OR EXTERNAL CLOCK ON TIN PIN
MCF5307
• PROGRAMMABLE DATA FORMAT, FIVE TO EIGHT
DATA BITS PLUS PARITY OR ADDRESS MARK BIT
I Addr Gen
I Fetch1
8K
Unified
Cache
System
Bus
Controller
PARITY OPTIONS:
I Fetch2
1- ODD PARITY
2- EVEN PARITY
3- FORCE PARITY
4- NO PARITY
I Decode
Instr Buf
Dec&Sel Op
A Gen & Ex
DRAM Cntr
&
4K SRAM
2 UARTs
2 Timers
4 DMA
• PROGRAMMABLE CHANNEL MODES
NORMAL (FULL DUPLEX)
Chip Selects
AUTOMATIC ECHO (HALF DUPLEX)
LOCAL LOOPBACK
REMOTE LOOPBACK
MAC
Interrupt Ctr
General
Purpose
I/O
Debug Rev B
Module
•UART CAN BE PROGRAMMED TO DIRECTLY
INTERRUPT DMA FOR FAST TRANSFERS
PLL
JTAG
M-Bus
5307 UART Module
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®
Motorola ColdFire
UART RECEIVER
FEATURES :
• AUTOMATIC WAKEUP FOR MULTIDROP APPLICATIONS
• FRAMING, PARITY AND OVERRUN ERROR DETECTIONS
• FALSE START BIT DETECTION
• LINE-BREAK DETECTION
• DETECTION OF A BREAK ORIGINATING IN THE MIDDLE OF A CHARACTER
• START/END BREAK INTERRUPT /STATUS
• FOUR STAGE FIFO RECEIVE BUFFER
• RECEIVER OPERATION MAY BE POLLED OR INTERRUPT DRIVEN
5307 UART Module
1- 3
®
Motorola ColdFire
UART TRANSMITTER
FEATURES:
• DOUBLE-BUFFERED OPERATION
• PARITY GENERATION: ODD, EVEN, NO PARITY OR FORCE PARITY
• STOP BIT GENERATION FROM .563 TO 2-BITS
• BREAK GENERATION
• AUTOMATIC NEGATION OF REQUEST-TO-SEND UPON COMPLETION
OF MESSAGE TRANSMISSION
• PROGRAMMABLE CHARACTER LENGTH FROM 5 TO 8-BITS
5307 UART Module
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®
Motorola ColdFire
UART BLOCK DIAGRAM
AND INTERFACE SIGNALS
RxD - SERIAL RECEIVE DATA PIN, DATA IS SAMPLED ON RISING EDGE
OF CLOCK SOURCE.
RxD
TxD
CTS
4-CHAR REC_BUFF
TxD - SERIAL TRANSMIT DATA PIN, DATA IS SHIFTED OUT ON FALLING
EDGE OF CLOCK SOURCE.
RTS - REQUEST-TO-SEND, THIS PIN MAY BE USED TO CONTROL
SERIAL DATA FLOW WHEN CONNECTED TO CTS INPUT
PIN OF THE TRANSMITTER.
2-CHAR TX_BUFF
INPUT PORT
DATA_BUS
CTS - CLEAR-TO-SEND, THIS SIGNAL GENERATES
INTERRUPT REQUEST TO THE CPU UPON CHANGE
OF STATE.
IRQ
SYS_CLK - CLOCK INPUT TO BAUD RATE GENERATOR OR
16-BIT TIMER TO GENERATE STANDARD
BAUD RATES.
OUTPUT PORT
RTS
TIN
IRQ - AN INTERNAL INTERRUPT REQUEST SIGNAL FROM THE DUART
INTERFACE.
TIN - CAN BE USED AS THE CLOCK SOURCE
16-BIT TIMER/
BAUD RATE
GENERATOR
SYS_CLK
INTERNAL
5307 UART Module
1- 5
®
Motorola ColdFire
BUFFERED DUART (Rx/Tx Buff)
TRANSMIT BUFFER 1, 2
TxD
TRANSMIT SHIFT REGISTER
DATA BUS
TRANSMIT HOLDING REGISTER
(WRITE ONLY)
TxRDY - TRANSMITTER READY FOR A CHAR TO
BE WRITTEN INTO HOLDING REGISTER.
TxEMP - TRANSMIT SHIFT REGISTER IS EMPTY.
RECEIVE BUFFER 1, 2
DATA BUS
RECEIVE HOLDING REGISTER 1
RECEIVE HOLDING REGISTER 2
RECEIVE HOLDING REGISTER 3
RECEIVER SHIFT REGISTER
(READ ONLY)
RxD
RxRDY - RECEIVER READY
FFULL - FIFO full at 3 bytes.
1 OR MORE CHAR
IN FIFO.
5307 UART Module
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®
Motorola ColdFire
RECEIVER REGISTERS
UMR1 - UART MODE REGISTER 1
RxRTS RxIRQ ERR PM1
PM0
PT
B/C1
B/C0
0
READ/WRITE
RST:
0
0
0
0
0
0
0
BITS/CHAR
00 - FIVE BITS
01 - SIX BITS
PARITY MODE AND TYPE
10 - SEVEN BITS
11 - EIGHT BITS
000 - EVEN PARITY
001 - ODD PARITY
010 - LOW PARITY
011 - HIGH PARITY
10x - NO PARITY
110 - MULTIDROP MODE / DATA CHAR
111 - MULTIDROP MODE / ADDRESS CHAR
ERROR MODE
1 - BLOCK MODE
0 - CHARACTER MODE
RECEIVER READY SELECT
1 - FFULL IS THE SOURCE THAT GENERATES IRQ
0 - RxRDY IS THE SOURCE THAT GENERATES IRQ
RXVR RTS CONTROL
1 - UPON RECEIPT OF A START BIT, RTS IS NEGATED IF THE CHANNEL'S FIFO IS FULL
0 - RECEIVER HAS NO EFFECT ON RTS
5307 UART Module
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®
Motorola ColdFire
UART REGISTERS
UMR2 - UART MODE REGISTER 2
CM1
CM0
TxRTS TxCTS SB3
SB2
SB1
SB0
READ/WRITE
RST:
0
0
0
0
0
0
0
0
STOP BIT LENGTH CONTROL
REFER TO USER’S MANUAL
FOR STOP BIT LENGTH
TRANSMITTER CLEAR-TO-SEND
1 = TRANSMITTER USES CTS TO
CONTROL SERIAL DATA FLOW
0 = CTS HAS NO EFFECT ON TRANSMITTER
TRANSMITTER READY-TO-SEND
1 = NEGATE RTS 1-BIT TIME AFTER THE LAST BIT
OF LAST CHARACTER HAS BEEN TRANSMITTED
0 = TRANSMITTER HAS NO EFFECT ON RTS
CHANNEL MODE
0 0 = NORMAL OPERATION
0 1 = AUTOMATIC ECHO
1 0 = LOCAL LOOPBACK
1 1 = REMOTE LOOPBACK
5307 UART Module
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®
Motorola ColdFire
UART MODES
TRANSMITTER
DISABLED
TRANSMITTER
RECEIVER
TxD
TxD
RxD
TRANSMITTER - - - - -
- - - - - - - -
C
P
U
C
P
U
RxD
RECEIVER
NORMAL OPERATION
AUTOMATIC ECHO
UMR2(CM1:0) = 00
UMR2(CM1:0) = 01
TRANSMITTER
DISABLED
TxD
OUTPUT
TRANSMITTER - - - - -
- - - - - - -
TRANSMITTER
RECEIVER
- - - - -
TxD
C
P
U
C
P
U
DISABLED
RxD
INPUT
RECEIVER
- - - - -
- - - - - - -
RxD
DISABLED
- - - - -
RECEIVER
DISABLED
LOCAL LOOPBACK
REMOTE LOOPBACK
UMR2(CM1:0) = 10
UMR2(CM1:0) = 11
5307 UART Module
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®
Motorola ColdFire
RECEIVER/TRANSMITTER STATUS
USR - STATUS REGISTER
READ ONLY
RB
FE
PE
OE
TxEMP TxRDY FFULL
RxRDY
RST:
0
0
0
0
0
0
0
0
RECEIVER READY
1 = 1 OR MORE CHARACTERS ARE WAITING TO BE READ
0 = CPU READ THE ENTIRE FIFO
FIFO IS FULL
1 = 3-STAGE RECEIVE BUFFER IS FULL
0 = FIFO IS NOT FULL AND MAY CONTAIN UP TO 2-CHAR
TRANSMITTER READY
1 = TRANSMIT HOLDING REGISTER IS EMPTY
0 = TRANSMITTER IS FULL OR DISABLED
TRANSMITTER EMPTY
1 = UNDERRUN CONDITION IS DETECTED
0 = TRANSMITTER IS NOT EMPTY OR DISABLED
OVERRUN ERROR
1 = ONE OR MORE CHARS IN THE
DATA STREAM HAS BEEN LOST
0 = NO OVERRUN CONDITION
PARITY ERROR
1 = PARITY ERROR
0 = NO PARITY ERROR
( IN MULTIDROP MODE, THIS BIT
STORES THE VALUE OF THE A/D BIT)
FRAMING ERROR
1 = NO STOP BIT WAS DETECTED WHEN
CHAR WAS RECEIVED IN THE FIFO.
0 = NO FRAMING ERROR WAS DETECTED
RECEIVED BREAK
1 = A BREAK CHAR HAS BEEN RECEIVED AND FURTHER ENTRIES TO
THE FIFO ARE INHIBITED UNTIL RxD RETURNS TO THE HIGH
STATE FOR AT LEAST ONE-HALF BIT TIME.
0 = NO BREAK RECEIVED
5307 UART Module
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®
Motorola ColdFire
BAUD RATE SELECTION
UCSR - CLOCK SELECT REGISTER
RCS3 RCS2
RCS1
RCS0 TCS3 TCS2
TCS1
TCS0
WRITE ONLY
RST:
1
1
0
1
1
1
0
1
1 1 0 1
1 1 1 0
1 1 1 1
TIMER
X16 CLK
X1 CLK
1 1 0 1
1 1 1 0
1 1 1 1
TIMER
X16 CLK
X1 CLK
RECEIVER BAUD RATE SELECTION
TRANSMITTER BAUD RATE SELECTION
5307 UART Module
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®
Motorola ColdFire
UART COMMANDS
UCR - COMMAND REGISTER
WRITE ONLY
-
MISC2
MISC1 MISC0 TC1
TC0
RC1
RC0
RST:
0
0
0
0
0
0
0
0
MISC2 MISC1 MISC0
COMMAND
TC1 TC0
COMMAND
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NO COMMAND
RESET MODE REG PNTR
RESET RECEIVER
RESET TRANSMITTER
RESET ERROR STATUS
RESET BRK CHANGE IRQ
START BREAK
0
0
1
1
0
1
0
1
NO COMMAND
ENABLE TRANSMITTER
DISABLE TRANSMITTER
DO NOT USE
TRANSMITTER COMMANDS
RC1 RC0 COMMAND
STOP BREAK
MISC COMMANDS
0
0
1
1
0
1
0
1
NO COMMAND
ENABLE RECEIVER
DISABLE RECEIVER
DO NOT USE
RECEIVER COMMANDS
5307 UART Module
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®
Motorola ColdFire
UART REGISTERS
UIPCR - INPUT PORT CHANGE REGISTER
0
0
0
COS
0
1
0
1
1
1
1
CTS
CTS
READ ONLY
RST:
0
0
0
COS - WHEN SET INDICATES A LOW-TO-HIGH OR HIGH-TO-LOW TRANSITION
LONGER THAN 25-50usec HAS OCCURRED ON INPUT PIN. AN IRQ IS
GENERATED TO THE CPU, IF ENABLED
CTS - INDICATES THE CURRENT PIN STATE INPUT
UIP - INPUT PORT REGISTER
-
-
-
-
-
-
-
CTS
CTS
READ ONLY
RST:
1
1
1
1
1
1
1
CTS - INDICATES THE CURRENT PIN STATE INPUT
UACR - AUXILIARY CONTROL REGISTER
BGR CTMS2 CTMS1 CTMS0
-
-
-
IEC
0
WRITE ONLY
RST:
0
0
0
0
0
0
0
IEC = 1, ENABLE IRQ TO CPU
BY A CHANGE OF STATE
BGR=1, SET 2 OF BAUD RATES IS SELECTED
BGR=0, SET 1 OF BAUD RATES IS SELECTED
ON CTS INPUT.
IEC = 0, NO IRQ IS GENERATED TO CPU
BECAUSE OF A CHANGE ON CTS
CTMS[2:0} SHOULD BE SET TO 110
5307 UART Module
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®
Motorola ColdFire
UART REGISTERS
UOP1 - OUTPUT PORT DATA REGISTER
WRITE ONLY
-
-
-
-
-
-
-
-
-
-
RTS
0
RST:
-
-
-
-
BIT SET
Write a 1 to force RTS low
UOP0 - OUTPUT PORT DATA REGISTER
WRITE ONLY
-
-
-
-
-
-
-
-
-
RTS
-
RST:
-
-
-
-
-
BIT RESET
Write a 1 to force RTS high
5307 UART Module
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®
Motorola ColdFire
INTERRUPT ENABLE & STATUS
UISR - INTERRUPT STATUS REGISTER
READ ONLY
COS
-
-
-
-
DB
RxRDY
TxRDY
RST:
0
0
0
0
0
0
0
0
UIMR - INTERRUPT MASK REGISTER
WRITE ONLY
COS
-
-
-
-
DB
RxRDY
TxRDY
RST:
0
0
0
0
0
0
0
0
TRANSMITTER READY
1 = TRANSMIT HOLDING
REGISTER IS EMPTY
0 = CPU LOADED TRANSMIT REG.
RECEIVER READY OR FIFO
CHANGE OF STATE
1 = INPUT PIN CHANGED STATE
0 = NO CHANGE OF STATE
FULL. DUPLICATE OF UMR1 BIT6
DELTA BREAK
1 = RECEIVER DETECTED BREAK
0 = NO BREAK DETECTED
5307 UART Module
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®
Motorola ColdFire
UART INTERRUPT CONTROL
ICR 3 & 4- UART INTERRUPT CONTROL REGISTER 3 & 4
B7.........................................................................................................B0
READ/WRITE
AVEC
-
-
IL2
IL1
IL0
IP1
IP0
INTERRUPT PRIORITY
1 1 = HIGHEST
-
-
0 0 = LOWEST
INTERRUPT LEVEL
1 1 1 = IRQ SOURCE HAS HIGHEST PRIORITY
-
-
0 0 1 = IRQ SOURCE HAS LOWEST PRIORITY
0 0 0 = NO INTERRUPT IS REQUESTED
AUTOVECTOR
0 - IRQ SOURCE RETURNS VECTOR
1 - SIM GENERATES AVEC FOR IRQ SOURCE
UIVR - INTERRUPT VECTOR REGISTER
READ/WRITE
IVR7
IVR6
IVR5
IVR4
IVR3
IVR2
IVR1
IVR0
RST:
0
0
0
0
1
1
1
1
5307 UART Module
1- 16
®
Motorola ColdFire
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