MCF5472VF200_技术文档

Advance Information

MCF5475EC/D

Rev. 1.1, 2/2004

MCF547x Integrated

Microprocessor

Hardware Specifications

®

The MCF547x is a highly-integrated implementation of the ColdFire family of reduced

instruction set computing (RISC) microprocessors. This document describes pertinent

electrical and physical characteristics of the MCF547x family: the MCF5470, MCF5471,

MCF5472, MCF5473, MCF5474, and MCF5475.

This document contains the following topics:

Topic

Page

1

Section 1.1, “MCF547x Family Overview”

Section 1.2, “MCF547x Block Diagram”

Section 1.3, “MCF547x Family Products”

Section 1.4, “MCF547x Family Features”

Section 1.5, “Signal Description”

3

4

5

14

43

45

54

58

62

67

68

69

Section 1.6, “Chip Configuration”

Section 1.7, “Design Recommendations”

Section 1.8, “MCF5475/5474 Pinout”

Section 1.9, “MCF5473/5472 Pinout”

Section 1.10, “MCF5471/5470 Pinout”

Section 1.11, “Mechanicals”

Section 1.12, “Ordering Information”

Section 1.13, “Device/Family Documentation List”

Section 1.14, “Document Revision History”

Appendix A, “Preliminary Electrical Characteristics”

To locate any published errata or updates for this document, refer to the web site at

http://motorola.com/semiconductors.

1.1 MCF547x Family Overview

The MCF547x family is based on the ColdFire V4e core, a complex which comprises the

ColdFire V4 central processor unit (CPU), an enhanced multiply-accumulate unit (EMAC), a

memory management unit (MMU), a double-precision floating point unit (FPU) conforming

to standard IEEE-754, and controllers for caches and local data memories. The MCF547x

family is capable of performing at an operating frequency of up to 266 MHz or 410 MIPS

(Dhrystone 2.1).

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MCF547x Family Overview

To maximize throughput, the MCF547x family incorporates three independent external bus interfaces:

1. The general-purpose local bus (FlexBus) is used for system boot memories and simple peripherals

and has up to six chip selects.

2. Program code and data can be stored in SDRAM connected to a dedicated 32-bit double data rate

(DDR) bus that can run at up to one half of the CPU core frequency. The glueless DDR SDRAM

controller handles all address multiplexing, input and output strobe timing, and memory bus clock

generation.

3. A 32-bit PCI bus compliant with the version 2.2 specification and running at a typical frequency of

33 MHz or 66 MHz supports peripherals that require high bandwidth, the ability to arbitrate for

bus mastership, and access to internal MCF547x memory resources.

The MCF547x family provides substantial communications functionality by integrating the following

connectivity peripherals:

•

Up to two 10/100 Mbps fast Ethernet controllers (FECs)

An optional USB 2.0 device (slave) module with seven endpoints and an integrated transceiver

Up to four UART/USART/IRDA/modem programmable serial controllers (PSCs)

A DMA serial peripheral interface (DSPI)

2

™

•

An inter-integrated circuit (I C ) bus controller

Additionally, the MCF547x provides hardware support for a range of Internet security standards with an

optional bus-mastering cryptography accelerator. This module incorporates units to speed DES/3DES and

AES block ciphers, the RC4 stream cipher, bulk data hashing (MD5/SHA-1/SHA-256/HMAC), and random

number generation. Hardware acceleration of these functions is critical to avoiding the throughput

bottlenecks associated with software-only implementations of SSH, SSL/TLS, IPsec, SRTP, WEP, and other

security standards. The incorporation of cryptography acceleration makes the MCF547x family a

compelling solution for a wide range of office automation, industrial control, and SOHO networking

devices that must have the ability to securely transmit critical equipment control information across

typically insecure Ethernet data networks.

Additional features of MCF547x products include a watchdog timer, two 32-bit slice timers for RTOS

scheduling and alarm functionality, up to four 32-bit general-purpose timers with capture, compare, and

pulse width modulation capability, a multisource vectored interrupt controller, a phase-locked loop (PLL)

to generate the system clock, 32 Kbytes of SRAM for high-speed local data storage, and multiple

general-purpose I/O ports. To manage current consumption, MCF547x products provide chip-wide internal

clock gating control on a per module basis under software control.

With on-chip support for multiple common communications interfaces, MCF547x products require only the

addition of memories and certain physical layer transceivers to be cost-effective system solutions for many

applications, such as industrial routers, high-end POS terminals, building automation systems, and process

control equipment.

MCF547x products require four supply voltages: 1.5V for the high-performance, low power, internal core

logic, 2.5V for the DDR SDRAM bus interface, 1.25V for the DDR SDRAM V , and 3.3V for all other

REF

I/O functionality, including the PCI and FlexBus interfaces.

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MCF547x Integrated Microprocessor Hardware Specifications

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MOTOROLA

MCF547xBlockDiagram

1.2 MCF547x Block Diagram

Figure 1 shows a top-level block diagram of the MCF547x products.

DDR SDRAM

Interface

FlexBus

Interface

ColdFire V4e Core

MMU, FPU

EMAC

PLL

32K I-cache

32K D-cache

XL Bus

Arbiter

Memory

Controller

FlexBus

Controller

XL Bus

Master/Slave

Interface

Interrupt

Controller

PCI 2.2

Controller

Watchdog

Timer

Cryptography

Accelerator***

Slice

Timers x 2

32K System

SRAM

XL Bus

Read/Write

GP

Timers x 4

Multi-Channel DMA

Master Bus Interface & FIFOs

PCI Interface

& FIFOs

CommBus

USB 2.0

DSPI

I²C

PSC x 4

FEC1

FEC2**

DEVICE*

USB 2.0

PHY*

Perpheral Communications I/O Interface and Ports

*Available in MCF5475, MCF5474, MCF5473, and MCF5472 devices.

**Available in MCF5475, MCF5474, MCF5471, and MCF5470 devices.

***Available in MCF5475, MCF5473, and MCF5471 devices.

Figure 1. MCF547x Block Diagram

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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MCF547x Family Products

1.3 MCF547xFamily Products

Table 1 summarizes the products available within the MCF547x product family. All products are available

in pin-compatible, 388 pin PBGA packaging allowing for ease of mirgration between products within the

family. A printed circuit board designed using the MCF5475/4 footprint is compatible with any of the

MCF547x family devices.

Table 1. MCF547x Family Products

Product

Performance

Features

Temperature Range

MCF5475

410 MIPS

266 MHz

Two 10/100 Ethernet Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

^{0 to 70}° C

DDR Memory Controller

Encryption Accelerator

MCF5474

MCF5473

410 MIPS

266 MHz

Two 10/100 Ethernet Controllers

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

^{0 to 70}° C

DDR Memory Controller

308 MIPS

200 MHz

One 10/100 Ethernet Controller

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

^{0 to 70}° C

DDR Memory Controller

Encryption Accelerator

MCF5472

MCF5471

MCF5470

308 MIPS

200 MHz

One 10/100 Ethernet Controller

USB 2.0 Device with Integrated PHY

v2.2 PCI Controller

^{0 to 70}° C

DDR Memory Controller

308 MIPS

200 MHz

Two 10/100 Ethernet Controllers

v2.2 PCI Controller

DDR Memory Controller

Encryption Accelerator

308 MIPS

200 MHz

Two 10/100 Ethernet Controllers

v2.2 PCI Controller

DDR Memory Controller

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF547xFamilyFeatures

1.4 MCF547x Family Features

•

ColdFire V4e core

— Limited superscalar V4 ColdFire processor core

— Up to 266 MHz peak internal core frequency (410 Dhrystone 2.1 MIPS)

— Harvard architecture

– 32-Kbyte instruction cache

– 32-Kbyte data cache

— Memory management unit (MMU)

– Separate, 32-entry, fully-associative instruction and data translation lookahead buffers

— Floating point unit (FPU)

– Double-precision support that conforms to IEEE-754 standard

– Eight floating point registers

•

Internal master bus (XLB) arbiter

— High performance split address and data transactions

— Support for various parking modes

32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller

— 66–133 MHz operation

— Supports both DDR and SDR DRAM

— Built-in initialization and refresh

— Up to four chip selects enabling up to 1 GB of external memory

Version 2.2 peripheral component interconnect (PCI) bus

— 32-bit target and initiator operation

•

— Support for up to five external PCI masters

— 33–66 MHz operation with PCI bus to XLB divider ratios of 1:1, 1:2, and 1:4

Flexible multifunction external bus (FlexBus)

— Supports operation with the following:

– Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over

PCI bus–PCI not usable)

– Multiplexed 32-bit address and 32-bit data (PCI usable)

– Multiplexed 32-bit address and 16-bit data

– Multiplexed 32-bit address and 8-bit data

— Provides a glueless interface to boot Flash/ROM, SRAM, and peripheral devices

— Up to six chip selects

— 33–66 MHz operation

•

Communications I/O subsystem

— Intelligent 16-channel DMA controller

— Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces

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MCF547x Family Features

— Up to two 10/100 Mbps fast Ethernet controllers (FECs), each with separate 2-Kbyte receive

and transmit FIFOs

— Universal serial bus (USB) version 2.0 device controller

– Support for one control and six programmable endpoints — interrupt, bulk, or isochronous

– 4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM

– Integrated physical layer interface

— Up to four programmable serial controllers (PSCs) each with separate 512-byte receive and

transmit FIFOs for UART, USART, modem, codec, and IrDA 1.1 interfaces

2

— I C peripheral interface

— DMA serial peripheral interface (DSPI)

Optional security encryption controller (SEC) module

— Execution units for the following:

– DES/3DES block cipher

•

– AES block cipher

– RC4 stream cipher

– MD5/SHA-1/SHA-256/HMAC hashing

– Random number generator compliant with FIPS 140-1 standards for randomness and

non-determinism

— Dual-channel architecture permits single-pass encryption and authentication

32-Kbyte system SRAM

•

— Arbitration mechanism shares bandwidth between internal bus masters (CPU, cryptography

accelerator, PCI, and DMA)

System integration unit (SIU)

— Interrupt controller

— Watchdog timer

— Two 32-bit slice timers for periodic alarm and interrupt generation

— Up to four 32-bit general-purpose timers with capture, compare, and PWM capability

— General-purpose I/O ports multiplexed with peripheral pins

Debug and test features

•

— Core debug support via ColdFire background debug mode (BDM) port

— Chip debug support via JTAG/ IEEE 1149.1 test access port

PLL and clock generator

•

— 30–66.67 MHz input frequency range

Operating Voltages

— 1.5V internal logic

— 2.5V DDR SDRAM bus I/O (1.25V V

— 3.3V PCI, FlexBus, and all other I/O

Estimated power consumption

— <1.5W

)

REF

•

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF547xFamilyFeatures

1.4.1 ColdFire V4e Core Overview

The ColdFire V4e core is a variable-length RISC, clock-multiplied core that includes a Harvard memory

architecture, branch cache acceleration logic, and limited superscalar dual-instruction issue capabilities. The

limited superscalar design approaches dual-issue performance with the cost of a scalar execution pipeline.

The ColdFire V4e processor core is comprised of two separate pipelines that are decoupled by an instruction

buffer. The four-stage instruction fetch pipeline (IFP) prefetches the instruction stream, examines it to

predict changes of flow, partially decodes instructions, and packages fetched data into instructions for the

operand execution pipeline (OEP). The IFP can prefetch instructions before the OEP needs them,

minimizing the wait for instructions. The instruction buffer is a 10 instruction, first-in-first-out (FIFO)

buffer that decouples the IFP and OEP by holding prefetched instructions awaiting execution in the OEP.

The OEP includes five pipeline stages: the first stage decodes instructions and selects operands (DS), and

the second stage generates operand addresses (OAG). The third and fourth stages fetch operands (OC1 and

OC2), and the fifth stage executes instructions (EX).

The ColdFire V4e processor contains a double-precision floating point unit (FPU). The FPU conforms to

the American National Standards Institute (ANSI)/Institute of Electrical and Electronics Engineers (IEEE)

Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754). The FPU operates on 64-bit,

double-precision floating point data and supports single-precision and signed integer input operands. The

FPU programming model is like that in the MC68060 microprocessor. The FPU is intended to accelerate

the performance of certain classes of embedded applications, especially those requiring high-speed floating

point arithmetic computations.

The ColdFire V4e processor also incorporates the ColdFire memory management unit (MMU), which

provides virtual-to-physical address translation and memory access control. The MMU consists of

memory-mapped control, status, and fault registers that provide access to translation lookaside buffers

(TLBs). Software can control address translation and access attributes of a virtual address by configuring

MMU control registers and loading TLBs. With software support, the MMU provides demand-paged,

virtual addressing.

The ColdFire V4e core implements the ColdFire instruction set architecture revision B with support for

floating Point instructions. Additionally, the ColdFire V4e core includes the enhanced multiply-accumulate

unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution

pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported

operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands and a

complete set of instructions to process these data types. The EMAC provides superb support for execution

of DSP operations within the context of a single processor at a minimal hardware cost.

1.4.2 Debug Module (BDM)

The ColdFire processor core debug interface is provided to support system debugging in conjunction with

low-cost debug and emulator development tools. Through a standard debug interface, users can access

real-time trace and debug information. This allows the processor and system to be debugged at full speed

without the need for costly in-circuit emulators.

The MCF547x debug module provides support in three different areas:

•

Real-time trace support: The ability to determine the dynamic execution path through an

application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel

output bus that reports processor execution status and data to an external BDM emulator system.

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MCF547x Family Features

•

Background debug mode (BDM): Provides low-level debugging in the ColdFire processor

complex. In BDM, the processor complex is halted and a variety of commands can be sent to the

processor to access memory and registers. The external BDM emulator uses a three-pin, serial,

full-duplex channel.

•

Real-time debug support: BDM requires the processor to be halted, which many real-time

embedded applications cannot permit. Debug interrupts let real-time systems execute a unique

service routine that can quickly save key register and variable contents and return the system to

normal operation without halting. External development systems can access saved data because

the hardware supports concurrent operation of the processor and BDM-initiated commands. In

addition, the option is provided to allow interrupts to occur.

1.4.3 JTAG

The MCF547x family supports circuit board test strategies based on the Test Technology Committee of

IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of

a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit

boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one

shift register. Test logic, implemented using static logic design, is independent of the device system logic.

The MCF547x implementation can do the following:

•

Perform boundary scan operations to test circuit board electrical continuity

Sample MCF547x system pins during operation and transparently shift out the result in the

boundary scan register

•

Bypass the MCF547x for a given circuit board test by effectively reducing the boundary-scan

register to a single bit

•

Disable the output drive to pins during circuit-board testing

Drive output pins to stable levels

1.4.4 On-Chip Memories

1.4.4.1 Caches

There are two independent caches associated with the ColdFire V4e core complex: a 32-Kbyte instruction

cache and a 32-Kbyte data cache. Caches improve system performance by providing single-cycle

access to the instruction and data pipelines. This decouples processor performance from system

memory performance, increasing bus availability for on-chip DMA or external devices.

1.4.4.2 System SRAM

The SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 32-Kbyte address boundary within the

4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the system

stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's

high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from

the debug module.

The SRAM module is also accessible by multiple non-core bus masters, such as the DMA controller, the

encryption accelerator, and the PCI Controller.

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF547xFamilyFeatures

1.4.5 PLL and Chip Clocking Options

MCF547x products contain an on-chip PLL capable of accepting input frequencies from 30–66.66 MHz.

Table 2 contains the frequencies of the system buses for the members of the MCF547x family under various

core/SDRAM/PCI/Flexbus clocking options.

Table 2. MCF547x Family Clocking Options

Internal XLB and SDRAM CLKIN—PCI and FlexBus

Core

(MHz)

Bus Frequency

(MHz)

Frequency

(MHz)

Clock Ratio

240.0–266.66

120.0–266.66

120–133.33

60.0–133.33

30.0–33.3

1:4

1:2

30.0–66.66

1.4.6 Communications I/O Subsystem

1.4.6.1 DMA Controller

The communications subsystem contains an intelligent DMA unit that provides front line interrupt control

and data movement interface via a separate peripheral bus to the on-chip peripheral functions, leaving the

processor core free to handle higher level activities. This concurrent operation enables a significant boost in

overall system performance.

The communications subsystem can support up to 16 simultaneously enabled DMA tasks, with support for

up to 2 external DMA requests. It uses internal buffers to prefetch reads and post writes such that bursting

is used whenever possible. This optimizes both internal and external bus activity. The following

communications and computer control peripheral functions are integrated and controlled by the

communications subsystem:

•

Up to two 10/100 Mbps fast Ethernet controllers (FECs)

Optional universal serial bus (USB) version 2.0 device controller

Up to four programmable serial controllers (PSCs)

2

I C peripheral interface

DMA serial peripheral interface (DSPI)

1.4.6.2 10/100 Fast Ethernet Controller (FEC)

The FEC supports the following standard MAC/PHY interfaces: 10/100 Mbps IEEE 802.3 MII, and

10Mbps 7-wire interface. The controller is full duplex, supports a programmable maximum frame length

and retransmission from the transmit FIFO following a collision.

Support for different Ethernet physical interfaces:

— 100 Mbps IEEE 802.3 MII

— 10 Mbps IEEE 802.3 MII

— 10 Mbps 7-wire interface

•

IEEE 802.3 full-duplex flow control.

Support for full-duplex operation (200 Mbps throughput) with a minimum system clock frequency

of 50 MHz.

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MCF547x Family Features

•

Support for half duplex operation (100 Mbps throughput) with a minimum system clock frequency

of 25 MHz.

•

Retransmit from transmit FIFO following collision.

Internal loopback for diagnostic purposes.

1.4.6.3 USB 2.0 Device (Universal Serial Bus)

The USB module implementation on the MCF547x product family provides all the logic necessary to

process the USB protocol as defined by version 2.0 specification for peripheral devices.

•

High-speed operation up to 480 Mbps, full-speed operation at 12 Mbps, and low-speed operation

at 1.5 Mbps

•

Physical interface on chip

Bulk, interrupt, and isochronous transport modes.

Six programmable in/out endpoints and one control endpoint

4 Kbytes of shared endpoint FIFO RAM and 1 Kbyte of endpoint descriptor RAM

1.4.6.4 Programmable Serial Controllers (PSCs)

The MCF547x product family supports four PSCs that can be independently configured to operate in the

following modes:

•

Universal asynchronous receiver transmitter (UART) mode

— 5,6,7,8 bits of data plus parity

— Odd, even, none, or force parity

— Stop bit width programmable in 1/16 bit increments

— Parity, framing, and overrun error detection

— Automatic PSCCTS and PSCRTS modem control signals

IrDA 1.0 SIR mode (SIR)

•

— Baud rate range of 2400–115200 bps

— Selectable pulse width: either 3/16 of the bit duration or 1.6 µs

IrDA 1.1 MIR mode (MIR)

•

— Baud rate of 0.576 or 1.152 Mbps

IrDA 1.1 FIR mode (FIR)

— Baud rate of 4.0 Mbps

•

8-bit soft modem mode (modem8)

16-bit soft modem mode (modem16)

AC97 soft modem mode (AC97)

Each PSC supports synchronous (USART) and asynchronous (UART) protocols. The PSCs can be used to

interface to external full-function modems or external codecs for soft modem support, as well as IrDA 1.1

or 1.0 interfaces. Both 8- and 16-bit data widths are supported. PSCs can be configured to support 1200 baud

plain old telephone system (POTS) modem, V.34 or V.90 protocols. The standard UART interface supports

connection to an external terminal/computer for debug support.

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MCF547xFamilyFeatures

2

1.4.6.5 I C (Inter-Integrated Circuit)

2

The MCF547x product family provides an I C two-wire, bidirectional serial bus for on-board

communication.

•

Multimaster operation with arbitration and collision detection

Calling address recognition and interrupt generation

Automatic switching from master to slave on arbitration loss

Software-selectable acknowledge bit

Start and stop signal generation and detection

Bus busy status detection

1.4.6.6 DMA Serial Peripheral Interface (DSPI)

The DSPI block operates as a basic SPI block with FIFOs providing support for external queue operation.

Data to be transmitted and data received reside in separate FIFOs. The FIFOs can be popped and pushed by

host software or by the system DMA controller. The DSPI supports these SPI features:

•

Full-duplex, three-wire synchronous transfers

Master and slave mode—two peripheral chip selects in master mode

DMA support

1.4.7 DDR SDRAM Memory Controller

The DDR SDRAM memory controller is a glueless interface to DDR memories. The module uses a 32 bit

memory port and can address a maximum of 1 Gbyte of data with sixteen 64M x 8 (512-Mbit) devices, 4

per chip select. The controller supplies two clock lines and respective inverted clock lines to help minimize

system complexity when using DDR. The module supports either DDR or SDR but not both. This is due to

voltage differences between the memory technologies. The supported memory clock rate is up to 133 MHz.

At this memory clock rate, DDR memory can receive data at an effective rate of up to 266 MHz.

•

Support for up to 13 lines of row address, 11 lines of column address, 2 lines of bank address, and

up to 4 chip selects

•

Memory bus width fixed at 32 bits

Four chip selects support up to 1 GByte of SDRAM memory

Support for page mode to maximize the data rate. Page mode remembers active pages for all four

chip selects

•

Support for sleep mode and self refresh

Cache line reads that can use critical word first. These reads can start in the center of a burst and

will wrap to the beginning. This allows the processor quicker access to a needed instruction.

All on-chip bus masters have access to DRAM. This includes PCI, the ColdFire V4e core, the cryptography

accelerator, and the DMA controller.

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF547x Family Features

1.4.8 Peripheral Component Interconnect (PCI)

The PCI controller is a PCI V2.2-compliant bus controller and arbiter. The PCI bus is capable of 66-MHz

operation with a 32-bit address/data bus and support for five external masters.

The PCI module includes an inbound FIFO to increase performance when using an external bus master. The

bus can address all 4 Gbytes of PCI-addressable space.

The PCI bus is also multiplexed with the flexible local bus (FlexBus) address lines. If 32-bit non-muxed

local address and data is required it can be obtained at the expense of utilizing the PCI bus.

When implemented, the PCI controller acts as the central resource, bus arbiter, and configuring master on

the PCI bus.

1.4.9 Flexible Local Bus (FlexBus)

The FlexBus module is intended to provide the user with basic functionality required to interface to

peripheral devices. The FlexBus interface is a multiplexed or non-multiplexed bus, with an operating

frequency from 33–66 MHz. The Flexbus is targeted to support external Flash memories, boot ROMs,

gate-array logic, or other simple target interfaces. Up to six chip selects are supported by the FlexBus.

Possible combinations of address and data bits are:

•

Non-multiplexed 32-bit address and 32-bit data (32-bit address muxed over

PCI bus–PCI not usable)

•

Multiplexed 32-bit address and 32-bit data (PCI usable)

Multiplexed 32-bit address and 16-bit data

Multiplexed 32-bit address and 8-bit data

The non-multiplexed 32-bit address and 32-bit data mode is determined at chip reset. For all other modes,

the full 32-bit address is driven during the address phase. The number of bytes used for data are determined

on a chip select by chip select basis.

1.4.10 Security Encryption Controller (SEC)

As consumers and businesses continue to embrace the Internet, the need for secure point-to-point

communications across what is an entirely insecure network has been met by the development of a range of

standard protocols. Computer cryptography fundamentally involves calculations with very large numbers.

Personal computers have sufficient processing power to implement these algorithms entirely in software.

When placed upon the embedded devices typically used for routing and remote access functions, this same

computational burden can potentially decrease the throughput of a 100 Mbps Ethernet interface down to 10

Mbps.

Hardware acceleration of common cryptography algorithms is the solution to the computational bandwidth

requirements of Internet security standards. Discrete solutions currently address this problem, but the next

logical step is to integrate a cryptography accelerator on an embedded processor, such as the MCF547x

family.

Motorola has developed the SEC on the MCF547x family for this purpose. This block accelerates the core

cryptography algorithms that underlie standard Internet security protocols like SSL/TLS, IPSec, IKE, and

WTLS/WAP.

•

The SEC includes execution units for the following:

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MCF547xFamilyFeatures

— DES/3DES block cipher

— AES block cipher

— RC4 stream cipher

— MD5/SHA-1/SHA-256/HMAC hashing

— Random number generator compliant with FIPS 140-1 standards for randomness and

non-determinism

•

Dual-channel architecture permits single-pass encryption and authentication

1.4.11 System Integration Unit (SIU)

1.4.11.1 Timers

The MCF547x family integrates several timer functions required by most embedded systems. Two internal

32-bit slice timers are provided to create short cycle periodic interrupts, typically utilized for RTOS

scheduling and alarm functionality. A watchdog timer is included which will reset the processor if not

regularly serviced, catching software hang-ups. Four 32-bit general purpose timers are included, which are

capable of input capture, output compare, and PWM functionality.

1.4.11.2 Interrupt Controller

The interrupt controller on the MCF547x family can support up to 63 interrupt sources. The interrupt

controller is organized as seven levels with nine interrupt sources per level. Each interrupt source has a

unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7]

and priority within the level.

•

Support for up to 63 interrupt sources organized as follows:

— 56 fully-programmable interrupt sources

— 7 fixed-level interrupt sources

•

Seven external interrupt signals

Unique vector number for each interrupt source

Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

Support for hardware and software interrupt acknowledge (IACK) cycles

Combinatorial path to provide wake-up from low power modes

1.4.11.3 General Purpose I/O

All peripheral I/O pins on the MCF547x family are muxed with GPIO, adding flexibility and usability to all

signals on the chip.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

13

Signal Description

1.5 Signal Description

Table 3 lists the signals for the MCF547x in functional group order.

NOTE

In this table and throughout this document, a single signal within a group

is designated without square brackets (for example, AD24), while

designations for multiple signals within a group use bracketed numbers

separated by a colon (for example, AD[31:0]).

Table 3. MCF547x Signal Description

Pin Functions

Reset

State

PBGA Pin

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

FlexBus

AE2, AF3, AF1,

AE3, AE4, AD5,

AF2, AD4

AD[31:24]

AD[23:16]

AD[15:8]

AD[7:0]

—

Multiplexed

address/data bus

I/O

16

Hi-Z

AD3, AC3, AD2,

AC2, AA4, AE1,

AC1, AD1

—

Multiplexed

address/data bus

AB2, AA3, W4,

AB1, AA2, AA1,

Y1, Y2

Multiplexed

address/data bus

W3, W1, W2, V3,

V1, V2, T4, U3

Multiplexed

address/data bus

R1, T2, T3, T1, U2 FBCS[5:1]

PFBCS[5:1]

—

Chip selects 5–1

Chip select 0

Transfer start

Read/write

O:I/O

O

24

16

High

Hi-Z

High

—

U1

FBCS0

TS

AD6

AE5

AF4,

AF5

AC4

AE7

AE6

AF6

PFBCTL0

PFBCTL2

PFBCTL7

PFBCTL6

PFBCTL5

PFBCTL4

PFBCTL3

PFBCTL1

TBST

TSIZ1

TSIZ0

FBADDR1

FBADDR0

—

O:I/O

O

R/W

BE/BWE3

BE/BWE2

BE/BWE1

BE/BWE0

OE

Byte enables

Output enable

O:I/O

I/O

TA

—

Transfer

I:I/O

acknowledge

SDRAM Controller

C10, B9, A8, D5, SDDATA[31:2

A6, C8, B7, A5 4]

—

SDRAM data bus

I/O

24

Hi-Z

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

14

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

SignalDescription

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

PBGA Pin

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

A4, C7, B6, B4, SDDATA[23:1

C5, B3, C4, D4 6]

—

SDRAM data bus

I/O

O

24

Hi-Z

Low

E2, D1, G4, E1, SDDATA[15:8

K4, F1, G2, H3

—

]

N4, G1, H2, J3, J1, SDDATA[7:0]

M4, K3, K2

A13, A12, D10, SDADDR[12:

SDRAM address

bus

B12, C12, A11,

D8, B11, C11,

0]

A10, D7, B10, A9

M2, M3

SDBA[1:0]

RAS

—

SDRAM bank

addresses

O

24

Low

High

E3

SDRAM row

address strobe

C2

CAS

SDRAM column

address strobe

R2, P2, P1, N3

B8, A3, G3, J2

SDCS[3:0]

SDDM[3:0]

—

SDRAM chip selects

O

24

High

SDRAM write data

byte mask

A7, B5, F2, H1

L1, N1

SDDQS[3:0]

SDCLK[1:0]

—

SDRAM data strobe

SDRAM clock

I/O

O

24

High

Low

M1, N2

Inverted SDRAM

clock

O

K1

E4

L2

D2

SDWE

SDCKE

SDRDQS

VREF

—

SDRAM write

enable

O

I

24

—

Low

—

SDRAM clock

enable

SDR SDRAM data

strobe

SDRAM reference

voltage

PCI Controller

V25, V26, U25, PCIAD[31:24]

U26, T24, T25,

—

FBADDR[31:

24]

—

PCI address/data

bus

I/O

16

Hi-Z

T26, R24

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

15

Signal Description

PBGA Pin

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

R25, R26, P26, PCIAD[23:16]

P24, P23, P25,

—

FBADDR[23:

16]

—

PCI address/data

bus

I/O

16

Hi-Z

N25, N23

N26, N24, M26, PCIAD[15:8]

M25, L26, L25,

—

FBADDR[15:

8]

—

PCI address/data

bus

I/O

16

K26, K25

J26, K24, J25,

H26, J24, G26,

H25, K23

PCIAD[7:0]

FBADDR[7:0]

—

PCI address/data

bus

F26, G25, E26, PCICXBE[3:0

PCI command/byte

enables

G24

J23

F25

C23

]

PCIDEVSEL

PCIFRM

—

PCI device select

PCI frame

I/O

I

16

—

Hi-Z

—

PCIIDSEL

PCI initialization

device select

D24

F23

D26

G23

F24

E25

C26

W24

PCIIRDY

PCIPAR

—

PCI initiator ready

PCI parity

I/O

O

16

Hi-Z

Low

Hi-Z

GPI

—

PCIPERR

PCIRESET

PCISERR

PCISTOP

PCITRDY

PCIBG4

—

PCI parity error

PCI reset

—

PCI system error

PCI stop

I/O

O

—

PCI target ready

PCI external grant 4

PPCIBG4

PPCIBG[3:0]

TBST

TOUT[3:0]

Y26, W25, V24,

W26

PCIBG[3:0]

PCI external grant

3–0

I/O

D21

PCIBR4

PPCIBR4

IRQ4

—

PCI external

request 4

I:I/O

8

GPI

B24, A25, B23,

A24

PCIBR[3:0]

PPCIBR[3:0]

TIN[3:0]

PCI external

request 3

External Interrupts Port

D14

IRQ7

PIRQ7

—

External interrupt

request 7

I

—

B14, A14

IRQ[6:5]

PIRQ[6:5]

External interrupt

request 6—5

Ethernet MAC 0

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

16

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

SignalDescription

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

PBGA Pin

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

AF10

E0MDIO

PFECI2C3

—

Management

channel

serial data

I/O

8

GPI

AD11

E0MDC

PFECI2C2

—

Management

channel clock

O:I/O

8

AF9

E0TXCLK

E0TXEN

PFEC0H7

PFEC0H6

—

MAC transmit clock

I:I/O

8

GPI

AE10

MAC transmit

enable

O:I/O

AD9

AC9

E0TXD0

E0COL

PFEC0H5

PFEC0H4

PFEC0H3

PFEC0H2

PFEC0H1

PFEC0H0

—

MAC transmit data

MAC collision

O:I/O

I:I/O

8

GPI

AD14

E0RXCLK

E0RXDV

E0RXD0

E0CRS

MAC receive clock

AE14

MAC receive enable I:I/O

AD13

MAC receive data

MAC carrier sense

MAC transmit data

I:I/O

AE19

AD8, AC6, AF7

AE9

E0TXD[3:1] PFEC0L[7:5]

E0TXER PFEC0L4

O:I/O

MAC transmit error O:I/O

AF11, AF12, AF13 E0RXD[3:1] PFEC0L[3:1]

MAC receive data

MAC receive error

I:I/O

AC14

E0RXER

PFEC0L0

Ethernet MAC 1

AD25¹

AD24¹

E1MDIO

E1MDC

—

SDA

—

Management

channel serial data

I/O

8

—

SCL

Management

channel clock

O:I/O

AE13¹

AD25¹

E1TXCLK

E1TXEN

PFEC1H7

PFEC1H6

—

MAC Transmit clock I:I/O

8

GPI

MAC Transmit

enable

O:I/O

AE12¹

AF8¹

B22¹

B25¹

E1TXD0

E1COL

PFEC1H5

PFEC1H4

PFEC1H3

PFEC1H2

—

MAC Transmit data O:I/O

8

GPI

MAC Collision

I:I/O

E1RXCLK

E1RXDV

MAC Receive clock

MAC Receive

enable

AF24¹

AC5¹

E1RXD0

E1CRS

PFEC1H1

PFEC1H0

—

MAC Receive data

MAC Carrier sense

I:I/O

8

GPI

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

17

Signal Description

PBGA Pin

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

AC8¹, AC11¹,

AE11¹

E1TXD[3:1] PFEC1L[7:5]

—

MAC Transmit data O:I/O

MAC Transmit error O:I/O

8

GPI

AE24¹

E1TXER

PFEC1L4

—

8

GPI

D25¹, B26¹, A26¹E1RXD[3:1] PFEC1L[3:1]

MAC Receive data

MAC Receive error

I:I/O

AE8¹

E1RXER

PFEC1L0

USB

AF16²

AF17²

AC17²

USBD+

USBD-

—

USB differential data

I/O

I

24

—

USBVBUS

USB Vbus monitor

input

AC15²

AF18²

AF15²

AF14²

NC

—

No Connect

I

—

24

—

USBRBIAS

USBCLKIN

USBCLKOUT

USB bias resistor

USB crystal input

USB crystal output

I

O

DSPI

Y24

DSPISOUT

DSPISIN

PDSPI0

PDSPI1

PDSPI2

PSC3TXD

PSC3RXD

PSC3CTS

—

QSPI data out

QSPI data in

QSPI clock

O:I/O

I:I/O

I/O

24

GPI

AC24

AD22

DSPISCK

PSC3BCL

K

W23

DSPICS5/PC

SS

PDSPI6

—

QSPI chip select

O:I/O

24

GPI

V23

AA26

Y25

DSPICS3

DSPICS2

PDSPI5

PDSPI4

PDSPI3

TOUT3

TOUT2

—

QSPI chip select

O:I/O

24

GPI

DSPICS0/SS

PSC3RTS

PSC3FSY

NC

I²C

C24

C25

SDA

SCL

PFECI2C1

PFECI2C0

—

I²C Serial data

I²C Serial clock

I/O

8

GPI

PSCs

AA25

AC21

PSC0TXD

PSC0RXD

PPSCL0

PPSCL1

—

PSC0 transmit data O:I/O

PSC0 receive data I:I/O

8

GPI

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

18

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

SignalDescription

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

PBGA Pin

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

AE23

AB26

PSC0CTS

PSC0RTS

PPSCL2

PPSCL3

PSC0BCLK

—

PSC0 clear to send

I:I/O

I/O

8

GPI

PSC0FSYNC

PSC0 request to

send

AB25

AE22

AF25

Y23

PSC1TXD

PSC1RXD

PSC1CTS

PSC1RTS

PPSCL4

PPSCL5

PPSCL6

PPSCL7

—

PSC1 transmit data O:I/O

8

GPI

—

PSC1 receive data

PSC1 clear to send

I:I/O

I/O

PSC1BCLK

PSC1FSYNC

PSC1 request to

send

AC26

AD21

AC19

AD26

PSC2TXD

PSC2RXD

PSC2CTS

PSC2RTS

PPSCH0

PPSCH1

PPSCH2

PPSCH3

—

PSC2 transmit data O:I/O

8

GPI

—

PSC2 receive data

PSC2 clear to send

I:I/O

I/O

PSC2BCLK

PSC2FSYNC

PSC2 request to

send

AE26

AE21

AF23

AB23

PSC3TXD

PSC3RXD

PSC3CTS

PSC3RTS

PPSCH4

PPSCH5

PPSCH6

PPSCH7

—

PSC3 transmit data O:I/O

8

GPI

—

PSC3 receive data

PSC3 clear to send

I:I/O

I/O

PSC3BCLK

PSC3FSYNC

PSC3 request to

send

DMA Controller

AF19

AF20

DREQ1

DREQ0

PDMA1

PDMA0

TIN1

TIN0

IRQ1

DMA request

I:I/O

8

GPI

—

AC25, AB24

DACK[1:0]

PDMA[3:2]

TOUT[1:0]

DMA acknowledge

O:I/O

Timer Module

AD19

AD23

AF21

AC22

AE20

AC23

AF22

AF26

TIN3

TOUT3

TIN2

PTIM7

PTIM6

PTIM5

PTIM4

—

IRQ3

—

Timer input

Timer output

Timer input

Timer output

Timer input

Timer output

Timer input

Timer output

I:I/O

O:I/O

I:I/O

8

GPI

IRQ2

—

TOUT2

TIN1

O:I/O

I:I/O

—

TOUT1

TIN0

—

O:I/O

I:I/O

—

TOUT0

—

O:I/O

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

19

Signal Description

PBGA Pin

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

Debug and JTAG Test Port Control

D20

PSTCLK

—

Processor clock

output

O

8

High

A23, B21, D18, PSTDDATA[7

C20, A22, B20,

A21, B19

Processor status

debug data

:0]

DSCLK

BKPT

DSI

C15

B15

A15

D17

A16

—

TRST

TMS

TDI

—

Debug clock / TAP

reset

I

—

8

—

Breakpoint/TAP test

mode select

Debug data in / TAP

data in

I

—

DSO

TCK

TDO

—

Debug data out /

TAP data out

O

I

High

—

TAP clock

—

Test, Reset, and Clock

B17, C14, A18, MTMOD[3:0]

B16

—

Test mode pins

I

—

B13

A20

A17

D15

RSTI

RSTO

CLKIN

NC

—

Reset input

Reset output

Clock input

No Connect

I

—

8

—

Low

—

I/O

I

—

Power Supplies

C16, C22, E24,

H24K M24, R3,

U24, Y3, AA24,

AB3, AC13, AC16,

AD7,AD10,AD16,

AD18, AD15,

EVDD

—

Positive I/O supply

I

—

AE18

C18, D11, D12,

D19, D22, H4,

H23, L23, P4,

R23, V4, AA23,

AC12, AC20

IVDD

—

Positive core supply

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

20

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

SignalDescription

Table 3. MCF547x Signal Description (continued)

Pin Functions

Reset

State

PBGA Pin

Description

I/O

Drive

Primary

GPIO

Secondary

Tertiary

A2, B2, C3, C17,

C19, C21, D6, D9,

D13, D23, E23,

F4, J4, L4, L11,

L12, L13, L14,

L15, L16, L24,

M11, M12, M13,

M14, M15, M16,

M23, N11, N12,

N13, N14, N15,

N16, P11, P12,

P13, P14, P15,

P16, R4, R11,

R12, R13, R14,

R15, R16, T11,

T12, T13, T14,

T15, T16, T23, U4,

U23, Y4, AB4,

AC7,AC10,AC18,

AD12, AE15,

VSS

—

Ground

AD17, AD20,

AE16, AE17

A1, B1, C1, C6,

C9, C13, D3, F3,

L3, P3

SDVDD

—

Positive SDRAM

supply

A19

PLLVDD

PLLVSS

Positive PLL analog

supply

B18

—

PLL ground

AC13³

USB_OSCVD

D

USB oscillator

supply

AC16³

AD14³

AD15³

AE17³

USB_PHYVD

D

—

USB PHY supply

USB_OSCAV

DD

USB oscillator

analog supply

USB_PLLVD

D

USB PLL supply

USBVDD

USB supply

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

21

Signal Description

Table 4 lists the MCF547x signals in pin number order for the 388 MAPBGA package.

Table 4. MCF5475/MCF5474 Signal Description by Pin Number

Pin Functions

GPIO Secondary

Pin Functions

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

GPIO

Secondary

Tertiary

A1

A2

SDVDD

VSS

—

P1

P2

SDCS1

SDCS2

EVDD

IVDD

—

A3

SDDM2

—

P3

—

A4

SDDATA23

SDDATA24

SDDATA27

SDDQS3

SDDATA29

SDADDR0

SDADDR3

SDADDR7

SDADDR11

SDADDR12

IRQ5

—

P4

—

A5

—

P11

P12

P13

P14

P15

P16

P23

P24

P25

P26

R1

VSS

—

A6

—

VSS

—

A7

—

VSS

—

A8

—

VSS

—

A9

—

VSS

—

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26¹

B1

—

VSS

—

PCIAD19

PCIAD20

PCIAD18

PCIAD21

FBCS5

SDCS3

EVDD

VSS

—

FBADDR19

—

FBADDR20

—

FBADDR18

PIRQ5

—

FBADDR21

DSI

—

TDI

—

PFBCS5

—

TCK

—

R2

—

CLKIN

—

R3

—

MTMOD1

PLLVDD

RSTO

—

R4

—

R11

R12

R13

R14

R15

R16

R23

R24

R25

R26

T1

VSS

—

VSS

—

PSTDDATA1

PSTDDATA3

PSTDDATA7

PCIBR0

—

VSS

—

VSS

—

VSS

—

PPCIBR0

PPCIBR2

PFEC1L5

—

TIN0

TIN2

—

VSS

—

PCIBR2

IVDD

—

E1RXD1

SDVDD

PCIAD24

PCIAD23

PCIAD22

FBCS2

—

FBADDR24

FBADDR23

FBADDR22

—

B2

VSS

—

B3

SDDATA18

—

PFBCS2

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

22

MCF547x Integrated Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

SignalDescription

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

GPIO

Secondary

Tertiary

B4

B5

SDDATA20

SDDQS2

SDDATA21

SDDATA25

SDDM3

—

T2

T3

FBCS4

FBCS3

AD1

PFBCS4

—

PFBCS3

—

B6

T4

—

B7

—

T11

T12

T13

T14

T15

T16

T23

T24

T25

T26

U1

VSS

—

B8

—

VSS

—

B9

SDDATA30

SDADDR1

SDADDR5

SDADDR9

RSTI

—

VSS

—

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22¹

B23

B24

B25¹

B26¹

C1

—

VSS

—

VSS

—

VSS

—

VSS

—

IRQ6

PIRQ6

—

PCIAD27

PCIAD26

PCIAD25

FBCS0

FBCS1

AD0

—

FBADDR27

BKPT

TMS

—

FBADDR26

MTMOD0

MTMOD3

PLLVSS

—

FBADDR25

—

U2

PFBCS1

—

PSTDDATA0

PSTDDATA2

PSTDDATA6

—

U3

—

U4

VSS

—

U23

U24

U25

U26

V1

VSS

—

E1RXCLK PFEC1H3

—

EVDD

PCIAD29

PCIAD28

AD3

—

PCIBR1

PCIBR3

E1RXDV

E1RXD2

SDVDD

CAS

PPCIBR1

TIN1

TIN3

—

FBADDR29

FBADDR28

—

PPCIBR3

—

PFEC1H2

—

PFEC1L2

—

V2

AD2

—

V3

AD4

—

C2

—

V4

EVDD

DSPICS3

PCIBG1

PCIAD31

PCIAD30

AD6

—

C3

VSS

—

V23

V24

V25

V26

W1

PDSPI5

PPCIBG1

—

TOUT3

TOUT1

FBADDR31

FBADDR30

—

C4

SDDATA17

SDDATA19

SDVDD

SDDATA22

—

C5

—

C6

—

C7

—

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

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MCF547x Integrated Microprocessor Hardware Specifications

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Signal Description

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

GPIO Secondary

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

Tertiary

C8

C9

SDDATA26

SDVDD

—

W2

W3

AD5

AD7

—

C10

C11

SDDATA31

SDADDR4

W4

AD13

W23

DSPICS5/PC PDSPI6

SS

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

SDADDR8

SDVDD

MTMOD2

DSCLK

EVDD

—

TRST

—

W24

W25

W26

Y1

PCIBG4

PCIBG2

PCIBG0

AD9

PPCIBG4

TBST

TOUT2

TOUT0

—

PPCIBG2

—

PPCIBG0

—

Y2

AD8

—

VSS

—

Y3

EVDD

—

IVDD

—

Y4

VSS

—

VSS

—

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA23

AA24

AA25

AA26

AB1

AB2

AB3

AB4

AB23

AB24

PSC1RTS

DSPISOUT

DSPICS0/SS

PCIBG3

AD10

PPSCL7 PSC1FSYNC

PSTDDATA4

VSS

—

PDSPI0

PSC3TXD

—

PDSPI3

—

TOUT3

—

EVDD

—

PPCIBG3

PCIIDSEL

SDA

—

PFECI2C1

AD11

—

SCL

PFECI2C0

AD14

—

PCITRDY

SDDATA14

VREF

—

AD19

—

IVDD

—

D2

EVDD

—

D3

SDVDD

SDDATA16

SDDATA28

VSS

PCS0TXD

DSPICS2

AD12

PPSCL0

PDSPI4

—

D4

TOUT2

—

D5

D6

AD15

—

D7

SDADDR2

SDADDR6

VSS

EVDD

—

D8

VSS

—

D9

PSC3RTS

DACK0

PPSCH7 PSC3FSYNC

PDMA2 TOUT0

D10

SDADDR10

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

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SignalDescription

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

GPIO

Secondary

Tertiary

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25¹

IVDD

—

AB25

AB26

AC1

PSC1TXD

PSC0RTS

AD17

PPSCL4

—

PPSCL3 PSC0FSYNC

VSS

—

IRQ7

PIRQ7

—

AC2

AD20

—

NC

—

AC3

AD22

—

VSS

—

AC4

BE/BWE1

E1CRS

E0TXD2

VSS

PFBCTL5

PFEC1H0

PFEC0L6

—

FBADDR1

DSO

—

TDO

—

AC5¹

AC6

—

PSTDDATA5

IVDD

—

AC7

PSTCLK

PCIBR4

IVDD

—

PPCIBR4

—

AC8¹

AC9

E1TXD3

E0COL

VSS

PFEC1L7

PFEC0H4

—

IRQ4

—

AC10

AC11¹

AC12

AC13³

VSS

—

E1TXD2

IVDD

PFEC1L6

—

PCIIRDY

E1RXD3¹

—

PFEC1L3

—

USB_OSCVD

D

—

D26

E1

PCIPERR

SDDATA12

SDDATA15

—

AC14

AC15

AC16³

E0RXER

NC

PFEC0L0

—

E2

USB_PHYVD

D

E3

E4

RAS

SDCKE

VSS

—

AC17²

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

USBVBUS

VSS

—

E23

E24

E25

E26

F1

PSC2CTS

IVDD

PPSCH2

—

PSC2BCLK

EVDD

—

PCISTOP

PCICXBE3

SDDATA10

SDDQS1

SDVDD

VSS

PSC0RXD

TOUT2

PPSCL1

PTIM4

—

TOUT1

F2

DSPISIN

DACK1

PSC2TXD

AD16

PDSPI1

PDMA3

PPSCH0

—

PSC3RXD

TOUT1

—

F3

F4

F23

PCIPAR

—

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

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Signal Description

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

GPIO Secondary

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

Tertiary

F24

F25

F26

G1

PCISERR

PCIFRM

—

AD2

AD3

AD21

AD23

—

PCICXBE3

SDDATA6

SDDATA9

SDDM1

—

AD4

AD24

—

AD5

AD26

—

G2

—

AD6

TS

PFBCTL0

—

TBST

—

G3

—

AD7

EVDD

E0TXD3

E0TXD0

EVDD

E0MDC

VSS

G4

SDDATA13

PCIRESET

PCICXBE0

PCICXBE2

PCIAD2

—

AD8

PFEC0L7

PFEC0H5

—

G23

G24

G25

G26

H1

—

AD9

—

AD10

AD11

AD12

AD13

AD14

AD15³

—

PFECI2C2

—

FBADDR2

—

SDDQS0

SDDATA5

SDDATA8

—

E0RXD0

E0RXLK

PFEC0H1

PFEC0H3

—

H2

—

H3

USB_OSCAV

DD

—

H4

H23

H24

H25

H26

J1

IVDD

—

AD16³USB_PLLVDD

—

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24¹

AD25¹

AD26

AE1

VSS

EVDD

—

EVDD

—

PCIAD1

PCIAD4

SDDATA3

SDDM0

SDDATA4

VSS

FBADDR1

E0CRS

VSS

PFEC0H0

—

FBADDR4

—

PSC2RXD

DSPISCK

TOUT3

E1MDC

E1TXEN

PSC2RTS

AD18

PPSCH1

PDSPI2

PTIM6

—

J2

—

PSC3CTS

—

PSC3BCLK

J3

—

J4

—

SCL

—

J23

J24

J25

J26

K1

PCIDEVSEL

PCIAD3

PCIAD5

PCIAD7

SDWE

PFEC1H6

FBADDR3

FBADDR5

FBADDR7

—

PPSCH3 PSC2FSYNC

—

AE2

AD31

AE3

AD28

K2

SDDATA0

—

AE4

AD27

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

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SignalDescription

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

GPIO

Secondary

Tertiary

K3

K4

SDDATA1

SDDATA11

PCIAD0

PCIAD6

PCIAD8

PCIAD9

SDCLK1

SDRDQS

SDVDD

VSS

—

AE5

AE6

R/W

OE

PFBCTL2

PFBCTL3

PFBCTL4

PFEC1L0

PFEC0L4

PFEC0H6

PFEC1L5

PFEC1h5

PFEC1H7

PFEC1H2

—

TBST

—

K23

K24

K25

K26

L1

FBADDR0

AE7

BE/BWE0

E1RXER

E0TXER

E0TXEN

E1TXD1

E1TXD0

E1TXCLK

E0RXDV

EVDD

FBADDR0

FBADDR6

AE8¹

AE9

—

FBADDR8

—

FBADDR9

AE10

AE11¹

AE12¹

AE13¹

AE14

AE15

AE16

AE17

AE18³

AE19

AE20

AE21

AE22

AE23

AE24¹

AE25¹

AE26

AF1

—

L2

—

L3

—

L4

—

L11

L12

L13

L14

L15

L16

L23

L24

L25

L26

M1

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

VSS

—

USBVDD

E0CRS

TIN1

—

VSS

—

PFEC0H0

—

VSS

—

IVDD

—

PSC3RXD

PSC1RXD

PSC0CTS

E1TXER

E1MDIO

PSC3TXD

AD29

PPSCH5

PPSCL5

PPSCL2

PFEC1L4

—

VSS

—

PCIAD10

PCIAD11

SDCLK1

SDBA1

SDBA0

SDDATA2

VSS

FBADDR10

PSC0BCLK

FBADDR11

—

SCL

—

M2

PPSCH4

—

M3

—

M4

AF2

AD25

—

M11

M12

M13

M14

M15

M16

AF3

AD30

—

VSS

AF4

BE/BWE3

BE/BWE2

TA

PFBCTL7

PFBCTL6

PFBCTL1

PFEC0L5

PFEC1H4

TSIZ1

TSIZ0

—

VSS

AF5

VSS

AF6

VSS

AF7

E0TXD1

E1COL

—

VSS

AF8¹

—

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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27

Signal Description

Table 4. MCF5475/MCF5474 Signal Description by Pin Number (continued)

Pin Functions

GPIO Secondary

Pin Functions

GPIO Secondary

MAPBGA

PBGA Pin

Primary

Tertiary

Primary

Tertiary

M23

M24

M25

M26

N1

VSS

EVDD

—

AF9

AF10

AF11

AF12

AF13

AF14²

AF15²

AF16²

AF17²

AF18²

AF19

AF20

AF21

AF22

AF23

AF24¹

AF25

AF26

E0TXCLK

E0MDIO

E0RXD3

E0RXD2

E0RXD1

USBCLKOUT

USBCLKIN

USBD+

PFEC0H7

PFECI2C3

PFEC0L3

PFEC0L2

PFEC0L1

—

PCIAD12

PCIAD13

SDCLK0

SDCS0

SDDATA7

VSS

FBADDR12

—

FBADDR13

—

N2

—

N3

—

N4

—

N11

N12

N13

N14

N15

N16

N23

N24

N25

N26

—

USBD-

—

VSS

—

USBRBIAS

DREQ1

—

VSS

PDMA1

PDMA0

PTIM5

—

TIN1

IRQ1

—

VSS

—

DREQ0

TIN0

VSS

—

TIN2

IRQ2

—

VSS

—

TIN0

—

PCIAD16

PCIAD14

PCIAD17

PCIAD15

FBADDR16

FBADDR14

FBADDR17

FBADDR15

PSC3CTS

E1RXD0

PSC1CTS

TOUT0

PPSCH6

PFEC1H1

PPSCL6

—

PSC3BCLK

—

PSC1BCLK

—

¹This pin is a “no connect” on the MCF5473 and MCF5472 devices.

²This pin is a “no connect” on the MCF5471 and MCF5470 devices.

³TBD if the USB power pins are connected when the USB is disabled or not used.

1.5.1 Signal Summary

1.5.1.1 FlexBus Signals

1.5.1.1.1 Address / Data Bus (AD[31:0])

The AD[31:0] bus carries address and data. The full 32-bit address is always driven on the first clock of a

bus cycle (address phase). The number of bytes used for data during the data phase is determined by the port

size associated with the matching chip select.

1.5.1.1.2 Chip Select (FBCS[5:0])

FBCS[5:0] are asserted to indicate which device is being selected. A particular chip select asserts when the

transfer address is within the device’s address space as defined in the base and mask address registers. Each

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SignalDescription

chip select can be programmed for a base address location, masking addresses, port size, burst-capability

indication, wait-state generation, and internal/external termination.

Reset clears all chip select programming; FBCS0 is the only chip select initialized out of reset. FBCS0 is

also unique because it can function at reset as a global chip select that allows boot ROM to be selected at

any defined address space. Port size and termination (internal vs. external) for boot FBCS0 are configured

by the levels on AD[2:0] on the rising edge of RSTI, as described in Section 1.5.1.6, “Reset Configuration

Pins.”

1.5.1.1.3 Transfer Start (TS)

The assertion of TS indicates that the MCF547x has begun a bus transaction and that the address and

attributes are valid. TS is asserted for one bus clock cycle. TS can be used externally as address latch enable

to capture the address phase of the bus transfer.

1.5.1.1.4 Read/Write (R/W)

The MCF547x drives the R/W signal to indicate the direction of the current bus operation. It is driven high

during read bus cycles and driven low during write bus cycles.

1.5.1.1.5 Transfer Burst (TBST)

Transfer burst indicates that a burst transfer is in progress. A burst transfer can be 2 to 16 beats depending

on the size of the transfer and the port size.

1.5.1.1.6 Transfer Size (TSIZ[1:0])

For memory accesses, these signals along with TBST, indicate the data transfer size of the current bus

operation. The FlexBus interface supports byte, word, and longword operand transfers and allows accesses

to 8-, 16-, and 32-bit data ports.

For misaligned transfers, TSIZ[1:0] indicate the size of each transfer. For example, if a longword access

through a 32-bit port device occurs at a misaligned offset of 0x1, a byte is transferred first (TSIZ[1:0] = 01),

a word is next transferred at offset 0x2 (TSIZ[1:0] = 10), then the final byte is transferred at offset 0x4

(TSIZ[1:0] = 01).

For aligned transfers larger than the port size, TSIZ[1:0] behaves as follows:

•

If bursting is used, TSIZ[1:0] is driven to the size of transfer.

If bursting is inhibited, TSIZ[1:0] first shows the size of the entire transfer and then shows the port

size.

Table 5. Data Transfer Size

TSIZ[1:0]

Transfer Size

00

01

10

11

4 bytes (longword)

1 byte

2 bytes (word)

16 bytes (line)

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Signal Description

For burst-inhibited transfers, TSIZ[1:0] changes with each TS assertion to reflect the next transfer size. For

transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer on the

first access and the size of the current port transfer on subsequent transfers. For example, for a longword

write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three transactions.

If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to 2’b00 for the

entire transfer.

1.5.1.1.7 Byte Selects (BE/BWE[3:0])

The four byte enables are multiplexed with the byte-write-enable signals. Each pin can be individually

programmed through the chip select control registers (CSCRs). For each chip select, assertion of byte

enables for reads and byte-write enables for write cycles can be programmed. Alternatively, users can

program byte-write enables to assert on writes and no byte enable assertion for read transfers.

The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data.

BE/BWE[3:0] signals are asserted only to the memory bytes used during a read or write access.

1.5.1.1.8 Output Enable (OE)

The output enable signal is sent to the interfacing memory and/or peripheral to enable a read transfer. OE is

asserted only when a chip select matches the current address decode.

1.5.1.1.9 Transfer Acknowledge (TA)

The external system drives this input to terminate the bus transfer. For write cycles, the processor continues

to drive data at least one clock after FBCSx is negated. During read cycles, the peripheral must continue to

drive data until TA is recognized. The number of wait states is determined either by an internally

programmed auto acknowledgement or the external TA input. If the external TA is used, the peripheral has

total control over the number of wait states.

1.5.1.2 SDRAM Controller Signals

These signals are used for SDRAM accesses.

1.5.1.2.1 SDRAM Data Bus (SDDATA[31:0])

SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled

by the MCF547x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge

of SDCLK when in DDR mode.

1.5.1.2.2 SDRAM Address Bus (SDADDR[12:0])

The SDADDR[12:0] signals are the 13-bit address bus used for multiplexed row and column addresses

during SDRAM bus cycles. The address multiplexing supports up to 256 Mbits of SDRAM per chip select.

1.5.1.2.3 SDRAM Bank Addresses (SDBA[1:0])

Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.

It is also used to select the SDRAM internal mode register during power-up initialization.

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MCF547x Integrated Microprocessor Hardware Specifications

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SignalDescription

1.5.1.2.4 SDRAM Row Address Strobe (RAS)

This output is the SDRAM synchronous row address strobe.

1.5.1.2.5 SDRAM Column Address Strobe (CAS)

This output is the SDRAM synchronous column address strobe.

1.5.1.2.6 SDRAM Chip Selects (SDCS[3:0])

These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one

SDCS line for each memory block (the MCF547x supports up to four SDRAM memory blocks).

1.5.1.2.7 SDRAM Write Data Byte Mask (SDDM[3:0])

These output signals are sampled by the SDRAM on both edges of SDDQS to determine which byte lanes

of the SDRAM data bus should be latched during a write cycle. In DDR mode, these bits are ignored during

read operations.

1.5.1.2.8 SDRAM Data Strobe (SDDQS[3:0])

These bidirectional signals indicate when valid data is on the SDRAM data bus when in DDR mode.

1.5.1.2.9 SDRAM Clock (SDCLK[1:0])

These signals are the output clock for SDRAM cycles.

1.5.1.2.10 Inverted SDRAM Clock (SDCLK[1:0])

These signals are the inverted version of the SDRAM clock. They are used with SDCLK to provide the

differential clocks for DDR SDRAM.

1.5.1.2.11 SDRAM Write Enable (SDWE)

The SDRAM write enable (SDWE) is asserted to signify that an SDRAM write cycle is underway. A read

cycle is indicated by the negation of SDWE.

1.5.1.2.12 SDRAM Clock Enable (SDCKE)

This output is the SDRAM clock enable. SDCKE is negated to put the SDRAM into low-power, self-refresh

mode.

1.5.1.2.13 SDR SDRAM Data Strobe (SDRDQS)

This signal is connected to SDDQS inputs. Used in SDR mode only.

1.5.1.2.14 SDRAM Reference Voltage (VREF)

Output reference voltage for differential SSTL_2 inputs. Used in both DDR and SDR modes.

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Signal Description

1.5.1.3 PCI Controller Signals

1.5.1.3.1 PCI Address/Data Bus (PCIAD[31:0])

The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during

the address phase while the data is presented on the bus during one or more data phases.

If the FlexBus is used in 32-bit address/32-bit data non-multiplexed mode, PCIAD[31:0] are used as a 32-bit

address for FlexBus transfers.

1.5.1.3.2 Command/Byte Enables (PCICXBE[3:0])

The PCICXBE[3:0] lines are time multiplexed. The PCI command is presented during the address phase

and the byte enables are presented during the data phase.

1.5.1.3.3 Device Select (PCIDEVSEL)

The PCIDEVSEL signal is asserted active low when the MCF547x decodes that it is the target of a PCI

transaction from the address presented on the PCI bus during the address phase.

1.5.1.3.4 Frame (PCIFRM)

The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated

when the initiator is ready to complete the final data phase.

1.5.1.3.5 Initialization Device Select (PCIIDSEL)

The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration

header.

1.5.1.3.6 Initiator Ready (PCIIRDY)

The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write

operation, assertion indicates that the master is driving valid data on the bus. During a read operation,

assertion indicates that the master is ready to accept data.

1.5.1.3.7 Parity (PCIPAR)

The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.

1.5.1.3.8 Parity Error (PCIPERR)

The PCIPERR signal is asserted when a data phase parity error is detected if enabled.

1.5.1.3.9 Reset (PCIRESET)

The PCIRESET signal is asserted active low by MCF547x to reset the PCI bus. This signal is asserted after

the MCF547x is reset and must be negated to enable usage of the PCI bus.

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SignalDescription

1.5.1.3.10 System Error (PCISERR)

The PCISERR signal, if enabled, is asserted when an address phase parity error is detected.

1.5.1.3.11 Stop (PCISTOP)

The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the current

transaction.

1.5.1.3.12 Target Ready (PCITRDY)

The PCITRDY signal is asserted by the currently addressed target to indicate that it is ready to complete the

current data phase.

1.5.1.3.13 External Bus Grant (PCIBG[4:1])

The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI arbiter

is enabled, it asserts one of the PCIBG[4:1] lines to grant ownership of the PCI bus to an external master.

When the PCI arbiter module is disabled, PCIBG[4:1] are driven high and should be ignored.

1.5.1.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)

The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI

arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the MCF547x

needs to initiate a PCI transaction.

1.5.1.3.15 External Bus Request (PCIBR[4:0])

The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.

1.5.1.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)

The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus. When

the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus, PCIGNTIN.

It is driven by an external PCI arbiter.

1.5.1.4 Interrupt Control Signals

The interrupt control signals supply the external interrupt level to the MCF547x device.

1.5.1.4.1 Interrupt Request (IRQ[7:1])

The IRQ[7:1] signals are the external interrupt inputs.

1.5.1.5 Clock and Reset Signals

The clock and reset signals configure the MCF547x and provide interface signals to the external system.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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Signal Description

1.5.1.5.1 Reset In (RSTI)

Asserting RSTI causes the MCF547x to enter reset exception processing. RSTO is asserted automatically

when RSTI is asserted.

1.5.1.5.2 Reset Out (RSTO)

After RSTI is asserted, the PLL temporarily loses its lock, during which time RSTO is asserted. When the

PLL regains its lock, RSTO negates again. This signal can be used to reset external devices.

1.5.1.5.3 Clock In (CLKIN)

CLKIN is the MCF547x input clock frequency to the on-board phase-locked loop (PLL) clock generator.

CLKIN is used to internally clock or sequence the MCF547x internal bus interface at a selected multiple of

the input frequency used for internal module logic. CLKIN is used as the clock reference for PCI and

FlexBus transfers.

1.5.1.6 Reset Configuration Pins

This section describes address/data pins, AD[12:0], that are read at reset to configure the MCF547x.

1.5.1.6.1 AD[12:8] / CLKIN to SDCLK Ratio (CLKCONFIG[4:0])

The clock configuration inputs, CLKCONFIG[4:0], indicate the CLKIN to SDCLK ratio. CLKIN is used

as the external reference for both PCI and FlexBus cycles. The CLKIN to SDCLK ratio is selectable, where

SDCLK is the clock frequency used for SDRAM accesses and the internal XLB bus. The core is always

clocked at twice the SDCLK frequency.

These signals are sampled on the rising edge of RSTI. Table 6 shows how the logic levels of AD[12:8]

correspond to the selected clock ratio.

Table 6. MCF547X Divide Ratio Encodings

CLKIN—PCI and FlexBus Internal XLB and SDRAM

Core Frequency Range

FB_AD[12:8]¹Clock Ratio

Frequency Range

(MHz)

Bus Frequency Range

(MHz)

00011

00101

01111

1:2

1:4

41.6–66.66

30.0–44.4

30.0–33.3

83.33–133.33

60.0–88.8

166.66–266.66

120.0–177.66

210–266.66

120–133.33

1

All other values of FB_AD[12:8] are reserved.

1.5.1.6.2 AD5—FlexBus Size Configuration (FBSIZE)

At reset, the enabling and disabling of BE/BWE[3:0] versus TSIZ[1:0] and ADDR[1:0] is determined by

the logic level driven on AD5 at the rising edge of RSTI. FBSIZE is multiplexed with AD5 and sampled

only at reset. Table 7 shows how the AD5 logic level corresponds to the BE/BWE[3:0] function.

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SignalDescription

Table 7. AD5/FBSIZE Selection of BE/BWE[3:0] Signals

AD5

FlexBus Byte Enable Mode

0

BE/BWE[3:0] used as byte/byte write

enables.

1

BE/BWE[3:2] configured as TSIZ[1:0].

BE/BWE[1:0] configured as FBADDR[1:0].

1.5.1.6.3 AD4—32-bit FlexBus Configuration (FBMODE)

During reset, the FlexBus can be configured to operate in a non-multiplexed 32-bit address with 32-bit data

mode. In this mode, the 32-bit FlexBus AD[31:0] is used for the data bus, and the PCI bus PCIAD[31:0] is

used as the address bus. The FlexBus operating mode is determined by the logic level driven on AD4 at the

rising edge of RSTI. Table 8 shows how the logic level of AD4 corresponds to the FlexBus mode.

Table 8. AD4/FBMODE Selection of Non-Multiplexed 32-bit Address/32-bit Data Mode

AD4

FlexBus Operating Mode

0

PCIAD[31:0] used for PCI bus.

AD[31:0] used for both address and data.

1

AD[31:0] used for data.

PCIAD[31:0] used for address ¹

1

If the non-multiplexed 32-bit address/32-bit data mode is selected the PCI bus

cannot be used.

1.5.1.6.4 AD3—Byte Enable Configuration (BECONFIG)

The default byte enable mode of the boot FBCS0 is determined by the logic level driven on AD3 at the rising

edge of RSTI. This logic level is reflected as the reset value of CSCR0[BEM]. Table 9 shows how the logic

level of AD3 corresponds to the byte enable mode for FBCS0 at reset.

Table 9. AD3/BECONFIG, BE/BWE[3:0] Boot Configuration

AD3

Boot FBCS0 Byte Strobe Configuration

0

1

BE[3:0] can assert for both read and write cycles.

BWE[3:0] are not asserted for reads;

BWE[3:0] only assert for write cycles

1.5.1.6.5 AD2—Auto Acknowledge Configuration (AACONFIG)

At reset, the enabling and disabling of auto acknowledge for boot FBCS0 is determined by the logic level

driven on AD2 at the rising edge of RSTI. AACONFIG is multiplexed with AD2 and sampled only at reset.

The AD2 logic level is reflected as the reset value of CSCR0[AA]. Table 10 shows how the AD2 logic level

corresponds to the auto acknowledge timing for FBCS0 at reset. Note that auto acknowledge can be disabled

by driving a logic 0 on AD2 at reset.

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Signal Description

Table 10. AD2/AA_CONFIG Selection of FBCS0 Automatic Acknowledge

AD2

Boot FBCS0 AA Configuration at Reset

Disabled

Enabled with 63 wait states

0

1

1.5.1.6.6 AD[1:0]—Port Size Configuration (PSCONFIG)

The default port size value of the boot FBCS0 is determined by the logic levels driven on AD[1:0] at the

rising edge of RSTI, which are reflected as the reset value of CSCR0[PS]. Table 11 shows how the logic

levels of AD[1:0] correspond to the FBCS0 port size at reset.

Table 11. AD[1:0]/PSCONFIG[1:0] Selection of FBCS0 Port Size

AD[1:0]

Boot FBCS0 Port Size

00

01

1X

32-bit port

8-bit port

16-bit port

1.5.1.7 Ethernet Module Signals

The following signals are used by the Ethernet module for data and clock signals.

1.5.1.7.1 Management Data (E0MDIO, E1MDIO)

The bidirectional EMDIO signals transfer control information between the external PHY and the

media-access controller. Data is synchronous to EMDC and applies to MII mode operation. This signal is

an input after reset. When the FEC operates in 10 Mbps 7-wire interface mode, this signal should be

connected to VSS.

1.5.1.7.2 Management Data Clock (E0MDC, E1MDC)

EMDC is an output clock which provides a timing reference to the PHY for data transfers on the EMDIO

signal and applies to MII mode operation.

1.5.1.7.3 Transmit Clock (E0TXCLK, E1TXCLK)

This is an input clock which provides a timing reference for ETXEN, ETXD[3:0] and ETXER.

1.5.1.7.4 Transmit Enable (E0TXEN, E1TXEN)

The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is

asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final

nibble of the frame.

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SignalDescription

1.5.1.7.5 Transmit Data 0 (E0TXD0, E1TXD0)

ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is

used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1].

1.5.1.7.6 Collision (E0COL, E1COL)

The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists.

This signal is not defined for full-duplex mode.

1.5.1.7.7 Receive Clock (E0RXCLK, E1RXCLK)

The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER.

1.5.1.7.8 Receive Data Valid (E0RXDV, E1RXDV)

Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the MII.

ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble.

Assertion of ERXDV must start no later than the SFD and exclude any EOF.

1.5.1.7.9 Receive Data 0 (E0RXD0, E1RXD0)

ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ERXDV

is asserted. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode Ethernet

data in conjunction with ERXD[3:1].

1.5.1.7.10 Carrier Receive Sense (E0CRS, E1CRS)

ECRS is an input signal which when asserted signals that transmit or receive medium is not idle, and applies

to MII mode operation.

1.5.1.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1])

These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII

mode.

1.5.1.7.12 Transmit Error (E0TXER, E1TXER)

When the ETXER output is asserted for one or more clock cycles while ETXEN is also asserted, the PHY

sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated, and applies

to MII mode operation.

1.5.1.7.13 Receive Data 1–3 (E0RXD[3:1], E1RXD[3:1])

These pins contain the Ethernet input data transferred from the PHY to the media-access controller when

ERXDV is asserted in MII mode operation.

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Signal Description

1.5.1.7.14 Receive Error (E0RXER, E1RXER)

ERXER is an input signal which when asserted along with ERXDV signals that the PHY has detected an

error in the current frame. When ERXDV is not asserted ERXER has no effect, and applies to MII mode

operation.

1.5.1.8 Universal Serial Bus (USB)

1.5.1.8.1 USB Differential Data (USBD+, USBD–)

USBD+ and USBD– are the outputs of the on-chip USB 2.0 transceiver. They provide differential data for

the USB 2.0 bus.

1.5.1.8.2 USBVBUS

USB cable Vbus monitor input.

1.5.1.8.3 USBRBIAS

Connection for external current setting resistor. Should be connected to a 1.9kΩ +/– 1% pull down resistor.

1.5.1.8.4 USBCLKIN

Input pin for 12 MHz USB crystal circuit.

1.5.1.8.5 USBCLKOUT

Output pin for 12 MHz USB crystal circuit.

1.5.1.9 DMA Serial Peripheral Interface (DSPI) Signals

1.5.1.9.1 DSPI Synchronous Serial Output (DSPISOUT)

The DSPISOUT output provides the serial data from the DSPI and can be programmed to be driven on the

rising or falling edge of DSPISCK.

1.5.1.9.2 DSPI Synchronous Serial Data Input (DSPISIN)

The DSPISIN input provides the serial data to the DSPI and can be programmed to be sampled on the rising

or falling edge of DSPISCK.

1.5.1.9.3 DSPI Serial Clock (DSPISCK)

DSPISCK is a serial communication clock signal. In master mode, the DSPI generates the DSPISCK. In

slave mode, DSPISCK is an input from an external bus master.

1.5.1.9.4 DSPI Peripheral Chip Select/Slave Select (DSPICS0/SS)

In master mode, the DSPICS0 signal is a peripheral chip select output that selects which slave device the

current transmission is intended for.

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SignalDescription

In slave mode, the SS signal is a slave select input signal that allows an SPI master to select the DSPI as the

target for transmission.

1.5.1.9.5 DSPI Chip Selects (DSPICS[2:3])

The synchronous peripheral chip selects (DSPICS[2:3]) outputs provide DSPI peripheral chip selects that

can be programmed to be active high or low.

1.5.1.9.6 DSPI Peripheral Chip Select 5/Peripheral Chip Select Strobe

(DSPICS5/PCSS)

DSPICS5 is a peripheral chip select output signal. When the DSPI is in master mode and the

DMCR[PCSSE] bit is cleared, this signal is used to select which slave device the current transfer is intended

for.

PCSS provides a strobe signal that can be used with an external demultiplexer for deglitching of the

DSPICSn signals. When the DSPI is in master mode and DMCR[PCSSE] is set, the PCSS provides the

appropriate timing for the decoding of the DSPICS[0,2,3] signals which prevents glitches from occurring.

This signal is not used in slave mode.

2

1.5.1.10 I C I/O SIGNALS

2

The I C serial interface module uses the signals in this section.

1.5.1.10.1 Serial Clock (SCL)

2

This bidirectional open-drain signal is the clock signal for the I C interface. It is either driven by the I C

module when the bus is in master mode or it becomes the clock input when the I C is in slave mode.

2

1.5.1.10.2 Serial Data (SDA)

2

This bidirectional open-drain signal is the data input/output for the I C interface.

1.5.1.11 PSC Module Signals

The PSC modules use the signals in this section. The baud rate clock inputs are not supported.

1.5.1.11.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD,

PSC3TXD)

PSCnTXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark

condition) when the transmitter is disabled, idle, or in the local loopback mode. The PSCxTXD pins can be

programmed to be driven low (break status) by a command.

1.5.1.11.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD,

PSC3RXD)

PSCnRXD are the receiver serial data inputs for the PSC modules. When the PSC clock is stopped for

power-down mode, any transition on the pins restarts them.

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Signal Description

1.5.1.11.3 Clear-to-Send (PSCnCTS/PSCBCLK)

These signals either operate as the clear to send input signals in UART mode or the bit clock input signals

in modem modes and IrDA modes. In MIR and FIR mode, the frequency is a multiple of the input bit clock

frequency, and the bit clock frequency should be within +/-0.1% and +/-0.01% of the ideal one, respectively.

1.5.1.11.4 Request to Send (PSCnRTS/PSCFSYNC)

The PSCnRTS signals act as transmitter request to send (RTS) outputs in UART mode, the frame sync input

in modem8 and modem16 modes or the RTS output (which acts as frame sync) in AC97 modem mode.

1.5.1.12 DMA Controller Module Signals

The DMA controller module uses the signals in the following subsections to provide external requests for

either a source or destination.

1.5.1.12.1 DMA Request (DREQ[1:0])

These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and

memory by either channel 0 or 1 of the on-chip DMA module.

1.5.1.12.2 DMA Acknowledge (DACK[1:0])

These outputs are asserted to acknowledge that a DMA request has been recognized.

1.5.1.13 Timer Module Signals

The signals in the following sections are external interfaces to the four general-purpose MCF547x timers.

These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count external

events.

1.5.1.13.1 Timer Inputs (TIN[3:0])

TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause

captures on the rising edge, falling edge, or both edges.

1.5.1.13.2 Timer Outputs (TOUT[3:0])

The programmable timer outputs, TOUTn, pulse or toggle on various timer events.

1.5.1.14 Debug Support Signals

The MCF547x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed with

background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If MTMOD0

is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0 should be

changed only while RSTI is asserted.

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SignalDescription

1.5.1.14.1 Processor Clock Output (PSTCLK)

The internal PLL generates this output signal, and is the processor clock output that is used as the timing

reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the core

processor and cache memory. The frequency is 2x the internal system clock.

1.5.1.14.2 Processor Status Debug Data (PSTDDATA[7:0])

Processor status data outputs indicate both processor status and captured address and data values. They

operate at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as

a sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may

appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.

1.5.1.14.3 Development Serial Clock/Test Reset (DSCLK/TRST)

If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to

the debug module. The maximum DSCLK frequency is 1/5 CLKIN.

If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the test

logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this occurs,

JTAG logic is benign and does not interfere with normal MCF547x functionality.

Although TRST is asynchronous, Motorola recommends that it makes an asserted-to-negated transition

only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a

logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EV . Tying TRST

DD

to ground places the JTAG controller in test logic reset state immediately. Tying it to EV causes the JTAG

DD

controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.

1.5.1.14.4 Breakpoint/Test Mode Select (BKPT/TMS)

If MTMOD0 is low, BKPT is selected. BKPT signals a hardware breakpoint to the processor in debug mode.

If MTMOD0 is high, TMS is selected. The TMS input provides information to determine the JTAG test

operation mode. The state of TMS and the internal 16-state JTAG controller state machine at the rising edge

of TCK determine whether the JTAG controller holds its current state or advances to the next state. This

directly controls whether JTAG data or instruction operations occur. TMS has an internal pull-up resistor so

that if it is not driven low, it defaults to a logic level of 1. But if TMS is not used, it should be tied to V

.

DD

1.5.1.14.5 Development Serial Input/Test Data Input (DSI/TDI)

If MTMOD0 is low, DSI is selected. DSI provides the single-bit communication for debug module

commands.

If MTMOD0 is high, TDI is selected. TDI provides the serial data port for loading the various JTAG

boundary scan, bypass, and instruction registers. Shifting in data depends on the state of the JTAG controller

state machine and the instruction in the instruction register. Shifts occur on the TCK rising edge. TDI has

an internal pull-up resistor, so when not driven low it defaults to high. But if TDI is not used, it should be

tied to EVDD.

1.5.1.14.6 Development Serial Output/Test Data Output (DSO/TDO)

If MTMOD0 is low, DSO is selected. DSO provides single-bit communication for debug module responses.

MOTOROLA

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Signal Description

If MTMOD0 is high, TDO is selected. The TDO output provides the serial data port for outputting data from

JTAG logic. Shifting out data depends on the JTAG controller state machine and the instruction in the

instruction register. Data shifting occurs on the falling edge of TCK. When TDO is not outputting test data,

it is three-stated. TDO can be three-stated to allow bused or parallel connections to other devices having a

JTAG port.

1.5.1.14.7 Test Clock (TCK)

TCK is the dedicated JTAG test logic clock independent of the MCF547x processor clock. Various JTAG

operations occur on the rising or falling edge of TCK. Holding TCK high or low for an indefinite period

does not cause JTAG test logic to lose state information. If TCK is not used, it must be tied to ground.

1.5.1.15 Test Signals

1.5.1.15.1 Test Mode (MTMOD[3:0])

The test mode signals choose between multiplexed debug module and JTAG signals. If MTMOD0 is low,

the part is in normal and background debug mode (BDM); if it is high, it is in normal and JTAG mode. All

other MTMOD values are reserved; MTMOD[3:1] should be tied to ground and MTMOD[3:0] should not

be changed while RSTI is negated

1.5.1.16 Power and Reference Pins

These pins provide system power, ground, and references to the device. Multiple pins are provided for

adequate current capability. All power supply pins must have adequate bypass capacitance for

high-frequency noise suppression.

1.5.1.16.1 Positive Pad Supply (EVDD)

This pin supplies positive power to the I/O pads.

1.5.1.16.2 Positive Core Supply (IVDD)

This pin supplies positive power to the core logic.

1.5.1.16.3 Ground (VSS)

This pin is the negative supply (ground) to the chip.

1.5.1.16.4 USB Power (USBVDD)

This pin supplies positive power to the USB module’s digital logic.

1.5.1.16.5 USB Oscillator Power (USB_OSCVDD)

This pin supplies positive power to the USB oscillator’s digital logic.

1.5.1.16.6 USB PHY Power (USB_PHYVDD)

This pin supplies positive power to the USB PHY’s digital logic.

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ChipConfiguration

1.5.1.16.7 USB Oscillator Analog Power (USB_OSCAVDD)

This pin supplies positive power to the USB oscillator’s analog circuits.

1.5.1.16.8 USB PLL Analog Power (USB_PLLVDD)

This pin supplies positive power to the USB PLL’s circuits.

1.5.1.16.9 SDRAM Memory Supply (SDVDD)

This pin supplies positive power to the SDRAM module.

1.5.1.16.10PLL Analog Power (PLLVDD)

This pin supplies the positive power for the PLL.

1.5.1.16.11PLL Analog Ground (PLLVSS)

This pin is the negative supply (ground) to the PLL.

1.6 Chip Configuration

1.6.1 Device Operating Options

•

FBCS0 boot chip select port size:

— 32-bit

— 16-bit

— 8-bit

•

FBCS0 boot chip select termination:

— External termination

— Internal termination

FlexBus operating mode

— FlexBus uses AD[31:0] as multiplexed address and data bus

— FlexBus uses AD[31:0] as non-multiplexed data bus and PCIAD[31:0] as non-multiplexed

address bus

•

Byte enable mode

— BE[3:0] can assert during reads and writes

— BWE[3:0] can only assert during writes

Clock mode:

— 1:1 SDCLK to CLKIN ratio

— 2:1 SDCLK to CLKIN ratio

— 4:1 SDCLK to CLKIN ratio

MOTOROLA

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Chip Configuration

1.6.2 Chip Configuration Pins

Table 12 shows the pins that are sampled at reset time to configure the MCF547x.

Table 12. Configuration Pin Descriptions

Chip Configuration

Pin State/Meaning

See Table 6

Function

AD[12:8]

AD5

PLL Clock

Configuration

Byte Strobe/Size

Configuration

0

1

Byte Strobe outputs driven

Size and Address outputs driven

AD4

FlexBus Operating

Mode

0

1

AD[31:0] used for multiplexed

address and data

AD[31:0] used for data,

PCIAD[31:0] used for address

AD3

Byte Enable

Configuration

0

1

BE[3:0] can assert on both read

and write cycles

BWE[3:0] can only assert on write

cycles

AD2

FBCS0 Boot Chip

Select Auto

Acknowledge

Configuration

0

1

Auto acknowledge disabled

Auto acknowledge enabled with 63

wait states

AD[1:0]

FBCS0 Boot Chip

Select Port Size

Configuration

00 32-bit port

01 8-bit port

1X 16-bit port

MTMOD0 ¹

BDM/JTAG Select

0

1

BDM mode

JTAG mode

1

The MTMOD0 pin should not be changed during normal operation.

1.6.3 Chip Configuration Circuit

Figure 2 shows a block diagram of the recommended circuit used to drive the reset configuration values for

the MCF547x.The signals are sampled at the rising clock edge immediately before RSTI negates, so the

signals must be stable and valid at this time.

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DesignRecommendations

MCF547X

74VCX16244

AD0

Inputs

driven

high or

low as

needed

AD1

AD2

AD3

AD4

AD5

AD8

AD9

AD10

AD11

AD12

OE

RSTI

Reset

Logic

EVDD/VSS

MTMOD0

Figure 2. MCF547x Recommended Reset Configuration Circuit

1.7 Design Recommendations

1.7.1 Layout

•

Use a 6-layer printed circuit board with the EVDD, IVDD, and VSS pins connected directly to the

power and ground planes for the MCF547x.

See application note AN1259 System Design and Layout Techniques for Noise Reduction in

MCU-Based Systems.

Match the PC layout trace width and routing to match trace length to operating frequency and

board impedance. Add termination (series or therein) to the critical clock traces to dampen

reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and

short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise

‘noisy.’ Use 6 mils trace and separation. Clocks get extra separation and more precise balancing,

plus termination.

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Design Recommendations

1.7.2 Power Supply/Analog Filtering

Figure 3 shows the recommended filter circuit for the MCF547x PLL power supply.

10 Ω

Vdd

PLL power pin

10 µF

0.1 µF

Figure 3. PLL Power Supply Filter Circuit

1.7.3 Decoupling

Place the decoupling caps on the power supply pins for the MCF547x as close to the pins as possible:

•

0.1µF and 1nF across each 3.3V supply input.

0.1µF and 1nF across each 2.5V supply input.

100pF and 1nF across each 1.5V supply input.

1.7.4 Buffering

•

Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses

when excessive loading is expected. See Section Appendix A, “Preliminary Electrical

Characteristics.”

1.7.5 Pull-up Recommendations

•

Use external pull-up resistors on unused inputs.

1.7.6 Clocking Recommendations

The following are general clocking recommendations for the MCF547x:

•

Use a multi-layer board with a separate ground plane.

Place the oscillator and all other associated components as close to the CLKIN pin as possible.

Keep the CLKIN signal isolated from other high frequency signals.

Ensure that the ground for the bypass capacitors is connected to a solid ground trace/plane.

Tie the ground trace to the ground pin nearest the oscillator. This prevents large loop currents in

the vicinity of the oscillator.

•

Tie the ground pin to the most solid ground in the system.

Do not connect the trace that connects the oscillator and the ground plane to any other circuit

element. This tends to make the oscillator unstable.

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1.7.7 Interface Recommendations

1.7.7.1 SDRAM Controller

The SDRAM controller has a glueless interface to both SDR and DDR memories. Since different voltages

are required for the two memory technologies, the module supports either DDR or SDR but not both.

Supported memory clock rate will be up to 133MHz. At this memory clock rate, DDR memory can receive

data at an effective rate of 266 MHz.

•

Support for up to 13 lines of row address, up to 12 lines of column address, 2 lines of bank address,

and up to 4 chip selects. Two memory chip selects are multiplexed with two chip selects for the

local bus.

•

Memory bus width fixed at 32 bits.

1.7.7.1.1 SDRAM Controller Address Configurations

The SDRAM controller supports up to 13 row addresses and up to 12 column addresses. However, the

maximum row and column addresses are not supported at the same time. The number of row and column

addresses must be less than 24. In addition to row/column address lines, there are always two row bank

address bits. Therefore, the greatest possible address space which can be accessed using a single chip select

26

is (2 ) x 32 bit, or 256 Mbytes.

Table 13 shows the address multiplexing used by the MCF547x for different configurations. When the

SDRAM controller receives the internal module enable, it latches the internal bus address lines A[27:2] and

multiplexes them into row, column and row bank addresses. A[9:2] are always used for CA[7:0], A[11:10]

are always used for BA[1:0], and A[23:12] are always used for RA[11:0]. A[27:24] can be used for

additional row or column address bits, as needed.

Table 13. SDRAM Address Multiplexing

Row bit x

Col bit x

Banks

Internal Address

Device

Configuration

27

26

25

24

23–12

11–10

9–2

64 Mbits

4M x 16 bit

8M x 8bits

12 x 8 x 4

12 x 9 x 4

13 x 8 x 4

12 x 10 x 4

13 x 9 x 4

12 x 9 x 4

13 x 8 x 4

12 x 10 x 4

13 x 9 x 4

12 x 11 x 4

13 x 10 x 4

—

RA11-0 BA1-0

RA11–0 BA1–0

CA7–0

CA8

—

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

16M x 4 bit

8M x 16 bit

16M x 8 bit

32M x 4 bit

—

CA9

CA8

—

128 Mbits

—

CA9

CA8

CA9

CA8

—

CA11

CA9

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Design Recommendations

Table 13. SDRAM Address Multiplexing (continued)

Row bit x

Col bit x

Banks

Internal Address

Device

Configuration

27

26

25

24

23–12

11–10

9–2

256 Mbits

16M x 16 bit

12 x 10 x 4

13 x 9 x 4

—

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

CA9

CA8

RA11–0 BA1–0

CA7–0

—

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

CA8 RA11–0 BA1–0

RA12 RA11–0 BA1–0

32M x 8 bit

64M x 4 bit

32M x 16 bit

64M x 8bit

12 x 11 x 4

13 x 10 x 4

12 x 12 x 4

13 x 11 x 4

12 x 11 x 4

13 x 10x 4

12 x 12 x 4

13 x 11 x 4

—

CA11

CA9

CA11

CA9

CA11

CA9

CA11

CA9

—

CA12

CA11

—

512 Mbits

—

CA12

CA11

1.7.7.1.2 SDRAM SDR Connections

Figure 4 shows a block diagram of the connections between the MCF547x and SDR SDRAM components.

SDR design requires special timing consideration for the SD_DQS[3:0] signals. For reads from DDR

SDRAMs, the memory will drive the DQS pins so that the data lines and DQS signals have concurrent

edges. The MCF547x SDRAMC is designed to latch data 1/4 clock after the SD_DQS[3:0] edge. For DDR

SDRAM, this ensures that the latch time is in the middle of the data valid window.

The MCF547x also uses the SDDQS[3:0] signals to determine when read data can be latched for SDR

SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides an

SDRDQS output that is routed back into the controller as SDDQS[3:0]. The SDRDQS signal should be

routed such that the valid data from the SDRAM reaches the MCF547x at the same time or just before the

SDRDQS reaches the SDDQS[3:0] inputs. The appropriate delay for SDRDQS can be generated using a

buffer or driver, as shown in Figure 4. Using a buffer or driver will also ensure that the SDRDQS signal can

drive all four of the MCF547x’s SDDQS[3:0] inputs.

48

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DesignRecommendations

SDR SDRAM

MCF547X

SDADDR[12:0]

A[12:0]

BA[1:0]

SDBA[1:0]

SDDATA[31:0]

DQ[31:0]

CS

SDCSx

RAS

CAS

RAS

CAS

WE

SDWE

SDCLK[1:0]

SDCKE

CLK

CKE

SDDM[3:0]

SDRDQS

DQM[3:0]

SDDQS[3:0]

Figure 4. MCF547x Connections to SDR SDRAM

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MCF547x Integrated Microprocessor Hardware Specifications

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Design Recommendations

1.7.7.1.3 SDRAM DDR Component Connections

Figure 5 shows a block diagram of the connections between the MCF547x and DDR SDRAM components.

MCF547X

DDR SDRAM

SDADDR[12:0]

A[12:0]

BA[1:0]

SDBA[1:0]

SDDATA[31:0]

DQ[31:0]

CS

SDCSx

RAS

CAS

RAS

CAS

WE

SDWE

SDCLK[1:0]

SDCKE

CLK

CKE

SDDM[3:0]

DM[3:0]

SDDQS[3:0]

DQS[3:0]

Figure 5. MCF547x Connections to DDR SDRAM

1.7.7.1.4 SDRAM DDR DIMM Connections

There is a JEDEC standard for a 100-pin DDR DIMM with a 32-bit wide data bus. This DIMM standard

was designed specifically to support 32-bit processors. The MCF547x can support current DIMM

configurations up to 512 Mbytes.

Figure 6 shows a block diagram of the connections between the MCF547x and DDR SDRAM Dims.

50

MCF547x Integrated Microprocessor Hardware Specifications

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DesignRecommendations

DDR SDRAM

MCF547X

SDADDR[12:0]

A[12:0]

BA[1:0]

SDBA[1:0]

SDDATA[31:0]

SDCS[1:0]

DQ[31:0]

S[1:0]

RAS

CAS

RAS

CAS

WE

SDWE

SDCLK[1:0]

SDCKE

CLK[1:0]

CKE

SDDM[3:0]

DM[3:0]

SDDQS[3:0]

DQS[3:0]

SCL

SDA

SCL

SDA

SDVDD

SA0

Figure 6. MCF547x Connections to 100-pin DDR SDRAM DIMM

1.7.7.1.5 DDR SDRAM Layout Considerations

Due to the critical timing for DDR SDRAM there are a number of considerations that should be taken into

account during PCB layout:

•

Minimize overall trace lengths.

Each DQS, DM, and DQ group must have identical loading and similar routing to maintain timing

integrity.

•

Control and clock signals are routed point-to-point.

Trace length for clock, address, and command signals should match.

Route DDR signals on layers adjacent to the ground plane

Use a VREF plane under the SDRAM.

VREF is decoupled from both SDVDD and VSS.

To avoid crosstalk keep address and command signals separate from data and data strobes.

Use different resistor packs for command/address and data/data strobes.

Use single series, single parallel termination (25 Ω series, 50 Ω parallel values are recommended,

but standard resistor packs with similar values can be substituted.)

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Design Recommendations

•

Series termination should be between MCF547x and memory, but closest to the processor.

The parallel termination at end of the signal line.

0.1 µF decoupling for every termination resistor pack.

1.7.7.1.6 Termination Example

Figure 7 shows the recommended termination circuitry for DDR SDRAM signals.

V

REF

50 Ω

DDR SDRAM

MCF547X

25 Ω

Figure 7. MCF547x DDR SDRAM Termination Circuit

1.7.7.2 Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps

Ethernet. The interface mode is selected by RCR[MII_MODE]. In MII mode, the 802.3 standard defines

and the FEC module supports 18 signals. Table 14 shows the signals used in MII mode.

Table 14. MII Mode

Signal Description

Transmit clock

MCF547x Pin

ETXCLK

Transmit enable

Transmit data

ETXEN

ETXD[3:0]

ETXER

ECOL

Transmit error

Collision

Carrier sense

ECRS

Receive clock

ERXCLK

ERXDV

ERXD[3:0]

ERXER

EMDC

Receive enable

Receive data

Receive error

Management channel clock

Management channel serial data

EMDIO

The serial mode interface operates in what is generally referred to as AMD mode. The MCF547x

configuration for seven-wire serial mode connections to the external transceiver are shown in Table 15.

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DesignRecommendations

Table 15. Seven-Wire Mode Configuration

Signal Description

Transmit clock

MCF547x Pin

ETXCLK

ETXEN

ETXD[0]

ECOL

Transmit enable

Transmit data

Collision

Receive clock

ERXCLK

ERXDV

ERXD[0]

ERXER

ECRS

Receive enable

Receive data

Unused, configure as PB14

Unused input, tie to ground

Unused, configure as PB[13:11]

Unused output, ignore

Unused, configure as PB[10:8]

Unused, configure as PB15

Input after reset, connect to ground

ERXD[3:1]

ETXER

ETXD[3:1]

EMDC

EMDIO

Refer to the M5282EVB evaluation board user’s manual for an example of how to connect an external PHY.

Schematics for this board are accessible at the MCF5282 site by navigating from:

http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx,

MCF5282, and M5282EVB links.

1.7.7.3 BDM

Use the BDM interface as shown in the M5407C3 evaluation board user’s manual. The schematics for this

board are accessible at the MCF5407 site by navigating from: http://e-www.motorola.com/ following the

32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5407 and M5407C3 links.

The ColdFire BDM connector, Figure 8, is a 26-pin Berg connector arranged 2 × 13.

NOTE

Some BDM cables tie pin 9 and pin 25 together, even though the official

specification lists the two pins at different voltages. A jumper can be added

to make the voltage on pin 25 selectable between IVDD and EVDD. This

allows the voltage to be changed for compatability with older BDM cables.

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MCF5475/5474 Pinout

Developer Reserved ¹

1

2

4

BKPT

GND

3

DSCLK

Developer Reserved¹

5

6

RESET

+3.3V²

7

8

DSI

9

10

12

14

16

18

20

22

24

26

DSO

11

13

15

17

19

21

23

25

PSTDDATA7

PSTDDATA5

PSTDDATA3

PSTDDATA1

GND

PSTDDATA6

PSTDDATA4

PSTDDATA2

PSTDDATA0

Motorola Reserved

GND

Motorola reserved

PSTCLK

TA

IVDD

¹Pins reserved for BDM developer use

²Supplied by target

Figure 8. Recommended BDM Connector

1.8 MCF5475/5474 Pinout

Figure 9–Figure 12 show the pinout for the each quadrant of the MCF5475/MCF5474 388

MAPBGA package. Figure 9 shows the pinout for the upper left quadrant.

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF5475/5474Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDVDD

VSS

SDDM2 SDDATA SDDATA SDDATA SDDQS SDDATA SDADD SDADD SDADD SDADD SDADD

A

B

C

D

E

F

23

24

27

3

29

R0

R3

R7

R11

R12

SDVDD

VSS

CAS

SDDDA SDDATA SDDQS SDDATA SDDATA SDDM3 SDDATA SDADD SDADD SDADD

TA18 20 21 25 30 R1 R5 R9

RSTI

2

VSS SDDATA SDDATA SDVDD SDDATA SDDATA SDVDD SDDATA SDADD SDADD SDVDD

17

19

22

26

31

R4

R8

SDDATA VREF SDVDD SDDATA SDDATA VSS

SDADD SDADD

R2 R6

VSS

SDADD IVDD

R10

IVDD

VSS

14

16

28

SDDATA SDDATA RAS

SDCKE

12

15

SDDDA SDDQS SDVDD

TA10

VSS

1

SDDATA SDDATA SDDM1 SDDATA

G

H

J

6

9

13

SDDQS SDDATA SDDATA IVDD

0

5

8

SDDATA SDDM0 SDDATA VSS

3

4

SDWE SDDATA SDDATA SDDATA

K

L

0

1

11

SDCLK1 SDRDQ SDVDD

S

VSS

SDCLK1 SDBA1 SDBA0 SDDATA

2

M

N

SDCLK0 SDCLK0 SDCS0 SDDATA

7

Figure 9. MCF5475/5474 Upper Left Quadrant Pinout (388 MAPBGA)

Figure 10 shows the pinout for the upper right quadrant of the MCF5475/MCF5474 pinout for the

388 MAPBGA package.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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55

MCF5475/5474 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

IRQ5

DSI/TDI

TCK

CLKIN MTMOD PLLVDD RSTO PSTDD PSTDD PSTDD PCIBR0 PCIBR2 E1RXD1

ATA1 ATA3 ATA7

A

B

C

D

E

F

1

IRQ6

BKPT/T MTMOD MTMOD PLLVSS PSTDD PSTDD PSTDD E1RXCL PCIBR1 PCIBR3 E1RXDV E1RXD2

MS

0

3

ATA0

ATA2

ATA6

K

MTMOD DSCLK/ EVDD

VSS

IVDD

VSS

PSTDD

ATA4

VSS

EVDD PCIIDSE SDA

L

SCL

PCITRD

Y

2

TRST

NC

IRQ7

VSS

DSO/TD PSTDD

ATA5

IVDD PSTCLK PCIBR4 IVDD

VSS

PCIIRD E1RXD3 PCIPER

O

Y

R

EVDD PCISTO PCICXB

E1

P

PCIPAR PCISER PCIFRM PCICXB

E3

R

PCIRES PCICXB PCICXB PCIAD2

G

H

J

ET

E0

E2

IVDD

EVDD PCIAD1 PCIAD4

PCIDEV PCIAD3 PCIAD5 PCIAD7

SEL

PCIAD0 PCIAD6 PCIAD8 PCIAD9

K

L

VSS

IVDD

VSS

PCIAD1 PCIAD1

0

1

EVDD PCIAD1 PCIAD1

M

N

2

3

PCIAD1 PCIAD1 PCIAD1 PCIAD1

6

4

7

5

Figure 10. MCF5475/5474 Upper Right Quadrant Pinout (388 MAPBGA)

Figure 11 shows the pinout for the lower left quadrant of the MCF5475/MCF5474 pinout for the

388 MAPBGA package.

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF5475/5474Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDCS1 SDCS2 SDVDD IVDD

VSS

P

R

FBCS5 SDCS3 EVDD

FBCS2 FBCS4 FBCS3

VSS

AD1

VSS

T

FBCS0 FBCS1

AD0

AD4

VSS

IVDD

AD13

VSS

AD19

VSS

U

AD3

AD6

AD2

AD5

V

AD7

W

AD9

AD8

EVDD

AD14

EVDD

Y

AD10

AD12

AD17

AD16

AD18

AD29

AD11

AD15

AD20

AD21

AD31

AD25

AA

AB

AC

AD

AE

AF

AD22 BE/BW E1CRS E0TXD2 VSS E1TXD3 E0COL

E1

VSS E1TXD2 IVDD USB_OS

CVDD

AD23

AD28

AD24

AD27

AD26

R/W

TS

OE

TA

EVDD E0TXD3 E0TXD0 EVDD E0MDC

VSS

E0RXD0

BE/BW E1RXE E0TXE E0TXE E1TXD1 E1TXD0 E1TXCLK

E0

R

N

AD30 BE/BW BE/BW

E3 E2

E0TXD1 E1COL E0TXCL E0MDIO E0RXD E0RXD E0RXD1

K

3

2

Figure 11. MCF5475/5474 Lower Left Quadrant Pinout (388 MAPBGA)

Figure 12 shows the pinout for the lower left quadrant of the MCF5475/MCF5474 pinout for the

388 MAPBGA package.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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57

MCF5473/5472 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

VSS

PCIAD1 PCIAD2 PCIAD1 PCIAD2

P

R

9

0

8

1

VSS

IVDD PCIAD2 PCIAD2 PCIAD2

4

3

2

VSS PCIAD2 PCIAD2 PCIAD2

T

7

6

5

VSS

EVDD PCIAD2 PCIAD2

U

9

8

DSPICS PCIBG1 PCIAD3 PCIAD3

V

3

1

0

DSPICS PCIBG4 PCIBG2 PCIBG0

5/PCSS

W

PSC1R DSPISO DSPICS PCIBG3

Y

TS

UT

0/SS

IVDD

EVDD PSC0T DSPICS

XD

AA

AB

AC

AD

AE

AF

2

PSC3R DACK0 PSC1T PSC0R

TS XD TS

E0RXE

R

NC

USB_P USBVB

VSS

PSC2C IVDD PSC0R TOUT2 TOUT1 DSPISI DACK1 PSC2T

HYVDD

US

TS

XD

N

XD

E0RXC USB_O USB_P

LK

VSS

EVDD

TIN3

VSS

PSC2R DSPISC TOUT3 E1MDC E1TXE PSC2R

XD TS

SCAVD LLVDD

D

K

N

E0RXD

V

VSS

USBVD E0CRS TIN1 PSC3R PSC1R PSC0C E1TXE E1MDI PSC3T

XD XD TS XD

D

R

O

USBCL USBCL USBD+ USBD- USBRBI DREQ1 DREQ0 TIN2

KOUT KIN AS

TIN0 PSC3C E1RXD PSC1C TOUT0

TS TS

0

Figure 12. MCF5475/5474 Lower Right Quadrant Pinout (388 MAPBGA)

1.9 MCF5473/5472 Pinout

Figure 13–Figure 16 show the pinout for the each quadrant of the MCF5473/MCF5472 388

MAPBGA package. Figure 13 shows the pinout for the upper left quadrant.

58

MCF547x Integrated Microprocessor Hardware Specifications

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MOTOROLA

MCF5473/5472Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDVDD

VSS

SDDM2 SDDATA SDDATA SDDATA SDDQS SDDATA SDADD SDADD SDADD SDADD SDADD

A

B

C

D

E

F

23

24

27

3

29

R0

R3

R7

R11

R12

SDVDD

VSS

CAS

SDDDA SDDATA SDDQS SDDATA SDDATA SDDM3 SDDATA SDADD SDADD SDADD

TA18 20 21 25 30 R1 R5 R9

RSTI

2

VSS SDDATA SDDATA SDVDD SDDATA SDDATA SDVDD SDDATA SDADD SDADD SDVDD

17

19

22

26

31

R4

R8

SDDATA VREF SDVDD SDDATA SDDATA VSS

SDADD SDADD

R2 R6

VSS

SDADD IVDD

R10

IVDD

VSS

14

16

28

SDDATA SDDATA RAS

SDCKE

12

15

SDDDA SDDQS SDVDD

TA10

VSS

1

SDDATA SDDATA SDDM1 SDDATA

G

H

J

6

9

13

SDDQS SDDATA SDDATA IVDD

0

5

8

SDDATA SDDM0 SDDATA VSS

3

4

SDWE SDDATA SDDATA SDDATA

K

L

0

1

11

SDCLK1 SDRDQ SDVDD

S

VSS

SDCLK1 SDBA1 SDBA0 SDDATA

2

M

N

SDCLK0 SDCLK0 SDCS0 SDDATA

7

Figure 13. MCF5473/5472 Upper Left Quadrant Pinout (388 MAPBGA)

Figure 14 shows the pinout for the upper right quadrant of the MCF5473/MCF5472 pinout for the

388 MAPBGA package.

MOTOROLA

MCF547x Integrated Microprocessor Hardware Specifications

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59

MCF5473/5472 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

IRQ5

DSI/TDI

TCK

CLKIN MTMOD PLLVDD RSTO PSTDD PSTDD PSTDD PCIBR0 PCIBR2

NC

A

B

C

D

E

F

1

ATA1

ATA3

ATA7

IRQ6

BKPT/T MTMOD MTMOD PLLVSS PSTDD PSTDD PSTDD

MS

NC

PCIBR1 PCIBR3

NC

SCL

NC

0

3

ATA0

VSS

ATA2

ATA6

VSS

MTMOD DSCLK/ EVDD

VSS

IVDD

PSTDD

ATA4

EVDD PCIIDSE SDA

L

PCITRD

Y

2

TRST

NC

IRQ7

VSS

DSO/TD PSTDD

ATA5

IVDD PSTCLK PCIBR4 IVDD

VSS

PCIIRD

Y

PCIPER

R

O

EVDD PCISTO PCICXB

E1

P

PCIPAR PCISER PCIFRM PCICXB

E3

R

PCIRES PCICXB PCICXB PCIAD2

G

H

J

ET

E0

E2

IVDD

EVDD PCIAD1 PCIAD4

PCIDEV PCIAD3 PCIAD5 PCIAD7

SEL

PCIAD0 PCIAD6 PCIAD8 PCIAD9

K

L

VSS

IVDD

VSS

PCIAD1 PCIAD1

0

1

EVDD PCIAD1 PCIAD1

M

N

2

3

PCIAD1 PCIAD1 PCIAD1 PCIAD1

6

4

7

5

Figure 14. MCF5473/5472 Upper Right Quadrant Pinout (388 MAPBGA)

Figure 15 shows the pinout for the lower left quadrant of the MCF5473/MCF5472 pinout for the

388 MAPBGA package.

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MCF547x Integrated Microprocessor Hardware Specifications

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MCF5473/5472Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDCS1 SDCS2 SDVDD IVDD

VSS

P

R

FBCS5 SDCS3 EVDD

FBCS2 FBCS4 FBCS3

VSS

AD1

VSS

T

FBCS0 FBCS1

AD0

AD4

VSS

IVDD

AD13

VSS

AD19

VSS

U

AD3

AD6

AD2

AD5

V

AD7

W

AD9

AD8

EVDD

AD14

EVDD

Y

AD10

AD12

AD17

AD16

AD18

AD29

AD11

AD15

AD20

AD21

AD31

AD25

AA

AB

AC

AD

AE

AF

AD22 BE/BW

E1

NC

AD26

R/W

E0TXD2 VSS

NC

E0COL

VSS

NC

IVDD USB_OS

CVDD

AD23

AD28

AD24

AD27

TS

OE

TA

EVDD E0TXD3 E0TXD0 EVDD E0MDC

VSS

NC

E0RXD0

NC

BE/BW

E0

NC

E0TXE E0TXE

NC

R

N

AD30 BE/BW BE/BW

E3 E2

E0TXD1

E0TXCL E0MDIO E0RXD E0RXD E0RXD1

K

3

2

Figure 15. MCF5473/5472 Lower Left Quadrant Pinout (388 MAPBGA)

Figure 16 shows the pinout for the lower left quadrant of the MCF5473/MCF5472 pinout for the

388 MAPBGA package.

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61

MCF5471/5470 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

VSS

PCIAD1 PCIAD2 PCIAD1 PCIAD2

P

R

9

0

8

1

VSS

IVDD PCIAD2 PCIAD2 PCIAD2

4

3

2

VSS PCIAD2 PCIAD2 PCIAD2

T

7

6

5

VSS

EVDD PCIAD2 PCIAD2

U

9

8

DSPICS PCIBG1 PCIAD3 PCIAD3

V

3

1

0

DSPICS PCIBG4 PCIBG2 PCIBG0

5/PCSS

W

PSC1R DSPISO DSPICS PCIBG3

Y

TS

UT

0/SS

IVDD

EVDD PSC0T DSPICS

XD

AA

AB

AC

AD

AE

AF

2

PSC3R DACK0 PSC1T PSC0R

TS XD TS

E0RXE

R

NC

USB_P USBVB

VSS

PSC2C IVDD PSC0R TOUT2 TOUT1 DSPISI DACK1 PSC2T

HYVDD

US

TS

XD

N

XD

E0RXC USB_O USB_P

LK

VSS

EVDD

TIN3

VSS

PSC2R DSPISC TOUT3

NC

PSC2R

TS

SCAVD LLVDD

D

XD

K

E0RXD

V

VSS

USBVD E0CRS TIN1 PSC3R PSC1R PSC0C

XD XD TS

NC

PSC3T

XD

D

USBCL USBCL USBD+ USBD- USBRBI DREQ1 DREQ0 TIN2

KOUT KIN AS

TIN0 PSC3C

TS

PSC1C TOUT0

TS

Figure 16. MCF5473/5472 Lower Right Quadrant Pinout (388 MAPBGA)

1.10 MCF5471/5470 Pinout

Figure 17–Figure 20 show the pinout for the each quadrant of the MCF5471/MCF5470 388

MAPBGA package. Figure 17 shows the pinout for the upper left quadrant.

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MCF5471/5470Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDVDD

VSS

SDDM2 SDDATA SDDATA SDDATA SDDQS SDDATA SDADD SDADD SDADD SDADD SDADD

A

B

C

D

E

F

23

24

27

3

29

R0

R3

R7

R11

R12

SDVDD

VSS

CAS

SDDDA SDDATA SDDQS SDDATA SDDATA SDDM3 SDDATA SDADD SDADD SDADD

TA18 20 21 25 30 R1 R5 R9

RSTI

2

VSS SDDATA SDDATA SDVDD SDDATA SDDATA SDVDD SDDATA SDADD SDADD SDVDD

17

19

22

26

31

R4

R8

SDDATA VREF SDVDD SDDATA SDDATA VSS

SDADD SDADD

R2 R6

VSS

SDADD IVDD

R10

IVDD

VSS

14

16

28

SDDATA SDDATA RAS

SDCKE

12

15

SDDDA SDDQS SDVDD

TA10

VSS

1

SDDATA SDDATA SDDM1 SDDATA

G

H

J

6

9

13

SDDQS SDDATA SDDATA IVDD

0

5

8

SDDATA SDDM0 SDDATA VSS

3

4

SDWE SDDATA SDDATA SDDATA

K

L

0

1

11

SDCLK1 SDRDQ SDVDD

S

VSS

SDCLK1 SDBA1 SDBA0 SDDATA

2

M

N

SDCLK0 SDCLK0 SDCS0 SDDATA

7

Figure 17. MCF5471/5470 Upper Left Quadrant Pinout (388 MAPBGA)

Figure 18 shows the pinout for the upper right quadrant of the MCF5471/MCF5470 pinout for the

388 MAPBGA package.

MOTOROLA

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63

MCF5471/5470 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

IRQ5

DSI/TDI

TCK

CLKIN MTMOD PLLVDD RSTO PSTDD PSTDD PSTDD PCIBR0 PCIBR2 E1RXD1

ATA1 ATA3 ATA7

A

B

C

D

E

F

1

IRQ6

BKPT/T MTMOD MTMOD PLLVSS PSTDD PSTDD PSTDD E1RXCL PCIBR1 PCIBR3 E1RXDV E1RXD2

MS

0

3

ATA0

ATA2

ATA6

K

MTMOD DSCLK/ EVDD

VSS

IVDD

VSS

PSTDD

ATA4

VSS

EVDD PCIIDSE SDA

L

SCL

PCITRD

Y

2

TRST

NC

IRQ7

VSS

DSO/TD PSTDD

ATA5

IVDD PSTCLK PCIBR4 IVDD

VSS

PCIIRD E1RXD3 PCIPER

O

Y

R

EVDD PCISTO PCICXB

E1

P

PCIPAR PCISER PCIFRM PCICXB

E3

R

PCIRES PCICXB PCICXB PCIAD2

G

H

J

ET

E0

E2

IVDD

EVDD PCIAD1 PCIAD4

PCIDEV PCIAD3 PCIAD5 PCIAD7

SEL

PCIAD0 PCIAD6 PCIAD8 PCIAD9

K

L

VSS

IVDD

VSS

PCIAD1 PCIAD1

0

1

EVDD PCIAD1 PCIAD1

M

N

2

3

PCIAD1 PCIAD1 PCIAD1 PCIAD1

6

4

7

5

Figure 18. MCF5471/5470 Upper Right Quadrant Pinout (388 MAPBGA)

Figure 19 shows the pinout for the lower left quadrant of the MCF5471/MCF5470 pinout for the

388 MAPBGA package.

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MCF5471/5470Pinout

1

2

3

4

5

6

7

8

9

10

11

12

13

SDCS1 SDCS2 SDVDD IVDD

VSS

P

R

FBCS5 SDCS3 EVDD

FBCS2 FBCS4 FBCS3

VSS

AD1

VSS

T

FBCS0 FBCS1

AD0

AD4

VSS

IVDD

AD13

VSS

AD19

VSS

U

AD3

AD6

AD2

AD5

V

AD7

W

AD9

AD8

EVDD

AD14

EVDD

Y

AD10

AD12

AD17

AD16

AD18

AD29

AD11

AD15

AD20

AD21

AD31

AD25

AA

AB

AC

AD

AE

AF

AD22 BE/BW E1CRS E0TXD2 VSS E1TXD3 E0COL

E1

VSS E1TXD2 IVDD USB_OS

CVDD ¹

AD23

AD28

AD24

AD27

AD26

R/W

TS

OE

TA

EVDD E0TXD3 E0TXD0 EVDD E0MDC

VSS

E0RXD0

BE/BW E1RXE E0TXE E0TXE E1TXD1 E1TXD0 E1TXCLK

E0

R

N

AD30 BE/BW BE/BW

E3 E2

E0TXD1 E1COL E0TXCL E0MDIO E0RXD E0RXD E0RXD1

K

3

2

1

TBD if the USB power pins are connected when the USB is disabled or not used.

Figure 19. MCF5471/5470 Lower Left Quadrant Pinout (388 MAPBGA)

Figure 20 shows the pinout for the lower left quadrant of the MCF5471/MCF5470 pinout for the

388 MAPBGA package.

MOTOROLA

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65

MCF5471/5470 Pinout

14

15

16

17

18

19

20

21

22

23

24

25

26

VSS

PCIAD1 PCIAD2 PCIAD1 PCIAD2

P

R

9

0

8

1

VSS

IVDD PCIAD2 PCIAD2 PCIAD2

4

3

2

VSS PCIAD2 PCIAD2 PCIAD2

T

7

6

5

VSS

EVDD PCIAD2 PCIAD2

U

9

8

DSPICS PCIBG1 PCIAD3 PCIAD3

V

3

1

0

DSPICS PCIBG4 PCIBG2 PCIBG0

5/PCSS

W

PSC1R DSPISO DSPICS PCIBG3

Y

TS

UT

0/SS

IVDD

EVDD PSC0T DSPICS

XD

AA

AB

AC

AD

AE

AF

2

PSC3R DACK0 PSC1T PSC0R

TS XD TS

E0RXE

R

NC

USB_P

NC

VSS

NC

VSS

PSC2C IVDD PSC0R TOUT2 TOUT1 DSPISI DACK1 PSC2T

HYVDD

TS

XD

N

XD

1

E0RXC USB_O USB_P

LK

EVDD

TIN3

VSS

PSC2R DSPISC TOUT3 E1MDC E1TXE PSC2R

XD TS

SCAVD LLVDD¹

D¹

K

N

E0RXD

V

VSS

USBVD E0CRS TIN1 PSC3R PSC1R PSC0C E1TXE E1MDI PSC3T

D¹

XD

TS

R

O

XD

NC

DREQ1 DREQ0 TIN2

TIN0 PSC3C E1RXD PSC1C TOUT0

TS

0

TS

1

TBD if the USB power pins are connected when the USB is disabled or not used.

Figure 20. MCF5475/5474 Lower Right Quadrant Pinout (388 MAPBGA)

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Mechanicals

1.11 Mechanicals

Figure 21. 388-pin PBGA Package Outline

MOTOROLA

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67

Ordering Information

1.12 Ordering Information

Table 16. Orderable Part Numbers

Motorola Part

Number

Description Package

Speed

Temperature

MCF5475VF266

MCF5474VF266

MCF5473VF200

MCF5472VF200

MCF5471VF200

MCF5470VF200

MCF5475 RISC Microprocessor 388 PBGA

MCF5474 RISC Microprocessor 388 PBGA

MCF5473 RISC Microprocessor 388 PBGA

MCF5472 RISC Microprocessor 388 PBGA

MCF5471 RISC Microprocessor 388 PBGA

MCF5470 RISC Microprocessor 388 PBGA

266MHz

200MHz

⁰° to +70° C

0° to +70° C

⁰° to +70° C

1.13 Device/Family Documentation List

Table 17. MCF547X Documentation

Motorola

Document

Number

Title

Revision

Status

MCF5475EC/D

MCF547x Integrated Microprocessor Hardware

Specifications

1.0

This Document

V4ECFUM/D

MCF5475UM/D

MCF5475PB/D

CFPRODFACT/D

ColdFire CF4e Core User’s Manual

MCF547X Advance Information Manual

MCF547X Product Brief

0

Available

In Process

Available

The ColdFire Family of 32-Bit Microprocessors Family

Overview and Technology Roadmap

MCF5XXXWP

CFPRM/D

MCF5XXXWP WHITE PAPER: Motorola ColdFire VL

RISC Processors

0

2

Available

ColdFire Family Programmer's Reference Manual

1.14 Document Revision History

Table 18 provides a revision history for the MCF547x hardware specification.

Table 18. Document Revision History

Rev. No.

Substantive Change(s)

0.1

1.0

1.1

Initial release.

Updated pinout information and signal names.

Updated VREFsignal description.

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Appendix A

Preliminary Electrical Characteristics

This section contains electrical specification tables and reference timing diagrams for the MCF547X

microprocessor. This section contains detailed information on power considerations, DC/AC electrical

characteristics, and AC timing specifications of MCF547X.

The electrical specifications are preliminary and are from previous designs or design simulations. These

specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized

specifications will be published after complete characterization and device qualifications have been

completed.

NOTE

The parameters specified in this MPU document supersede any values

found in the module specifications.

A.1 Maximum Ratings

Table 19 lists maximum and minimum ratings for supply and operating voltages and storage temperature.

Operating outside of these ranges may cause erratic behavior or damage to the processor.

Table 19. Absolute Maximum Ratings

Rating

Symbol

Value

Units

External (I/O pads) supply voltage (3.3-V power pins)

Internal logic supply voltage

EV_DD

IV_DD

-0.3 to +4.0

-0.5 to +2.0

V

Memory (I/O pads) supply voltage (2.5-V power pins)

SD V_DD

-0.3 to +4.0 SDR Memory

-0.3 to +2.8 DDR Memory

PLL supply voltage

PLL V_DD

V_in

-0.5 to +2.0

-0.5 to +3.6

-55 to +150

V

Internal logic supply voltage, input voltage level

Storage temperature range

T_stg

^oC

A.2 Thermal Characteristics

A.2.1 Operating Temperatures

Table 20 lists junction and ambient operating temperatures.

Table 20. Operating Temperatures

Characteristic

Symbol

Value

Units

Maximum operating junction temperature

Maximum operating ambient temperature

T_j

105

<70 ¹

0

^oC

T_Amax

T_Amin

Minimum operating ambient temperature

1

This published maximum operating ambient temperature should be used only as a system design guideline. All

device operating parameters are guaranteed only when the junction temperature lies within the specified range.

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A.2.2 Thermal Resistance

Table 21 lists thermal resistance values.

Table 21. Thermal Resistance

Characteristic

Symbol

Value

Unit

388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p)

convection

θ_JMA

20–22^1,2

°C/W

Junction to ambient (@200 ft/min)

Junction to board

Four layer board (2s2p)

θ_JMA

θ_JB

θ_JC

Ψ_jt

23^1,2

15 ¹

10 ²

2^{1, 3}

°C/W

Junction to case

Junction to top of package

Natural convection

1

2

3

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter

is written as Psi-JT.

A.3 DC Electrical Specifications

Table 22 lists DC electrical operating temperatures. This table is based on an operating voltage of

EV = 3.3 V ± 0.3 V and IV of 1.5 ± 0.07 V .

DD

DC

DD

DC

Table 22. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Units

External (I/O pads) operation voltage range

EV_DD

SD V_DD

IV_DD

3.0

2.30

1.43

3.0

3.6

2.70

1.58

3.6

V

Memory (I/O pads) operation voltage range (DDR Memory)

1

Internal logic operation voltage range

PLL Analog operation voltage range ¹

USB oscillator operation voltage range

USB digital logic operation voltage range

USB PHY operation voltage range

PLL V_DD

USB_OSV_DD

USBV_DD

USB_PHYV_DD

USB_OSCAV_DD

USB_PLLV_DD

V_IH

3.0

3.6

3.0

3.6

USB oscillator analog operation voltage range

USB PLL operation voltage range

1.43

2.0

1.58

3.6

Input high voltage SSTL 3.3V (SDR DRAM)

Input low voltage SSTL 3.3V (SDR DRAM)

Input high voltage SSTL 2.5V (DDR DRAM)

Input low voltage SSTL 2.5V (DDR DRAM)

Output high voltage I_OH= 8 mA, 16 mA ,24 mA

V_IL

-0.5

2.0

0.8

V_IH

2.8

V_IL

-0.5

2.4

0.8

V_OH

—

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Table 22. DC Electrical Specifications

Characteristic

Symbol

Min

Max

Units

Output low voltage I_OL= 8 mA , 16 mA ,24 mA⁵

Capacitance ², V_in= 0 V, f = 1 MHz

V_OL

C_IN

—

0.5

V

TBD

pF

1

IV_DDand PLL V_DDshould be at the same voltage. PLL V_DDshould have a filtered input. Please see Figure 22 for an

example circuit. Note: There are three PLL V_DDinputs. A filter circuit should used on each PLL V_DDinput.

Capacitance C_INis periodically sampled rather than 100% tested.

2

A.3.1 PLL Power Filtering

To further enhance noise isolation, an external filter is strongly recommended for PLL analog V

DD

pins. The filter shown in Figure 22 should be connected between the board V and the PLL V

DD

pins. The resistor and capacitors should be placed as close to the dedicated PLL V pin as

DD

possible.

10 Ω

Board V_DD

PLL V_DDPin

10 µF

0.1 µF

GND

Figure 22. System PLL V_DDPower Filter

A.3.2 USB Power Filtering

To minimize noise, a external filters are required for each of the USB power pins. The filter shown in

Figure 23 should be connected between the board EV or IV and each of the USB V pins. The

DD

resistor and capacitors should be placed as close to the dedicated USB V pin as possible. A separate filter

DD

circuit should be included for each USB V pin, a total of five circuits.

DD

R

Board EV_DD/IV_DD

USB V_DDPin

10 µF

0.1 µF

GND

Figure 23. USB V_DDPower Filter

Lists the resistor values and supply voltages to be used in the circuit for each of the USB V pins.

DD

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Table 23. USB Filter Circuit Values

USB V_DDPin

Nominal Voltage

Resistor Value (R)

USB_OSCV_DD

USBV_DD

3.3V

1.5V

0Ω

USB_PHYV_DD

USB_OSCAV_DD

USB_PHYV_DD

0Ω

10Ω

A.4 Supply Voltage Sequencing and Separation

Cautions

Figure 24 shows situations in sequencing the I/O V (EV ), SDRAM V (SD V ), PLL V (PLL

DD

V

), and Core V (IV ).

DD

DD DD

EV_DD, SD V_DD(3.3V)

SD V_DD(2.5V)

3.3V

Supplies Stable

2.5V

1.5V

IV_DD, PLL V_DD

1

2

0

Time

NOTES:

1. IV_DDshould not exceed EV_DD, SD V_DDor PLL V_DDby more than

0.4V at any time, including power-up.

2. Recommended that IV_DD/PLL V_DDshould track EV_DD/SD V_DDup to

0.9V, then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (EV_DD, SD V_DD

,

IV_DD, or PLL V_DD) by more than 0.5V at any time, including during power-up.

4. Use 1 microsecond or slower rise time for all supplies.

Figure 24. Supply Voltage Sequencing and Separation Cautions

The relationship between SD V and EV is non-critical during power-up and power-down sequences.

DD

Both SD V (2.5V or 3.3V) and EV are specified relative to IV .

DD

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A.4.1 Power Up Sequence

If EV /SD V are powered up with the IV at 0V, then the sense circuits in the I/O pads will cause all

DD

pad output drivers connected to the EV /SD V to be in a high impedance state. There is no limit on how

DD

long after EV /SD V powers up before IV must power up. IV should not lead the EV , SD V

DD

or PLL V by more than 0.4V during power ramp up or there will be high current in the internal ESD

DD

protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid

turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 microsecond or slower rise time for all supplies.

2. IV /PLL V and EV /SD V should track up to 0.9V and then separate for the completion

DD

of ramps with EV /SD V going to the higher external voltages. One way to accomplish this is

DD

to use a low drop-out voltage regulator.

A.4.2 Power Down Sequence

If IV PLL V are powered down first, then sense circuits in the I/O pads will cause all output drivers to

DD

be in a high impedance state. There is no limit on how long after IV and PLL V power down before

DD

EV or SD V must power down. IV should not lag EV , SD V , or PLL V going low by more

DD

than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IV /PLL V to 0V.

DD

2. Drop EV /SD V supplies.

DD

A.5 Output Driver Capability and Loading

Table 24 lists values for drive capability and output loading.

Table 24. I/O Driver Capability

Drive

Output

Signal

Capability Load (C_L)

SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0],

SDWE, SDBA[1:0]

24 mA

15 pF

SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0],

SDCLK[1:0], SDCKE)

24 mA

15 pF

SDRAMC chip selects (SDCS[3:0])

24 mA

16 mA

8 mA

15 pF

20 pF

15 pF

50 pF

30 pF

50 pF

FlexBus (AD[31:0], FBCS[5:0], TS, R/W, BE/BWE[3:0], OE)

FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER

Timer (TOUT[3:0])

8 mA

DACK[1:0]

8 mA

PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC,

DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS)

8 mA

24 mA

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Table 24. I/O Driver Capability

Signal

Drive

Output

Capability Load (C_L)

PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL,

PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP,

PCIPAR, PCITRDY, PCIIRDY

16 mA

50 pF

I2C (SCL, SDA)

8 mA

50 pF

25 pF

50 pF

BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO,

RSTO

A.6 PLL Timing Specifications

The specifications in Table 25 are for the CLKIN pin.

Table 25. Clock Timing Specification

Num

Characteristic

Min

Max

Units

C1 Cycle time

15.15

—

33.3

2

ns

%

C2 Rise time (20% of Vdd to 80% of vdd)

C3 Fall time (80% of Vdd to 20% of Vdd)

C4 Duty cycle (at 50% of Vdd)

—

2

40

60

C1

CLKIN

C4

C2

C3

Figure 25. Input Clock Timing Diagram

Table 6 shows the supported PLL encodings.

Table 26. MCF547X Divide Ratio Encodings

CLKIN—PCI and FlexBus Internal XLB and SDRAM

Core Frequency Range

(MHz)

AD[12:8] ¹

Clock Ratio

Frequency Range

(MHz)

Bus Frequency Range

(MHz)

00011

00101

01111

1:2

1:4

41.6–66.66

30.0–44.4

30.0–33.3

83.33–133.33

60.0–88.8

166.66–266.66

120.0–177.66

240–266.66

120–133.33

1

All other values of AD[12:8] are reserved.

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Figure 26 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.

CLKIN

Internal Clock

Core Clock

2x

4x

2x

30.0

66.66

60.0

133.33

120.0

266.66

30.0 33.33

30 50

120.0 133.33

240.0

70

30

50

70

90 110 130

60

80 100 120 140 160 180 200 220 240 260

Core Clock (MHz)

CLKIN (MHz)

Internal Clock (MHz)

Figure 26. CLKIN, Internal Bus, and Core Clock Ratios

A.7 Reset Timing Specifications

Table 27 lists specifications for the reset timing parameters shown in Figure 27

Table 27. Reset Timing Specification

66 MHz CLKIN

Num

Characteristic

Units

Min

Max

1

R1

Valid to CLKIN (setup)

CLKIN to invalid (hold)

RSTI to invalid (hold)

8

—

nS

R2

R3

1.0

1

RESET and FlexBus data lines are synchronized internally. Setup and hold

times must be met only if recognition on a particular clock is required.

Figure 27 shows reset timing for the values in Table 27.

CLKIN

R1

RSTI

R2

Mode Select

FlexBus

R1

R3

NOTE:

Mode selects are registered on the rising clock edge before

the cycle in which RSTI is recognized as being negated.

Figure 27. Reset Timing

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A.8 FlexBus

A multi-function external bus interface called FlexBus is provided on MCF5472 with basic functionality to

interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to

asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or

other simple target (slave) devices with little or no additional circuitry. For asynchronous devices a simple

chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects

(FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed to be byte

(8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM

/ flash memories.

A.8.1 FlexBus AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the system clock.

Table 28. FlexBus AC Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

1

Frequency of Operation

Clock Period (CLKIN)

30

15.15

—

66

33.33

7.0

Mhz

ns

2

3

FB1

FB2

Address, Data, and Control Output Valid (AD[31:0],

ns

FBCS[5:0], R/W, TS, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

3, 4

FB3

Address, Data, and Control Output Hold ((AD[31:0],

1

—

ns

FBCS[5:0], R/W, TS, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)

FB4

FB5

FB6

FB7

FB8

FB9

Data Input Setup

3.5

0

—

6.0

—

ns

Data Input Hold

Transfer Acknowledge (TA) Input Setup

Transfer Acknowledge (TA) Input Hold

Address Output Valid (PCIAD[31:0])

Address Output Hold (PCIAD[31:0])

4

0

5

—

0

1

The frequency of operation is the same as the PCI frequency of operation. The MCF547X supports a single

external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI.

Max cycle rate is determined by CLKIN and how the user has the system PLL configured.

Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section A.9.2, “DDR SDRAM AC Timing

Characteristics” for SDCS[3:0] timing.

The FlexBus supports programming an extension of the address hold. Please consult the MCF547X specification

manual for more information.

These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address

signals.

2

3

4

5

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CLKIN

FB1

FB3

AD[X:0]

A[X:0]

FB2

FB5

AD[31:Y]

A[31:Y]

DATA

R/W

FB4

TS

TSIZ[1:0]

FBCSn, BE/BWEn

FB7

OE

TA

FB6

Figure 28. FlexBus Read Timing

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CLKIN

FB1

FB3

AD[X:0]

A[X:0]

FB2

AD[31:Y]

A[31:Y]

DATA

R/W

TS

TSIZ[1:0]

FBCSn, BE/BWEn

FB7

OE

TA

FB6

Figure 29. FlexBus Write Timing

A.9 SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports

either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for

either Class I or Class II drive strength.

A.9.1 SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read

cycles. The MCF547X SDRAM controller is a DDR controller that has an SDR mode. Because it is

designed to support DDR, a DQS pulse must still be supplied to MCF547X for each data beat of an SDR

read. MCF547X accomplishes this by asserting a signal called SDR_DQS during read cycles. Care must be

taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS

signal and its usage.

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Table 29. SDR Timing Specifications

Symbol

Characteristic

Frequency of Operation

Clock Period (t_CK

Clock Skew (t_SK

Pulse Width High (t_CKH

Pulse Width Low (t_CKL

Address, CKE, CAS, RAS, WE, BA, CS - Output Valid

Min

Max

Unit

Notes

1

83

133

12

Mhz

ns

2

SD1

SD2

SD3

SD4

SD5

)

7.52

)

TBD

0.55

3

4

)

0.45

SDCLK

ns

)

0.5*SDCLK

+ 1.0ns

(t_CMV

)

SD6

Address, CKE, CAS, RAS, WE, BA, CS - Output Hold

2.0

ns

(t_CMH

SDRDQS Output Valid (t_DQSOV

SDDQS[3:0] input setup relative to SDCLK (t_DQSIS

)

5

6

SD7

SD8

)

Self timed

ns

)

0.25*SDCL 0.40*SDCL

K

7

8

SD9

SDDQS[3:0] input hold relative to SDCLK (t_DQSIH

)

Does not apply. 0.5 SDCLK fixed

width.

SD10

Data Input Setup relative to SDCLK (reference only) (t_DIS

)

0.25*SDCL

K

ns

SD11

SD12

Data Input Hold relative to SDCLK (reference only) (t_DIH

)

1.0

ns

Data and Data Mask Output Valid (t_DV

)

0.75*SDCL

K +0.500ns

SD13

Data and Data Mask Output Hold (t_DH

)

1.5

ns

1

The frequency of operation is either 2x or 4x the CLKIN frequency of operation. MCF547X supports a single external

reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock

operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF547X Specification

for more information on setting the SDRAM clock rate.

2

3

4

5

SDCLK is one SDRAM clock in (ns).

Pulse width high plus pulse width low cannot exceed min and max clock period.

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle

variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for

each data beat.

SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only.

Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will

occur for each data beat.

The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling

edge does not affect the memory controller.

Since a read cycle in SDR mode still uses the DQS circuit within MCF547X, it is most critical that the data valid

window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR

reads. The input setup spec is just provided as guidance.

6

7

8

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SD1

SD3

SD2

SDCLK0

SDCLK1

SD2

SD4

SD6

SDCSn,SDWE,

RAS, CAS

CMD

SD5

SDADDR,

SDBA[1:0]

ROW

COL

SD12

SDDM

SD13

WD2

SDDATA

WD1

Figure 30. SDR Write Timing

WD3

WD4

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SD1

SD2

SDCLK0

SDCLK1

SD2

SD6

SDCSn,SDWE,

RAS, CAS

CMD

3/4 MCLK

Reference

SD5

SDADDR,

SDBA[1:0]

ROW

COL

tDQS

SDDM

SD7

SDRQS (Measured at Output Pin)

SDDQS (Measured at Input Pin)

Board Delay

SD9

SD8

Delayed

SDCLK

SD10

SDDATA

form

Memories

WD1

WD2

WD3

WD4

NOTE: Data driven from memories relative

to delayed memory clock.

SD11

Figure 31. SDR Read Timing

A.9.2 DDR SDRAM AC Timing Characteristics

When using the DDR SDRAM controller the following timing numbers must be followed to properly latch

or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.

Table 30. DDR Clock Timing Specifications

Symbol

Characteristic

Clock output mid-point voltage

Min

Max

Unit

V_MP

1.05

-0.3

1.45

V

V_OUT

Clock output voltage level

SD_VDD +

0.3

V_ID

V_IX

Clock output differential voltage (peak to peak swing)

Clock crossing point voltage

0.7

SD_VDD +

0.6

V

1.05

1.45

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SDCLK

V_IX

V_ID

V_MP

V_IX

SDCLK

Figure 32. DDR Clock Timing Diagram

Table 31. DDR Timing Specifications

Symbol

Characteristic

Frequency of Operation

Clock Period (t_CK

Pulse Width High (t_CKH

Pulse Width Low (t_CKL

Address, SDCKE, CAS, RAS, WE, SDBA, SDCS - Output

Min

Max

Unit

Notes

1

83

7.52

0.45

—

133

12

MHz

ns

2

3

4

DD1

DD2

DD3

DD4

)

0.55

SDCLK

ns

)

0.5*SDCLK+

1.0 ns

Valid (t_CMV

)

DD5

Address, SDCKE, CAS, RAS, WE, SDBA, SDCS - Output

2.0

—

ns

Hold (t_CMH

Write Command to first DQS Latching Transition (t_DQSS

Data and Data Mask Output Setup (DQ-->DQS) Relative

)

DD6

DD7

)

—

1.25

—

SDCLK

ns

5

6

1.5

to DQS (DDR Write Mode) (t_QS

)

7

DD8

Data and Data Mask Output Hold (DQS-->DQ) Relative to

1.0

—

ns

DQS (DDR Write Mode) (t_QH

)

8

9

DD9

Input Data Skew Relative to DQS (Input Setup) (t_IS)

Input Data Hold Relative to DQS (t_IH)

1

ns

DD10

0.25*SDCLK

+0.5ns

—

DD11

DD12

DQS falling edge to SDCLK rising (output setup time)

0.5

—

ns

(t_DSS

)

DQS falling edge from SDCLK rising (output hold time)

0.5

(t_DSH

DQS input read preamble width (t_RPRE

DQS input read postamble width (t_RPST

DQS output write preamble width (t_WPRE

DQS output write postamble width (t_WPST

)

DD13

DD14

DD15

DD16

)

0.9

0.4

1.1

0.6

—

SDCLK

)

0.25

0.4

)

0.6

1

The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single

external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but

SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter for more

information on setting the SDRAM clock rate.

SDCLK is one memory clock in (ns).

Pulse width high plus pulse width low cannot exceed max clock period.

2

3

4

5

Pulse width high plus pulse width low cannot exceed max clock period.

This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to

SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is

relative SDDQS0.

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6

7

The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The

remaining data beats will be valid for each subsequent SDDQS edge.

This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to

SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is

relative SDDQS0.

Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last

data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due

to routing or other factors).

Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first

data line becomes invalid.

8

9

DD1

DD2

SDCLK0

SDCLK1

SDCLK0

SDCLK1

DD3

DD5

SDCSn,SDWE,

RAS, CAS

CMD

ROW

DD4

DD6

SDADDR,

SDBA[1:0]

COL

DD7

SDDM

SDDQS

SDDATA

DD8

DD7

WD1 WD2 WD3 WD4

DD8

Figure 33. DDR Write Timing

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DD1

DD2

SDCLK0

SDCLK1

SDCLK0

DD3

SDCLK1

DD5

CL=2

SDCSn,SDWE,

CMD

RAS, CAS

DD4

CL=2.5

SDADDR,

SDBA[1:0]

ROW

COL

DD9

DQS Read

Postamble

DQS Read

Preamble

SDDQS

SDDATA

SDDQS

SDDATA

DD10

WD1 WD2 WD3 WD4

DQS Read

Preamble

DQS Read

Postamble

WD1 WD2 WD3 WD4

Figure 34. DDR Read Timing

A.10 PCI Bus

The PCI bus on the MCF547X is PCI 2.2 compliant. The following timing numbers are mostly from the PCI

2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis.

Table 32. PCI Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

1

Frequency of Operation

Clock Period (t_CK

30

15.15

3.0

66

33.33

—

Mhz

ns

2

P1

P2

)

Address, Data, and Command (33< PCI <= 66 Mhz) - Input

Setup (t_IS)

ns

P2

P3

Address, Data, and Command (0 < PCI <= 33 Mhz) - Input

Setup (t_IS)

7.0

—

ns

3

Address, Data, and Command (33-66 Mhz) - Output Valid (t_DV

)

6.0

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Num

Characteristic

Min

Max

Unit

Notes

P3

P4

P5

P6

P7

P8

P9

P10

Address, Data, and Command (0 -33 Mhz) - Output Valid (t_DV

)

—

0

11.0

—

6

ns

4

5

6

PCI signals (0 - 66 Mhz) - Output Hold (t_DH

PCI signals (0 - 66 Mhz) - Input Hold (t_IH)

)

0

PCI REQ/GNT (33 < PCI <= 66Mhz) - Output valid (t_DV

)

—

12

10

PCI REQ/GNT (0 < PCI <= 33Mhz) - Output valid (t_DV

)

12

5

PCI REQ/GNT (33 < PCI <= 66Mhz) - Input Setup (t_IS)

PCI REQ (0 < PCI <= 33Mhz) - Input Setup (t_IS)

PCI GNT (0 < PCI <= 33Mhz) - Input Setup (t_IS)

—

1

Please see the PLL chapter for more information on setting the PCI clock rate. Also specific guidelines may need

to be followed when operating the system PLL below certain frequencies.

Max cycle rate is determined by CLKIN and how the user has the system PLL configured.

All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals.

PCI 2.2 spec does not require an output hold time. Although the MCF547X may provide a slight amount of hold, it

is not required or guaranteed.

2

3

4

5

6

PCI 2.2 spec requires zero input hold.

These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec.

P1

CLKIN

P3

P4

Output

Valid/Hold

Output Valid

P2

Input

Setup/Hold

Input Valid

P5

Figure 35. PCI Timing

A.11 Fast Ethernet AC Timing Specifications

A.11.1 MII/7-WIRE Interface Timing Specs

The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of

transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be

altered to match that specific transceiver.

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Table 33. MII Receive Signal Timing

Characteristic MIN

NUM

MAX

UNIT

M1

M2

M3

M4

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

RXCLK pulse width high

5

—

ns

5

ns

35%

65%

RXCLK period

RXCLK pulse width low

M3

M1

RXCLK (Input)

M4

RXD[3:0] (Inputs)

RXDV,

RXER

M2

Figure 36. MII Receive Signal Timing Diagram

A.11.2 MII Transmit Signal Timing

Table 34. MII Transmit Signal Timing

NUM

Characteristic

MIN

MAX

UNIT

M5

M6

M7

M8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

TXCLK pulse width high

0

—

ns

—

25

ns

35%

65%

TXCLK period

TXCLK pulse width low

M7

TXCLK (Input)

M5

M8

TXD[3:0] (Outputs)

TXEN,

TXER

M6

Figure 37. MII Transmit Signal Timing Diagram

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A.11.3 MII Async Inputs Signal Timing (CRS, COL)

Table 35. MII Transmit Signal Timing

Characteristic MIN

CRS, COL minimum pulse width 1.5

NUM

MAX

UNIT

M9

—

TX_CLK period

CRS, COL

M9

Figure 38. MII Async Inputs Timing Diagram

A.11.4 MII Serial Management Channel Timing

(MDIO,MDC)

Table 36. MII Serial Management Channel Signal Timing

MIN

(nS)

MAX

(nS)

NUM

Characteristic

UNIT

M10

MDC falling edge to MDIO output invalid

(min prop delay)

0

—

ns

M11

MDC falling edge to MDIO output valid

(max prop delay)

—

25

ns

M12

M13

M14

M15

MDIO (input) to MDC rising edge setup

MDIO (input) to MDC rising edge hold

MDC pulse width high

10

0

—

ns

40%

60%

MDC period

MDC pulse width low

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M14

M10

M12

M15

MDC (Output)

MDIO (Output)

MDIO (Input)

M11

M13

Figure 39. MII Serial Management Channel TIming Diagram

A.12 General Timing Specifications

Table 37 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts.

Table 37. General AC Timing Specifications

Name

Characteristic

CLKIN high to signal output valid

Min

Max

Unit

G1

G2

G3

—

0

2

PSTCLK

ns

CLKIN high to signal invalid (output hold)

Signal input pulse width

—

2

PSTCLK

A.13 I²C Input/Output Timing Specifications

2

Table 38 lists specifications for the I C input timing parameters shown in Figure 40.

Table 38. I²C Input Timing Specifications between SCL and SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1

I2

I3

I4

I5

I6

I7

I8

I9

2

8

—

1

Bus clocks

mS

Clock low period

SCL/SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

—

0

—

1

ns

SCL/SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

4

mS

—

Bus clocks

ns

Data setup time

0

Start condition setup time (for repeated start condition only)

Stop condition setup time

2

Bus clocks

2

Table 39 lists specifications for the I C output timing parameters shown in Figure 40.

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Table 39. I²C Output Timing Specifications between SCL and SDA

Num

Characteristic

Start condition hold time

Min

Max

Units

I1 ¹

I2 ¹

6

10

—

7

—

3

Bus clocks

µS

Clock low period

2

I3

SCL/SDA rise time (V_IL= 0.5 V to V_IH= 2.4 V)

Data hold time

I4 ¹

Bus clocks

ns

3

I5

SCL/SDA fall time (V_IH= 2.4 V to V_IL= 0.5 V)

Clock high time

—

10

2

I6 ¹

I7 ¹

I8 ¹

—

Bus clocks

Data setup time

Start condition setup time (for repeated start

condition only)

20

I9 ¹

Stop condition setup time

10

—

Bus clocks

1

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed

with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in

Table 39. The I²C interface is designed to scale the actual data transition time to move it to the

middle of the SCL low period. The actual position is affected by the prescale and division values

programmed into the IFDR; however, the numbers given in Table 39 are minimum values.

Because SCL and SDA are open-collector-type outputs, which the processor can only actively

drive low, the time SCL or SDA take to reach a high level depends on external signal

capacitance and pull-up resistor values.

2

3

Specified at a nominal 50-pF load.

Figure 40 shows timing for the values in Table 38 and Table 39.

I2

I6

I5

SCL

SDA

I1

I3

I7

I4

I8

I9

Figure 40. I²C Input/Output Timings

A.14 JTAG and Boundary Scan Timing

Table 40. JTAG and Boundary Scan Timing

Num

Characteristics ¹

TCLK Frequency of Operation

Symbol

Min

Max

Unit

J1

J2

J3

J4

f_JCYC

t_JCYC

t_JCW

DC

2

10

—

MHz

t_CK

ns

TCLK Cycle Period

TCLK Clock Pulse Width

TCLK Rise and Fall Times

15.15

0.0

—

t_JCRF

3.0

ns

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Table 40. JTAG and Boundary Scan Timing (continued)

Num

Characteristics ¹

Symbol

Min

Max

Unit

J5

J6

J7

J8

J9

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

t_BSDST

t_BSDHT

t_BSDV

5.0

24.0

0.0

—

ns

15.0

—

t_BSDZ

0.0

TMS, TDI Input Data Setup Time to TCLK Rise

t_TAPBST

t_TAPBHT

t_TDODV

t_TDODZ

t_TRSTAT

t_TRSTST

5.0

J10 TMS, TDI Input Data Hold Time after TCLK Rise

J11 TCLK Low to TDO Data Valid

10.0

0.0

—

15.0

—

J12 TCLK Low to TDO High Z

0.0

J13 TRST Assert Time

100.0

10.0

J14 TRST Setup Time (Negation) to TCLK High

—

1

MTMOD is expected to be a static signal. Hence, it is not associated with any timing

J2

J3

V_IH

TCLK (Input)

V_IL

J4

Figure 41. Test Clock Input Timing

V_IH

TCLK

V_IL

5

6

Data Inputs

Data Outputs

Input Data Valid

7

8

Output Data Valid

7

Output Data Valid

Figure 42. Boundary Scan (JTAG) Timing

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V_IH

10

TCLK

TDI, TMS, BKPT

TDO

V_IL

9

Input Data Valid

11

12

Output Data Valid

TDO

11

TDO

Output Data Valid

Figure 43. Test Access Port Timing

TCLK

TRST

14

13

Figure 44. TRST TimingDebug AC Timing Specifications

Table 41 lists specifications for the debug AC timing parameters shown in Figure 46.

Table 41. Debug AC Timing Specification

66 MHz

Num

Characteristic

Units

Min

Max

D1

D2

D3

PSTDDATA to PSTCLK setup

PSTCLK to PSTDDATA hold

DSI-to-DSCLK setup

4.5

1

ns

PSTCLKs

1

D4

DSCLK-to-DSO hold

4

D5

DSCLK cycle time

5

1

DSCLK and DSI are synchronized internally. D4 is measured from the

synchronized DSCLK input relative to the rising edge of CLKOUT.

Figure 45 shows real-time trace timing for the values in Table 41.

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Document Revision History

PSTCLK

D1

D2

PSTDDATA[7:0]

Figure 45. Real-Time Trace AC Timing

Figure 46 shows BDM serial port AC timing for the values in Table 41.

D5

DSCLK

D3

DSI

Current

DSO

Past

Figure 46. BDM Serial Port AC Timing

Current

A.15 DSPI Electrical Specifications

Table 42 lists DSPI timings.

Table 42. DSPI Modules AC Timing Specifications

Name

Characteristic

Min

Max

Unit

DS1

DS2

DS3

DS4

DS5

DSPI_CS[3:0] to DSPI_CLK

1 × tck

—

510 × tck

ns

DSPI_CLK high to DSPI_DOUT valid.

DSPI_CLK high to DSPI_DOUT invalid. (Output hold)

DSPI_DIN to DSPI_CLK (Input setup)

DSPI_DIN to DSPI_CLK (Input hold)

12

—

2

10

The values in Table 42 correspond to Figure 47.

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DSPI_CS[3:0]

DSPI_CLK

DS1

DS2

DSPI_DOUT

DSPI_DIN

DS3

DS4

DS5

Figure 47. DSPI Timing

A.16 Timer Module AC Timing Specifications

Table 43 lists timer module AC timings.

Table 43. Timer Module AC Timing Specifications

0–66 MHz

Name

Characteristic

Unit

Min

Max

T1

T2

TIN0 / TIN1 / TIN2 / TIN3 cycle time

TIN0 / TIN1 / TIN2 / TIN3 pulse width

3

1

—

PSTCLK

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Information in this document is provided solely to enable system and software implementers to

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MCF5475EC/D, Rev. 1.1, 2/2004


型号：	MCF5472VF200
厂家：	MOTOROLA
描述：	Microprocessor
文件：	总96页 (文件大小：1898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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