MCM218165BVT70R [MOTOROLA]
EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44;
| 型号： | MCM218165BVT70R |
| 厂家： | 
MOTOROLA |
| 描述： | EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM218165BV/D
SEMICONDUCTOR
TECHNICAL DATA
1M x 16
Advance Information
MCM218165BV
16M CMOS Wide DRAM Family
EDO
EDO, 1M x 16, and 1K Refresh
1024 Cycle Refresh
The family of 16M Dynamic RAMs is fabricated using 0.4µ CMOS
high–speed silicon–gate process technology. It includes devices organized as
1,048,576 sixteen–bit words. Advanced circuit design and fine line processing
provide high performance, improved reliability, and low cost.
The MCM218165BV is designed to operate from a single 3.3 V only power
supply.
These devices are packaged in a standard 400 mil J–lead small outline
package (SOJ) and a standard 400 mil thin–small–outline package (TSOP II).
J PACKAGE
400 MIL SOJ
CASE 986B–01
•
•
•
•
•
•
•
•
•
Single 3.3 V ± 0.3 V Power Supply
Extended Data Out (EDO) Page Mode Access
LVTTL–Compatible Inputs and Outputs (V
2 CAS Byte Control
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: 16 ms
= 3.3 V)
CC
T PACKAGE
400 MIL TSOP II
CASE 985A–01
Fast Access Time (t
):
RAC
MCM218165BV–60 = 60 ns (Max)
MCM218165BV–70 = 70 ns (Max)
•
•
Low Active Power Dissipation: 990/935 mW (Max)
Low Standby Power Dissipation: 1.8 mW (Max)
PIN NAMES
A0 – A9 . . . . . . . . . . . . . . . Address Input UCAS, LCAS . . Column Address Strobe
DQ1 – DQ16 . . . . . . . Data Input/Output
G . . . . . . . . . . . . . . . . . . . Output Enable
V
CC
V
SS
. . . . . . . . . . Power Supply (+ 3.3 V)
. . . . . . . . . . . . . . . . . . . . . . . . Ground
W . . . . . . . . . . . . . . . . Read/Write Enable NC . . . . . . . . . . . . . . . . . . No Connection
RAS . . . . . . . . . . . . Row Address Strobe
This document contains information on a new product. Specifications and information herein are subject to change without notice.
12/19/96
Motorola, Inc. 1996
PIN ASSIGNMENTS
400 MIL SOJ
400 MIL TSOP II
V
1
2
3
4
5
50
49
48
47
46
V
SS
CC
V
1
2
42
41
V
SS
CC
DQ1
DQ2
DQ3
DQ4
DQ16
DQ15
DQ14
DQ13
DQ1
DQ16
DQ2
DQ3
DQ4
3
4
5
6
7
40
39
38
37
36
DQ15
DQ14
DQ13
V
6
45
44
43
42
41
40
V
SS
CC
DQ5
DQ6
DQ7
DQ8
NC
7
DQ12
DQ11
DQ10
DQ9
NC
8
V
V
SS
CC
9
10
11
DQ5
DQ6
DQ12
DQ11
8
35
DQ7
DQ8
9
34
33
DQ10
DQ9
NC
NC
15
16
36
35
NC
10
LCAS
NC
NC
11
12
32
31
NC
W
RAS
NC
NC
A0
17
18
19
20
21
22
23
24
25
34
33
32
31
30
29
28
27
26
UCAS
G
LCAS
A9
A8
W
RAS
NC
13
14
15
30
29
28
UCAS
G
A7
A1
A6
A9
A2
A5
A3
A4
NC
A0
A1
16
17
18
27
26
25
A8
A7
A6
V
V
SS
CC
A2
A3
19
20
21
24
23
22
A5
A4
V
V
SS
CC
MCM218165BV
2
MOTOROLA DRAM
BLOCK DIAGRAM
W
CAS
LCAS
UCAS
CONTROL
LOGIC
DATA IN BUFFER
DQ1
•
•
•
DQ16
NO. 2 CLOCK
GENERATOR
DATA OUT
BUFFER
G
COLUMN
DECODER
COLUMN
ADDRESS
A0
A1
A2
A3
A4
A5
BUFFERS (10)
1024
• ••
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
1024 x 16
• ••
REFRESH
COUNTER
MEMORY
ARRAY
1024 x 1024 x 16
A6
A7
A8
A9
•
•
•
1024
ROW
ADDRESS
BUFFERS (10)
V
V
CC
SS
NO. 1 CLOCK
GENERATOR
RAS
MCM218165BV
3
MOTOROLA DRAM
TRUTH TABLE
Addresses
Function
RAS
LCAS
UCAS
W
X
G
X
L
DQx
Notes
Row
Column
Standby
H
L
L
H
X
H
X
X
X
High–Z
Read: Word
Read: Lower Byte
L
L
L
H
H
Row
Row
Column Data Out
H
L
Column Lower Byte: Data Out
Upper Byte: High–Z
Read: Upper Byte
L
H
L
H
L
Row
Column Lower Byte: High–Z
Upper Byte: Data Out
Write: Word (Early Write)
Write: Lower Byte (Early)
L
L
L
L
L
L
L
X
X
Row
Row
Column Data In
H
Column Lower Byte: Data In
Upper Byte High–Z
Write: Upper Byte (Early)
Read–Write
L
H
L
L
L
L
X
Row
Column Lower Byte: High–Z
Upper Byte: Data In
L
L
L
L
L
L
L
H
H
L
H
L
L
H
Row
Row
N/A
Row
N/A
Row
N/A
Row
Row
Row
X
Column Data Out, Data In
Column Data Out
1, 2
2
EDO Page Mode
Read
1st Cycle
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
L
L
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
Read
Column Data Out
2
EDO Page Mode
Write
X
X
Column Data In
1
L
Column Data In
1
EDO Page Mode
Read Write
H
H
L
L
L
L
H
H
Column Data Out, Data In
Column Data Out, Data In
Column Data Out
1, 2
1, 2
2
Hidden Refresh
L
L
L
L
L
L
L
L
H
L
L
X
X
X
Write
Column Data In
1, 3
RAS–Only Refresh
H
L
H
L
X
X
N/A
X
High–Z
High–Z
CAS Before RAS Refesh
NOTES:
H
L
4
1. These write cycles may also be byte write cycles (either LCAS or UCAS active).
2. These read cycles may also be byte read cycles (either LCAS or UCAS active).
3. Early write only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Power Supply Voltage
Symbol
Value
– 0.5 to 4.6
– 0.5 to 4.6
50
Unit
V
3.3 V
3.3 V
V
CC
Voltage Relative to V
Data Out Current
Power Dissipation
V , V
in out
V
SS
I
mA
W
out
P
D
1.0
Operating Temperature Range
Storage Temperature Range
T
0 to + 70
– 55 to + 125
°C
°C
A
T
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM218165BV
4
MOTOROLA DRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All Voltages Referenced to V
)
SS
Parameter
Supply Voltage (Operating Voltage Range)
Logic High Voltage, All Inputs
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
5 V
5 V
5 V
V
CC
3.6
V
IH
2.0
V
+ 0.3
V
CC
Logic Low Voltage, All Inputs
V
IL
– 0.3
—
0.8
V
DC CHARACTERISTICS AND SUPPLY CURRENTS (All Voltages Referenced to V
)
SS
MCM218165BV–60 MCM218165BV–70
Characteristic
Symbol
Min
Max
Min
Max
Unit
Notes
Power Supply Current
(RAS, LCAS, UCAS Cycling, t
I
—
180
—
170
mA
1, 2
CC1
CC2
= min)
RC
Power Supply Current (Standby)
I
mA
(TTL Interface RAS, CAS = V
Data Out = High–Z)n
,
IH
—
2
—
2
(CMOS Interface RAS, CAS ≥ V
Data Out = High–Z)n
– 0.2 V,
CC
—
—
0.5
—
—
0.5
Power Supply Current During RAS–Only Refresh Cycles
(RAS Cycling, CAS = V , t = Min)
I
180
170
mA
2
CC3
IH RC
Power Supply Current During EDO Page Mode Cycle (t
= Min)
I
I
—
—
100
180
—
—
90
mA
mA
1, 3
PC
Power Supply Current During CAS Before RAS Refresh Cycle
(t = Min, RAS, CAS Cycling)
CC4
170
CC5
RC
Input Leakage Current (0 V ≤ V ≤ V
in
)
I
– 5
– 5
2.4
—
5
5
– 5
– 5
2.4
—
5
5
µA
µA
V
CC
lkg(I)
Output Leakage Current (0 V ≤ V
≤ V , Data Out = Disable)
I
lkg(O)
out
CC
Output High Voltage (I
= – 5 mA)
V
—
0.4
—
0.4
OH
= 4.2 mA)
OH
Output Low Voltage (I
NOTES:
V
V
OL
OL
1. I
depends on the output load condition when the device is selected. I max is specified at the ouput open condition.
CC
CC
2. Address may be changed once or less while RAS = V
IL
3. Address may be changed once or less while LCAS and UCAS = V
4. All V
.
.
IL
and V
pins will be supplied with the same voltage.
SS
CC
CAPACITANCE (f = 1.0 MHz, T = 25°C, V
= 3.3 V ± 0.3 V, Periodically Sampled Rather Than 100% Tested)
A
CC
Characteristic
Symbol
Max
Unit
Notes
Input Capacitance
A0 – A9
G, RAS, UCAS, LCAS, W
DQ1 – DQ16
C
5
7
7
pF
1
in
Input/Output Capacitance
NOTES:
C
pF
1, 2
I/O
1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
2. LCAS and UCAS = V to disable data out.
IH
MCM218165BV
5
MOTOROLA DRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 0.3 V, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
Input Timing Reference Level . . . . . . . . . . . VIH = 2.0 V, VIL = 0.8 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . VOL = 0.8 V, VOH = 2.0 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . One TTL Load and 100 pF
ALL DEVICES: READ, WRITE, READ–MODIFY–WRITE, AND REFRESH CYCLES (See Notes 1, 2, 3, 4, and 5)
Symbol MCM218165BV–60 MCM218165BV–70
Std
Alt
Min
110
40
60
10
0
Max
—
Min
130
50
70
12
0
Max
—
Parameter
Random Read or Write Cycle Time
RAS Precharge Time
Unit Notes
t
t
ns
ns
RELREL
RC
t
t
t
t
—
—
REHREL
RELREH
CELCEH
RP
RAS Pulse Width
t
t
t
10 k
10 k
—
10 k
10 k
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
6
7
RAS
CAS
ASR
RAH
LCAS/UCAS Pulse Width
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to LCAS/UCAS Delay Time
RAS to Column Address Delay Time
Column Address to RAS Lead Time
RAS Hold Time
t
AVREL
t
t
10
0
—
10
0
—
RELAX
t
t
—
—
8
AVCEL
ASC
CAH
RCD
t
t
10
20
15
30
15
60
5
—
15
20
15
35
18
70
5
—
CELAX
t
t
42
30
—
50
35
—
9
RELCEL
t
t
10
RELAV
RAD
t
t
AVREH
RAL
RSH
CSH
CRP
t
t
t
t
t
t
—
—
CELREH
RELCEH
CEHREL
LCAS/UCAS Hold Time
—
—
LCAS/UCAS to RAS Precharge Time
G to Data In Delay Time
Transition Time (Rise and Fall)
Refresh Period
—
—
11
12
t
t
15
1
—
18
1
—
GLHDX
GD
t
T
t
T
50
16
—
50
16
—
t
t
—
0
—
0
RVRV
REF
CAS to Output in Low–Z
Access Time from RAS
t
t
t
t
CLZ
CELQX
RELQV
CELQV
t
—
—
—
—
60
18
30
15
—
—
—
—
70
20
35
18
13
RAC
CAC
Access Time from LCAS/UCAS
Access Time from Column Address
Access Time from G
t
14, 15
15, 16
t
t
AVQV
AA
t
t
GLQV
GA
NOTES:
(continued)
1. AC measurements assume t = 2.0 ns.
T
2. An initial pause of 100 µs is required after power–up, followed by a minimum of initialization cycles (RAS–only refresh cycle or CAS before
RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are required.
3. In delayed write or read–modify–write cycles, G must disable the output buffer prior to applying data to the device.
4. When both LCAS and UCAS go low at the same time, all 16 bits of data are written into the device. LCAS and UCAS can not be staggered
within the same write/read cycles.
5. All V
and V
pins will be supplied with the same voltages.
SS
CC
6. t
7. t
8. t
(min) = t
(min) = t
(min) + t
(min) + t
(min) + t in read–modify–write cycle.
RAS
CAS
ASC
RWD
CWD
RWL
CWL
T
(min) + t in read–modify–write cycle.
T
(min), t
(min), t
(min), and t
are determined by the earlier falling edge of LCAS or UCAS.
RPC
RCS
WCS
(max) limit ensures that t
9. Operation within the t
is greater than the specified t
10. Operation within the t
(max) can be met. t (max) is specified as a reference point only; if t
RCD
RAC
RCD
RCD
RAD
(max) limit, then access time is controlled exclusively by t .
CAC
RCD
(max) limit ensures that t
(max) can be met. t (max) is specified as a reference point only; if t
RAD
RAC
RAD
is greater than the specified t
(max), then access time is controlled exclusively by t .
AA
RAD
, and t
11. t
, t
, t
, t
are determined by the latter rising edge of LCAS or UCAS.
CRP CHR RCH CPA
CPW
12. V (min) and V (max) are reference levels for measuring timing or input signals. Transition times are measured between V and V
.
IL
IH
IL
IH
13. Assumes that t
≤ t
RCD RCD
(max) and t
exceeds the value shown.
≤ t
(max). If t
or t
is greater than the maximum recommended value shown
RAD
RAD RAD
RCD
in this table, t
RAC
14. Assumes that t
15. Access time is determined by the longer of t , t
16. Assumes that t
≥ t
(max) and t
≤ t
(max).
, t .
RCD RCD
RAD RAD
AA CAC CPA
≤ t
(max) and t
≥ t (max).
RCD RCD
RAD RAD
MCM218165BV
6
MOTOROLA DRAM
ALL DEVICES: READ, WRITE, READ–MODIFY–WRITE, AND REFRESH CYCLES (continued)
Symbol MCM218165BV–60 MCM218165BV–70
Std
Alt
Min
0
Max
—
Min
0
Max
—
Parameter
Read Command Setup Time
Unit Notes
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
11, 17
17
WHCEL
CEHWX
REHWX
RCS
RCH
RRH
Read Command Hold Time to LCAS/UCAS
Read Command Hold Time to RAS
Output Buffer Turn–Off Time
t
t
t
t
0
—
0
—
10
0
—
10
0
—
t
t
15
15
—
18
18
—
18
CEHQZ
OFF
Output Buffer Turn–Off Time from G
Write Command Setup Time
t
t
0
0
18
GHQZ
GZ
t
t
0
0
8, 19
WLCEL
WCS
Write Command Hold Time
t
t
10
10
15
15
0
—
10
10
18
18
0
—
CELWH
WCH
Write Command Pulse Width
t
t
—
—
WLWH
WP
Write Command to RAS Lead Time
Write Command to LCAS/UCAS Lead Time
Data In Setup Time
t
t
—
—
WLREH
WLCEH
RWL
CWL
t
t
—
—
20
21
21
t
t
—
—
DVCEL
DS
Data In Hold Time
t
t
10
10
133
77
32
47
15
10
10
5
—
15
10
157
89
37
54
18
10
10
5
—
CELDX
DH
W to Data In Delay
t
t
—
—
WLDV
WD
Read–Modify–Write Cycle Time
RAS to W Delay Time
t
t
t
—
—
RELREL
RWC
RWD
CWD
t
—
—
19
19
19
RELWL
CELWL
LCAS/UCAS to W Delay Time
Column Address to W Delay Time
G Hold Time from W
t
t
—
—
t
t
—
—
AVWL
WLGL
AWD
t
t
—
—
GH
LCAS/UCAS Setup Time (CAS Before RAS Refresh)
LCAS/UCAS Hold Time (CAS Before RAS Refresh)
RAS Precharge to LCAS/UCAS Hold Time
LCAS/UCAS Precharge Time (Normal Mode)
EDO Page Mode Cycle Time
t
t
—
—
CELCEL
RELCEH
REHCEL
CEHCEL
CSR
CHR
t
t
t
t
—
—
11
8
t
—
—
RPC
CPN
t
10
25
10
60
—
10
30
10
70
—
22
t
t
—
—
RELREL
CEHCEL
RELREH
PC
CP
EDO Page Mode LCAS/UCAS Precharge Time
EDO Page Mode RAS Pulse Width
NOTES:
t
t
t
—
—
22
23
t
100 k
100 k
RASP
(continued)
17. Either t
or t
must be satisfied for a read cycle.
(max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage
RCH
RRH
(max) and/or t
18. t
OFF
GZ
is determined by the later rising edge of RAS or CAS.
, t , and t are not restrictive operating parameters. They are included in the data sheet as electrical char-
acteristics only; if t
levels. t
OFF
19. t
, t
WCS RWD CWD
AWD
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
≥ t
WCS
WCS
CWD
throughout the entire cycle. If t
≥ t
(min), t
≥ t
(min), t
≥ t
(min), and t
≥ t
(min), the cycle is a
CPW
CWD
RWD
RWD
AWD
AWD
CPW
read–modify–write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
20. t
shall be satisfied by both LCAS and UCAS.
CWL
21. Theseparameters are referenced to LCAS or UCAS separately in an early write cycle and to W edge in a delayed write or read–modify–write
cycle.
22. t
23. t
and t
are determined by the time that both LCAS and UCAS are high.
defines RAS pulse width in EDO page mode cycles.
CPN
CP
RASP
MCM218165BV
7
MOTOROLA DRAM
ALL DEVICES: READ, WRITE, READ–MODIFY–WRITE, AND REFRESH CYCLES (continued)
Symbol MCM218165BV–60 MCM218165BV–70
Std
Parameter
Access Time from LCAS /UCAS Precharge
RAS Hold Time from LCAS/UCAS Precharge
G High Hold Time from CAS High
G High Pulse Width
Unit Notes
Alt
Min
—
35
5
Max
35
—
Min
—
40
5
Max
40
—
t
t
ns
ns
ns
ns
ns
ns
ns
ns
11, 15
CEHQV
CPA
t
t
CPRH
CEHREH
t
t
—
—
CEHGL
GHC
t
t
10
5
—
10
5
—
GHGL
GP
Data Output Hold After CAS Low
Output Disable Delay from W
t
t
—
—
CELDX
COH
WHZ
t
t
3
10
—
3
10
—
WELDX
W Pulse Width for Output Disable When CAS High
t
t
7
7
WLWH
WPZ
CPW
EDO Page Mode Read–Modify–Write Cycle
LCAS/UCAS Precharge to W Delay Time
t
t
55
—
65
—
11
CEHWL
EDO Page Mode Read–Modify–Write Cycle Time
t
t
68
—
75
—
ns
CELCEL
PRWC
MCM218165BV
8
MOTOROLA DRAM
TIMING DIAGRAMS
WORD READ CYCLE
t
RC
V
V
IH
IL
t
RAS
RAS
t
RP
t
t
CSH
CRP
t
t
RSH
RCD
t
V
V
CAS
IH
IL
UCAS, LCAS
t
T
t
RAD
t
RAL
t
t
ASC
ASR
t
t
CAH
RAH
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
RRH
t
t
RCH
RCS
V
V
IH
IL
W
G
t
AA
t
GA
V
V
IH
IL
t
t
CAC
OFF
t
RAC
t
GZ
t
CLZ
V
OH
DQ1 – DQ16
HIGH–Z
DATA OUT
V
OL
MCM218165BV
9
MOTOROLA DRAM
BYTE READ CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
t
CAS
V
IH
UCAS
(OR LCAS)
V
IL
t
T
V
IH
LCAS
(OR UCAS)
V
IL
t
RAD
t
t
RAL
RAH
t
t
t
CAH
ASR
ASC
V
IH
ROW
COLUMN
ADDRESSES
V
IL
t
RCH
t
RRH
t
RCS
V
IH
W
G
V
IL
t
AA
t
GA
V
IH
V
IL
t
t
OFF
CAC
t
V
t
GZ
OH
RAC
DQ9 – DQ16
(OR DQ1 – DQ8)
V
OL
DATA OUT
t
CLZ
V
OH
DQ1 – DQ8
HIGH–Z
(OR DQ9 – DQ16)
V
OL
MCM218165BV
10
MOTOROLA DRAM
WORD EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
t
CAS
V
IH
UCAS, LCAS
t
V
T
IL
t
RAH
t
CAH
t
t
ASR
ASC
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
t
RAL
RAD
t
t
WCH
WCS
V
IH
W
V
IL
t
t
DH
DS
V
OH
DQ1 – DQ16
DATA IN
V
OL
BYTE EARLY WRITE CYCLE
t
RC
V
t
IH
RAS
RAS
V
IL
t
RP
t
CSH
t
t
t
CRP
RCD
RSH
CAS
t
V
IH
UCAS
(OR LCAS)
V
IL
t
T
V
IH
LCAS
(OR UCAS)
V
t
IL
t
RAL
RAH
t
t
t
ASR
ASC
CAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
RAD
t
t
WCH
WCS
V
IH
W
V
IL
t
t
DH
DS
V
IH
DQ9 – DQ16
(OR DQ1 – DQ8)
DATA IN
V
IL
V
DQ1 – DQ8 IH
(OR DQ9 – DQ16)
V
IL
MCM218165BV
11
MOTOROLA DRAM
WORD DELAYED WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
CAS
t
V
IH
LCAS, UCAS
V
IL
t
T
t
RAH
t
ASR
t
CAH
t
ASC
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
CWL
t
t
RWL
RCS
t
WP
V
IH
W
G
V
IL
t
GD
t
GH
V
IH
V
IL
t
DH
t
DS
V
OPEN
IH
DATA IN
DQ1 – DQ16
V
IL
MCM218165BV
12
MOTOROLA DRAM
BYTE DELAYED WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
CAS
t
V
IH
UCAS
(OR LCAS)
V
IL
t
T
V
IH
LCAS
(OR UCAS)
V
IL
t
RAH
t
ASR
t
CAH
t
ASC
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
CWL
t
t
RWL
RCS
t
WP
V
V
IH
W
G
V
IL
t
GD
t
GH
IH
V
IL
t
DH
t
DS
V
OPEN
DQ9 – DQ16
(OR DQ1 – DQ8)
IH
DATA IN
V
IL
V
DQ1 – DQ8
IH
(OR DQ9 – DQ16)
V
IL
MCM218165BV
13
MOTOROLA DRAM
WORD READ–MODIFY–WRITE CYCLE
t
RWC
t
t
t
RAS
RP
V
IH
RAS
UCAS, LCAS
ADDRESSES
V
IL
t
T
t
t
CAS
RCD
CRP
V
IH
V
t
IL
RAD
t
t
ASC
ASR
t
t
CAH
RAH
V
IH
ROW
COLUMN
V
IL
t
t
AWD
CWL
t
t
CWD
RWL
t
t
WP
RCS
V
V
V
IH
W
G
V
t
IL
AA
t
RWD
t
GH
t
GA
IH
V
IL
t
GD
t
DH
t
t
RAC
DS
IH
DATA IN
V
IL
t
GZ
t
CAC
DQ1 – DQ16
V
OH
DATA OUT
V
OL
MCM218165BV
14
MOTOROLA DRAM
BYTE READ–MODIFY–WRITE CYCLE
t
RWC
t
t
t
RP
RAS
V
IH
RAS
V
IL
t
T
t
t
CAS
RCD
CRP
V
UCAS
IH
(OR LCAS)
V
IL
V
LCAS
IH
(OR UCAS)
V
IL
t
RAD
t
ASC
t
ASR
t
t
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
t
AWD
CWL
t
t
CWD
RWL
WP
t
t
RCS
V
IH
W
G
V
IL
t
AA
t
RWD
t
t
GH
GA
V
IH
V
IL
t
t
DH
GD
t
RAC
t
DS
V
IH
OPEN
OPEN
DATA IN
V
IL
t
t
GZ
CAC
DQ1 – DQ16
V
OH
DATA OUT
V
OL
MCM218165BV
15
MOTOROLA DRAM
EDO PAGE MODE WORD READ CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
t
CSH
PC
RSH
CPRH
t
t
CRP
t
RCD
t
t
t
t
CP
CRP
CP
CP
t
t
t
CAS
CAS
CAS
V
IH
UCAS, LCAS
V
IL
t
t
RAL
RAD
t
t
t
ASC
t
ASC
ASC
ASR
t
t
CAH
t
t
RAH
CAH
CAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ROW
ADDRESSES
V
IL
t
t
RRH
t
RCH
RCS
V
IH
W
V
IL
t
AA
t
t
AA
AA
t
t
CPA
CPA
t
t
t
GP
GA
GA
V
IH
G
V
IL
t
t
RAC
GHC
t
OFF
t
t
t
t
t
CAC
CAC
t
OFF
GZ
CAC
t
GZ
COH
V
OH
OPEN
DQ1 – DQ16
D
1
D
2
D
N
out
out
out
V
OL
MCM218165BV
16
MOTOROLA DRAM
EDO PAGE MODE BYTE READ CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
t
CSH
PC
RSH
CPRH
t
t
CRP
t
RCD
t
t
t
t
CP
CRP
CP
CP
t
t
t
CAS
CAS
CAS
V
IH
UCAS
(OR LCAS)
V
IL
V
IH
LCAS
(OR UCAS)
V
IL
t
RAL
t
ASC
t
RAD
t
t
ASC
ASC
t
ASR
t
t
t
CAH
t
CAH
RAH
CAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ROW
ADDRESSES
V
IL
t
t
RRH
t
RCH
RCS
V
IH
W
V
IL
t
AA
t
t
AA
AA
t
t
CPA
CPA
t
t
t
GP
GA
GA
V
IH
G
V
IL
t
t
RAC
GHC
t
OFF
t
t
t
t
t
CAC
CAC
t
OFF
GZ
CAC
t
GZ
COH
V
OH
DQ9 – DQ16
(OR DQ1 – DQ8)
OPEN
D
1
D
2
D
N
out
out
out
V
OL
V
IH
DQ1 – DQ8
(OR DQ9 – DQ16)
V
IL
MCM218165BV
17
MOTOROLA DRAM
EDO PAGE MODE WORD EARLY WRITE CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
RSH
PC
t
t
t
CP
RCD
CP
t
CRP
t
t
t
t
CAS
t
CAS
CAS
T
V
IH
UCAS, LCAS
V
IL
t
CSH
t
t
t
ASC
ASR
ASC
ASC
t
t
t
t
CAH
CAH
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN 1
COLUMN 2
COLUMN N
V
IL
t
t
t
WCS
WCS
WCS
WCH
t
t
t
WCH
WCH
V
IH
W
V
IL
t
DH
t
t
DH
DH
t
t
t
DS
DS
DS
V
OH
DQ1 – DQ16
D
1
D
2
D
N
in
in
in
V
OL
MCM218165BV
18
MOTOROLA DRAM
EDO PAGE MODE BYTE EARLY WRITE CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
RSH
PC
t
t
t
CP
RCD
CP
t
CRP
t
t
CAS
t
CAS
t
CAS
T
V
IH
UCAS
(OR LCAS)
V
IL
V
IH
LCAS
(OR UCAS)
V
IL
t
CSH
t
ASC
t
t
t
ASR
ASC
ASC
t
t
t
t
CAH
CAH
CAH
RAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESSES
V
IL
t
t
t
WCS
WCS
WCS
WCH
t
t
t
WCH
WCH
V
IH
W
V
IL
t
DH
t
t
DH
DH
t
t
t
DS
DS
DS
V
OH
DQ9 – DQ16
(OR DQ1 – DQ8)
D
1
D
2
D
in
N
in
in
V
OL
V
DQ1 – DQ8
IH
(OR DQ9 – DQ16)
V
IL
MCM218165BV
19
MOTOROLA DRAM
EDO PAGE MODE WORD READ–EARLY–WRITE CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
t
CSH
PC
RSH
CPRH
t
t
CRP
t
RCD
t
t
t
t
CP
CRP
CP
CP
t
t
t
CAS
CAS
CAS
V
IH
UCAS, LCAS
V
IL
t
CAL
t
t
RAL
RAD
t
t
t
ASC
ASC
ASC
t
ASR
t
t
t
t
CAH
RAH
CAH
CAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ROW
ADDRESSES
V
IL
t
RCH
t
t
t
WCH
WCS
RCS
V
IH
W
V
IL
t
t
AA
AA
t
CPA
t
WD
t
GA
V
IH
G
V
IL
t
t
RAC
DH
t
t
t
WHZ
CAC
CAC
t
t
DS
COH
V
OH
OPEN
DQ1 – DQ16
D
1
D
2
D
N
out
out
out
V
OL
MCM218165BV
20
MOTOROLA DRAM
EDO PAGE MODE BYTE READ–EARLY–WRITE CYCLE
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
t
CSH
PC
RSH
CPRH
t
t
CRP
t
RCD
t
t
t
t
CP
CRP
CP
CP
t
t
t
CAS
CAS
CAS
V
IH
UCAS
(OR LCAS)
V
IL
V
IH
LCAS
(OR UCAS)
V
IL
t
CAL
t
t
RAL
RAD
t
t
t
ASC
ASC
ASC
t
ASR
t
t
t
t
CAH
RAH
CAH
CAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ROW
ADDRESSES
V
IL
t
RCH
t
t
t
WCH
WCS
RCS
V
IH
W
V
IL
t
t
AA
AA
t
CPA
t
WD
t
GA
V
IH
G
V
IL
t
t
RAC
DH
t
t
t
WHZ
CAC
CAC
t
DS
t
COH
V
OH
DQ9 – DQ16
(OR DQ1 – DQ8)
OPEN
D
1
D
2
D
N
out
out
out
V
OL
V
DQ1 – DQ8
IH
(OR DQ9 – DQ16)
V
IL
MCM218165BV
21
MOTOROLA DRAM
EDO PAGE MODE WORD READ–MODIFY–WRITE CYCLE
t
RP
t
RASP
t
CPRH
V
V
IH
RAS
V
IL
t
t
t
t
CP
CRP
RCD
CP
t
t
PRWC
T
t
t
t
CAS
CAS
CAS
IH
UCAS, LCAS
V
IL
t
RAD
RAH
ASR
t
t
CAH
t
t
t
CAH
t
RAL
CAH
t
t
t
ASC
ASC
ASC
V
IH
COL. 1
COL. 2
COL. N
ADDRESSES
V
IL
t
t
t
RWD
CWD
CPW
ROW
t
t
t
t
CWD
CPW
CWD
RWL
t
t
t
t
CWL
CWL
RCS
CWL
V
IH
W
G
V
t
t
t
AWD
IL
AWD
AWD
t
t
AA
t
AA
AA
t
t
RCS
t
t
GA
RCS
GA
t
t
t
GA
t
WP
WP
WP
V
IH
V
IL
t
t
t
GH
GH
GH
t
CPA
t
t
t
RAC
CPA
t
t
t
CAC
t
DS
CAC
t
CAC
DS
DS
V
IH
OPEN
OPEN
OPEN
D
1
D
2
D
N
in
in
in
V
IL
t
t
t
DH
DH
DH
DQ1 –
DQ16
t
t
t
GD
GZ
GD
GD
GZ
t
t
t
GZ
V
OH
V
OL
D
1
D
2
D
N
out
out
out
MCM218165BV
22
MOTOROLA DRAM
EDO PAGE MODE BYTE READ–MODIFY–WRITE CYCLE
t
RP
t
RASP
t
CPRH
V
V
IH
RAS
V
IL
t
t
t
t
CP
CRP
RCD
CP
t
t
PRWC
T
t
t
t
CAS
CAS
CAS
IH
UCAS
(OR LCAS)
V
IL
V
IH
LCAS
(OR UCAS)
V
IL
t
RAD
t
t
RAH
ASR
CAH
t
t
t
CAH
t
RAL
CAH
t
t
t
ASC
ASC
ASC
V
IH
COL. 1
COL. 2
COL. N
ADDRESSES
V
IL
t
t
t
RWD
CWD
CPW
ROW
t
t
t
t
CWD
CPW
CWD
RWL
t
t
t
t
CWL
CWL
RCS
CWL
V
IH
W
G
V
t
t
t
AWD
IL
AWD
AWD
t
t
AA
t
AA
AA
t
t
RCS
t
t
GA
RCS
GA
t
t
t
GA
t
WP
WP
WP
V
IH
V
IL
t
t
t
GH
GH
GH
t
CPA
t
t
t
RAC
CPA
t
t
t
CAC
t
DS
CAC
t
CAC
DS
DS
V
IH
OPEN
OPEN
OPEN
D
t
1
D
2
D
N
in
in
in
V
DQ9 –
DQ16
(OR
IL
t
t
t
DH
DH
DH
t
t
GD
GZ
GD
t
GD
t
t
DQ1 –
GZ
GZ
DQ8)
V
OH
V
OL
D
1
D
2
D
N
out
out
out
MCM218165BV
23
MOTOROLA DRAM
READ CYCLE WITH W CONTROLLED DISABLE
V
IH
RAS
V
IL
t
CSH
t
t
RCD
CAS
V
IH
UCAS, LCAS
t
T
V
IL
t
RAD
t
t
ASC
t
ASR
t
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
WPZ
t
t
RCH
RCS
V
IH
W
G
V
IL
t
AA
t
t
WHZ
GA
V
IH
V
IL
t
t
GD
CAC
t
RAC
t
GZ
t
CLZ
V
OH
DQ1 – DQ16
DATA OUT
V
OL
HIDDEN REFRESH CYCLE
t
RC
t
t
RC
RC
RAS
(REFRESH)
t
t
t
t
t
t
RP
RAS
(READ)
RP
RP
RAS
(REFRESH)
V
IH
RAS
V
IL
t
T
t
t
t
t
CRP
RCD
RSH
CHR
t
CAS
V
V
IH
UCAS, LCAS
ADDRESSES
t
CAH
V
t
IL
RAD
t
ASC
t
ASR
IH
COLUMN
ROW
V
IL
t
t
t
RAL
RRH
t
RAH
t
RCH
RCS
V
IH
W
G
V
IL
t
AA
t
t
GZ
ORD
t
GA
V
IH
V
IL
t
t
OFF
CAC
t
t
OFF
RAC
V
OH
DQ1 – DQ16
DATA OUT
V
OL
MCM218165BV
24
MOTOROLA DRAM
RAS–ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
T
t
t
CRP
t
RPC
CRP
V
IH
UCAS, LCAS
ADDRESSES
V
IL
t
t
RAH
ASR
V
IH
ROW
V
IL
t
OFF
V
OH
DQ1 – DQ16
OPEN
V
OL
CAS BEFORE RAS REFRESH CYCLE
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
V
IH
RAS
V
IL
t
T
t
t
t
t
CRP
CHR
RPC
CHR
t
RPC
t
t
t
CSR
CSR
CPN
t
CPN
V
IH
UCAS, LCAS
ADDRESSES
V
IL
V
IH
V
IL
t
OFF
V
OH
DQ1 – DQ16
OPEN
V
OL
MCM218165BV
25
MOTOROLA DRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 218165BV X XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel,
Blank = Rails for SOJ, Trays for TSOP II)
Speed (60 = 60 ns, 70 = 70 ns)
Package (J = 400 mil SOJ, T = 400 mil TSOP II
and 400 mil TSOP II Reverse)
Full Part Numbers — MCM218165BVJ60 MCM218165BVJ60R MCM218165BVT60
MCM218165BVJ70 MCM218165BVJ70R MCM218165BVT70
MCM218165BVT60R
MCM218165BVT70R
MCM218165BV
26
MOTOROLA DRAM
PACKAGE DIMENSIONS
J PACKAGE
400 MIL SOJ
CASE 986B–01
NOTES:
42
22
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 (0.15) PER END.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH. INTERLEAD FLASH SHALL NOT EXCEED
0.010 (0.25) PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSIONS b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005 (0.13). THE DAMBAR
INTRUSION(S) SHALL NOT REDUCE THE
SHOULDER WIDTH TO LESS THAN 0.001 (0.03
BELOW b2 MIN.
E1
1
21
B
A
D
42X b1
L
0.007 (0.18)
C
A B
40X
e
A
A3
SEATING
PLANE
A
INCHES
MILLIMETERS
e /2
DIM
A
A1
A2
A3
b
b1
D
E
MIN
MAX
0.148
–––
MIN
3.25
0.635
2.08
0.89
0.38
MAX
3.75
–––
0.004 (0.1)
C
42X b
C
0.128
0.025
0.082
0.035
0.015
0.026
1.070
0.435
0.395
42X
M
0.007 (0.18)
C
A B
–––
–––
0.045
0.020
0.032
1.080
0.445
0.405
1.14
0.50
0.81
27.43
11.30
10.28
0.66
27.19
11.05
10.03
9.40 BSC
1.27 BSC
0.76 1.01
E
E1
E2
e
M
0.007 (0.18)
C
A B
0.370 BSC
0.050 BSC
0.030 0.040
A
R1
42X R R1
A2
A1
E2 /2
0.015 (0.38)
B
E2
21 ZONES 2X
VIEW A–A
MCM218165BV
27
MOTOROLA DRAM
T PACKAGE
400 MIL TSOP II
CASE 985A–01
VIEW A
B
50
40
36
26
E1
1
11
15
25
D
A
A
22X E
M
0.2 (0.008)
C A B
C
0.1 (0.004)
C
L
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MM.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION IS 0.15
(0.006) MAXIMUM PER SIDE.
SEATING
PLANE
C
40X e
4. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58
(0.023).
4X e1
5. FOR LEAD IDENTIFICATION PURPOSES, PIN
POSITIONS 12, 13, 14, 37, 38 AND 39 ARE NOT
USED.
MILLIMETERS
INCHES
MIN
DIM
A
A1
b
b1
c
c1
D
MIN
–––
MAX
1.20
0.15
0.45
0.40
0.25
0.20
21.06
MAX
0.047
0.006
0.018
0.016
0.010
0.008
0.829
b1
–––
0.002
0.010
0.010
0.005
0.004
0.821
R (R1)
R (R2)
BASE METAL
0.05
0.25
0.25
0.12
0.10
20.85
c1
c
A
e
e1
E
E1
L
0.80 BSC
1.60 BSC
0.0315 BSC
0.063 BSC
A
A1
11.56
11.96
10.26
0.60
0.455
0.471
0.404
0.024
b
10.06
0.40
0.396
0.016
L
M
0.13 (0.005)
C
B
A
VIEW A
ROTATED 90 CW
R1
R2
0.10 REF
0.10 REF
10
0.004 REF
0.004 REF
10
SECTION A–A
0
0
44 PLACES
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