MCM36400ASHG60 [MOTOROLA]
Fast Page DRAM Module, 4MX36, 60ns, CMOS, SIMM-72;
| 型号： | MCM36400ASHG60 |
| 厂家： | 
MOTOROLA |
| 描述： | Fast Page DRAM Module, 4MX36, 60ns, CMOS, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM36400/D
SEMICONDUCTOR
TECHNICAL DATA
MCM36400
4M x 36 Bit Dynamic Random
Access Memory Module
The MCM36400 is a dynamic random access memory (DRAM) module organized
as 4,194,304 x 36 bits. The module is a 72–lead single–in–line memory module
(SIMM) consisting of eight MCM517400B DRAMs, housed in 300 mil J–lead small
outline packages (SOJ), and four MCM54100AN DRAMs housed in 300 mil J–lead
small outline packages (SOJ), mounted on a substrate along with a 0.22 µF (min)
decoupling capacitor mounted adjacent to each DRAM. The MCM517400B is a
CMOS high–speed dynamic random access memory organized as 4,194,304 four–
bit words and fabricated with CMOS silicon–gate process technology.
AS PACKAGE
SIMM MODULE
CASE 866J–01
ASH PACKAGE
SIMM MODULE
(LOW PROFILE)
CASE 866–02
TOP VIEW
1
•
•
•
•
•
•
•
•
•
Three–State Data Output
Early–Write Common I/O Capability
Fast Page Mode Capability
TTL–Compatible Inputs and Outputs
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
2048 Cycle Refresh: 32 ms
Consists of Eight 4M x 4 DRAMs, Four 4M x 1 DRAMs, and Twelve 0.22 µF (Min)
Decoupling Capacitors
36
37
•
•
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (t
RAC
): MCM36400–60 = 60 ns (Max)
MCM36400–70 = 70 ns (Max)
•
•
•
Low Active Power Dissipation: MCM36400–60 = 7.48 W (Max)
MCM36400–70 = 6.38 W (Max)
Low Standby Power Dissipation: TTL Levels = 132 mW (Max)
CMOS Levels = 66 mW (Max)
Available in Doublesided, Low Profile Module (MCM36400ASH)
PIN ASSIGNMENTS
Pin
1
Name
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Name
A1
Pin
25
26
27
28
29
30
31
32
33
34
35
36
Name
DQ24
DQ7
DQ25
A7
Pin
37
38
39
40
41
42
43
44
45
46
47
48
Name
DQ17
DQ35
Pin
49
50
51
52
53
54
55
56
57
58
59
60
Name
DQ9
Pin
61
62
63
64
65
66
67
68
69
70
71
72
Name
DQ14
DQ33
DQ15
DQ34
DQ16
NC
V
SS
2
DQ0
DQ18
DQ1
A2
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
72
3
A3
V
SS
4
A4
CAS0
CAS2
CAS3
CAS1
RAS0
NC
5
DQ19
DQ2
A5
NC
PIN NAMES
6
A6
V
CC
A0 – A10 . . . . . . . . . . . . . Address Inputs
DQ0 – DQ35 . . . . . . . Data Input/Output
CAS0 – CAS3 Column Address Strobe
PD1 – PD4 . . . . . . . . . Presence Detect
RAS0, RAS2 . . . . . Row Address Strobe
W . . . . . . . . . . . . . . . . . Read/Write Input
7
DQ20
DQ3
A10
DQ4
DQ22
DQ5
DQ23
DQ6
A8
A9
PD1
8
PD2
9
DQ21
NC
PD3
10
11
12
V
RAS2
DQ26
DQ8
NC
PD4
CC
V
V
. . . . . . . . . . . . . . . . . . Power (+ 5 V)
. . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
NC
A0
W
V
NC
CC
NC . . . . . . . . . . . . . . . . . . No Connection
NC
DQ32
V
SS
All power supply and ground pins must be
connected for proper operation of the
device.
REV 2
10/95
Motorola, Inc. 1995
BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
I/O1
CAS
RAS
G
CAS0
RAS0
I/O2
I/O3
I/O4
W
A0 – A10
DQ4
DQ5
DQ6
DQ7
I/O1
I/O2
I/O3
I/O4
CAS
RAS
G
W
W
A0 – A10
A0 – A10
D
in
CAS
RAS
DQ8
D
out
I/O1
I/O2
I/O3
DQ9
CAS
RAS
G
CAS1
DQ10
DQ11
DQ12
W
A0 – A10 I/O4
I/O1
I/O2
I/O3
DQ13
DQ14
DQ15
DQ16
CAS
RAS
G
I/O4
W
W
A0 – A10
A0 – A10
D
in
DQ17
CAS
RAS
D
out
I/O1
I/O2
I/O3
I/O4
DQ18
DQ19
DQ20
DQ21
CAS
RAS
G
CAS2
RAS2
W
A0 – A10
I/O1
I/O2
I/O3
I/O4
DQ22
DQ23
DQ24
DQ25
CAS
RAS
G
W
W
A0 – A10
A0 – A10
D
in
DQ26
CAS
RAS
D
out
DQ27
DQ28
DQ29
DQ30
I/O1
I/O2
I/O3
I/O4
CAS
RAS
G
CAS3
W
A0 – A10
I/O1
I/O2
I/O3
I/O4
DQ31
DQ32
DQ33
DQ34
CAS
RAS
G
W
W
A0 – A10
A0 – A10
D
in
DQ35
CAS
RAS
D
out
W
A0 – A10
U0 – U11
U0 – U11
V
CC
0.22 µF (MIN)
V
SS
PRESENCE DETECT PIN OUT
Pin Name
60 ns
70 ns
PD1
PD2
PD3
PD4
V
V
SS
SS
NC
NC
NC
NC
V
SS
NC
MCM36400
2
MOTOROLA DRAM
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
visedthatnormalprecautionsbetakentoavoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
Rating
Symbol
Value
Unit
V
Power Supply Voltage
V
CC
– 1 to + 7
– 1 to + 7
Voltage Relative to V
SS
for Any Pin
V , V
in out
V
Except V
CC
Data Output Current
Power Dissipation
I
50
8.4
mA
W
out
P
D
Operating Temperature Range
Storage Temperature Range
T
0 to + 70
– 55 to + 150
°C
°C
A
T
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All voltages referenced to V
)
SS
Parameter
Symbol
Min
4.5
Typ
5.0
0
Max
5.5
0
Unit
Supply Voltage (Operating Voltage Range)
V
CC
V
V
SS
0
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
* –2.0 V at pulse width≤ 20 ns.
V
2.4
—
V
CC
+ 0.5 V
V
V
IH
V
– 0.5*
—
0.8
IL
DC CHARACTERISTICS AND SUPPLY CURRENTS (All voltages referenced to V
)
SS
Symbol
Characteristic
Min
Max
Unit
Notes
V
CC
Power Supply Current
MCM36400–60, t
MCM36400–70, t
= 110 ns
= 130 ns
I
—
—
1360
1160
mA
1, 2
RC
RC
CC1
V
V
Power Supply Current (Standby) (RAS = CAS = V
)
I
I
—
24
mA
mA
CC
IH
CC2
Power Supply Current During RAS–Only Refresh Cycles (CAS = V
IH
)
1, 2
CC
CC3
MCM36400–60, t
MCM36400–70, t
= 110 ns
= 130 ns
—
—
1360
1160
RC
RC
V
CC
V
CC
V
CC
Power Supply Current During Fast Page Mode Cycle (RAS = V
)
I
CC4(P)
—
—
720
12
mA
mA
mA
1, 2
1
IL
Power Supply Current (Standby) (RAS = CAS = V
CC
– 0.2 V)
I
CC5
CC6
Power Supply Current During CAS Before RAS Refresh Cycle
MCM36400–60, t
I
= 110 ns
= 130 ns
—
—
1360
1160
RC
RC
MCM36400–70, t
Input Leakage Current (0 V ≤ V ≤ V
in CC
)
I
– 120
– 10
2.4
120
10
µA
µA
V
lkg(I)
Output Leakage Current (0 V ≤ V ≤ V , Output Disable)
out CC
I
lkg(O)
Output High Voltage (I
= – 5 mA)
= 4.2 mA)
V
—
OH
OH
Output Low Voltage (I
NOTES:
V
—
0.4
V
OL
OL
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Address may be changed once or less while RAS = V . In the case of I
, it can be changed once or less during t .
CC4 PC
IL
MCM36400
3
MOTOROLA DRAM
CAPACITANCE (f = 1.0 MHz, T = 25°C, V
= 5 V, Periodically Sampled Rather Than 100% Tested)
CC
Characteristic
A
Symbol
Max
Unit
Input Capacitance
A0 – A10
W
RAS0, RAS2
CAS0 – CAS3
C
70
94
52
31
pF
in
I/O Capacitance
DQ0 – DQ7, DQ9 – DQ16, DQ18 – DQ25, DQ27 – DQ34
DQ8, DQ17, DQ26, DQ35
C
17
22
pF
I/O
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
Std
MCM36400–60
MCM36400–70
Parameter
Random Read or Write Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from Precharge CAS
CAS to Output in Low–Z
Output Buffer and Turn–Off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
Alt
Min
110
—
—
—
—
0
Max
—
Min
130
—
—
—
—
0
Max
—
Unit
Notes
5
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RELREL
RC
t
t
t
60
20
30
40
—
70
20
35
40
—
6, 7
6, 8
6, 9
6
RELQV
CELQV
RAC
CAC
t
t
t
AA
AVQV
t
t
t
CEHQV
CPA
t
t
6
CELQX
CLZ
t
0
20
50
—
0
20
50
—
10
CEHQZ
OFF
t
T
t
T
3
3
t
t
45
60
20
60
40
20
20
15
5
50
70
20
70
40
20
20
15
5
REHREL
RELREH
CELREH
RELCEH
RP
RAS Pulse Width
t
t
t
t
10 k
—
10 k
—
RAS
RSH
CSH
RAS Hold Time
t
t
CAS Hold Time
—
—
CAS Precharge to RAS Hold Time
CAS Pulse Width
t
t
—
—
CEHREH
RHCP
t
t
10 k
40
30
—
10 k
50
35
—
CELCEH
CAS
RCD
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
t
t
11
12
RELCEL
t
t
RELAV
RAD
CRP
t
t
CEHREL
t
t
15
0
—
10
0
—
CEHCEL
CP
Row Address Setup Time
Row Address Hold Time
NOTES:
t
t
—
—
AVREL
ASR
t
t
10
—
10
—
RELAX
RAH
(continued)
11. V (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V
.
IH IL IH IL
12. An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
13. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V and V (or between V and V ) in a monotonic manner.
IH IL IL IH
14. AC measurements t = 5.0 ns.
T
15. The specification for t
(min) is used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T
A
RC
≤ 70°C) is ensured.
16. Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at V
= 2.0 V
OH
and V
OL
= 0.8 V.
17. Assumes that t
18. Assumes that t
19. Assumes that t
≤ t
≥ t
(max).
(max).
(max).
RCD RCD
RCD RCD
≥ t
RAD RAD
10. t
(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
OFF
11. Operation within the t
(max) limit ensures that t
(max) can be met. t
(max) is specified as a reference point only; if t
RCD
RAC
RCD
RCD
RAD
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
(max) limit ensures that t
CAC
(max) is specified as a reference point only; if t
12. Operation within the t
(max) can be met. t
RAD
is greater than the specified t
RAC
(max), then access time is controlled exclusively by t
RAD
.
AA
RAD
MCM36400
MOTOROLA DRAM
4
READ AND WRITE CYCLES (Continued)
Symbol
Std
MCM36400–60
MCM36400–70
Parameter
Column Address Setup Time
Alt
Min
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
Min
0
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
t
AVCEL
CELAX
AVREH
ASC
Column Address Hold Time
t
t
15
30
0
15
35
0
CAH
Column Address to RAS Lead Time
Read Command Setup Time
t
t
RAL
RCS
RCH
RRH
t
t
WHCEL
CEHWX
REHWX
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Hold Time Referenced to CAS
Write Command Pulse Width
t
t
t
t
0
0
13
13
0
0
t
t
10
10
20
20
0
15
15
20
20
0
CELWH
WCH
t
t
WP
WLWH
WLREH
WLCEH
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Setup Time
t
t
t
RWL
CWL
t
t
t
14
14
15
DVCEL
CELDX
WLCEL
DS
DH
Data In Hold Time
t
t
15
0
15
0
Write Command Setup Time
t
t
WCS
Refresh Period
t
t
—
5
—
5
RVRV
RFSH
CAS Setup Time for CAS Before RAS Refresh
CAS Hold Time for CAS Before RAS Refresh
RAS Precharge to CAS Active Time
t
t
RELCEL
RELCEH
REHCEL
CEHCEL
CSR
t
t
t
t
15
5
15
5
CHR
t
RPC
CAS Precharge Time for CAS Before RAS
Counter Time
t
30
40
CPT
Write Command Setup Time (Test Mode)
Write Command Hold Time (Test Mode)
t
t
10
10
10
—
—
—
10
10
10
—
—
—
ns
ns
ns
WLREL
RELWH
WHREL
WTS
WTH
WRP
t
t
Write to RAS Precharge Time (CAS Before RAS
Refresh)
t
t
Write to RAS Hold Time (CAS Before RAS
Refresh)
t
t
10
—
10
—
ns
RELWL
WRH
Fast Page Mode Cycle Time
t
t
45
35
—
—
45
40
—
—
ns
ns
CELCEL
PC
CAS Precharge to RAS Hold Time (Fast Page
Mode)
t
t
RHCP
CEHREH
RAS Pulse Width (Fast Page Mode)
NOTES:
t
t
60
200 k
70
200 k
ns
RELREH
RASP
13. Either t
or t
must be satisfied for a read cycle.
RCH
RRH
14. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write cycles.
15. t is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if t
≥ t (min),
WCS
WCS
WCS
the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition
is not satisfied, the condition of the data out (at access time) is indeterminate.
MCM36400
5
MOTOROLA DRAM
READ CYCLE (FAST PAGE MODE)
t
RC
V
V
IH
IL
t
RAS
CAS
RAS
t
RP
t
t
CSH
CAS
t
t
t
t
CRP
RSH
CRP
RCD
V
V
IH
IL
t
RAD
t
RAL
t
t
t
ASC
ASR
t
CAH
RAH
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
RCH
RRH
t
t
RCS
V
V
IH
IL
W
t
AA
t
t
CAC
OFF
t
RAC
t
CLZ
V
OH
DQ
HIGH–Z
VALID DATA OUT
V
OL
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
CRP
t
RCD
t
RSH
t
CRP
t
V
CAS
IH
CAS
ADDRESSES
W
V
IL
t
RAD
t
ASR
t
t
CAH
ASC
t
RAH
V
IH
ROW
COLUMN
V
IL
t
CWL
t
t
WCH
WCS
V
IH
t
WP
V
IL
t
RWL
t
t
DH
DS
V
IH
DQ
VALID DATA IN
HIGH–Z
V
IL
MCM36400
6
MOTOROLA DRAM
FAST PAGE MODE READ CYCLE
V
V
t
IH
IL
RASP
RAS
CAS
t
RHCP
t
RP
t
CRP
t
t
t
CRP
PC
t
t
RSH
RCD
CP
V
V
t
t
t
IH
IL
CAS
t
CAS
t
CAS
t
RAD
t
t
RAL
CSH
t
t
CAH
CAH
RCH
RAH
CAH
t
t
t
t
ASR
ASC
ASC
ASC
V
V
IH
IL
ADDRESSES
ROW
COLUMN
COLUMN
t
COLUMN
t
t
t
RCS
RCS
RCS
RCH
t
t
RCH
V
V
IH
IL
W
t
t
RRH
t
t
AA
AA
AA
t
t
t
CAC
CAC
CAC
t
t
t
t
OFF
OFF
RAC
OFF
t
t
t
CLZ
CLZ
CLZ
V
V
VALID
DATA OUT
VALID
DATA OUT
VALID
DATA OUT
OH
DQ
OL
FAST PAGE MODE EARLY WRITE CYCLE
t
t
RP
RASP
V
IH
IL
t
RAS
RHCP
V
t
t
t
CRP
ASR
PC
RSH
CAS
t
t
t
RCD
CP
CRP
t
t
t
CAS
t
CAS
t
V
V
IH
IL
CAS
t
t
t
RAL
CSH
t
t
CAH
CAH
RAH
CAH
t
t
t
t
ASC
ASC
ASC
V
V
IH
IL
ADDRESSES
ROW
COLUMN
COLUMN
COLUMN
t
t
t
t
CWL
RWL
t
RAD
CWL
CWL
t
t
WCS
t
WCS
WCS
t
t
t
V
V
WP
WP
WP
IH
IL
W
t
t
t
WCH
WCH
WCH
t
t
t
t
t
DH
DS
DH
DS
DH
DS
V
V
IH
IL
VALID
DATA IN
VALID
DATA IN
VALID
DATA IN
DQ
MCM36400
7
MOTOROLA DRAM
RAS–ONLY REFRESH CYCLE
(W is Don’t Care)
t
RC
t
RP
t
RAS
V
IH
IL
RAS
CAS
V
t
t
CRP
RPC
V
IH
IL
V
t
RAH
t
ASR
V
IH
ROW
V
IL
ADDRESSES
DQ
V
OH
HIGH–Z
V
OL
CAS BEFORE RAS REFRESH CYCLE
(A0 – A10 are Don’t Care)
t
RC
t
t
RAS
RP
V
IH
RAS
V
IL
t
CSR
RPC
t
t
CP
t
CHR
t
V
IH
IL
V
CAS
W
t
WRP
WRH
V
IH
V
IL
t
OFF
V
OH
DQ
HIGH–Z
V
OL
MCM36400
8
MOTOROLA DRAM
HIDDEN REFRESH CYCLE (READ) (FAST PAGE MODE)
t
t
RC
RC
t
t
RP
RP
t
t
RAS
RAS
V
V
IH
IL
RAS
CAS
t
t
t
t
CRP
t
CRP
CHR
RCD
RSH
V
V
IH
IL
t
RAD
t
t
t
ASR
ASC
t
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
WRP
t
RCS
t
t
RRH
WRH
V
V
IH
IL
W
t
AA
t
CAC
t
OFF
t
CLZ
t
RAC
V
OH
OL
VALID DATA OUT
DQ
V
HIDDEN REFRESH CYCLE (EARLY WRITE)
t
t
RC
RC
t
t
t
t
RAS
RAS
RP
RP
V
IH
RAS
CAS
V
IL
t
t
t
t
CRP
RCD
CRP
RSH
CHR
t
V
IH
t
V
IL
RAD
t
t
ASR
ASC
t
t
CAH
RAH
V
IH
ADDRESSES
ROW
t
COLUMN
V
IL
t
t
WRP
WCS
WRH
t
WCH
V
IH
t
WP
W
V
IL
t
t
DS
DH
V
IH
DQ
VALID DATA IN
V
IL
MCM36400
9
MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
V
IH
IL
t
RAS
t
RAS
CAS
RP
V
t
t
CSR
RSH
V
t
t
IH
IL
CHR
CAS
t
CPT
V
t
RAL
t
COLUMN
t
t
CAH
ASC
V
IH
IL
ADDRESSES
V
t
t
t
WRH
AA
READ CYCLE
WRP
RRH
V
IH
W
V
IL
t
t
t
RCS
CAC
RCH
t
t
CLZ
OFF
V
OH
DQ
HIGH–Z
VALID DATA OUT
V
OL
t
RWL
WRITE CYCLE
t
t
t
CWL
WRP
WRH
t
WCS
V
IH
t
WCH
W
V
IL
t
t
DS
DH
V
IH
IL
DQ
HIGH–Z
VALID DATA IN
V
MCM36400
10
MOTOROLA DRAM
DEVICE INITIALIZATION
(V ). Minimum active time t
IL
and t
, and precharge
CAS
RAS
time t , apply to write mode, as in the read mode.
RP
On power–up, an initial pause of 200 microseconds is
required for the internal substrate generator to establish the
correct bias voltage. This must be followed by a minimum of
eight active cycles of the row address strobe (clock) to
initialize all dynamic nodes within the RAM. During an
extended inactive state (greater than 16 milliseconds), a
wakeup sequence of eight active cycles is necessary to
ensure proper operation.
An early write cycle is characterized by W active transition
at minimum time t
before CAS active transition. Column
WCS
address setup and hold times (t
, t
) and data in (D)
ASC CAH
setup and hold times (t , t ) are referenced to CAS in
DS DH
an early write cycle. RAS and CAS clocks must stay active
for t
and t
, respectively, after the start of the
RWL
CWL
early write operation to complete the cycle.
Q remainsinthree–stateconditionthroughoutanearlywrite
cycle because W active transition precedes or coincides with
CAS active transition, keeping data–out buffers disabled.
ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
atthe beginning of a memory cycle by two clocks, row address
strobe (RAS ) and column address strobe (CAS), into two sep-
arate 11–bit address fields. A total of twenty two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 word locations in the device. RAS active transition
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
column locations (2048 columns) on a selected row of the
module family. Read access time in page mode (t
) is typi-
CAC
.Pagemode
callyhalftheregularRASclockaccesstime,t
is followed by CAS active transition (active = V , t
mini-
RAC
operation consists of keeping RAS active while toggling CAS
between V and V . The row is latched by RAS active transi-
IL RCD
mum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external ad-
dresses into the RAM.
IH
IL
tion,whileeachCASactivetransitionallowsselectionofanew
column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing require-
ments for the first cycle are met, CAS transitions to inactive for
The external CAS signal is ignored until an internal RAS
signalis available. This gate feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
minimum t , while RAS remains low (V ). The second CAS
time(t
)specificationismet(anddefinest minimum).
CP IL
RAH
RCD
active transition while RAS is low initiates the first page mode
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
cycle (t ). Either a read or write operation can be performed
PC
ina page mode cycle, subject to the same conditions as in nor-
mal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and per-
formed in any order. The maximum number of consecutive
There are three other variations in addressing the module
family per device: RAS–only refresh cycle, CAS before RAS
refresh cycle, and page mode. All are discussed in separate
sections that follow.
pagemodecyclesislimitedbyt
ended when RAS transitions to inactive, coincident with or fol-
lowing CAS inactive transition.
.Pagemodeoperationis
RASP
READ CYCLE
The DRAM may be read with two different cycles: “normal”
randomreadcycleandfastpagemodereadcycle. Thenormal
read cycle is outlined here, while the fast page mode cycles
are discussed in separate sections.
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Each bit must be periodi-
cally refreshed (recharged) to maintain the correct bit state.
Bits in the module require refresh every 32 milliseconds.
This is accomplished by cycling through the 2048 row ad-
dresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is ad-
dressed. Distributed refresh implies a row refresh every
15.6 microseconds for the module family. Burst refresh, a re-
fresh of all rows consecutively, must be performed every 32
milliseconds.
(V ), t
to enable read mode.
(minimum) before the CAS or active transition,
IH RCS
Both the RAS and CAS clocks trigger a sequence of events
that are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read
access time of the device is independent of the address multi-
plex window.
A normal read or write operation to the RAM will refresh all
thebits associated with the particular row decoded. Three oth-
er methods of refresh, RAS–only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.
CAS controls read access time: CAS must be active before
or at t
maximum to guarantee valid data out (Q) at
RCD
. If the t
t
maximum is exceeded, read access time
RAC
RCD
is determined by the CAS clock active transition (t
).
CAC
WRITE CYCLE
RAS–Only Refresh
Theuser can write to the DRAM with any of two cycles: early
write or fast page mode early write. Early write mode is dis-
cussed here, while fast page mode write operation is covered
in a separate section.
RAS–onlyrefreshconsistsof RAStransitiontoactive, latch-
ing the row address to be refreshed, while CAS remains high
(V ) throughout the cycle. An external counter should be
IH
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
employed to ensure that all rows are refreshed within the
specified limit.
MCM36400
11
MOTOROLA DRAM
CAS Before RAS Refresh
During this test, the internal refresh counter generates the row
address, while the external address input supplies the column
address. The entire array is refreshed after 2048 test cycles,
as indicated by the check data written in each row. See CAS
before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counterthatgeneratestherowaddresstoberefreshed. Exter-
nal address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was in
during the previous cycle (hidden refresh). W must be inactive
fortimet
beforeandtimet afterRASactivetransition
WRP
WRH
to prevent switching the device into a test mode cycle.
1. Write 0s into all memory cells (normal write mode).
2. Select a column address, and read 0 out of the cell by
performing CAS before RAS refresh counter test,
read cycle. Repeat this operation 2048 times.
3. Select a column address, and write 1 into the cell by per-
forming CAS before RAS refresh counter test, write
cycle. Repeat this operation 2048 times.
4. Read 1s (normal read mode), which were written at step
three.
5. Using the same starting column address as in step two,
read 1 out and write 0 into the cell by performing the CAS
before RAS refresh counter test, read and write
cycles. Repeat this operation 2048 times.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while main-
taining valid data at the output pin. Holding CAS active at the
end of a read or write cycle while RAS cycles inactive for t
and back to active starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). W is subject to the same conditions
with respect to RAS active transition (to prevent test mode
entry) as in CAS before RAS refresh.
RP
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested
with a CAS before RAS refresh counter test. This refresh
counter test is performed with read and write operations.
6. Read 0s which were written in step five in normal read
mode.
7. Repeat steps one through six using complement data.
CAS BEFORE RAS
REFRESH CYCLE
CAS BEFORE RAS
REFRESH CYCLE
MEMORY CYCLE
RAS
CAS
VALID DATA OUT
DQ
HIGH–Z
Figure 1. Hidden Refresh Cycle
ORDERING INFORMATION
(Order by Full Part Number)
MCM 36400
X
XX
Motorola Memory Prefix
Part Number
Speed (60 = 60 ns, 70 = 70 ns)
Package (AS = SIMM, ASG = Gold Pad SIMM, ASH = Low
Profile SIMM, ASHG = Low Profile Gold Pad SIMM))
Full Part Numbers — MCM36400AS60
MCM36400AS70
MCM36400ASG60
MCM36400ASG70
MCM36400ASH60 MCM36400ASHG60
MCM36400ASH70 MCM36400ASHG70
MCM36400
12
MOTOROLA DRAM
PACKAGE DIMENSIONS
AS PACKAGE
SIMM MODULE
CASE 866J–01
A
M
S
0.006 (0.15)
T Y X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C
NOTE 5
U
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALIZATION.
4. DIMENSION C AND S DEFINE A DOUBLE–SIDED
MODULE.
COMPONENT
AREA
B
5. DIMENSION V DEFINES OPTIONAL SINGLE–
SIDED MODULE.
R Y
S
NOTE 4
1
INCHES
MIN MAX
4.255 107.82 108.08
MILLIMETERS
MIN MAX
36
37
72
DIM
A
B
C
D
F
G
H
J
4.245
1.345
–––
–Y–
–X–
1.355
0.360
0.042
34.16
–––
1.02
34.42
9.14
1.07
P
J
2X
N
F
2X
2X (L)
0.040
V
VIEW AA
0.125 BSC
0.050 BSC
3.18 BSC
1.27 BSC
NOTE 5
–––
0.047
0.100
0.010
0.053
–––
–––
1.19
2.54
0.25
1.35
–––
0.003 (0.08)
2X W
K
L
2X W
–T–
1.750 REF
44.45 REF
2X
Q
M
N
P
Q
R
S
0.075
0.400 BSC
0.085
1.90
10.16 BSC
2.16
M
L
0.006 (0.15)
T Y X
0.125
0.123
0.245
0.225
0.060
–––
0.127
0.255
–––
3.18
3.12
6.22
5.72
1.52
–––
3.23
6.48
–––
72X D
R
T
0.064
1.63
L
S
0.004 (0.10)
T Y X
U
V
W
Y
3.984 BSC
101.19 BSC
–––
0.044
0.060
0.208
–––
0.064
–––
1.12
1.52
5.28
–––
1.63
72X K
M
R T
VIEW AA
72X H
70X
G
MCM36400
13
MOTOROLA DRAM
ASH PACKAGE
SIMM MODULE (LOW PROFILE)
CASE 866–02
A
M
S
0.006 (0.15)
T Y X
U
C
NOTE 4
COMPONENT AREA
S
B
R Y
NOTE 4
P
NOTES:
1
36 37
72
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
N
2X
2. CONTROLLING DIMENSION:INCH
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALIZATION.
4. DIMENSIONS C AND S DEFINE A DOUBLE–SIDED
MODULE.
–Y–
VIEW AA
–X–
J
V
5. DIMENSION V DEFINES OPTIONAL
SINGLE–SIDED MODULE.
2X L
F
2X
NOTE 5
–T–
0.003 (0.08)
INCHES
MIN MAX
4.255 107.82 108.08
MILLIMETERS
MIN MAX
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
4.245
0.995
–––
2X W
1.005
0.360
0.042
25.27
–––
1.02
25.53
9.14
1.07
2X
Q
0.040
2X W
R
0.125 BSC
0.050 BSC
3.18 BSC
1.27 BSC
M
L
0.006 (0.15)
T
Y X
–––
0.047
0.100
0.010
0.053
–––
–––
1.19
2.54
0.25
1.35
–––
72X D
0.004 (0.10)
1.750 REF
44.45 REF
L
S
T
Y X
0.075
0.085
1.91
2.16
0.400 BSC
10.16 BSC
0.125
0.123
0.245
0.225
0.060
–––
0.127
0.255
–––
3.18
3.12
6.22
5.72
1.52
–––
3.23
6.48
–––
Q
R
S
72X K
72X H
R T
M
T
0.064
1.63
U
V
W
Y
3.984 BSC
101.19 BSC
VIEW AA
–––
0.044
0.060
0.208
–––
0.064
–––
1.12
1.52
5.28
–––
1.63
G
70X
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