MCM40400SH50 [MOTOROLA]
Fast Page DRAM Module, 4MX40, 50ns, CMOS, SIMM-72;
| 型号： | MCM40400SH50 |
| 厂家： | 
MOTOROLA |
| 描述： | Fast Page DRAM Module, 4MX40, 50ns, CMOS, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM40400/D
SEMICONDUCTOR
TECHNICAL DATA
MCM40400
Advance Information
4M x 40 Bit Dynamic Random
Access Memory Module
for Error Correction Applications
The MCM40400 is a dynamic random access memory (DRAM) module
organized as 4,194,304 x 40 bits. The module is a single–sided 72–lead
single–in–line memory module (SIMM) consisting of ten MCM517400B DRAMs
housed in J–lead small outline packages (SOJ), mounted on a substrate along
with a 0.22 µF (min) decoupling capacitor mounted adjacent to each DRAM. The
MCM517400B is a CMOS high–speed dynamic random access memory
organized as 4,194,304 four–bit words and fabricated with CMOS silicon–gate
process technology.
TOP VIEW
1
•
•
•
•
•
•
•
•
•
•
•
Three–State Data Output
Early–Write Common I/O Capability
Fast Page Mode Capability
TTL–Compatible Inputs and Outputs
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
2048 Cycle Refresh: MCM40400 = 32 ms (Max)
Consists of Ten 4M x 4 DRAMs, and Ten 0.22 µF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (t
RAC
): MCM40400–50 = 50 ns (Max)
MCM40400–60 = 60 ns (Max)
MCM40400–70 = 70 ns (Max)
36
37
•
•
Low Active Power Dissipation: MCM40400–50 = 7.15 W (Max)
MCM40400–60 = 6.05 W (Max)
MCM40400–70 = 5.23 W (Max)
Low Standby Power Dissipation: TTL Levels = 110 mW (Max)
CMOS Levels= 55 mW (Max)
PIN ASSIGNMENTS
Pin
1
Name
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Name
A1
Pin
25
26
27
28
29
30
31
32
33
34
35
36
Name
DQ13
DQ14
DQ15
A7
Pin
37
38
39
40
41
42
43
44
45
46
47
48
Name
DQ19
DQ20
Pin
49
50
51
52
53
54
55
56
57
58
59
60
Name
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Pin
61
62
63
64
65
66
67
68
69
70
71
72
Name
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
PD1
V
SS
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A2
3
A3
V
SS
72
4
A4
CAS0
A10
NC
5
A5
DQ16
6
A6
V
CC
PIN NAMES
7
G
A8
A9
NC
A0 – A10 . . . . . . . . . . . . . . . Address Inputs
DQ0 – DQ39 . . . . . . . . . Data Input/Output
CAS0 . . . . . . . . . . Column Address Strobe
PD1 – PD5 . . . . . . . . . . . Presence Detect
RAS0 . . . . . . . . . . . . . Row Address Strobe
W . . . . . . . . . . . . . . . . . . . Read/Write Input
ECC . . . . . . . . . . . Configuration Detection
G . . . . . . . . . . . . . . . . . . . . . Output Enable
8
DQ8
DQ9
DQ10
DQ11
DQ12
RAS0
NC
PD2
9
NC
PD3
10
11
12
V
NC
DQ21
W
PD4
CC
PD5
A0
DQ17
DQ18
V
DQ39
CC
ECC
DQ32
V
SS
V
V
. . . . . . . . . . . . . . . . . . . . Power (+ 5 V)
. . . . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
NC . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connectedfor proper operation of the device.
REV 2
10/95
Motorola, Inc. 1995
BLOCK DIAGRAM
I/O1
I/O2
I/O3
DQ0
DQ1
DQ2
DQ3
CAS
RAS
G
W
W
A0 – A10 I/O4
I/O1
I/O2
DQ4
DQ5
DQ6
DQ7
CAS
RAS
G
I/O3
A0 – A10 I/O4
DQ8
DQ9
DQ10
I/O1
I/O2
CAS
RAS
G
CAS0
RAS0
I/O3
A0 – A10 I/O4
W
W
W
W
W
W
W
W
DQ11
DQ12
I/O1
I/O2
CAS
RAS
G
DQ13
DQ14
DQ15
I/O3
A0 – A10 I/O4
DQ16
I/O1
I/O2
CAS
RAS
G
DQ17
DQ18
DQ19
I/O3
A0 – A10 I/O4
DQ20
I/O1
I/O2
CAS
RAS
G
DQ21
DQ22
I/O3
A0 – A10 I/O4
DQ23
DQ24
DQ25
DQ26
DQ27
I/O1
I/O2
CAS
RAS
G
I/O3
A0 – A10 I/O4
I/O1
I/O2
DQ28
DQ29
DQ30
DQ31
CAS
RAS
G
I/O3
A0 – A10 I/O4
I/O1
I/O2
DQ32
DQ33
DQ34
DQ35
CAS
RAS
G
I/O3
A0 – A10 I/O4
DQ36
DQ37
DQ38
DQ39
I/O1
I/O2
CAS
RAS
G
I/O3
A0 – A10 I/O4
G
W
A0 – A10
V
U0 – U9
U0 – U9
CC
0.22 µF (MIN)
V
SS
PRESENCE DETECT PIN OUT
50 ns 60 ns
Pin Name
70 ns
PD1
PD2
PD3
PD4
PD5*
ECC
V
V
V
SS
NC
SS
SS
NC
NC
NC
NC
V
V
SS
NC
SS
SS
SS
SS
V
V
V
V
V
V
V
SS
SS
SS
SS
*PD5 tied to V
through a 2.6 kΩ resistor.
SS
MCM40400
2
MOTOROLA DRAM
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
visedthatnormalprecautionsbetakentoavoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
Rating
Symbol
Value
– 0.5 to + 7
– 0.5 to + 7
50
Unit
V
Power Supply Voltage
V
CC
Voltage Relative to V
Data Output Current
Power Dissipation
for Any Pin Except V
CC
V , V
in out
V
SS
I
mA
W
out
P
D
9.0
Operating Temperature Range
Storage Temperature Range
T
0 to + 70
– 55 to + 125
°C
°C
A
T
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All voltages referenced to V
)
SS
Symbol
Parameter
Min
4.5
Typ
5.0
0
Max
5.5
0
Unit
Supply Voltage (Operating Voltage Range)
V
V
CC
V
0
SS
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
* –2.0 V at pulse width≤ 20 ns.
V
2.4
—
V
+ 0.5 V
CC
0.8
V
V
IH
V
– 0.5*
—
IL
DC CHARACTERISTICS AND SUPPLY CURRENTS (All voltages referenced to V
)
SS
Symbol
Characteristic
Min
Max
Unit
Notes
V
CC
Power Supply Current
MCM40400–50, t
RC
= 90 ns
= 110 ns
= 130 ns
I
—
—
—
1300
1100
950
mA
1, 2
CC1
MCM40400–60, t
RC
RC
MCM40400–70, t
V
V
Power Supply Current (Standby) (RAS = CAS = V
)
I
I
—
20
mA
mA
CC
IH
CC2
Power Supply Current During RAS–Only Refresh Cycles (CAS = V
)
1, 2
1, 2
CC
IH
CC3
MCM40400–50, t
RC
MCM40400–60, t
MCM40400–70, t
= 90 ns
= 110 ns
= 130 ns
—
—
—
1300
1100
950
RC
RC
V
CC
Power Supply Current During Fast Page Mode Cycle (RAS = V
)
IL
I
CC4(P)
mA
MCM40400–50, t
MCM40400–60, t
MCM40400–70, t
= 35 ns
= 40 ns
= 45 ns
—
—
—
800
700
600
PC
PC
PC
V
V
Power Supply Current (Standby) (RAS = CAS = V
CC
– 0.2 V)
I
I
—
10
mA
mA
CC
CC5
Power Supply Current During CAS Before RAS Refresh Cycle
MCM40400–50, t
1
CC
CC6
= 90 ns
= 110 ns
= 130 ns
—
—
—
1300
1100
950
RC
RC
RC
MCM40400–60, t
MCM40400–70, t
Input Leakage Current (0 V ≤ V ≤ V
in CC
)
I
– 100
– 10
2.4
100
10
µA
µA
V
lkg(I)
Output Leakage Current (0 V ≤ V ≤ V , Output Disable)
out CC
I
lkg(O)
Output High Voltage (I
= – 5 mA)
= 4.2 mA)
V
—
OH
OH
Output Low Voltage (I
NOTES:
V
—
0.4
V
OL
OL
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Address may be changed once or less while RAS = V . In the case of I , it can be changed once or less during t
.
IL CC4 PC
CAPACITANCE (f = 1.0 MHz, T = 25°C, V
= 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic
A
CC
Symbol
Max
Unit
Input Capacitance
I/O Capacitance
A0 – A10
W, G, RAS0, CAS0
C
60
80
pF
in
DQ0 – DQ39
C
17
pF
I/O
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
MCM40400
3
MOTOROLA DRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol MCM40400–50
Std
MCM40400–60
MCM40400–70
Parameter
Random Read or Write Cycle Time
Read–Write Cycle Time
Access Time from RAS
Alt
Min
90
135
—
—
—
—
0
Max
—
Min
110
155
—
—
—
—
0
Max
—
Min
130
180
—
—
—
—
0
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5
t
t
t
RC
RELREL
t
—
—
—
5
RELREL
RWC
t
t
t
50
13
25
30
—
60
15
30
35
—
70
20
35
40
—
6, 7
6, 8
6, 9
6
RELQV
RAC
Access Time from CAS
t
CELQV
CAC
Access Time from Column Address
Access Time from Precharge CAS
CAS to Output in Low–Z
Output Buffer and Turn–Off Delay
Transition Time (Rise and Fall)
RAS Precharge Time
t
t
AA
AVQV
t
t
t
CPA
CEHQV
t
t
6
CELQX
CLZ
t
0
13
50
—
0
15
50
—
0
15
50
—
10
CEHQZ
OFF
t
T
t
T
3
3
3
t
t
30
50
13
50
30
13
17
12
5
40
60
15
60
35
15
20
15
5
50
70
20
70
40
20
20
15
5
REHREL
RELREH
CELREH
RELCEH
RP
RAS Pulse Width
t
t
t
t
10 k
—
10 k
—
10 k
—
RAS
RSH
CSH
RAS Hold Time
t
t
CAS Hold Time
—
—
—
CAS Precharge to RAS Hold Time
CAS Pulse Width
t
t
—
—
—
CEHREH
RHCP
t
t
10 k
37
25
—
10 k
45
30
—
10 k
50
35
—
CELCEH
CAS
RCD
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
t
t
11
12
RELCEL
t
t
RELAV
RAD
CRP
t
t
CEHREL
CEHCEL
t
t
10
0
—
10
0
—
10
0
—
CP
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address to RAS Lead Time
Read Command Setup Time
NOTES:
t
t
—
—
—
AVREL
RELAX
ASR
RAH
t
t
7
—
10
0
—
10
0
—
t
t
0
—
—
—
AVCEL
CELAX
AVREH
ASC
CAH
t
t
t
10
25
0
—
10
30
0
—
15
35
0
—
t
t
—
—
—
RAL
RCS
t
—
—
—
WHCEL
(continued)
11. V (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V
.
IH IL IH IL
12. An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
13. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V and V (or between V and V ) in a monotonic manner.
IH IL IL IH
14. AC measurements t = 5.0 ns.
T
15. The specification for t
(min) is used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T
A
RC
≤ 70°C) is ensured.
16. Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at V
= 2.0 V
OH
and V
OL
= 0.8 V.
17. Assumes that t
18. Assumes that t
19. Assumes that t
≤ t
RCD RCD
RCD RCD
≥ t
RAD RAD
(max).
(max).
(max).
≥ t
10. t
(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
OFF
11. Operation within the t
(max) limit ensures that t
(max) can be met. t
(max) is specified as a reference point only; if t
RCD
RAC
RCD
RCD
RAD
is greater than the specified t
(max) limit, then access time is controlled exclusively by t
.
RCD
(max) limit ensures that t
CAC
(max) is specified as a reference point only; if t
12. Operation within the t
(max) can be met. t
RAD
RAD
is greater than the specified t
RAC
(max), then access time is controlled exclusively by t
.
AA
RAD
MCM40400
MOTOROLA DRAM
4
READ, WRITE, AND READ–WRITE CYCLES (Continued)
Symbol
MCM40400–50
MCM40400–60
MCM40400–70
Parameter
Std
Alt
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Command Hold Time
Referenced to CAS
t
t
t
t
0
—
0
—
0
—
ns
13
CEHWX
RCH
Read Command Hold Time
Referenced to RAS
0
—
—
0
—
—
0
—
—
ns
ns
13
REHWX
RRH
Write Command Hold Time
Referenced to CAS
t
t
10
10
15
CELWH
WCH
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Setup Time
t
t
10
15
15
0
—
—
—
—
—
—
—
—
—
32
—
10
15
15
0
—
—
—
—
—
—
—
—
—
32
—
15
20
20
0
—
—
—
—
—
—
—
—
—
32
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
WLWH
WLREH
WLCEH
WP
t
t
t
RWL
CWL
t
t
t
14
14
15
15
15
15
DVCEL
CELDX
WLCEL
DS
Data In Hold Time
t
t
10
0
10
0
15
0
DH
Write Command Setup Time
CAS to Write Delay
t
t
WCS
CWD
RWD
t
t
t
35
73
48
—
5
40
85
55
—
5
45
95
60
—
5
CELWL
RELWL
RAS to Write Delay
t
Column Address to Write Delay
Refresh Period
t
t
AWD
AVWL
RVRV
t
t
RFSH
CAS Setup Time for CAS Before RAS
Refresh
t
t
RELCEL
CSR
CAS Hold Time for CAS Before RAS
Refresh
t
t
10
—
10
—
10
—
ns
RELCEH
CHR
RAS Precharge to CAS Active Time
t
t
t
5
—
—
5
—
—
5
—
—
ns
ns
REHCEL
RPC
CAS Precharge Time for CAS Before
RAS Counter Time
t
20
20
20
CEHCEL
CPT
Write Command Setup Time (Test
Mode)
t
t
10
10
10
10
—
—
—
—
10
10
10
10
—
—
—
—
10
10
10
10
—
—
—
—
ns
ns
ns
ns
WLREL
RELWH
WHREL
WTS
WTH
WRP
WRH
Write Command Hold Time (Test
Mode)
t
t
Write to RAS Precharge Time (CAS
Before RAS Refresh)
t
t
Write to RAS Hold Time (CAS Before
RAS Refresh)
t
t
RELWL
RAS Hold Time Referenced to G
G Access Time
t
t
10
—
13
0
—
13
—
13
10
—
15
0
—
15
—
15
10
—
15
0
—
15
—
15
ns
ns
ns
ns
GLREH
ROH
t
t
6
GLQV
GA
GD
G to Data Delay
t
t
GLHDX
Output Buffer Turn–Off Delay Time
from G
t
t
16
GHQZ
GZ
G Command Hold Time
Output Disable Setup Time
NOTES:
t
t
15
0
—
—
15
0
—
—
15
0
—
—
ns
ns
WLGL
GH
t
t
GHCEL
ODS
13. Either t
or t
must be satisfied for a read cycle.
RCH
RRH
14. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write or read–write cycles.
15. t , t , t , t , and t are not restrictive operating parameters. They are included in the data sheet as electrical
WCS RWD CWD AWD
CPWD
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
≥ t (min), t ≥ t (min), t ≥ t (min), and t ≥ t (min) (page
characteristics only; if t
≥ t
WCS WCS
throughout the entire cycle; if t
CWD
CWD
RWD
RWD
AWD
AWD
CPWD
CPWD
mode), the cycle is a read–write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions
is satisfied, the condition of the data out (at access time) is indeterminate.
16. t
(max) and/or t
(max) define the time at which the output achieves the open circuit condition and is not referenced to output
OFF
GZ
voltage levels.
MCM40400
5
MOTOROLA DRAM
FAST PAGE MODE READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol MCM40400–50 MCM40400–60
Std
MCM40400–70
Parameter
Alt
Min
Max
Min
Max
Min
Max
Unit
ns
Notes
Fast Page Mode Cycle Time
t
t
35
—
40
—
45
—
CELCEL
PC
CAS Precharge to RAS Hold Time
(Fast Page Mode)
t
t
ns
CEHREH
RHCP
30
—
35
—
40
—
Fast Page Mode Read–Write Cycle
Time
t
t
ns
CELCEL
PRWC
80
50
53
—
200 k
—
85
60
60
—
200 k
—
95
70
65
—
200 k
—
RAS Pulse Width (Fast Page Mode)
CAS Precharge to Write Delay
NOTES:
t
t
ns
ns
RELREH
RASP
t
t
5
CEHWL
CPWD
1. V (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V
.
IH IL IH IL
2. An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V and V (or between V and V ) in a monotonic manner.
IH IL IL IH
4. AC measurements t = 5.0 ns.
T
5. t
, t
, t
, t
WCS WCS
through–out the entire cycle; if t
, and t
≥ t
are not restrictive operating parameters. They are included in the data sheet as electrical
WCS RWD CWD AWD
CPWD
(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
≥ t (min), t ≥ t (min), t ≥ t (min), and t ≥ t (min) (page
characteristics only; if t
CWD
CWD
RWD
RWD
AWD
AWD
CPWD
CPWD
mode), the cycle is a read–write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions
is satisfied, the condition of the data out (at access time) is indeterminate.
MCM40400
MOTOROLA DRAM
6
READ CYCLE (FAST PAGE MODE)
t
RC
V
V
IH
IL
t
RAS
CAS
RAS
t
RP
t
t
CSH
CAS
t
t
t
t
CRP
RSH
CRP
RCD
V
V
IH
IL
t
RAD
t
RAL
t
t
t
ASC
ASR
t
CAH
RAH
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
RCH
RRH
t
t
RCS
V
V
IH
IL
W
G
t
ROH
t
AA
t
GA
V
V
IH
IL
t
t
CAC
OFF
t
RAC
t
t
GZ
CLZ
V
OH
DQ
HIGH–Z
VALID DATA OUT
V
OL
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
CRP
t
RCD
t
RSH
t
CRP
t
V
CAS
IH
CAS
V
IL
t
RAD
t
ASR
t
t
CAH
ASC
t
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
CWL
t
t
WCH
WCS
V
IH
t
WP
W
G
V
IL
t
RWL
V
IH
V
IL
t
t
DH
DS
V
IH
DQ
VALID DATA IN
HIGH–Z
V
IL
MCM40400
7
MOTOROLA DRAM
G CONTROLLED LATE WRITE CYCLE
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
CRP
t
t
t
RCD
RSH
CAS
CRP
t
V
IH
CAS
V
IL
t
ASC
t
t
RAD
ASR
t
t
RAH
CAH
V
IH
ROW
COLUMN
ADDRESSES
V
IL
t
CWL
t
RWL
V
t
WP
IH
W
G
V
IL
t
GH
t
GDS
V
IH
V
IL
t
t
DS
DH
V
IH
VALID DATA IN
DQ
V
IL
READ–WRITE CYCLE
t
RWC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
t
CRP
t
CAS
V
IH
CAS
V
IL
t
ASC
t
t
ASR
RAL
t
t
CAH
RAH
V
IH
ROW
COLUMN
ADDRESSES
V
IL
t
t
AWD
CWL
t
t
RAD
t
CWD
RWL
WP
t
RWD
t
V
IH
W
G
V
IL
t
AA
t
GA
V
IH
V
IL
t
DH
t
GD
t
CAC
t
DS
t
RAC
t
GZ
V
/V
IH OH
VALID
DATA OUT
DQ
VALID DATA IN
HIGH–Z
V
/V
IL OL
t
CLZ
MCM40400
8
MOTOROLA DRAM
FAST PAGE MODE READ CYCLE
V
V
t
IH
IL
RASP
RAS
CAS
t
RHCP
t
RP
t
CRP
t
t
t
CRP
PC
t
t
RSH
RCD
CP
V
V
t
t
t
IH
IL
CAS
t
CAS
t
CAS
t
RAD
t
t
RAL
CSH
t
t
CAH
CAH
RCH
RAH
CAH
t
t
t
t
ASR
ASC
ASC
ASC
V
V
IH
IL
ADDRESSES
ROW
COLUMN
COLUMN
t
COLUMN
t
t
t
RCS
RCS
RCS
RCH
t
t
RCH
V
V
IH
IL
W
G
t
t
RRH
t
t
AA
AA
AA
t
t
t
GA
GA
GA
V
V
IH
IL
t
t
t
CAC
CAC
CAC
t
t
t
t
OFF
OFF
RAC
OFF
t
t
GZ
CLZ
GZ
CLZ
t
GZ
t
t
t
CLZ
V
V
VALID
DATA OUT
VALID
DATA OUT
VALID
DATA OUT
OH
DQ
OL
FAST PAGE MODE EARLY WRITE CYCLE
t
t
RP
RASP
V
IH
IL
t
RAS
RHCP
V
t
t
t
CRP
ASR
PC
RSH
CAS
t
t
t
RCD
CP
CRP
t
t
t
CAS
t
CAS
t
V
V
IH
IL
CAS
t
t
t
RAL
CSH
t
t
CAH
CAH
RAH
CAH
t
t
t
t
ASC
ASC
ASC
V
V
IH
IL
ADDRESSES
ROW
COLUMN
COLUMN
COLUMN
t
t
t
t
CWL
RWL
t
RAD
CWL
CWL
t
t
WCS
WCS
WCS
t
t
t
V
V
WP
WP
WP
IH
IL
W
G
t
t
t
WCH
WCH
WCH
V
V
IH
IL
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
V
V
IH
IL
VALID
DATA IN
VALID
DATA IN
VALID
DATA IN
DQ
MCM40400
9
MOTOROLA DRAM
FAST PAGE MODE READ–WRITE CYCLE
t
RASP
V
V
IH
IL
RAS
CAS
t
t
RP
t
CSH
PRWC
t
RSH
t
t
CP
t
t
CP
CRP
RCD
t
t
t
CAS
CAS
CAS
V
V
IH
IL
t
RAD
t
t
RAL
RAH
t
t
t
t
CAH
ASC
CAH
ASR
CAH
t
t
t
ASC
ASC
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
COL
t
COL
t
t
t
RWL
t
t
RWD
CWD
CWD
t
CWL
t
CPWD
CPWD
t
RCS
CWD
t
CWL
CWL
V
V
IH
IL
W
G
t
t
t
AWD
AWD
AWD
t
t
t
WP
t
WP
WP
AA
t
t
GA
t
GA
GA
V
V
IH
IL
t
t
CPA
t
t
CPA
GD
t
t
t
t
t
GD
GD
t
t
CAC
GZ
CAC
CAC
GZ
t
t
DH
t
t
AA
t
AA
DS
GZ
DS
t
RAC
t
t
t
DS
DH
DH
V
/ V
/ V
IH
OH
DQ
V
IL
OL
t
t
t
CLZ
CLZ
CLZ
VALID
DATA OUT
VALID
DATA IN
VALID
DATA OUT
VALID
DATA IN
VALID
DATA OUT
VALID
DATA IN
RAS–ONLY REFRESH CYCLE
(W and G are Don’t Care)
t
RC
t
RP
t
RAS
V
IH
RAS
CAS
V
IL
t
t
CRP
RPC
V
IH
IL
V
t
RAH
t
ASR
V
IH
ADDRESSES
DQ
ROW
V
IL
V
OH
HIGH–Z
V
OL
MCM40400
10
MOTOROLA DRAM
CAS BEFORE RAS REFRESH CYCLE
(G and A0 – A10 are Don’t Care)
t
RC
t
t
RAS
RP
V
IH
IL
RAS
V
t
CSR
RPC
t
t
CP
t
CHR
V
IH
IL
CAS
W
V
t
t
WRP
WRH
V
IH
V
IL
t
OFF
V
OH
DQ
HIGH–Z
V
OL
HIDDEN REFRESH CYCLE (READ) (FAST PAGE MODE)
t
t
RC
RC
t
t
RP
RP
t
t
RAS
RAS
V
IH
RAS
CAS
V
IL
t
t
t
t
CRP
t
CRP
CHR
RCD
RSH
V
V
IH
IL
t
RAD
t
t
t
ASR
ASC
t
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
WRP
t
RCS
t
t
RRH
WRH
V
V
IH
IL
W
G
t
AA
t
V
V
GA
IH
IL
t
CAC
t
OFF
t
CLZ
t
t
GZ
RAC
V
OH
OL
DQ
VALID DATA OUT
V
MCM40400
11
MOTOROLA DRAM
HIDDEN REFRESH CYCLE (EARLY WRITE)
t
t
RC
RC
t
t
t
t
RAS
RAS
RP
RP
V
IH
RAS
CAS
V
IL
t
t
t
t
CRP
RCD
CRP
RSH
CHR
t
V
IH
V
t
IL
RAD
t
t
ASR
ASC
t
t
CAH
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
t
t
WRP
WCS
WRH
t
WCH
V
IH
t
WP
W
G
V
IL
V
IH
V
IL
t
t
DS
DH
V
IH
DQ
VALID DATA IN
V
IL
MCM40400
12
MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
V
IH
IL
t
RAS
t
RAS
CAS
RP
V
t
RSH
t
CSR
V
t
t
IH
IL
CHR
CAS
t
CPT
V
t
RAL
t
COLUMN
t
t
CAH
ASC
V
IH
IL
ADDRESSES
V
t
t
t
WRH
AA
READ CYCLE
WRP
RRH
V
IH
t
CAC
W
t
V
t
RCS
IL
t
RCH
ROH
V
IH
IL
t
G
GA
V
t
OFF
t
GZ
t
CLZ
V
OH
DQ
WRITE CYCLE
W
HIGH–Z
VALID DATA OUT
V
OL
t
RWL
t
t
t
CWL
WRP
WRH
t
WCS
V
IH
t
WCH
V
IL
V
IH
G
V
IL
t
t
DS
DH
V
IH
IL
DQ
HIGH–Z
VALID DATA IN
V
t
t
CWL
AWD
READ–WRITE
CYCLE
t
t
t
t
t
WRP
RWL
WRH
RCS
CWD
t
WP
V
V
IH
IL
W
t
AA
V
V
IH
IL
t
GA
G
t
GD
t
DS
t
t
CAC
GZ
t
DH
t
CLZ
V
/V
IH OH
VALID
HIGH–Z
DQ
DATA IN
V
/V
IL OL
VALID
DATA OUT
MCM40400
13
MOTOROLA DRAM
DEVICE INITIALIZATION
cussed here, while fast page mode write operation is covered
in a separate section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
On power–up, an initial pause of 200 microseconds is
required for the internal substrate generator to establish the
correct bias voltage. This must be followed by a minimum of
eight active cycles of the row address strobe (clock) to
initialize all dynamic nodes within the RAM. During an
extended inactive state (greater than 32 milliseconds), a
wakeup sequence of eight active cycles is necessary to
ensure proper operation.
(V ). Early and late write modes are distinguished by the
IL
active transition of W, with respect to CAS. Minimum active
time t
and t
, and precharge time t , apply to write
RAS
CAS RP
mode, as in the read mode.
An early write cycle is characterized by W active transition
at minimum time t
before CAS active transition. Column
WCS
address setup and hold times (t
, t
) and data in (D)
ASC CAH
ADDRESSING THE RAM
setup and hold times (t , t ) are referenced to CAS in
an early write cycle. RAS and CAS clocks must stay active
DS DH
The eleven address pins on the device are time multiplexed
atthe beginning of a memory cycle by two clocks, row address
strobe (RAS ) and column address strobe (CAS), into two sep-
arate 11–bit address fields. A total of twenty two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 forty bit word locations in the device. RAS active
for t
and t
, respectively, after the start of the early
RWL
CWL
write operation to complete the cycle.
Q remainsinthree–stateconditionthroughoutanearlywrite
cycle because W active transition precedes or coincides with
CAS active transition, keeping data–out buffers disabled.
A late–write cycle (referred to as G–controlled write) occurs
when W active transition is made after CAS active transition.
W active transition could be delayed for almost 10 microsec-
transition is followed by CAS active transition (active = V ,
IL
t
minimum)forallreadorwritecycles. Thedelaybetween
RCD
RAS and CAS active transitions, referred to as the multiplex
window, gives a system designer flexibility in setting up the
external addresses into the RAM.
ondsafter CASactivetransition, (t
+ t +2t )
+ t
RCD CWD RWL T
≤ t
RAS
, if other timing minimums (t , t , and t ) are
RCD RWL
T
The external CAS signal is ignored until an internal RAS
signal is available. This ‘‘gate” feature on the external CAS
clock enables the internal CAS line as soon as the row
maintained. D timing parameters are referenced to W active
transition in a late write cycle. Output buffers are enabled by
CAS active transition. Outputs are switched off by G inactive
transition, which is required to write to the device. Q may be
indeterminate(see note 15 of AC Operating Conditions table).
address hold time (t
) specification is met (and defines
RAH
minimum). The multiplex window can be used to absorb
t
RCD
skew delays in switching the address bus from row to column
addresses and in generating the CAS clock.
RAS and CAS must remain active for t
and t
,
RWL
respectively, after W active transition to complete the write
CWL
Therearethreeothervariationsinaddressingthe16Mmod-
ule family per device: RAS–only refresh cycle, CAS before
RAS refresh cycle, and page mode. All are discussed in
separate sections that follow.
cycle. G must remain inactive for t
to complete the write cycle.
after W active transition
GH
READ–WRITE CYCLE
A read–write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussed in the WRITE CYCLE section,
READ CYCLE
The DRAM may be read with four different cycles: “normal”
random read cycle, fast page mode read cycle, read–write
cycle, and fast page mode read–write cycle. The normal read
cycle is outlined here, while the other cycles are discussed in
separate sections.
except W must remain high for t
to guarantee valid Q before writing the bit.
and/or t
minimum,
CWD
AWD
PAGE MODE CYCLES
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
Page mode allows fast successive data operations at all
column locations (2048 columns) on a selected row of the
module family. Read access time in page mode (t
) is
CAC
. Page
(V ), t
enable read mode.
(minimum) before the CAS or active transition, to
IH RCS
typically half the regular RAS clock access time, t
RAC
mode operation consists of keeping RAS active while toggling
CAS between V and V . The row is latched by RAS active
Both the RAS and CAS clocks trigger a sequence of events
that are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read
access time of the device is independent of the address multi-
plex window.
IH
IL
transition, while each CAS active transition allows selection of
a new column location on the row.
A page mode cycle is initiated by a normal read, write, or
read–write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transitions
Both CAS and output enable (G) control read access time:
CAS must be active before or at t
maximum and G
RCD
(both minimum) after RAS active
to inactive for minimum t , while RAS remains low (V ).
CP IL
must be active t
–t
RAC GA
The second CAS active transition while RAS is low initiates
the first page mode cycle (t or t ). Either a read, write,
transition to guarantee valid data out (Q) at t
. If the t
RAC
RCD
PC
PRWC
maximum is exceeded and/or G active transition does not oc-
cur in time, read access time is determined by either the CAS
or read–write operation can be performed in a page mode
cycle, subject to the same conditions as in normal operation
(previously described). These operations can be intermixed in
consecutive page mode cycles and performed in any order.
The maximum number of consecutive page mode cycles is
or G clock active transition (t
or t ).
CAC
GA
WRITE CYCLE
The user can write to the DRAM with any of four cycles:
early write, late write, fast page mode early write, and fast
page mode read–write. Early and late write modes are dis-
limited by t
. Page mode operation is ended when RAS
RASP
transitions to inactive, coincident with or following CAS
inactive transition.
MCM40400
14
MOTOROLA DRAM
REFRESH CYCLES
Hidden Refresh
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Each bit must be periodi-
cally refreshed (recharged) to maintain the correct bit state.
Bits in the module require refresh every 32 milliseconds.
This is accomplished by cycling through the 2048 row ad-
dresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is ad-
dressed. Distributed refresh implies a row refresh every
15.6 microseconds for the module family. Burst refresh, a re-
fresh of all rows consecutively, must be performed every 32
milliseconds.
Anormalread, write, orread–writeoperationtotheRAMwill
refresh all the bits associated with the particular row decoded.
Three other methods of refresh, RAS–only refresh, CAS be-
fore RAS refresh, and hidden refresh are available on this
device for greater system flexibility.
Hidden refresh allows refresh cycles to occur while main-
taining valid data at the output pin. Holding CAS active at the
end of a read or write cycle while RAS cycles inactive for t
RP
and back to active starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). W is subject to the same conditions
with respect to RAS active transition (to prevent test mode
entry) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
Theinternalrefreshcounterofthisdevicecanbetestedwith
a CAS before RAS refresh counter test. This test is per-
formed with a read–write operation. During the test, the inter-
nal refresh counter generates the row address, while the
external address supplies the column address. The entire
array is refreshed after 2048 cycles, as indicated by the check
data written in each row. See CAS before RAS refresh
counter test cycle timing diagram.
RAS–Only Refresh
The test can be performed after a minimum of eight CAS
before RAS initialization cycles. Test procedure:
RAS–onlyrefreshconsistsof RAStransitiontoactive, latch-
ing the row address to be refreshed, while CAS remains high
(V ) throughout the cycle. An external counter should be
employed to ensure that all rows are refreshed within the
specified limit.
IH
1. Write 0s into all memory cells with normal write mode.
2. Select a column address, read 0 out and write 1 into the
cell by performing the CAS before RAS refresh count-
er test, read–write cycle. Repeat this operation 2048
times.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counterthatgeneratestherowaddresstoberefreshed. Exter-
nal address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was
in during the previous cycle (hidden refresh). W must be inac-
3. Read the 1s that were written in step two in normal read
mode.
4. Using the same starting column address as in step two,
read 1 out and write 0 into the cell by performing the CAS
before RAS refresh counter test, read–write cycle.
Repeat this operation 2048 times.
tive for time t
before and time t
after RAS active
5. Read 0s which were written in step four in normal read
mode.
6. Repeat steps one through five using complement data.
WRP
WRH
transition to prevent switching the device into a test mode
cycle.
CAS BEFORE RAS
REFRESH CYCLE
CAS BEFORE RAS
REFRESH CYCLE
MEMORY CYCLE
RAS
CAS
VALID DATA OUT
DQ
HIGH–Z
Figure 1. Hidden Refresh Cycle
ORDERING INFORMATION
(Order by Full Part Number)
MCM
40400
X
XX
Motorola Memory Prefix
Part Number
Speed (50 = 50 ns, 60 = 60 ns, 70 = 70 ns)
Package (SH = SIMM, SHG = Gold Pad SIMM)
Full Part Numbers — MCM40400SH50 MCM40400SHG50
MCM40400SH60 MCM40400SHG60
MCM40400SH70 MCM40400SHG70
MCM40400
15
MOTOROLA DRAM
PACKAGE DIMENSIONS
SH PACKAGE
SIMM MODULE
CASE 866–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALIZATION.
MILLIMETERS
MIN MAX
107.82 108.08 4.245
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
MIN
MAX
4.255
1.005
0.360
0.042
25.27
—
1.02
25.53 0.995
9.14
1.07 0.040
—
3.18 BSC
1.27 BSC
0.125 BSC
0.050 BSC
—
0.25
—
0.010
0.054
—
1.19
0.25
1.37 0.047
—
0.100
44.45 REF
1.90 2.16 0.075
10.16 BSC 0.400 BSC
1.750 REF
0.085
3.18
3.12
6.22
5.72
—
0.125
3.22 0.123
6.48 0.245
—
0.127
0.255
—
Q
R
S
—
0.225
U
V
W
X
101.19 BSC
3.984 BSC
—
5.28
—
0.044
0.208
—
1.12
1.52
—
1.63 0.060
0.064
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