MCM417405CJ70 [MOTOROLA]
EDO DRAM, 4MX4, 70ns, CMOS, PDSO24;
| 型号： | MCM417405CJ70 |
| 厂家： | 
MOTOROLA |
| 描述： | EDO DRAM, 4MX4, 70ns, CMOS, PDSO24 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM417405C/D
SEMICONDUCTOR
TECHNICAL DATA
4M x 4
Advance Information
MCM417405C
16M CMOS Dynamic RAM Family
EDO
EDO, x4 2K Refresh
2048 Cycle Refresh
The family of 16M dynamic RAMs is fabricated using sub–micron CMOS
high–speed silicon–gate process technology. It includes devices organized as
4,194,304 four–bit words. Advanced circuit design and fine line processing
provide high performance, improved reliability, and low cost.
The MCM417405C is a x4 device with 2048 cycle refresh, requiring only 11
address lines.
The device is packaged in a standard 300 mil J–lead small outline package
(SOJ).
J PACKAGE
300 MIL SOJ
CASE 880A–02
•
•
•
•
•
•
•
•
Three–State Data Output
Extended Data Out (EDO) Capability
TTL–Compatible Inputs and Outputs
RAS–Only Refresh
CAS Before RAS Refresh
Hidden Refresh
PIN ASSIGNMENT
300 MIL SOJ
2048 Cycle Refresh: 32 ms
Fast Access Time (t
):
RAC
V
1
2
3
26
25
24
V
SS
CC
MCM417405C–60 = 60 ns (Max)
MCM417405C–70 = 70 ns (Max)
Low Active Power Dissipation:
MCM417405C–60 = 605 mW (Max)
MCM417405C–70 = 550 mW (Max)
Low Standby Power Dissipation: 11 mW (Max)
DQ0
DQ1
DQ3
DQ2
•
•
W
4
5
23
22
CAS
G
RAS
NC
6
21
A9
A10
A0
8
9
19
18
A8
A7
PIN NAMES
A1
A2
A3
10
11
12
13
17
16
15
14
A6
A5
A4
A0 – A10 . . . . . . . . . . . . . . Address Input CAS . . . . . . . . . Column Address Strobe
DQ0 – DQ3 . . . . . . . . Data Input/Output
G . . . . . . . . . . . . . . . . . . . Output Enable
V
CC
V
SS
. . . . . . . . . . . Power Supply (+ 5 V)
. . . . . . . . . . . . . . . . . . . . . . . . Ground
W . . . . . . . . . . . . . . . . Read/Write Enable NC . . . . . . . . . . . . . . . . . . No Connection
RAS . . . . . . . . . . . . Row Address Strobe
V
V
CC
SS
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
4/24/97
Motorola, Inc. 1997
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to these high–
impedance circuits.
Rating
Symbol
Value
Unit
V
Power Supply Voltage
V
CC
– 1 to + 7
– 1 to + 7
Voltage Relative to V
for Any Pin
V , V
in out
V
SS
Except V
CC
Data Output Current
Power Dissipation
I
50
1.0
mA
W
out
P
D
Operating Temperature Range
Storage Temperature Range
T
0 to + 70
– 55 to + 125
°C
°C
A
T
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (All Voltages Referenced to V
Parameter
)
SS
Symbol
Min
4.5
0
Typ
5.0
0
Max
5.5
0
Unit
Supply Voltage (Operating Voltage Range)
V
V
CC
V
SS
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
V
2.4
– 1.0
—
6.5
0.8
V
V
IH
V
—
IL
DC CHARACTERISTICS AND SUPPLY CURRENTS (All Voltages Referenced to V
)
SS
Characteristic
Symbol
Min
Max
Unit
Notes
V
CC
Power Supply Current
MCM417405C–60, t
MCM417405C–70, t
= 104 ns
= 124 ns
I
—
—
110
100
mA
1, 2
RC
RC
CC1
V
V
Power Supply Current (Standby) (RAS = CAS = V ) Output Open
IH
I
I
—
2
mA
mA
CC
CC2
Power Supply Current During RAS–Only Refresh Cycles (RAS = V
)
2
CC
IH
RC
RC
CC3
MCM417405C–60, t
MCM417405C–70, t
= 104 ns
= 124 ns
—
—
90
80
V
CC
Power Supply Current During EDO Page Mode Cycle (RAS = V
)
I
mA
1, 3
IL
CC4
MCM417405C–60, t
MCM417405C–70, t
= 25 ns
= 30 ns
—
—
80
70
PC
PC
V
V
Power Supply Current (Standby) (RAS = CAS = V
– 0.2 V)
I
I
—
1.0
mA
mA
CC
CC
CC5
Power Supply Current During CAS Before RAS Refresh Cycle
MCM417405C–60, t
CC
CC6
= 104 ns
= 124 ns
—
—
90
80
RC
RC
MCM417405C–70, t
Standby Current RAS = V , CAS = V , Output = Enabled
I
—
–10
–10
2.0
0
5
mA
µA
µA
V
1
IH
IL
CC7
Input Leakage Current (0 V ≤ V ≤ V
)
I
lkg(I)
10
10
in
CC
Output Leakage Current (0 V ≤ V
≤ V , Output Disable)
CC
I
lkg(O)
out
Output High Voltage (I
= – 2 mA)
V
V
OH
= 2 mA)
OH
CC
Output Low Voltage (I
NOTES:
V
0.4
V
OL
OL
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Address may be changed once or less while RAS = V
3. Address may be changed once or less while CAS = V
.
IL
.
IH
MCM417405C
2
MOTOROLA DRAM
CAPACITANCE (T = 25°, V
= 5 V, Periodically Sampled Rather Than 100% Tested)
CC
A
Characteristic
Symbol
Max
Unit
Notes
Input Capacitance
A0 – A10
C
5
7
7
pF
1
in
G, RAS, CAS, W
DQ0 – DQ3
Output Capacitance (CAS = V to Disable Output)
IH
C
pF
1, 2
I/O
NOTES:
1. Capacitance measured with a Boonton Meter or effective capacitance measuring method.
2. CAS = V to disable outputs.
IH
16M FAMILY AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, 4, and 5)
Symbol MCM417405C–60
Std
MCM417405C–70
Parameter
Random Read or Write Cycle Time
Read Modify–Write Cycle Time
Access Time From RAS
Unit
ns
Notes
Alt
Min
104
136
—
Max
—
Min
124
161
—
Max
—
t
t
t
RC
RELREL
t
—
—
ns
RELREL
RWC
t
t
60
70
ns
8, 9
RELQV
CELQV
RAC
CAC
Access Time From CAS
t
t
—
15
—
18
ns
9, 10,
17
Access Time From Column Address
t
t
—
30
—
35
ns
9, 11,
17
AVQV
AA
CAS to Output in Low–Z
Output Buffer and Turn–Off Delay
NOTES:
t
t
0
—
0
—
ns
ns
CELQX
CLZ
t
t
—
15
—
15
13
CEHQZ
OFF
(continued)
1. AC measurements assume t = 2.0 ns.
T
2. Aninitialpauseof200µsisrequiredafterpower–upfollowedbyaminimumof8RASinitalizationcycles(anycombinationofcyclescontaining
RAS–only refersh or CAS–before–RAS refresh). If the internal refresh counter is used, a minimum of 8 CAS–before–RAS refresh cycles
are required.
3. Operation within the t
(max) limit ensures that t
(max) limit, then access time is controlled exclusively by t
RCD CAC
(max) limit ensures that t
(max) can be met. t (max) is specified as a reference point only; if t
RCD
RCD
is greater than the specified t
RAC
RCD
.
4. Operation within the t
RAD
is greater than the specified t
(max) can be met. t (max) is specified as a reference point only; if t
RAC
RAD
RAD
(max) limit, then access time is controlled exclusively by t
.
RAD
AA
5. Either t
6. Either t
or t
or t
must be satisfied.
must be satisfied.
ODD
DZO
CDD
DZC
7. V (min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V (min) and
IH
IL
IL
IH
V
(max).
8. Assume that t
≤ t
(max) and t
≤ t
(max). If t
RCD
or t is greater than the maximum recommended value shown
RAD
RCD
RCD
RAD
RAD
in the table, t
exceeds the value shown.
RAC
9. Measured with a current load equivalent to 1 TTL loads and 100 pF.
10. Assume that t
11. Assume that t
≥ t
(max) and t
(max) and t
≤ t
(max).
(max).
RCD RCD
RAD RAD
≤ t
RCD RCD
≥ t
RAD RAD
12. Either t
or t
must be satisfied for a read cycle.
RRH
RCH
(max)definethetimeatwhichtheoutputachievetheopencircuitconditionandarenotreferencedtooutputvoltagelevels.
, t , t , and t are not restrictive operating parameters. They are included in the data sheet as electrical
13. t
14. t
(max)andt
OFF
GZ
, t
WCS RWD CWD AWD
CPW
≥ t (min), the cycle is an early write cycle and the data out pin will remain open circuit (high
WCS
characteristics only; if t
WCS
impedance) throughout the entire cycle; if t
≥ t
(min), t
≥ t
(min), and t
≥ t
(min), or t
≥ t (min),
CWD CWD
RWD RWD
(min), the cycle is a read–modify–write and the data output will contain data read from the selected
CWD CWD
AWD AWD
t
≥ t
(min), and t
≥ t
CPW CPW
AWD AWD
cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in delayed write or read–modify–write
cycles.
16. t
defines RAS pulse width in EDO mode cycles.
RASP
17. Access time is determined by the longer of t
or t
or t
.
ACP
AA
CAC
MCM417405C
3
MOTOROLA DRAM
ALL DEVICES, READ, WRITE, AND READ–WRITE CYCLES (continued)
Symbol MCM417405C–60
Std
MCM417405C–70
Parameter
Transition Time (Rise and Fall)
RAS Precharge Time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Notes
Alt
Min
2
Max
50
—
10 k
—
—
—
10 k
45
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
Min
2
Max
50
—
10 k
—
—
—
10 k
52
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
—
—
—
—
t
t
7
T
T
t
t
t
t
t
40
60
13
40
35
10
14
12
5
50
70
13
45
40
13
14
12
5
REHREL
RELREH
CELREH
RELCEH
RP
RAS Pulse Width
t
RAS
RSH
CSH
RAS Hold Time
t
t
CAS Hold Time
CAS Precharge to RAS Hold Time
CAS Pulse Width
t
t
RHCP
CEHREH
t
t
CELCEH
CAS
RCD
RAS to CAS Delay Time
t
t
3
4
RELCEL
RAS to Column Address Delay Time
CAS to RAS Precharge Time
CAS Precharge Time
t
t
RELAV
RAD
CRP
t
t
CEHREL
t
t
10
0
13
0
CEHCEL
CP
Row Address Setup Time
t
t
AVREL
ASR
RAH
Row Address Hold Time
t
t
10
0
10
0
RELAX
Column Address Setup Time
Column Address Hold Time
Column Address to RAS Lead Time
Column Address to CAS Lead Time
Read Command Setup Time
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Hold Time Referenced to CAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data In Setup Time
t
t
AVCEL
CELAX
AVREH
AVCEH
ASC
t
t
10
30
18
0
13
35
23
0
CAH
t
t
t
RAL
CAL
RCS
RCH
RRH
t
t
t
WHCEL
CEHWX
REHWX
t
t
t
t
0
0
12
12
5
5
t
t
10
10
10
10
0
13
10
13
13
0
CELWH
WCH
t
t
WP
WLWH
WLREH
WLCEH
t
t
t
RWL
t
CWL
t
t
15
15
14
14
14
14
DVCEL
CELDX
WLCEL
DS
Data In Hold Time
t
t
10
0
13
0
DH
Write Command Setup Time
CAS to Write Delay
t
t
WCS
t
t
34
79
49
—
5
40
92
57
—
5
CELWL
RELWL
CWD
RAS to Write Delay
t
t
RWD
Column Address to Write Delay
Refresh Period
t
t
AWD
AVWL
t
t
RFSH
RVRV
CAS Setup Time for CAS Before RAS Refresh
CAS Hold Time for CAS Before RAS Refresh
RAS Precharge to CAS Active Time
t
t
RELCEL
RELCEH
REHCEL
CEHCEL
CSR
t
t
t
t
10
5
10
5
CHR
t
RPC
CAS Precharge Time for CAS Before RAS
Counter Time
t
20
30
CPT
Write Command Setup Time (Test Mode)
Write Command Hold Time (Test Mode)
t
t
0
10
0
—
—
—
0
10
0
—
—
—
ns
ns
ns
WLREL
RELWH
WHREL
WTS
WTH
WRP
t
t
Write to RAS Precharge Time (CAS Before RAS
Refresh)
t
t
Write to RAS Hold Time (CAS Before RAS
Refresh)
t
t
10
—
—
10
—
—
ns
RELWL
WRH
G Access Time
t
t
15
18
ms
9
GLQV
GA
MCM417405C
4
MOTOROLA DRAM
ALL DEVICES, READ, WRITE, AND READ–WRITE CYCLES (continued)
Symbol MCM417405C–60
Std
MCM417405C–70
Parameter
Alt
Min
15
—
15
25
—
—
35
3
Max
—
Min
18
—
18
30
—
—
40
3
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
5
G to Data Delay
t
t
GD
GLHDX
Output Buffer Turn–Off Delay Time From G
G Command Hold Time
t
t
15
—
15
—
13
GHQZ
GZ
t
t
WLGL
GH
EDO Mode Cycle Time
t
t
—
—
19
16
CELCEL
EPC
EDO Mode RAS Pulse Width
t
t
100 k
35
—
100 k
40
—
RELREH
RASP
Access Time From CAS Precharge
RAS Hold Time From CAS Precharge
Output Data Hold Time From CAS Low
CAS Hold Time Referenced to G
CAS to G Setup Time
t
t
9, 17
CEHQV
ACP
t
t
CEHREH
RHCP
t
t
—
—
9, 17
CELQZ
GLCEH
CEHGL
DOH
t
t
t
10
5
—
13
5
—
COL
COP
t
—
—
Read Command Hold Time From CAS Precharge
EDO Mode Read–Modify–Write Cycle Time
W Delay Time From CAS Precharge
NOTES:
t
t
35
68
54
—
40
79
62
—
CEHWX
RCHP
t
t
—
—
CELCEL
ERWC
t
t
—
—
14
CEHWL
CPW
(continued)
18. In delayed write or read–modify–write cycles, G must disable output buffer prior to applying data to the device. After RAS is reset, if t
≥
OEH
t , the I/O pin will remain open circuit (high impedance); if t
CWL
≤ t , invalid data will be out at each I/O.
OEH CWL
19. The 16M DRAM offers a 16–bit time saving parallel test mode. Addesses CA0 and CA1, for the 4M x 4, are don’t care during test mode. Test
mode is set by performing a W– and CAS–before–RAS (WCBR) cycle. In 16–bit parallel test mode, data is written into 4 bits in parallel at
each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is high state during test mode
read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test
mode oepration can be performed by normal read cycles or by WCBR refresh cycles. To ge tout of test mode and enter a normal operation
mode, perform either a regular CAS–before–RAS refresh cycle or RAS–only refresh cycle.
20. In a test mode read cycle, the value of t
, t , t
, and t
is delayed by 2 ns to 5 ns for the specified value. These parameters
ACP
RAC AA CAC
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
21. t
22. t
23. t
24. t
(min) = t
(min) = t
(min) + t
(min) + t
(min) + t in read–modify–write cycle.
T
RAS
CAS
OFF
CSH
RWD
CWD
RWL
CWL
(min) + t in read–modify–write cycle.
T
and t
are determined by the later rising edge of RAS or CAS.
OFR
(min) can be achieved when t
≤ t
(min) – t (min).
RCD CSH
CAS
25. EDO High–Z control by G or W. G rising edge disables data outputs. When G goes high during CAS high, the data will not come out until
next CAS access. When W goes low during CAS high, the data will not come out until next CAS access.
26. t
(min) can be achieved during a series of EDO mode write cycles or EDO mode read cycles. If both write and read operations are mixed
+ t + 2 t ) becomes greater than the specified
CAS CP t
(min) value. The value of CAS cycle time of mixed EDO mode is shown in EDO mode mix cycles 1 and 2 (see Figures 11 and 12).
HPC
in a EDO mode RAS cycle (EDO mode mix cycles 1 or 2) minimum value of CAS cycle (t
t
HPC
MCM417405C
5
MOTOROLA DRAM
TIMING DIAGRAMS
t
RC
V
V
IH
IL
t
RAS
CAS
RAS
t
RP
t
CSH
t
t
t
t
CRP
RSH
CRP
RCD
t
V
V
CAS
t
IH
IL
t
RAD
RAL
t
CAL
t
t
ASC
ASR
t
t
CAH
RAH
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
RCH
RRH
t
t
RCS
V
V
IH
IL
W
G
t
AA
t
GA
V
V
IH
IL
t
t
CAC
OFF
t
RAC
t
GZ
t
CLZ
V
OH
DQ0 – DQ3
HIGH–Z
VALID DATA OUT
V
OL
Figure 1. Read Cycle
MCM417405C
6
MOTOROLA DRAM
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
CRP
t
CRP
t
t
RSH
RCD
t
V
CAS
IH
CAS
V
IL
t
t
RAD
ASR
t
t
CAH
ASC
t
RAH
V
IH
ADDRESSES
ROW
COLUMN
V
IL
t
CWL
t
t
WCH
WCS
V
IH
t
WP
W
G
V
IL
t
RWL
V
IH
V
IL
t
t
DH
DS
V
IH
DQ0 – DQ3
HIGH–Z
VALID DATA IN
V
IL
Figure 2. Early Write Cycle
MCM417405C
7
MOTOROLA DRAM
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
CRP
t
t
t
RCD
RSH
CAS
CRP
t
V
IH
CAS
V
IL
t
ASC
RAD
t
t
ASR
t
t
CAH
RAH
V
IH
ROW
COLUMN
ADDRESSES
V
IL
t
CWL
t
RWL
t
WP
V
IH
W
G
V
IL
t
GH
V
IH
V
IL
t
t
DH
DS
V
IH
VALID DATA IN
DQ0 – DQ3
V
IL
Figure 3. G Controlled Late Write Cycle
MCM417405C
8
MOTOROLA DRAM
t
RWC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
RSH
CRP
RCD
t
CRP
t
CAS
V
IH
CAS
V
IL
t
ASC
t
t
ASR
RAL
t
t
CAH
RAH
V
IH
ROW
COLUMN
ADDRESSES
V
IL
t
t
AWD
CWL
t
RAD
t
CWD
t
RWL
WP
t
RWD
t
V
IH
W
G
V
IL
t
AA
t
t
GA
GH
V
IH
V
IL
t
t
DH
t
GD
CAC
t
DS
t
RAC
t
GZ
VALID
DATA OUT
V
/V
IH OH
HIGH–Z
VALID DATA IN
DQ0 – DQ3
V
/V
IL OL
t
CLZ
Figure 4. Read–Write Cycle
MCM417405C
9
MOTOROLA DRAM
t
RC
t
RP
t
RAS
V
IH
IL
RAS
CAS
V
t
t
t
CRP
RPC
CRP
V
IH
IL
V
t
RAH
t
ASR
V
IH
ADDRESSES
DQ0 – DQ3
ROW
V
IL
V
OH
HIGH–Z
V
OL
Figure 5. RAS Only Refresh Cycle
(W and G are Don’t Care)
MCM417405C
10
MOTOROLA DRAM
t
RASP
t
t
RP
RHCP
V
IH
RAS
CAS
V
IL
t
t
t
HPC
RSH
T
t
CSH
t
CRP
t
t
t
t
t
t
RCD
CAS
CP
CAS
CP
CAS
V
IH
t
RAH
V
IL
t
t
t
RAL
CAL
CAL
t
RAD
t
t
t
ASC
ASC
ASC
t
t
t
CAH
CAH
CAH
t
ASR
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESSES
V
IL
t
RCH
t
RCHP
t
RCS
t
RRH
V
IH
W
t
CAL
V
IL
t
AA
t
AA
t
WZ
t
OFF
t
ACP
t
ACP
t
t
t
t
OAC
CAC
CAC
OH
V
IH
G
V
IL
t
t
t
RAC
GZ
t
AA
OFR
t
t
t
t
DOH
OHR
CAC
DOH
V
OH
DQ0 – DQ3
HIGH–Z
D
1
D
2
D
out
N
out
out
V
OL
Figure 6. EDO Read Cycle
MCM417405C
11
MOTOROLA DRAM
t
RP
t
RASP
V
IH
RAS
V
IL
t
t
t
RSH
CSH
HPC
t
CRP
t
t
t
CP
RCD
CP
t
t
t
T
t
CAS
CAS
CAS
V
IH
CAS
V
IL
t
t
t
t
ASC
ASR
ASC
ASC
t
t
t
t
CAH
RAH
CAH
CAH
V
IH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESSES
V
IL
t
t
t
WCS
WCS
WCS
t
t
t
WCH
WCH
WCH
V
IH
W
V
IL
t
t
t
DH
DH
DH
t
t
t
DS
DS
DS
V
OH
DQ0 – DQ3
D
1
D
2
D
N
in
in
in
V
OL
Figure 7. EDO Early Write Cycle
MCM417405C
12
MOTOROLA DRAM
t
RP
t
RASP
V
V
IH
RAS
CAS
t
CSH
V
IL
t
t
t
CRP
RCD
CP
t
t
t
RSH
ERWC
CAS
ERWC
t
t
t
CAS
t
CAS
IH
CAH
V
IL
t
RAD
RAH
t
t
CP
t
t
CAH
t
t
RAL
ASR
CAH
t
t
t
ASC
ASC
ASC
V
IH
COL. 1
COL. 2
COL. N
t
ADDRESSES
V
IL
t
t
CWD
CPWD
t
RWD
t
ROW
t
t
CWD
CPWD
CWD
RWL
t
t
CWL
RCS
V
IH
W
G
V
t
AWD
t
IL
t
AWD
AWD
t
t
t
t
CWL
AA
t
AA
AA
CWL
t
t
GA
t
GA
GA
t
t
t
WP
WP
WP
V
IH
V
IL
t
t
GD
GD
t
GD
t
t
CPA
CPA
t
t
DS
t
t
DS
RAC
DS
t
t
CAC
t
CAC
CAC
V
IH
D
t
1
D
2
in
D
t
N
in
in
V
IL
t
t
CLZ
t
t
t
DH
DH
DH
DQ0 –
DQ3
t
CLZ
t
GZ
CLZ
GZ
GZ
V
OH
V
OL
D
1
D
2
D
N
out
out
out
Figure 8. EDO Read–Modify–Write Cycle
MCM417405C
13
MOTOROLA DRAM
t
RASP
t
RP
V
V
t
IH
IL
CSH
RAS
CAS
t
t
t
t
CRP
t
EPC
EPC
EPC
CRP
t
t
t
t
CP
CP
CP
CP
t
RCD
t
t
t
CAS
t
CAS
t
CAS
CAS
CAS
V
V
IH
IL
t
RAD
RAH
ASR
t
t
t
ASC
t
t
ASC
t
ASC
ASC
t
CAH
t
t
t
CAH
t
CAH
CAH
t
ASC
CAH
V
V
IH
IL
ADDRESSES
COL. 1
COL. 2
COL. 3
t
COL. 4
COL. N
ROW
ROW
t
RCS
RCH
V
V
IH
IL
W
G
t
WCS
t
t
GA
WCH
V
V
t
t
t
IH
IL
CPA
CPA
CPA
t
DH
t
t
t
t
t
CAC
CAC
CAC
CAC
t
t
t
t
DS
t
AA
AA
AA
AA
V
t
t
IH
CLZ
RAC
D
4
in
V
IL
DQ0 –
DQ3
t
t
COH
WED
t
COH
REZ
t
CLZ
t
WEZ
V
OH
D
1
D
2
D
out
3
D
N
out
out
out
V
OL
Figure 9. EDO Mix Cycle
MCM417405C
14
MOTOROLA DRAM
t
RC
t
t
RP
RAS
V
IH
IL
RAS
V
t
CSR
RPC
t
t
CRP
t
CP
t
CHR
t
V
IH
IL
CAS
W
V
t
WRP
WRH
V
IH
V
IL
t
OFF
V
OH
DQ0 – DQ3
HIGH–Z
V
OL
Figure 10. CAS Before RAS Refresh Cycle
(G and A0 – A10 are Don’t Care)
t
t
RC
RC
t
t
RP
RP
t
t
RAS
RAS
V
IH
RAS
CAS
V
IL
t
t
t
t
CRP
t
CRP
CHR
RCD
RSH
V
V
IH
IL
t
RAD
t
t
t
ASR
ASC
t
CAH
RAH
V
V
IH
IL
ADDRESSES
ROW
COLUMN
t
WRP
t
RCS
t
t
RRH
WRH
V
V
IH
IL
W
G
t
AA
t
V
V
GA
IH
IL
t
CAC
t
OFF
t
CLZ
t
t
GZ
RAC
V
OH
OL
DQ0 – DQ3
VALID DATA OUT
V
Figure 11. Hidden Refresh Cycle
MCM417405C
15
MOTOROLA DRAM
TEST MODE TIMING DIAGRAMS
SET CYCLE
TEST MODE CYCLE
RESET CYCLE
NORMAL CYCLE
RAS
CAS
W
Figure 12. Test Mode Cycle
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
t
CHR
RPC
t
t
CSR
CP
V
V
IH
IL
CAS
W
t
WTH
t
WTS
V
V
IH
IL
t
OFF
V
V
OH
OL
HIGH–Z
DQ0 – DQ3
Figure 13. CAS Before RAS Refresh Cycle (Test Mode Entry)
(G and A0 – A10 are Don’t Care)
NOTE: Once the device is put into Test Mode with the Test Mode Entry Cycle, any of the standard cycles (Read or Write) may be used to test the
part, providing that the timing parameters are modified as described in the Test Mode AC Operating Conditions and Characteristics table.
The timing diagrams previously presented are valid for all cycles performed in Test Mode.
MCM417405C
16
MOTOROLA DRAM
t
RC
t
t
t
RP
RAS
RP
V
V
IH
IL
RAS
t
t
RPC
RPC
t
CHR
t
CRP
t
CSR
t
CP
V
V
IH
IL
CAS
W
t
CP
V
V
IH
IL
t
t
WRH
WRP
t
OFF
V
V
OH
OL
HIGH–Z
DQ0 – DQ3
Figure 14. CAS Before RAS Refresh Cycle (Test Mode Exit)
(G and A0 – A10 are Don’t Care)
MODE DEPENDENT ON CAS AND W WHEN RAS FALLS
Mode
CAS
W*
1
CBR Refresh, Test Mode Exit
Test Mode Entry
0
0
0
*Logic state when RAS transitions low.
MCM417405C
17
MOTOROLA DRAM
t
RC
V
IH
IL
t
RAS
t
RAS
CAS
RP
V
t
RSH
t
CAS
t
CSR
V
t
IH
IL
CHR
t
CPT
V
t
RAL
t
t
CAH
ASC
V
IH
IL
ADDRESSES
COLUMN
V
t
CAL
t
t
t
t
WRH
AA
READ CYCLE
WRP
RRH
V
V
IH
t
CAC
W
t
V
t
RCS
IL
RCH
IH
IL
t
G
GA
V
t
t
OFF
RAC
t
GZ
t
CLZ
V
OH
HIGH–Z
DQ0 – DQ3
VALID DATA OUT
V
OL
t
RWL
WRITE CYCLE
t
t
t
CWL
WRP
WRH
t
WCS
V
IH
IL
t
WCH
W
G
V
V
IH
V
IL
t
t
DS
DH
V
IH
IL
DQ0 – DQ3
HIGH–Z
VALID DATA IN
V
Figure 15. CAS Before RAS Refresh Counter Test Cycle
MCM417405C
18
MOTOROLA DRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 417405C
X
XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel, Blank = Rails for SOJ)
Speed (60 = 60 ns, 70 = 70 ns)
Package (J = 300 mil SOJ)
Full Part Numbers — MCM417405CJ60 MCM417405CJ60R
MCM417405CJ70 MCM417405CJ70R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
MCM417405C
19
MOTOROLA DRAM
PACKAGE DIMENSIONS
J PACKAGE
300 MIL SOJ
CASE 880A–02
C
E
26
21
19
14
B
P
–Y–
1
6
8
13
24X RADIUS S
12X R
M
S
S
0.007 (0.18)
T
Y
Z
M
S
S
0.007 (0.18)
T
Y
Z
A
–Z–
NOTE 3
C
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE –T–.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.006 (0.150) PER SIDE.
0.004 (0.100)
SEATING
PLANE
–T–
20 X G
4X L
5. DIMENSIONS A AND B INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT THE
PARTING LINE.
DETAIL AA
6. DIMENSION F DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE F DIMENSION TO EXCEED 0.037
(0.94).
7. FOR LEAD IDENTIFICATION PURPOSES, PIN
POSITIONS 7 AND 20 ARE NOT USED.
24X F
0.007 (0.18)
M
S
S
T
Y
Z
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
0.680
0.305
0.148
0.020
0.116
0.032
MIN
17.01
7.50
3.26
0.38
2.62
0.66
1.270 BSC
0.80
1.270 BSC
MAX
17.28
7.74
3.75
0.51
0.670
0.295
0.128
0.015
0.103
0.026
0.050 BSC
0.031
0.050 BSC
0.035
0.328
0.260
0.030
24X N
2.95
0.481
24X D
0.007 (0.18)
F
G
K
L
N
P
M
S
S
T
Y
Z
0.045
1.14
NOTE 3
0.045
0.340
0.275
0.040
0.89
8.35
6.61
0.77
1.14
DETAIL AA
8.63
6.99
1.01
R
S
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