MCM56824AZP35 [MOTOROLA]
8K x 24 Bit Fast Static RAM; 8K ×24位高速静态RAM
| 型号： | MCM56824AZP35 |
| 厂家： | 
MOTOROLA |
| 描述： | 8K x 24 Bit Fast Static RAM |
| 文件： | 总10页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM56824A/D
SEMICONDUCTOR TECHNICAL DATA
MCM56824A
DSPRAM
8K x 24 Bit Fast Static RAM
The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple
chipenableinputs, outputenable, andanexternallycontrolledsingleaddresspin
multiplexer. These functions allow for direct connection to the Motorola
DSP56001 Digital Signal Processor and provide a very efficient means for imple-
mentation of a reduced parts count system requiring noadditionalinterfacelogic.
The availability of multiple chip enable (E1 and E2) and output enable (G) in-
puts provides for greater system flexibility when multiple devices are used. With
either chip enable input unasserted, the device will enter standby mode, useful
inlow–powerapplications. Asingleon–chipmultiplexerselectsA12orX/Yasthe
highest order address input depending upon the state of the V/S control input.
This feature allows one physical static RAM component to efficiently store pro-
gram and vector or scalar operands by dynamically re–partitioning the RAM
array. Typical applications will logically map vector operands into upper memory
with scalar operands being stored in lower memory. By connecting
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control
pin, such partitioning can occur with no additional components. This al-
lows efficient utilization of the RAM resource irrespective of operand
FN PACKAGE
52–LEAD PLCC
CASE 778–02
9 x 10 GRID
86 BUMP PBGA
CASE 896A–01
PIN ASSIGNMENTS
PLCC
7
6
5
4
3
2
1
52 51 50 49 48 47
46
DQ0
8
9
DQ23
DQ22
DQ21
type. See application diagrams at the end of this document for addition-
al information.
Multiplepowerandgroundpinshavebeenutilizedtominimizeeffects
induced by output noise.
The MCM56824A is available in a 52 pin plastic leaded chip–carrier
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.
45
44
43
42
DQ1
DQ2
10
11
12
13
14
15
16
17
18
19
20
V
V
DQ20
SS
SS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
41
40
39
38
37
36
35
34
DQ19
DQ18
DQ17
DQ16
DQ15
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fast Access and Cycle Times: 20/25/35 ns Max
Fully Static Read and Write Operations
Equal Address and Chip Enable Access Times
Single Bit On–Chip Address Multiplexer
Active High and Active Low Chip Enable Inputs
Output Enable Controlled Three State Outputs
High Board Density PLCC Package
Low Power Standby Mode
V
DQ9
V
SS
SS
DQ14
DQ13
DQ10
21 22 23 24 25 26 27 28 29 30 31 32 33
VIEW OF PBGA PACKAGE BOTTOM
Fully TTL Compatible
10
9
8
7
6
5
4
3
2
1
PIN NAMES
A
B
C
D
E
D13
V
D16 D17 D18 D20 D21 D23
SS
A0 – A11 . . . . . . . . . . . . . . . Address Inputs
A12, X/Y . . . . . . . . . . Multiplexed Address
V/S . . . . . . . . . Address Multiplexer Control
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ23 . . . . . . . . . . Data Input/Output
. . . . . . . . . . . . . . . +5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
W
D12 D14 D15
E2
D19
V
D22 A5
A3
A4
SS
A2
A0
E1
SS
V
V
SS
A1
V
V
CC
CC
V
CC
V
SS
F
G
A6
A8
V/S NC
G
A7
A9
X/Y
A12
For proper operation of the device, all V
SS
pins must be connected to ground.
H
J
D11
D9
D8
D7
D4
D5
V
D1 A10 A11
SS
D10
V
D6
D3
D2
D0
SS
DSPRAM is a trademark of Motorola, Inc.
Not to Scale
REV 2
4/95
Motorola, Inc. 1995
BLOCK DIAGRAM
V/S
A12
X/Y
1
0
Q
A12
V
V
CC
2 TO 1 MUX
A0
•
•
•
SS
MEMORY ARRAY
ROW
DECODER
•
•
•
A5
512 ROWS x
384 COLUMNS
A10
A11
• • •
DQ0
INPUT
DATA
CONTROL
•
•
•
•
•
•
•
•
COLUMN I/O
•
DQ23
E1
E2
COLUMN DECODER
• • •
W
G
A9
A6
(LSB)
(MSB)
TRUTH TABLE
Supply
Current
I/O
Status
High–Z
High–Z
High–Z
Data Out
Data Out
Data In
Data In
E1
H
X
L
E2
X
G
X
X
H
L
W
X
X
H
H
H
L
V/S
X
Mode
Not Selected
Not Selected
I
I
SB
SB
CC
CC
CC
CC
CC
L
X
H
H
H
H
H
X
Output Disable
Read Using X/Y
Read Using A12
Write Using X/Y
Write Using A12
I
I
I
I
I
L
H
L
L
L
L
X
X
H
L
L
L
NOTE: X=don’t care.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect
against damage due to high static voltages
or electric fields; however, it is advised that
normalprecautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high–impedance
circuit.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equi-
librium has been established. The circuit is
assumed to be in a test socket or mounted
on a printed circuit board with at least 300
LFPM of transverse air flow being
maintained.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
– 0.5 to + 7.0
V
CC
V , V
for Any Pin
– 0.5 to V
CC
+ 0.5
V
SS
in out
Except V
CC
Output Current (per I/O)
Power Dissipation
I
± 20
mA
W
out
P
D
1.75
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to + 70
°C
°C
°C
T
A
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM56824A
2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to V
= 0 V)
Symbol
SS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Min
4.5
Typ
5.0
—
Max
Unit
V
V
CC
5.5
V
+ 0.3
V
IH
2.2
V
CC
Input Low Voltage
V
IL
– 0.5*
—
0.8
V
*V (min) = – 3.0 V ac (pulse width ≤ 20 ns)
IL
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, V = 0 to V
Symbol
Min
Max
± 1.0
± 1.0
Unit
µA
)
I
lkg(i)
—
—
in
CC
Output Leakage Current (G = V , E1 = V , E2 = V , V
= 0 to V
)
I
lkg(O)
µA
IH IH IL out
CC
AC Supply Current (G = V , E1 = V , E2 = V , I
All Other Inputs ≥ V = 0.0 V and V ≥ 3.0 V)
IL IH
= 0 mA,
I
mA
IH IL IH out
CCA
—
—
—
260
220
180
MCM56824A–20 Cycle Time: ≥ 20 ns
MCM56824A–25 Cycle Time: ≥ 25 ns
MCM56824A–35 Cycle Time: ≥ 35 ns
Standby Current (E1 = V , E2 = V , All Inputs = V or V
)
I
—
—
15
10
0.4
—
mA
mA
V
IH
IL
IL
IH
SB1
CMOS Standby Current (E1 ≥ V
– 0.2 V, E2 ≤ 0.2 V, All Inputs ≥ V
– 0.2 V or ≤ 0.2 V)
CC
I
CC
SB2
Output Low Voltage (I
= + 8.0 mA)
V
—
OL
OL
Output High Voltage (I
= – 4.0 mA)
V
2.4
V
OH
OH
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
4
Max
6
Unit
pF
Input Capacitance
All Pins Except DQ0 – DQ23
DQ0 – DQ23
C
in
Input/Output Capacitance
C
6
8
pF
out
+ 5 V
480
Ω
R
= 50 Ω
L
OUTPUT
255
OUTPUT
Ω
5 pF
Z
= 50 Ω
0
V
= 1.5 V
L
(a)
(b)
Figure 1. AC Test Loads
MCM56824A
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Read Cycle Time
Symbol
Min
20
—
Max
—
Min
25
—
Max
—
Min
35
—
Max
—
Unit
ns
Notes
t
AVAV
Address Access Time
t
20
25
35
ns
AVQV
MUX Control Valid to Output Valid
Chip Enable to Output Valid
t
t
—
20
—
25
—
35
ns
VSVQV
t
—
20
—
25
—
35
ns
4
E1LQV
E2HQV
Output Enable to Output Valid
Output Active from Chip Enable
t
—
2
8
—
2
10
—
—
0
15
—
ns
ns
GLQV
t
—
4, 5
5
E1LQX
E2HQX
t
Output Active from Output Enable
Output Hold from Address Change
Output Hold from MUX Control Change
Chip Enable to Output High–Z
t
0
4
4
0
—
—
—
10
0
5
5
0
—
—
—
15
0
5
5
0
—
—
—
15
ns
ns
ns
ns
GLQX
AXQX
t
t
VSXQX
t
t
4, 5
5
E1HQZ
E2LQZ
Output Enable High to Output High–Z
t
0
8
0
15
0
15
ns
GHQZ
NOTES:
1. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, t
max is less than t
min, t
max is less than t
min, and t
max is less than
GHQZ
E1HQZ
E1LQX
E2LQZ
E2HQX
t
min for a given device and from device to device.
GLQX
READ CYCLE
t
AVAV
A (ADDRESS)
t
t
AXQX
AVQV
V/S (MUX CONTROL)
E1 (CHIP ENABLE)
t
t
VSXQX
VSVQV
t
t
E1LQV
E1HQZ
t
GLQV
G (OUTPUT ENABLE)
Q (DATA OUT)
t
t
GLQX
GHQZ
HIGH–Z
HIGH–Z
DATA VALID
t
E1LQX
MCM56824A
4
MOTOROLA FAST SRAM
WRITE CYCLE TIMING (Write Enable Initiated, See Note 1)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Write Cycle Time
Symbol
Min
20
0
Max
—
Min
25
0
Max
—
Min
35
0
Max
—
Unit
ns
Notes
t
AVAV
Address Setup Time
t
—
—
—
ns
2
AVWL
MUX Control Setup Time
Address Valid to End of Write
MUX Control Valid to End of Write
Write Pulse Width
t
0
—
0
—
0
—
ns
VSVWL
t
15
15
15
15
—
20
20
15
15
—
30
30
20
20
—
ns
AVWH
t
—
—
—
ns
VSVWH
t
—
—
—
ns
3
WLWH
Write Enable to Chip Enable Disable
t
t
—
—
—
ns
3, 4
WLE1H
WLE2L
Chip Enable to End of Write
t
15
—
15
—
20
—
ns
3, 4
E1LWH
t
E2HWH
Data Valid to End of Write
Data Hold Time
t
8
0
0
0
4
0
—
—
—
—
—
15
10
0
—
—
—
—
—
15
15
0
—
—
—
—
—
15
ns
ns
ns
ns
ns
ns
DVWH
WHDX
t
5
2
Write Recovery Time
t
0
0
WHAX
MUX Control Recovery Time
Write High to Output Low–Z
t
0
0
WHVSX
t
5
5
6
6
WHQX
Write Low to Output High–Z
NOTES:
t
0
0
WLQZ
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. Write must be high for all address transitions.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, t
max is less than t
min, t
max is less than t
min, and t max is less than
E1HQZ
E1LQX
E2LQZ
E2HQX
GHQZ
t
min for a given device and from device to device.
GLQX
WE INITIATED WRITE CYCLE
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
V/S (MUX CONTROL)
t
t
WHVSX
VSVWH
t
E1LWH
E1 (CHIP ENABLE)
W (WRITE ENABLE)
t
t
WLWH
VSVWL
t
AVWL
t
t
WHDX
DVWH
VALID DATA IN
D (DATA IN)
t
t
WLQZ
WHQX
HIGH–Z
HIGH–Z
Q (DATA OUT)
t
WLE1H
MCM56824A
5
MOTOROLA FAST SRAM
WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Write Cycle Time
Symbol
Min
20
0
Max
—
Min
25
0
Max
—
Min
35
0
Max
—
Unit
ns
Notes
t
AVAV
Address Setup Time
t
—
—
—
ns
2
2
AVE1L
t
AVE2H
MUX Control Setup Time
Address Valid to End of Write
MUX Control Valid to End of Write
Chip Enable to End of Write
Data Valid to End of Write
Data Hold Time
t
0
15
15
12
8
—
—
—
—
—
—
—
—
0
20
20
15
10
0
—
—
—
—
—
—
—
—
0
30
30
20
15
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
VSVE1L
t
VSVE2H
t
t
2
AVE1H
AVE2L
t
2
VSVE1H
t
VSVE2L
t
t
2, 3
2
E1LE1H
E2HE2L
t
t
DVE1H
DVE2L
t
t
0
2, 4
2
E1HDX
E2LDX
Write Recovery Time
t
t
0
0
0
E1HAX
E2LAX
MUX Control Recovery Time
NOTES:
t
0
0
0
2
E1HVSX
t
E2LVSX
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
E1 OR E2 INITIATED WRITE CYCLE
t
AVAV
A (ADDRESS)
t
t
E1HAX
AVE1H
V/S (MUX CONTROL)
t
t
E1HVSX
VSVE1H
t
E1LE1H
E1 (CHIP ENABLE)
W (WRITE ENABLE)
t
AVE1L
t
VSVE1L
t
t
E1HDX
DVE1H
D (DATA IN)
DATA VALID
Q (DATA OUT)
HIGH–Z
MCM56824A
6
MOTOROLA FAST SRAM
DSPRAM Multiplexed Vector/Scalar Address Maps
8K x 24 DSPRAM Used in Typical Application
DSP56001
MCM56824A
DSP56001
D0 – D23
MCM56824A
D0 – D23
A0 – A11
A0 – A11
A0 – A11
A0 – A11
A12
X/Y
RAM A12
MUX
A12
A12
MEMORY
MANAGEMENT
PINS
V/S
X/Y
A15
X/Y
V/S
WR
W
4K x 24
“X” OPERANDS
8K x 24
“X” OPERANDS
PROGRAM
MEMORY
HIGH
4K x 24
“Y” OPERANDS
PROGRAM
MEMORY
LOW
PROGRAM
MEMORY
V/S = “1”
V/S = “0”
ORDERING INFORMATION
(Order by Full Part Number)
MCM
56824A XX XX XX
Motorola Memory Prefix
Part Number
Shipping Method (R2 = Tape and Reel, Blank = rails)
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)
Package (FN = PLCC, ZP = PBGA)
Full Part Numbers — MCM56824AFN20 MCM56824AFN25
MCM56824AZP20 MCM56824AZP25
MCM56824AFN35
MCM56824AZP35
MCM56824AZP20R2 MCM56824AZP25R2 MCM56824AZP35R2
MCM56824A
7
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
ZP PACKAGE
9 x 10 PBGA
CASE 896A–01
0.20 (0.008)
-T-
B
-B-
10
9
8
7
6
5
4
3
2
1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
A
B
C
D
E
F
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
16.16
17.68
1.33
MAX
16.36
17.88
1.73
MIN
MAX
0.644
0.703
0.068
0.031
0.637
0.697
0.053
0.028
A
N
0.69
0.81
G
H
J
1.524 BSC
0.060 BSC
G
L
N
1.84
13.80
15.29
2.44
14.20
15.69
0.073
0.544
0.602
0.096
0.559
0.617
R
G
R
C
L
D 86 PL
M
S
S
-A-
0.50 (0.020)
A
T
B
MCM56824A
8
MOTOROLA FAST SRAM
FN PACKAGE
52–LEAD PLCC
CASE 778–02
M
S
S
S
S
S
0.18(0.007)
T
N
–P
N
L
–M
L
B
Y BRK
-M-
-N-
M
S
S
S
D
D
0.18(0.007)
T
–P
–M
U
NOTE 1
-L-
52
LEADS
ACTUAL
Z1
W
1
(NOTE 1) 52
-P-
G1
V
S
S
S
S
S
0.25(0.010)
T
N
–P
L
–M
VIEW D–D
S
S
S
S
S
A
0.25(0.010)
0.25(0.010)
L
–M
–M
N
N
–P
–P
T
Z
M
M
S
S
S
S
S
S
S
S
0.18(0.007)
0.18(0.007)
L
–M
–P
N
L
–P
T
T
S
S
S
S
S
R
T
L
X
H
N
–M
K1
C
E
K
0.10 (0.004)
52
(NOTE 1)
M
M
S
S
S
S
S
S
S
S
SEATING
0.18(0.007)
0.18(0.007)
L
–M
–P
N
L
–P
T
T
-T-
G
J
PLANE
F
N
–M
DETAIL S
DETAIL S
G
1
MILLIMETERS
INCHES
MIN MAX
DIM
A
B
C
E
F
MIN
19.94
19.94
4.20
MAX
20.19
20.19
4.57
S
S
S
S
S
0.25(0.010)
T
L
–M
N
–P
0.785
0.785
0.165
0.090
0.013
0.795
0.795
0.180
0.110
0.019
2.29
2.79
0.33
0.48
G
H
J
K
R
U
V
W
X
Y
1.27 BSC
0.050 BSC
NOTES:
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
—
0.81
—
—
19.20
19.20
1.21
1.21
1.42
0.50
0.026
0.032
—
—
0.756
0.756
0.048
0.048
0.056
0.020
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP
OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
0.020
0.025
0.750
0.750
0.042
0.042
0.042
—
Z
2°
10
°
2°
10°
G1
K1
Z1
18.04
1.02
18.54
—
0.710
0.040
0.730
—
2°
10
°
2°
10°
6. CONTROLLING DIMENSION: INCH.
MCM56824A
9
MOTOROLA FAST SRAM
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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How to reach us:
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JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
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MCM56824A/D
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