MCM6226BBXJ20 [MOTOROLA]
128K x 8 Bit Static Random Access Memory; 128K ×8位的静态随机存取存储器
| 型号： | MCM6226BBXJ20 |
| 厂家： | 
MOTOROLA |
| 描述： | 128K x 8 Bit Static Random Access Memory |
| 文件： | 总8页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM6226BB/D
SEMICONDUCTOR TECHNICAL DATA
MCM6226BB
128K x 8 Bit Static Random
Access Memory
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
ortimingstrobeswhileCMOScircuitryreducespowerconsumptionandprovides
for greater reliability.
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
The MCM6226BB is equipped with both chip enable (E1 and E2) and output
enable(G)pins, allowingforgreatersystemflexibilityandeliminatingbusconten-
tion problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
EJ PACKAGE
300 MIL SOJ
CASE 857–02
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
PIN ASSIGNMENT
Fast Access Times: 15/17/20/25/35 ns
Equal Address and Chip Enable Access Times
All Inputs and Outputs are TTL Compatible
Three State Outputs
V
A
NC
A
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
CC
Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
E2
W
A
A
A
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
A
A
A
G
9
24
23
22
21
20
19
18
17
10
11
12
A
MEMORY MATRIX
ROW
DECODER
E1
DQ
A
A
512 ROWS x
2048 COLUMNS
A
A
A
DQ 13
DQ 14
DQ 15
DQ
DQ
DQ
DQ
A
A
V
16
SS
DQ
COLUMN I/O
INPUT
DATA
PIN NAMES
DQ
COLUMN DECODER
CONTROL
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . Chip Enables
DQ . . . . . . . . . . . . . Data Inputs/Outputs
NC . . . . . . . . . . . . . . . . . . No Connection
E1
E2
A
A
A
A
A
A
A
A
W
G
V
CC
V
SS
. . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 2
10/31/96
Motorola, Inc. 1996
TRUTH TABLE
E1
H
X
L
E2
X
G
X
X
H
L
W
X
X
H
H
L
Mode
Not Selected
Not Selected
Output Disabled
Read
I/O Pin
High–Z
High–Z
High–Z
Cycle
—
Current
I
I
, I
SB1 SB2
L
—
, I
SB1 SB2
H
H
H
—
I
I
I
CCA
CCA
CCA
L
D
Read
Write
out
L
X
Write
D
in
H = High, L = Low, X = Don’t Care
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
andtransverse air flow of at least500linearfeet
per minute is maintained.
Rating
Symbol
Value
Unit
Power Supply Voltage Relative to V
V
CC
– 0.5 to 7.0
V
V
SS
Voltage Relative to V
for Any Pin
V , V
in out
– 0.5 to V + 0.5
CC
SS
Except V
CC
Output Current (per I/O)
I
mA
± 20
1.0
out
Power Dissipation
P
D
W
°C
°C
°C
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to + 70
T
A
T
stg
– 55 to + 150
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
4.5
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
CC
5.5
V
IH
2.2
V
+ 0.3**
V
CC
Input Low Voltage
V
IL
– 0.5*
0.8
V
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns).
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2 V ac (pulse width ≤ 20 ns).
IH IH
CC
CC
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
—
Max
± 1
Unit
µA
Input Leakage Current (All Inputs, V = 0 to V
in
)
I
lkg(I)
CC
Output Leakage Current (E* = V , V
IH out
= 0 to V
)
I
—
± 1
µA
CC
lkg(O)
AC Active Supply Current (I
= 0 mA, all inputs =
MCM6226BB–15: t
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
I
CCA
—
—
—
—
—
195
180
165
150
130
mA
out
AVAV
AVAV
AVAV
AVAV
AVAV
V
V
or V , V = 0, V ≥ 3 V, cycle time ≥ t
= max)
min, MCM6226BB–17: t
MCM6226BB–20: t
MCM6226BB–25: t
MCM6226BB–35: t
IL
IH IL IH AVAV
CC
AC Standby Current (V
CC
= max, E* = V , f = f
IH max
)
MCM6226BB–15: t
MCM6226BB–17: t
MCM6226BB–20: t
MCM6226BB–25: t
MCM6226BB–35: t
= 15 ns
= 17 ns
= 20 ns
= 25 ns
= 35 ns
I
—
—
—
—
—
45
40
35
30
25
mA
AVAV
AVAV
AVAV
AVAV
AVAV
SB1
CMOS Standby Current (E* ≥ V
– 0.2 V, V ≤ V
in
+ 0.2 V
SS
I
—
5
mA
CC
= max, f = 0 MHz)
SB2
or ≥ V
– 0.2 V, V
CC
CC
OL
Output High Voltage (I
Output Low Voltage (I
= + 8.0 mA)
= – 4.0 mA)
V
—
0.4
—
V
V
OL
V
2.4
OH
OH
*E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
MCM6226BB
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
I/O Capacitance
All Inputs Except Clocks and DQs
E1, E2, G, and W
C
4
5
6
8
pF
in
C
ck
DQ
C
5
8
pF
I/O
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1a
READ CYCLE TIMING (See Notes 1, 2, and 3)
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Parameter
Read Cycle Time
Symbol
Min
15
—
—
—
3
Max
—
Min
17
—
—
—
3
Max
—
Min
20
—
—
—
3
Max
—
Min
25
—
—
—
3
Max
—
Min
35
—
—
—
3
Max
—
Unit
ns
Notes
t
4
AVAV
Address Access Time
Enable Access Time
t
15
15
6
17
17
7
20
20
7
25
25
8
35
35
8
ns
AVQV
t
ns
5
ELQV
GLQV
AXQX
Output Enable Access Time
t
t
ns
Output Hold from Address
Change
—
—
—
—
—
ns
Enable Low to Output Active
t
5
0
—
—
5
0
—
—
5
0
—
—
5
0
—
—
5
0
—
—
ns
ns
6, 7, 8
6, 7, 8
ELQX
Output Enable Low to Output
Active
t
GLQX
Enable High to Output High–Z
t
—
—
6
6
—
—
7
7
—
—
7
7
—
—
8
8
—
—
8
8
ns
ns
6, 7, 8
6, 7, 8
EHQZ
GHQZ
Output Enable High to Output
High–Z
t
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. All timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, t
and from device to device.
max is less than t
ELQX
min, and t
GHQZ
max is less than t
min, both for a given device
GLQX
EHQZ
7. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E ≤ V , G ≤ V ).
IL
IL
TIMING LIMITS
+5 V
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
480
Ω
OUTPUT
OUTPUT
255
Z
= 50 Ω
R
= 50 Ω
0
L
Ω
5 pF
V
= 1.5 V
L
(a)
(b)
Figure 1. AC Test Loads
MCM6226BB
3
MOTOROLA FAST SRAM
READ CYCLE 1 (See Notes 1, 2, 3, and 9)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Notes 3 and 5)
t
AVAV
A (ADDRESS)
t
ELQV
E (CHIP ENABLE)
t
t
EHQZ
ELQX
G (OUTPUT ENABLE)
t
t
GHQZ
GLQV
t
GLQX
HIGH–Z
Q (DATA OUT)
DATA VALID
t
AVQV
t
t
EHICCL
ELICCH
I
CC
SUPPLY CURRENT
I
SB
MCM6226BB
4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4)
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Parameter
Write Cycle Time
Symbol
Min
15
0
Max
—
Min
17
0
Max
—
Min
20
0
Max
—
Min
25
0
Max
—
Min
35
0
Max
—
Unit
ns
Notes
t
5
AVAV
Address Setup Time
t
—
—
—
—
—
ns
AVWL
Address Valid to End of Write
Write Pulse Width
t
12
12
—
14
14
—
15
15
—
17
17
—
20
20
—
ns
AVWH
t
—
—
—
—
—
ns
WLWH,
t
WLEH
Data Valid to End of Write
Data Hold TIme
t
t
7
0
—
—
6
8
0
—
—
7
9
0
—
—
7
10
0
—
—
8
11
0
—
—
8
ns
ns
ns
ns
ns
DVWH
WHDX
Write Low to Data High–Z
Write High to Output Active
t
—
5
—
5
—
5
—
5
—
5
6, 7, 8
6, 7, 8
WLQZ
t
—
—
—
—
—
—
—
—
—
—
WHQX
Write Recovery Time
NOTES:
t
0
0
0
0
0
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, t
max is less than t
min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLWH
t
WLEH
W (WRITE ENABLE)
t
t
DVWH
t
WHDX
AVWL
D (DATA IN)
DATA VALID
t
t
WHQX
WLQZ
HIGH–Z
HIGH–Z
Q (DATA OUT)
MCM6226BB
MOTOROLA FAST SRAM
5
WRITE CYCLE 2 (E Controlled, See Notes 1, 2, 3, and 4)
6226BB–15
6226BB–17
6226BB–20
6226BB–25
6226BB–35
Parameter
Write Cycle Time
Symbol
Min
15
0
Max
—
Min
17
0
Max
—
Min
20
0
Max
—
Min
25
0
Max
—
Min
35
0
Max
—
Unit
ns
Notes
t
5
AVAV
Address Setup Time
t
—
—
—
—
—
ns
AVEL
Address Valid to End of Write
Enable to End of Write
t
12
12
—
14
14
—
15
15
—
17
17
—
20
20
—
ns
AVEH
t
t
—
—
—
—
—
ns
6, 7
ELEH,
ELWH
Write Pulse Width
t
12
7
—
—
—
—
14
8
—
—
—
—
15
9
—
—
—
—
17
10
0
—
—
—
—
20
11
0
—
—
—
—
ns
ns
ns
ns
WLEH
Data Valid to End of Write
Data Hold Time
t
t
DVEH
0
0
0
EHDX
Write Recovery Time
NOTES:
t
0
0
0
0
0
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-
tention conditions during read and write cycles.
3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.
4. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
5. All timings are referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance state.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance state.
WRITE CYCLE 2 (E Controlled See Notes 1, 2, 3, and 4)
t
AVAV
A (ADDRESS)
t
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
t
EHAX
AVEL
ELWH
t
WLEH
W (WRITE ENABLE)
t
DVEH
D (DATA IN)
DATA VALID
t
EHDX
HIGH–Z
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6226BB XX XX XX
Motorola Memory Prefix
Part Number
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns, 25 = 25 ns,
35 = 35 ns)
Package (XJ = 400 mil SOJ, EJ = 300 mil SOJ)
Full Part Numbers — MCM6226BBXJ15
MCM6226BBXJ15R2 MCM6226BBEJ15 MCM6226BBEJ15R2
MCM6226BBXJ17
MCM6226BBXJ20
MCM6226BBXJ25
MCM6226BBXJ35
MCM6226BBXJ17R2 MCM6226BBEJ17 MCM6226BBEJ17R2
MCM6226BBXJ20R2 MCM6226BBEJ20 MCM6226BBEJ20R2
MCM6226BBXJ25R2 MCM6226BBEJ25 MCM6226BBEJ25R2
MCM6226BBXJ35R2 MCM6226BBEJ35 MCM6226BBEJ35R2
MCM6226BB
6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32 LEAD
400 MIL SOJ
CASE 857A–02
NOTES:
F
32 PL
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
32
1
17
16
S
S
S
A
0.17 (0.007)
T
B
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
DETAIL Z
N
32 PL
D
5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.
S
S
S
A
0.17 (0.007)
T
B
NOTE 3
MILLIMETERS
INCHES
-A-
P
DIM
A
B
C
D
E
MIN
20.83
10.03
3.26
0.41
2.24
0.67
MAX
21.08
10.29
3.75
0.50
2.48
MIN
MAX
0.830
0.405
0.148
0.020
0.098
0.032
S
S
S
0.820
0.395
0.128
0.016
0.088
0.026
B
0.17 (0.007)
T
A
A
L
G
-B-
F
0.81
C
E
G
K
L
N
P
1.27 BSC
0.050 BSC
0.10 (0.004)
0.89
1.14
0.035
0.045
SEATING
PLANE
-T-
0.64 BSC
0.025 BSC
K
R
DETAIL Z
RADIUS
S
0.76
11.05
9.27
1.14
11.30
9.52
0.030
0.435
0.365
0.030
0.045
0.445
0.375
0.040
S
S
S
B
R
S
0.25 (0.010)
T
NOTE 3
0.77
1.01
MCM6226BB
7
MOTOROLA FAST SRAM
32 LEAD
300 MIL SOJ
CASE 857–02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DATUM PLANE -X- LOCATED AT TOP OF MOLD
PARTING LINE AND COINCIDENT WITH TOP OF
LEAD, WHERE LEAD EXITS BODY.
F
32 PL
S
S
0.17 (0.007)
A
4. TO BE DETERMINED AT PLANE -X-.
5. TO BE DETERMINED AT PLANE -T-.
6. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
NOTE 4
32
1
17
16
M
32 PL
NOTE 5
D
S
S
0.17 (0.007)
A
7. 857-01 IS OBSOLETE, NEW STANDARD 857-02.
P
MILLIMETERS
INCHES
–A–
S
S
0.17 (0.007)
B
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
MIN
20.83
7.50
3.26
0.41
2.24
0.67
MAX
21.08
7.74
3.75
0.50
2.48
0.81
MIN
MAX
0.830
0.305
0.148
0.020
0.098
0.032
L
G
0.820
0.295
0.128
0.016
0.088
0.026
-B-
–X–
NOTE 3
C
E
0.10 (0.004)
DETAIL Z
1.27 BSC
0.050 BSC
K
SEATING
PLANE
RADIUS
S
R
-T-
0.89
1.14
0.035
0.045
0.64 BSC
0.025 BSC
NOTE 5
S
S
0.25 (0.010)
B
0.76
8.38
6.60
0.77
1.14
8.64
6.86
1.01
0.030
0.330
0.260
0.030
0.045
0.340
0.270
0.040
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://motorola.com/sps
MCM6226BB/D
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