MCM63D736TQ5 [MOTOROLA]

Dual-Port SRAM, 128KX36, 5ns, CMOS, PQFP176, TQFP-176;
MCM63D736TQ5
型号: MCM63D736TQ5
厂家: MOTOROLA    MOTOROLA
描述:

Dual-Port SRAM, 128KX36, 5ns, CMOS, PQFP176, TQFP-176

静态存储器 内存集成电路
文件: 总14页 (文件大小:215K)
中文:  中文翻译
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Order this document  
by MCM63D736/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63D736  
128K x 36 Bit Synchronous  
Dual I/O, Dual Address SRAM  
The MCM63D736 is a 4M–bit static random access memory, organized as  
128K words of 36 bits. It features common data input and data output buffers and  
incorporates input and output registers on–board with high speed SRAM.  
The MCM63D736 allows the user to concurrently perform reads, writes, or  
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
TQ PACKAGE  
176 LEAD TQFP  
CASE 1101–01  
The pass–through feature allows data to be passed from one port to the other,  
in either direction. The PTX input must be asserted to pass data from port X to  
port Y. The PTY will likewise pass data from port Y to port X. A pass–through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain protocols are followed. If  
both ports are read, the reads occur normally. If one port is written and the other  
is read, the read from the array will occur before the data is written. If both ports  
are written, only the data on DQY will be written to the array.  
Single 3.3 V ±5% Power Supply  
Fast Access Times: 4/5 ns Max  
Throughput of 4.8 Gigabits/Second  
Single Clock Operation  
Address, Data Input, E1X, E2X, E1Y, E2Y, PTX, PTY, WX, WY, and Data  
Output Registers On–Chip  
133 MHz Maximum Clock Frequency  
Self–Timed Write  
Two Bi–Directional Data Buses  
Can be Configured as Separate I/O  
Pass–Through Feature  
Asynchronous Output Enables (GX, GY)  
LVTTL Compatible I/O  
Concurrent Reads and Writes  
176–Pin TQFP Package  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cellular Base Stations  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory — RAID Systems  
Product Family Configurations  
Part  
Number  
Dual  
Address  
Single  
Address  
Dual  
I/O  
Separate  
I/O  
Configuration  
128K x 36  
32K x 36  
V
DD  
MCM63D736  
MCM69D536  
MCM69D618  
MCM67Q709A  
MCM67Q909  
NOTES:  
Note 1  
Note 1  
Note 1  
Note 2  
Note 2  
Note 2  
3.3 V  
3.3 V  
3.3 V  
5.0 V  
5.0 V  
64K x 18  
128K x 9  
512K x 9  
1. Tie AX and AY address ports together for the part to function as a single address part.  
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.  
REV 1  
8/26/99  
Motorola, Inc. 1999  
BLOCK DIAGRAM  
17  
17  
ADDRESS  
REGISTER  
ADDRESS  
REGISTER  
AX  
AY  
128K x 36 ARRAY  
WRITE X  
REGISTER  
WRITE Y  
REGISTER  
WX  
WRITE  
DRIVER  
SENSE  
AMPS  
SENSE  
AMPS  
WRITE  
DRIVER  
WY  
PTX  
REGISTER  
PTY  
REGISTER  
PTX  
PTY  
PASS–THROUGH  
DATA IN  
REGISTER  
OUTPUT  
REGISTER  
OUTPUT  
REGISTER  
DATA IN  
REGISTER  
K
ENABLE X  
REG 1  
E1X  
E2X  
ENABLE Y  
REG 1  
E1Y  
E2Y  
ENABLE X  
REG 2  
ENABLE Y  
REG 2  
DQX  
DQY  
GX  
GY  
MCM63D736  
2
MOTOROLA FAST SRAM  
PIN ASSIGNMENT  
V
132  
131  
130  
129  
128  
127  
126  
125  
SS  
1
2
3
4
5
6
7
V
SS  
DQX20  
DQY20  
DQX15  
DQY15  
V
V
V
DD  
SS  
SS  
V
DD  
DQX14  
DQY14  
DQX21  
DQY21  
DQX22  
DQY22  
8
9
DQX13  
DQY13  
124  
V
V
10  
11  
12  
13  
14  
15  
16  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
DD  
SS  
V
V
SS  
DD  
DQX12  
DQY12  
DQX23  
DQY23  
DQX24  
DQY24  
DQX11  
DQY11  
V
V
V
DD  
SS  
SS  
17  
V
DD  
DQX10  
DQY10  
DQX9  
DQX25  
DQY25  
DQX26  
DQY26  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
DQY9  
V
V
V
DD  
DD  
SS  
SS  
V
DQY8  
DQX8  
DQY7  
DQX7  
DQY27  
DQX27  
DQY28  
DQX28  
108  
107  
106  
105  
104  
V
V
V
DD  
SS  
SS  
V
DD  
DQY6  
103  
DQY29  
DQX29  
30  
31  
102  
101  
100  
99  
98  
97  
96  
95  
DQX6  
DQY5  
DQX5  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
DQY30  
DQX30  
V
V
V
DD  
SS  
SS  
V
DD  
DQY4  
DQX4  
DQY3  
DQX3  
DQY31  
DQX31  
DQY32  
DQX32  
94  
93  
92  
V
V
V
DD  
SS  
SS  
V
DD  
91  
90  
89  
DQY2  
DQX2  
DQY33  
DQX33  
42  
43  
44  
V
V
SS  
SS  
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 6162 63 64 65  
6768 69 70 71 7273 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88  
66  
MCM63D736  
3
MOTOROLA FAST SRAM  
PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
65, 63, 61, 59, 57, 55, 169, 167, 145,  
143, 68, 70, 72, 74, 76, 78, 80  
AX0 –  
AX16  
Input  
Address Port X: Never allow floating addresses for inputs AX0 – AX16.  
A pullup resistor is needed.  
64, 62, 60, 58, 56, 54, 168, 166, 144,  
142, 69, 71, 73, 75, 77, 79, 81  
AY0 –  
AY16  
Input  
I/O  
Address Port Y: Never allow floating addresses for inputs AY0 – AY16.  
A pullup resistor is needed.  
82, 86, 90, 94, 96, 100, 102, 106, 108,  
113. 115, 119, 121, 125, 127, 131, 135,  
139, 170, 174, 2, 6, 8, 12, 14, 18, 20, 25,  
27, 31, 33, 37, 39, 43, 47, 51  
DQX0 –  
DQX35  
Data Input/Output Port X.  
Data Input/Output Port Y.  
83, 87, 91, 95, 97, 101, 103, 107, 109,  
112, 114, 118, 120, 124, 126, 130, 134,  
138, 171, 175, 3, 7, 9, 13, 15, 19, 21, 24,  
26, 30, 32, 36, 38, 42, 46, 50  
DQY0 –  
DQY35  
I/O  
150  
151  
157  
158  
152  
E1X  
E2X  
E1Y  
E2Y  
GX  
Input  
Input  
Input  
Input  
Input  
Synchronous Chip Enable Port X: Active low.  
Synchronous Chip Enable Port X: Active high.  
Synchronous Chip Enable Port Y: Active low.  
Synchronous Chip Enable Port Y: Active high.  
Asynchronous Output Enable Port X Input:  
Low — enables output buffers (DQXx pins).  
High — DQXx pins are high impedance.  
153  
156  
GY  
K
Input  
Input  
Asynchronous Output Enable Port Y Input:  
Low — enables output buffers (DQYx pins).  
High — DQYx pins are high impedance.  
Clock: This signal registers the address, data in, and all control signals  
except G.  
146  
147  
148  
149  
PTX  
PTY  
WX  
Input  
Input  
Input  
Input  
Pass–Through Port X.  
Pass–Through Port Y.  
Synchronous Write Enable Port X.  
Synchronous Write Enable Port Y.  
WY  
4, 10, 16, 22, 28, 34, 40, 49, 67, 84,  
92, 98, 104, 110, 116, 122, 128, 137,  
155, 172  
V
DD  
Supply 3.3 V Power Supply.  
5, 11, 17, 23, 29, 35, 41, 48, 66, 85, 93,  
99, 105, 111, 117, 123, 129, 136, 140,  
141, 154, 161, 173  
V
Supply Ground.  
SS  
SS  
1, 44, 45, 52, 53, 88, 89, 132,  
133, 165, 176  
V
Supply Rounded to die flag. No chip current flows through these pins.  
159, 159, 160, 162, 163, 164  
NC  
No Connection: There is no connection to the chip.  
MCM63D736  
4
MOTOROLA FAST SRAM  
TRUTH TABLE (See Notes 1 through 5)  
Input at t Clock  
n
Operation  
No.  
E1X  
H
X
E2X  
X
E1Y  
H
X
E2Y  
X
WX  
WY  
X
PTX  
X
PTY  
X
Operation  
Deselected  
1
2
3
4
5
6
7
8
X
X
0
L
L
X
X
X
Deselected  
L
H
X
X
X
X
X
Write X Port  
X
X
L
H
X
X
X
1
0
X
X
Write Y Port  
L
H
L
H
X
0
X
Pass–Through X to Y  
Pass–Through Y to X  
Read X  
L
H
L
H
X
X
0
L
H
X
X
X
1
1
X
X
L
H
X
1
1
1
Read Y  
NOTES:  
1. GX/GY must be negated during write and pass–through cycles.  
2. Operation numbers 3 – 6 can be used in any combination.  
3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.  
4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.  
5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.  
t
t
n + 1  
n
K
ADDRESS & CONTROL  
VALID  
PIPELINED READ ACCESS  
VALID  
DATA INPUT D  
PASS–THROUGH  
VALID  
DATA OUTPUT Q  
ABSOLUTE MAXIMUM RATINGS (See Note)  
This is a synchronous device. All syn-  
Rating  
Power Supply Voltage  
Voltage Relative to V  
Symbol  
Value  
Unit  
V
chronous inputs must meet specified setup and  
hold times with stable logic levels for ALL  
rising edges of clock (K) while the device is  
selected.  
This device contains circuitry to protect the  
inputs against damage due to high static volt-  
ages or electric fields; however, it is advised  
that normal precautions be taken to avoid  
application of any voltage higher than maxi-  
mum rated voltages to these high–impedance  
circuits.  
V
DD  
–0.5 to 4.6  
for Any Pin  
V , V  
in out  
–0.5 to V + 0.5  
DD  
V
SS  
Except V  
DD  
Output Current  
I
±20  
1.6  
mA  
W
out  
Package Power Dissipation  
Temperature Under Bias  
Operating Temperature  
Storage Temperature — Plastic  
NOTES:  
P
D
T
bias  
–10 to 85  
0 to 70  
°C  
°C  
°C  
T
A
T
stg  
–55 to 125  
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are  
exceeded. Functional operation should be restricted to RECOMMENDED  
OPERATING CONDITIONS. Exposure to higher than recommended voltages for  
extended periods of time could affect device reliability.  
2. Power dissipation capability is dependent upon package characteristics and use  
environment. See Package Thermal Characteristics.  
MCM63D736  
5
MOTOROLA FAST SRAM  
PACKAGE THERMAL CHARACTERISTICS (See Note 1)  
Rating  
Symbol  
TQFP  
Unit  
Notes  
Junction to Ambient (@ 200 lfm)  
Single–Layer Board  
Four–Layer Board  
R
40  
35  
°C/W  
2
θJA  
Junction to Board (Bottom)  
Junction to Case (Top)  
NOTES:  
R
R
23  
9
°C/W  
°C/W  
3
4
θJB  
θJC  
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient  
temperature, air flow, board population, and board thermal resistance.  
2. Per SEMI G38–87.  
3. Indicates the average thermal resistance between the die and the printed circuit board.  
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).  
DC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V ±5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS  
Parameter  
Supply Voltage (Operating Voltage Range)  
Input High Voltage  
Symbol  
Min  
3.135  
2.0  
Max  
Unit  
V
V
DD  
3.465  
V
IH  
V
+ 0.5**  
V
DD  
Input Low Voltage  
V
–0.5*  
0.8  
V
IL  
Input Leakage Current (All Inputs, V = 0 to V  
)
I
±1.0  
±1.0  
µA  
µA  
mA  
in  
DD  
lkg(I)  
Output Leakage Current (E = V , V  
IH out  
= 0 to V  
)
I
DD  
lkg(O)  
AC Supply Current (I  
= 0 mA) (V  
= Max, f = f  
)
I
I
–133  
–100  
400  
350  
out  
DD  
max  
DDA  
DDA  
CMOS Standby Supply Current (Deselected, Clock (K)  
Cycle Time t , All Inputs Toggling at CMOS Levels  
I
100  
mA  
SB1  
KHKH  
+ 0.2 V or V  
V
V  
– 0.2 V)  
in  
SS  
DD  
= +8.0 mA)  
Output Low Voltage (I  
V
0.4  
V
V
OL  
OL  
Output High Voltage (I  
= –4.0 mA)  
V
2.4  
V
DD  
OH  
OH  
*V –1.5 V for t t  
/2.  
IL  
KHKH  
**V V  
IH  
+ 1.0 V (not to exceed 4.6 V) for t t  
/2.  
KHKH  
DD  
CAPACITANCE (f = 1.0 MHz, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)  
A
Parameter  
Address and Data Input Capacitance  
Control Pin Input Capacitance  
Symbol  
Max  
Unit  
pF  
C
C
6
6
8
in  
in  
pF  
Output Capacitance  
C
pF  
out  
MCM63D736  
6
MOTOROLA FAST SRAM  
AC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V ±5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V  
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V  
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)  
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V  
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted  
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)  
MCM63D736–4  
MCM63D736–5  
Parameter  
Symbol  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Notes  
Min  
7.5  
3
Max  
4
Min  
10  
4
Max  
5
Cycle Time  
t
1
KHKH  
Clock Access Time  
t
KHQV  
Clock Low Pulse Width  
t
3
3
KLKH  
Clock High Pulse Width  
t
3
4
KHKL  
Clock High to Data Output Active  
Clock High to Data Output Invalid  
Clock High to Data Output High–Z  
Output Enable Low to Data Output Valid  
Output Enable Low to Data Output Low–Z  
Output Enable High to Data Output High–Z  
t
t
0
0
KHQX1  
1
1
KHQX2  
t
t
t
0
0
2
KHQZ  
GLQV  
GLQX  
GHQZ  
4
5
3
t
1.5  
3
1.5  
2
3
Setup Times:  
Hold Times:  
NOTES:  
AWR0 – AWR16  
ARD0 – ARD16  
t
AVKH  
AVKH  
WVKH  
t
t
W
PT  
t
PTVKH  
E1X, E2X, E1Y, E2Y  
D0 – D35  
t
t
EVKH  
DVKH  
AWR0 – AWR16  
ARD0 – ARD16  
W
t
t
0.5  
0.5  
ns  
3
KHAX  
KHAX  
t
KHWX  
PT  
t
KHPTX  
t
E1X, E2X, E1Y, E2Y  
D0 – D35  
KHEX  
KHDX  
t
1. All read and write cycles are referenced from K.  
2. This parameter is sampled and not 100% tested.  
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising  
edges of clock (K) while the device is selected.  
R
= 50 Ω  
L
OUTPUT  
Z
= 50 Ω  
0
V
= 1.5 V  
L
Figure 1. AC Test Load  
MCM63D736  
7
MOTOROLA FAST SRAM  
READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH)  
t
KHKH  
t
t
KHKL  
KLKH  
K
t
AVKH  
t
KHAX  
1
2
3
4
5
6
7
8
9
AX  
GX  
PORT X  
t
GLQV  
t
KHQV  
t
GHQZ  
t
KHQX1  
Q(1)  
Q(2)  
Q(3)  
Q(5)  
Q(6)  
Q(7)  
DQX  
t
GLQX  
t
EVKH  
E
t
KHEX  
12  
13  
14  
15  
16  
6
7
19  
20  
AY  
PORT Y  
GY  
t
KHQZ  
Q(12)  
Q(13)  
Q(14)  
Q(16)  
Q(6)  
Q(7)  
DQY  
t
KHQV  
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.  
MCM63D736  
8
MOTOROLA FAST SRAM  
WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH)  
t
t
t
KHKL  
KHKH  
KLKH  
K
1
2
3
4
5
6
7
8
9
AX  
t
KHWX  
t
WVKH  
WX  
PORT X  
GX  
t
t
KHDX  
DVKH  
D(2)  
D(3)  
D(4)  
D(8)  
D(9)  
DQX  
E
12  
13  
14  
5
6
18  
19  
20  
AY  
15  
WY  
PORT Y  
GY  
D(14)  
D(15)  
D(5)  
D(6)  
D(18)  
D(19)  
DQY  
PORT Y TAKES PRECEDENCE  
OVER PORT X WHEN AX = AY  
AND WRITING BOTH PORTS.  
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.  
MCM63D736  
9
MOTOROLA FAST SRAM  
WRITE TO PORT X AND PASS–THROUGH TO PORT Y (SEE NOTE)  
t
t
t
KHKL  
KHKH  
KLKH  
K
1
2
3
4
5
6
7
8
9
AX  
WX  
PORT X  
GX  
t
t
PTVKH  
KHPTX  
PTX  
t
t
DVKH  
KHDX  
D(2)  
D(3)  
D(X)  
D(Y)  
D(6)  
DQX  
E
12  
13  
14  
16  
17  
18  
19  
20  
AY  
15  
WY  
GY  
PORT Y  
PTY  
t
KHQV  
t
KHQZ  
t
KHQX2  
D(3)  
D(X)  
D(Y)  
D(17)  
DQY  
E Low = E1 Low and E2 High. E High = E1 High or E2 Low.  
NOTE: The timing diagram is valid for the opposite case as well, i.e., writing to Port Y and passing through to Port X.  
MCM63D736  
10  
MOTOROLA FAST SRAM  
COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT  
t
t
t
KHKL  
KHKH  
KLKH  
K
TRY TO  
WRITE  
TRY TO  
WRITE  
READ  
1
READ  
READ  
READ  
2
READ  
READ  
3
1
2
AX  
WX  
GX  
PORT X  
D(ABC)  
D(DEF)  
Q(PQR)  
Q(XYZ)  
Q(JKL)  
DQX  
READ  
1
READ  
READ  
WRITE  
2
READ  
READ  
3
WRITE  
1
WRITE  
2
AY  
WY  
GY  
PORT Y  
D(PQR)  
D(XYZ)  
Q(PQR)  
D(JKL)  
Q(JKL)  
DQY  
PORT Y TAKES PRECEDENCE  
OVER PORT X WHEN AX = AY  
AND WRITING BOTH PORTS.  
PTX = PTY = high.  
D(Value) = Value is the input to the data port.  
Q(Value) = Value is the output from the data port.  
MCM63D736  
11  
MOTOROLA FAST SRAM  
ORDERING INFORMATION  
(Order by Full Part Number)  
MCM 63D736 XX XX X  
Motorola Memory Prefix  
Part Number  
Shipping Method (Blank = Rails)  
Speed (4 = 4 ns, 5 = 5 ns)  
Package (TQ = TQFP)  
Full Part Numbers — MCM63D736TQ4  
MCM63D736TQ5  
MCM63D736  
12  
MOTOROLA FAST SRAM  
PACKAGE DIMENSIONS  
TQFP PACKAGE  
176 LEAD  
CASE 1101–01  
G
P
4X  
0.20  
H
L–M  
N
4X 44 TIPS  
0.20 T L–M N  
C
C
PIN 1  
IDENT  
L
L
176  
133  
AB  
AB  
–X–  
X=L, M, N  
1
132  
VIEW Y  
3X VIEW Y  
–M–  
F
PLATING  
BASE  
METAL  
B
C
L
V
–L–  
U
J
V1  
B1  
D
M
S
S
0.08  
T
L–M  
N
44  
89  
SECTION AB–AB  
45  
88  
ROTATED 90 CLOCKWISE  
–N–  
NOTES:  
A1  
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
S1  
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS  
COINCIDENT WITH THE LEAD WHERE THE THE LEAD EXITS THE  
PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.  
4. DATUMS –L–, –M–, AND –N– TO BE DETERMINED AT DATUM PLANE  
–H–.  
A
S
5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–.  
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.  
ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A  
AND B DO INLCUDE MOLD MISMATCH AND ARE DETERMINED AT  
DATUM PLANE –H–.  
VIEW AA  
C
7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR  
PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35  
(0.014) MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT  
LEAD 0.07 (0.003).  
–H–  
–T–  
SEATING  
PLANE  
4X  
2
0.08  
T
MILLIMETERS  
DIM  
A
MIN  
24.00 BSC  
MAX  
A1  
B
B1  
C
C1  
C2  
D
12.00 BSC  
24.00 BSC  
12.00 BSC  
–––  
0.05  
1.35  
0.17  
0.45  
0.17  
1.60  
S
0.05  
–––  
1.45  
0.23  
0.75  
0.27  
W
E
F
2X R R1  
0.25  
1
G
J
K
P
R1  
S
S1  
U
0.50 BSC  
C2  
0.09  
0.20  
GAGE  
PLANE  
0.50 REF  
0.25 BSC  
0.10 0.20  
26.00 BSC  
13.00 BSC  
C1  
K
0.09  
0.16  
E
V
26.00 BSC  
13.00 BSC  
0.20 REF  
1,00 REF  
Z
V1  
W
Z
VIEW AA  
0
0
7
1
2
–––  
12 REF  
MCM63D736  
13  
MOTOROLA FAST SRAM  
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and  
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola  
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,includingTypicals”  
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of  
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other  
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury  
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Motorola was negligent regarding the design or manufacture of the part. Motorola and  
Opportunity/Affirmative Action Employer.  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal  
Mfax is a trademark of Motorola, Inc.  
How to reach us:  
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;  
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569  
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,  
– US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong.  
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,  
Motorola Fax Back System  
– http://sps.motorola.com/mfax/  
852-26668334  
HOME PAGE: http://motorola.com/sps/  
CUSTOMER FOCUS CENTER: 1-800-521-6274  
MCM63D736/D  

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