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MCM63P819TQ133 [MOTOROLA]

256KX18 CACHE SRAM, 4ns, PQFP100, TQFP-100;
MCM63P819TQ133
型号： MCM63P819TQ133
厂家： MOTOROLA    MOTOROLA
描述：

256KX18 CACHE SRAM, 4ns, PQFP100, TQFP-100

静态存储器
文件： 总21页 (文件大小：320K)
中文：  中文翻译
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MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM63P737/D  
MCM63P737  
MCM63P819  
128K x 36 and 256K x 18 Bit  
Pipelined BurstRAM  
Synchronous Fast Static RAM  
The MCM63P737 and MCM63P819 are 4M–bit synchronous fast static RAMs  
designed to provide a burstable, high performance, secondary cache for the  
PowerPC and other high performance microprocessors. The MCM63P737 is  
organized as 128K words of 36 bits each and the MCM63P819 is organized as  
256K words of 18 bits each. These devices integrate input registers, an output  
register, a 2–bit address counter, and high speed SRAM onto a single monolithic  
circuit for reduced parts count in cache data RAM applications. Synchronous  
design allows precise cycle control with the use of an external clock (K).  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K)  
controlled through positive–edge–triggered noninverting registers.  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM63P737 and MCM63P819  
(burstsequenceoperatesinlinearorinterleavedmodedependentuponthestate  
of LBO) and controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
ZP PACKAGE  
PBGA  
CASE 999–02  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The bytes are designated as “a”, “b”, etc. SBa controls DQa, SBb  
controls DQb, etc. Individual bytes are written if the selected byte writes SBx are  
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and  
SW are asserted.  
For read cycles, pipelined SRAMs output data is temporarily stored by an  
edge–triggeredoutput register and then released to the output buffers at the next  
rising edge of clock (K).  
The MCM63P737 and MCM63P819 operate from a 3.3 V core power supply  
and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs  
are JEDEC standard JESD8–5 compatible.  
•
MCM63P737/MCM63P819–166 = 3.5 ns Access/6 ns Cycle (166 MHz)  
MCM63P737/MCM63P819–150 = 3.8 ns Access/6.7 ns Cycle (150 MHz)  
MCM63P737/MCM63P819–133 = 4 ns Access/7.5 ns Cycle (133 MHz)  
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
•
•
•
•
•
•
•
•
Byte Write and Global Write Control  
Sleep Mode (ZZ)  
JEDEC Standard 100–Pin TQFP and 119–Pin PBGA Packages  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
REV 2  
3/12/99  
Motorola, Inc. 1999  
FUNCTIONAL BLOCK DIAGRAM  
LBO  
ADV  
K
BURST  
COUNTER  
CLR  
2
17/18  
ADSC  
ADSP  
128K x 36/256K x 18  
ARRAY  
K2  
2
SA  
SA1  
SA0  
17/18  
15/16  
ADDRESS  
REGISTER  
SGW  
SW  
WRITE  
REGISTER  
a
36/18  
36/18  
SBa  
WRITE  
REGISTER  
b
SBb  
SBc*  
SBd*  
4/2  
DATA–IN  
REGISTER  
DATA–OUT  
REGISTER  
WRITE  
REGISTER  
c*  
K
WRITE  
REGISTER  
d*  
K2  
K
SE1  
SE2  
SE3  
ENABLE  
REGISTER  
ENABLE  
REGISTER  
G
DQa – DQd/  
DQa–DQb  
ZZ  
* Valid only for MCM63P737.  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
2
MCM63P737 PIN ASSIGNMENTS  
1
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A
B
C
D
E
V
SA SA ADSP SA  
SA V  
DQc  
DQc  
DQc  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQb  
DQb  
DQb  
V
DDQ  
DDQ  
2
3
4
5
6
7
8
9
NC  
SE2 SA ADSC SA SE3  
SA SA SA SA  
NC  
V
DDQ  
DDQ  
NC  
V
DD  
NC  
V
V
SS  
SS  
DQc  
DQc  
DQc  
DQc  
DQb  
DQb  
DQb  
DQb  
DQc DQc  
DQc DQc  
V
NC  
SE1  
G
V
DQb DQb  
DQb DQb  
SS  
SS  
V
SS  
V
SS  
F
V
SS  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SS  
V
DDQ  
DQc  
V
SS  
V
SS  
DQb V  
DDQ  
V
V
DDQ  
DQc  
DQc  
NC  
V
DD  
NC  
DDQ  
G
DQb  
DQb  
DQc DQc SBc ADV SBb DQb DQb  
H
DQc DQc  
V
SS  
SGW  
V
SS  
DQb DQb  
V
SS  
NC  
J
V
V
NC  
V
DD  
NC  
V
V
V
DDQ DD  
DD DDQ  
DD  
V
ZZ  
K
L
SS  
DQd DQd  
V
SS  
K
V
SS  
DQa DQa  
DQd  
DQa  
DQa  
DQd  
DQd DQd SBd NC SBa DQa DQa  
V
V
DDQ  
DDQ  
M
N
P
V
V
SS  
SS  
V
DDQ  
DQd  
V
SW  
SA1  
SA0  
V
DQa V  
DDQ  
SS  
SS  
DQd  
DQd  
DQd  
DQd  
DQa  
DQa  
DQa  
DQa  
DQd DQd  
DQd DQd  
V
SS  
V
SS  
DQa DQa  
DQa DQa  
V
SS  
V
SS  
V
V
SS  
DDQ  
DQd  
SS  
R
T
U
V
V
DDQ  
NC  
NC  
SA LBO  
NC SA  
V
NC  
SA  
NC  
SA  
NC  
NC  
NC  
ZZ  
DD  
DQa  
DQa  
DQa  
SA  
NC  
DQd  
DQd  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
V
DDQ  
NC  
NC  
V
DDQ  
100–PIN TQFP  
TOP VIEW  
119–BUMP PBGA  
TOP VIEW  
Not to Scale  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
3
MCM63P737 TQFP PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
85  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
84  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
83  
ADV  
DQx  
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63  
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80  
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b, c, d).  
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30  
86  
G
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
89  
31  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G, LBO, and ZZ.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
32, 33, 34, 35, 44, 45, 46,  
47, 48, 49, 50, 81, 82, 99, 100  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
36, 37  
SA1, SA0  
Synchronous Address Inputs: these pins must be wired to the two LSBs  
of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
93, 94, 95, 96  
(a) (b) (c) (d)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b, c, d). SGW overrides SBx.  
98  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
97  
92  
88  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
87  
64  
SW  
ZZ  
Input  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
Sleep Mode: This active high asynchronous signal places the RAM into  
the lowest power mode. The ZZ pin disables the RAMs internal clock  
when placed in this mode. When ZZ is negated, the RAM remains in  
low power mode until it is commanded to READ or WRITE. Data  
integrity is maintained upon returning to normal operation.  
15, 41, 65, 91  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
4, 11, 20, 27, 54, 61, 70, 77  
V
DDQ  
5, 10, 17, 21, 26, 40,  
55, 60, 67, 71, 76, 90  
V
SS  
14, 16, 38, 39, 42, 43, 66  
NC  
—
No Connection: There is no connection to the chip.  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
4
MCM63P737 PBGA PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
4B  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
4A  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
4G  
ADV  
DQx  
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P  
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H  
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H  
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b, c, d).  
4F  
G
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
4K  
3R  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G, LBO, and ZZ.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,  
5C, 6C, 2R, 6R, 3T, 4T, 5T  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
4N, 4P  
SA1, SA0  
Synchronous Address Inputs: These pins must be wired to the two  
LSBs of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
5L, 5G, 3G, 3L  
(a) (b) (c) (d)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b, c, d). SGW overrides SBx.  
4E  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
2B  
6B  
4H  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
4M  
7T  
SW  
ZZ  
Input  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
Sleep Mode: This active high asynchronous signal places the RAM into  
the lowest power mode. The ZZ pin disables the RAMs internal clock  
when placed in this mode. When ZZ is negated, the RAM remains in  
low power mode until it is commanded to READ or WRITE. Data  
integrity is maintained upon returning to normal operation.  
4C, 2J, 4J, 6J, 4R  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U  
V
DDQ  
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,  
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P  
V
SS  
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,  
7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U  
NC  
—
No Connection: There is no connection to the chip.  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
5
MCM63P818 PIN ASSIGNMENTS  
1
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
A
B
C
D
E
V
SA SA ADSP SA  
SA V  
NC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
SA  
NC  
NC  
V
DDQ  
DDQ  
2
3
4
5
6
7
8
9
NC  
SE2 SA ADSC SA SE3  
SA SA SA SA  
NC  
NC  
V
DDQ  
DDQ  
NC  
V
DD  
NC  
V
V
SS  
SS  
NC  
NC  
NC  
DQb  
V
NC  
SE1  
G
V
DQa NC  
NC DQa  
SS  
SS  
DQa  
DQa  
DQa  
DQb  
DQb  
V
SS  
DDQ  
DQb  
DQb  
NC  
V
DD  
NC  
NC DQb  
NC  
V
SS  
V
SS  
F
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SS  
V
V
SS  
V
SS  
DQa V  
DDQ  
DDQ  
V
V
DDQ  
G
DQa  
DQa  
NC DQb SBb ADV  
V
SS  
NC DQa  
DQa NC  
H
DQb  
NC  
V
SS  
SGW V  
SS  
V
SS  
NC  
J
V
V
NC  
V
DD  
NC  
V
V
V
DDQ DD  
DD DDQ  
DD  
V
ZZ  
K
L
SS  
NC DQb  
V
SS  
K
V
SS  
NC DQa  
DQb  
DQa  
DQa  
DQb  
DQb  
NC  
DQb  
NC  
V
NC SBa DQa NC  
SS  
V
V
DDQ  
DDQ  
M
N
P
V
V
SS  
SS  
V
DDQ  
V
SS  
SW  
SA1  
SA0  
V
NC  
V
DDQ  
SS  
DQb  
DQb  
DQb  
NC  
DQa  
DQa  
NC  
DQb  
V
SS  
V
SS  
DQa NC  
NC DQa  
NC  
NC DQb  
V
SS  
V
SS  
V
SS  
V
SS  
R
T
U
V
V
DDQ  
NC  
NC  
SA LBO  
SA SA  
V
NC  
SA  
NC  
SA  
SA  
NC  
NC  
ZZ  
DDQ  
NC  
NC  
NC  
DD  
NC  
NC  
NC  
NC  
NC  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
V
DDQ  
NC  
NC  
V
DDQ  
100–PIN TQFP  
TOP VIEW  
119–BUMP PBGA  
TOP VIEW  
Not to Scale  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
6
MCM63P819 TQFP PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
85  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
84  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
83  
ADV  
DQx  
G
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74  
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b).  
86  
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
89  
31  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G, LBO, and ZZ.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
32, 33, 34, 35, 44, 45, 46, 47, 48,  
49, 50, 80, 81, 82, 99, 100  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
36, 37  
SA1, SA0  
Synchronous Address Inputs: These pins must be wired to the two  
LSBs of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
93, 94  
(a) (b)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b). SGW overrides SBx.  
98  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
97  
92  
88  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
87  
64  
SW  
ZZ  
Input  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
Sleep Mode: This active high asynchronous signal places the RAM into  
the lowest power mode. The ZZ pin disables the RAMs internal clock  
when placed in this mode. When ZZ is negated, the RAM remains in  
low power mode until it is commanded to READ or WRITE. Data  
integrity is maintained upon returning to normal operation.  
15, 41, 65, 91  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
4, 11, 20, 27, 54, 61, 70, 77  
V
DDQ  
5, 10, 17, 21, 26, 40,  
55, 60, 67, 71, 76, 90  
V
SS  
1, 2, 3, 6, 7, 14, 16, 25, 28, 29,  
30, 38, 39, 42, 43, 51, 52, 53,  
56, 57, 66, 75, 78, 79, 95, 96  
NC  
—
No Connection: There is no connection to the chip.  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
7
MCM63P819 PBGA PIN DESCRIPTIONS  
Pin Locations  
Symbol  
Type  
Description  
4B  
ADSC  
Input  
Synchronous Address Status Controller: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
READ, WRITE, or chip deselect.  
4A  
ADSP  
Input  
Synchronous Address Status Processor: Active low, interrupts any  
ongoing burst and latches a new external address. Used to initiate a  
new READ, WRITE, or chip deselect (exception — chip deselect does  
not occur when ADSP is asserted and SE1 is high).  
4G  
ADV  
DQx  
G
Input  
I/O  
Synchronous Address Advance: Increments address count in  
accordance with counter type selected (linear/interleaved).  
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P  
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P  
Synchronous Data I/O: “x” refers to the byte being read or written  
(byte a, b).  
4F  
Input  
Asynchronous Output Enable Input:  
Low — enables output buffers (DQx pins).  
High — DQx pins are high impedance.  
4K  
3R  
K
Input  
Input  
Clock: This signal registers the address, data in, and all control signals  
except G, LBO, and ZZ.  
LBO  
Linear Burst Order Input: This pin must remain in steady state (this  
signal not registered or latched). It must be tied high or low.  
Low — linear burst counter (68K/PowerPC).  
High — interleaved burst counter (486/i960/Pentium).  
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,  
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T  
SA  
Input  
Input  
Synchronous Address Inputs: These inputs are registered and must  
meet setup and hold times.  
4N, 4P  
SA1, SA0  
Synchronous Address Inputs: These pins must be wired to the two  
LSBs of the address bus for proper burst operation. These inputs are  
registered and must meet setup and hold times.  
5L, 3G  
(a) (b)  
SBx  
SE1  
Input  
Input  
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte  
a, b). SGW overrides SBx.  
4E  
Synchronous Chip Enable: Active low to enable chip.  
Negated high — blocks ADSP or deselects chip when ADSC is  
asserted.  
2B  
6B  
4H  
SE2  
SE3  
Input  
Input  
Input  
Synchronous Chip Enable: Active high for depth expansion.  
Synchronous Chip Enable: Active low for depth expansion.  
SGW  
Synchronous Global Write: This signal writes all bytes regardless of the  
status of the SBx and SW signals. If only byte write signals SBx are  
being used, tie this pin high.  
4M  
7T  
SW  
ZZ  
Input  
Input  
Synchronous Write: This signal writes only those bytes that have been  
selected using the byte write SBx pins. If only byte write signals SBx  
are being used, tie this pin low.  
Sleep Mode: This active high asynchronous signal places the RAM into  
the lowest power mode. The ZZ pin disables the RAMs internal clock  
when placed in this mode. When ZZ is negated, the RAM remains in  
low power mode until it is commanded to READ or WRITE. Data  
integrity is maintained upon returning to normal operation.  
4C, 2J, 4J, 6J, 4R  
V
Supply Core Power Supply.  
Supply I/O Power Supply.  
Supply Ground.  
DD  
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U  
V
DDQ  
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,  
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P  
V
SS  
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,  
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,  
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,  
5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U  
NC  
—
No Connection: There is no connection to the chip.  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
8
TRUTH TABLE (See Notes 1 Through 5)  
Address  
Used  
3
2, 4  
Next Cycle  
Deselect  
SE1  
1
SE2  
X
X
0
SE3  
X
1
ADSP  
ADSC  
ADV  
X
X
X
X
X
X
X
0
G
DQx  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
DQ  
Write  
None  
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
1
X
1
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
Deselect  
None  
0
X
X
X
X
X
X
1
Deselect  
None  
0
X
1
Deselect  
None  
X
X
0
X
0
Deselect  
None  
X
0
Begin Read  
Begin Read  
Continue Read  
Continue Read  
Continue Read  
Continue Read  
Suspend Read  
Suspend Read  
Suspend Read  
Suspend Read  
Begin Write  
External  
External  
Next  
1
0
1
0
READ  
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
0
READ  
READ  
READ  
READ  
READ  
READ  
READ  
READ  
WRITE  
WRITE  
WRITE  
WRITE  
WRITE  
Next  
0
0
Next  
0
1
High–Z  
DQ  
Next  
1
0
0
Current  
Current  
Current  
Current  
External  
Next  
X
X
1
1
1
High–Z  
DQ  
1
0
1
1
High–Z  
DQ  
1
1
0
0
X
0
X
X
X
X
X
High–Z  
High–Z  
High–Z  
High–Z  
High–Z  
Continue Write  
Continue Write  
Suspend Write  
Suspend Write  
NOTES:  
X
1
X
X
X
X
X
X
X
X
Next  
0
Current  
Current  
X
1
1
1
1. X = don’t care. 1 = logic high. 0 = logic low.  
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.  
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t  
) following G going low.  
GLQX  
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must  
also remain negated at the completion of the write cycle to ensure proper write data hold times.  
ASYNCHRONOUS TRUTH TABLE  
Operation  
Read  
ZZ  
L
G
L
I/O Status  
Data Out (DQx)  
High–Z  
Read  
L
H
X
X
X
Write  
L
High–Z  
Deselected  
Sleep  
L
High–Z  
H
High–Z  
LINEAR BURST ADDRESS TABLE (LBO = V  
)
SS  
1st Address (External)  
X . . . X00  
2nd Address (Internal)  
X . . . X01  
3rd Address (Internal)  
X . . . X10  
4th Address (Internal)  
X . . . X11  
X . . . X01  
X . . . X10  
X . . . X11  
X . . . X00  
X . . . X10  
X . . . X11  
X . . . X00  
X . . . X01  
X . . . X11  
X . . . X00  
X . . . X01  
X . . . X10  
INTERLEAVED BURST ADDRESS TABLE (LBO = V  
)
DD  
2nd Address (Internal)  
1st Address (External)  
X . . . X00  
3rd Address (Internal)  
X . . . X10  
4th Address (Internal)  
X . . . X11  
X . . . X01  
X . . . X00  
X . . . X11  
X . . . X10  
X . . . X01  
X . . . X11  
X . . . X10  
X . . . X10  
X . . . X00  
X . . . X01  
X . . . X11  
X . . . X01  
X . . . X00  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
9
WRITE TRUTH TABLE  
SBc  
SBd  
(See Note 1)  
(See Note 1)  
Cycle Type  
Read  
SGW  
H
SW  
H
L
SBa  
X
SBb  
X
X
H
H
H
L
X
H
H
H
H
L
Read  
H
H
H
Write Byte a  
H
L
L
H
Write Byte b  
H
L
H
L
Write Byte c (See Note 1)  
Write Byte d (See Note 1)  
Write All Bytes  
Write All Bytes  
H
L
H
H
H
L
H
H
H
L
H
L
L
L
L
L
X
X
X
X
X
NOTE:  
1. Valid only for MCM63P737.  
ABSOLUTE MAXIMUM RATINGS (See Note 1)  
This device contains circuitry to protect the  
inputs against damage due to high static volt-  
ages or electric fields; however, it is advised  
that normal precautions be taken to avoid  
application of any voltage higher than maxi-  
mum rated voltages to this high–impedance  
circuit.  
Rating  
Power Supply Voltage  
I/O Supply Voltage  
Symbol  
Value  
– 0.5 to 4.6  
Unit Notes  
V
DD  
V
V
SS  
V
DDQ  
V
SS  
– 0.5 to V  
V
V
2
2
DD  
– 0.5 to  
Input Voltage Relative to V  
Any Pin Except V  
DD  
for  
V , V  
in out  
V
V
SS  
SS  
+ 0.5  
DD  
Input Voltage (Three–State I/O)  
V
V
V
– 0.5 to  
+ 0.5  
V
2
3
IT  
SS  
DDQ  
± 20  
1.6  
Output Current (per I/O)  
Package Power Dissipation  
Temperature Under Bias  
Storage Temperature  
NOTES:  
I
mA  
W
out  
P
D
T
bias  
– 10 to 85  
°C  
°C  
T
stg  
– 55 to 125  
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are  
exceeded. Functional operation should be restricted to RECOMMENDED OPER-  
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended  
periods of time could affect device reliability.  
2. This is a steady–state DC parameter that is in effect after the power supply has  
achieved its nominal operating level. Power sequencing is not necessary.  
3. Power dissipation capability is dependent upon package characteristics and use  
environment. See Package Thermal Characteristics.  
PACKAGE THERMAL CHARACTERISTICS — TQFP  
Rating  
Symbol  
Max  
Unit  
Notes  
Junction to Ambient (@ 200 lfm)  
Single–Layer Board  
Four–Layer Board  
R
40  
25  
°C/W  
1, 2  
θJA  
Junction to Board (Bottom)  
Junction to Case (Top)  
NOTES:  
R
R
17  
9
°C/W  
°C/W  
3
4
θJB  
θJC  
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient  
temperature, air flow, board population, and board thermal resistance.  
2. Per SEMI G38–87.  
3. Indicates the average thermal resistance between the die and the printed circuit board.  
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
10  
PACKAGE THERMAL CHARACTERISTICS — PBGA  
Rating  
Symbol  
Max  
Unit  
Notes  
Junction to Ambient (@ 200 lfm)  
Single–Layer Board  
Four–Layer Board  
R
38  
22  
°C/W  
1, 2  
θJA  
Junction to Board (Bottom)  
Junction to Case (Top)  
NOTES:  
R
R
14  
5
°C/W  
°C/W  
3
4
θJB  
θJC  
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient  
temperature, air flow, board population, and board thermal resistance.  
2. Per SEMI G38–87.  
3. Indicates the average thermal resistance between the die and the printed circuit board.  
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).  
DC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 2.5 V I/O SUPPLY  
(Voltages Referenced to V  
= 0 V)  
Parameter  
SS  
Symbol  
Min  
3.135  
2.375  
– 0.3  
1.7  
Typ  
3.3  
2.5  
—
Max  
3.465  
2.9  
Unit  
V
Supply Voltage  
V
DD  
I/O Supply Voltage  
Input Low Voltage  
Input High Voltage  
V
DDQ  
V
V
IL  
0.7  
V
V
IH  
—
V
+ 0.3  
V
DD  
Input High Voltage I/O Pins  
V
IH2  
1.7  
—
V
DDQ  
+ 0.3  
V
Output Low Voltage (I  
= 2 mA)  
V
OL  
—
—
0.7  
V
OL  
Output High Voltage (I  
= – 2 mA)  
V
OH  
1.7  
—
—
V
OL  
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS: 3.3 V I/O SUPPLY  
(Voltages Referenced to V  
= 0 V)  
SS  
Parameter  
Symbol  
Min  
3.135  
3.135  
– 0.5  
2
Typ  
3.3  
3.3  
—
Max  
Unit  
V
Supply Voltage  
V
DD  
3.465  
I/O Supply Voltage  
Input Low Voltage  
Input High Voltage  
V
DDQ  
V
DD  
V
V
IL  
0.8  
V
V
IH  
—
V
+ 0.5  
V
DD  
Input High Voltage I/O Pins  
V
IH2  
2
—
V
DDQ  
+ 0.5  
V
Output Low Voltage (I  
= 8 mA)  
V
OL  
—
—
0.4  
V
OL  
Output High Voltage (I  
= – 4 mA)  
V
OH  
2.4  
—
—
V
OL  
V
IH  
V
SS  
V
SS  
– 1.0 V  
20% t  
KHKH  
(MIN)  
Figure 1. Undershoot Voltage  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
11  
SUPPLY CURRENTS  
Parameter  
Input Leakage Current (0 V ≤ V ≤ V  
Symbol  
Min  
—
Typ  
—
Max  
± 1  
Unit  
µA  
Notes  
)
I
lkg(I)  
1
in  
DD  
Output Leakage Current (0 V ≤ V ≤ V  
)
I
lkg(O)  
—
—
± 1  
µA  
in  
DDQ  
AC Supply Current (Device Selected,  
All Outputs Open, Freq = Max)  
MCM63P737/819–166  
MCM63P737/819–150  
MCM63P737/819–133  
I
—
—
500/430  
470/400  
450/380  
mA  
2, 3, 4  
DDA  
Includes V  
Only  
DD  
CMOS Standby Supply Current (Device Deselected, Freq = 0,  
= Max, All Inputs Static at CMOS Levels)  
I
—
—
—
—
15  
mA  
mA  
5, 6  
SB2  
V
DD  
Sleep Mode Supply Current (Device Deselected, Freq = Max,  
= Max, All Other Inputs Static at CMOS Levels,  
I
5
1, 5, 6  
ZZ  
V
DD  
ZZ ≥ V  
– 0.2 V)  
DD  
TTL Standby Supply Current (Device Deselected, Freq = 0,  
= Max, All Inputs Static at TTL Levels)  
I
—
—
—
—
35  
mA  
mA  
5, 7  
5, 6  
SB3  
V
DD  
Clock Running (Device Deselected,  
Freq = Max, V = Max, All Inputs  
MCM63P737/819–166  
MCM63P737/819–150  
MCM63P737/819–133  
I
185/170  
175/160  
160/145  
SB4  
DD  
Toggling at CMOS Levels)  
Static Clock Running (Device Deselected, MCM63P737/819–166  
I
—
—
75/65  
70/60  
65/55  
mA  
5, 7  
SB5  
Freq = Max,V  
DD  
= Max, All Inputs  
MCM63P737/819–150  
MCM63P737/819–133  
Static at TTL Levels)  
NOTES:  
1. LBO and ZZ pins have an internal pull–up and pull–down, respectively; and will exhibit leakage currents of ± 5 µA.  
2. Reference AC Operating Conditions and Characteristics for input and timing.  
3. All addresses transition simultaneously low (LSB) then high (MSB).  
4. Data states are all zero.  
5. Device is deselected as defined by the Truth Table.  
6. CMOS levels for I/Os are V ≤ V  
7. TTL levels for I/Os are V ≤ V or ≥ V  
IT IL  
+ 0.2 V or ≥ V  
. TTL levels for other inputs are V ≤ V or ≥ V  
IH2 in IL  
– 0.2 V. CMOS levels for other inputs are V ≤ V  
in  
+ 0.2 V or ≥ V – 0.2 V.  
DD  
IT  
SS  
DDQ  
SS  
IH.  
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)  
A
Parameter  
Symbol  
Min  
—
Typ  
4
Max  
5
Unit  
pF  
Input Capacitance  
C
in  
Input/Output Capacitance  
C
—
7
8
pF  
I/O  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
12  
AC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)  
DD  
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V  
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V  
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%)  
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V  
Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted  
READ/WRITE CYCLE TIMING (See Notes 1 and 2)  
MCM63P737–166 MCM63P737–150 MCM63P737–133  
MCM63P819–166 MCM63P819–150 MCM63P819–133  
Parameter  
Symbol  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Notes  
Min  
6
Max  
—
Min  
6.7  
2.6  
2.6  
—
Max  
—
Min  
7.5  
3
Max  
—
Cycle Time  
t
KHKH  
Clock High Pulse Width  
Clock Low Pulse Width  
Clock Access Time  
t
2.4  
2.4  
—
—
—
—
3
3
KHKL  
KLKH  
KHQV  
t
—
—
3
—
t
3.5  
3.5  
—
3.8  
3.5  
—
—
—
0
4
Output Enable to Output Valid  
Clock High to Output Active  
Clock High to Output Change  
Output Enable to Output Active  
Output Disable to Q High–Z  
Clock High to Q High–Z  
Setup Times:  
t
—
—
3.8  
—
GLQV  
t
t
0
0
4, 5  
4
KHQX1  
1.5  
0
—
1.5  
0
—
1.5  
0
—
KHQX2  
t
—
—
—
4, 5  
4, 5  
4, 5  
GLQX  
t
—
3.5  
3.5  
—
—
3.5  
3.5  
—
—
1.5  
1.5  
3.8  
3.5  
—
GHQZ  
t
1.5  
1.5  
1.5  
1.5  
KHQZ  
ADKH  
Address  
t
ADSP, ADSC, ADV  
Data In  
t
ADSKH  
DVKH  
t
Write  
Chip Enable  
t
WVKH  
t
EVKH  
Hold Times:  
NOTES:  
Address  
ADSP, ADSC, ADV  
Data In  
t
0.5  
—
0.5  
—
0.5  
—
ns  
KHAX  
t
KHADSX  
t
KHDX  
Write  
Chip Enable  
t
KHWX  
t
KHEX  
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP  
or ADSC is asserted.  
2. All read and write cycle timings are referenced from K or G.  
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between  
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V  
/2. In some  
DDQ  
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is  
given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.  
4. This parameter is sampled and not 100% tested.  
5. Measured at ± 200 mV from steady state.  
OUTPUT  
Z = 50 Ω  
0
R = 50 Ω  
L
1.5 V  
Figure 2. AC Test Load  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
13  
2400  
2200  
2000  
1800  
1600  
1400  
OUTPUT  
1200  
1000  
800  
C
L
600  
400  
200  
0
0
20  
40  
60  
80  
100  
LUMPED CAPACITANCE, C (pF)  
L
Figure 3. Lumped Capacitive Load and Typical Derating Curve  
OUTPUT LOAD  
OUTPUT  
TEST POINT  
BUFFER  
UNLOADED RISE AND FALL TIME MEASUREMENT  
2.4  
2.4  
0.6  
INPUT  
WAVEFORM  
0.6  
2.4  
2.4  
0.6  
OUTPUT  
WAVEFORM  
0.6  
t
r
t
f
NOTES:  
1. Input waveform has a slew rate of 1 V/ns.  
2. Rise time is measured from 0.6 to 2.4 V unloaded.  
3. Fall time is measured from 2.4 to 0.6 V unloaded.  
Figure 4. Unloaded Rise and Fall Time Characterization  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
14  
2.9  
2.5  
2.3  
2.1  
PULL–UP  
VOLTAGE (V)  
I (mA) MIN  
I (mA) MAX  
– 0.5  
0
– 38  
– 38  
– 38  
– 26  
– 105  
– 105  
– 105  
– 83  
0.8  
1.25  
1.25  
0.8  
1.5  
2.3  
2.7  
2.9  
– 20  
0
– 70  
– 30  
– 10  
0
0
0
0
0
– 38  
CURRENT (mA)  
– 105  
(a) Pull–Up for 2.5 V I/O Supply  
3.6  
3.135  
2.8  
PULL–UP  
VOLTAGE (V)  
I (mA) MIN  
I (mA) MAX  
– 0.5  
0
– 50  
– 50  
– 50  
– 46  
– 150  
– 150  
– 150  
– 130  
1.65  
1.4  
1.4  
1.65  
2.0  
3.135  
3.6  
– 35  
0
– 101  
– 25  
0
0
0
0
– 50  
– 100  
– 150  
CURRENT (mA)  
(b) Pull–Up for 3.3 V I/O Supply  
V
DD  
PULL–DOWN  
VOLTAGE (V)  
I (mA) MIN  
I (mA) MAX  
– 0.5  
0
0
0
0
0
1.6  
0.4  
0.8  
10  
20  
20  
40  
1.25  
1.25  
1.6  
31  
40  
40  
63  
80  
80  
2.8  
0.3  
0
3.2  
3.4  
40  
40  
80  
80  
0
40  
CURRENT (mA)  
80  
(c) Pull–Down  
Figure 5. Typical Output Buffer Characteristics  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
15  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
16  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
17  
APPLICATION INFORMATION  
SLEEP MODE  
current (I ). All inputs are allowed to toggle — the RAM will  
ZZ  
not be selected and perform any reads or writes. However, if  
A sleep mode feature, the ZZ pin, has been implemented  
on the MCM63P737 and MCM63P819. It allows the system  
designer to place the RAM in the lowest possible power  
condition by asserting ZZ. The sleep mode timing diagram  
shows the different modes of operation: Normal Operation,  
No READ/WRITE Allowed, and Sleep Mode. Each mode has  
its own set of constraints and conditions that are allowed.  
Normal Operation: All inputs must meet setup and hold  
inputs toggle, the I (max) specification will not be met.  
Note: It is invalid to go from stop clock mode directly into  
sleep mode.  
ZZ  
NON–BURST SYNCHRONOUS OPERATION  
Although this BurstRAM has been designed for PowerPC–  
and other high end MPU–based systems, these SRAMs can  
be used in other high speed L2 cache or memory applica-  
tions that do not require the burst address feature. Most L2  
caches designed with a synchronous interface can make use  
of the MCM63P737 and MCM63P819. The burst counter  
feature of the BurstRAMs can be disabled, and the SRAMs  
can be configured to act upon a continuous stream of ad-  
dresses. See Figure 6.  
times prior to sleep and t  
nanoseconds after re-  
ZZREC  
covering from sleep. Clock (K) must also meet cycle, high,  
and low times during these periods. Two cycles prior to  
sleep, initiation of either a read or write operation is not  
allowed.  
No READ/WRITE: During the period of time just prior to  
sleep and during recovery from sleep, the assertion of either  
ADSC, ADSP, or any write signal is not allowed. If a write  
operation occurs during these periods, the memory array  
may be corrupted. Validity of data out from the RAM can not  
be guaranteed immediately after ZZ is asserted (prior to  
being in sleep).  
Sleep Mode: The RAM automatically deselects itself. The  
RAM disconnects its internal clock buffer. The external clock  
may continue to run without impacting the RAMs sleep  
CONTROL PIN TIE VALUES EXAMPLE (H ≥ V , L ≤ V  
IH  
)
IL  
Non–Burst  
ADSP ADSC ADV SE1 SE2 LBO  
Sync Non–Burst,  
Pipelined SRAM  
H
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin  
must be tied either high or low.  
K
ADDR  
SE3  
A
B
C
D
E
F
G
H
W
G
DQ  
Q(A)  
Q(B)  
Q(C)  
Q(D)  
D(E)  
D(F)  
D(G)  
D(H)  
READS  
WRITES  
Figure 6. Example Configuration as Non–Burst Synchronous SRAM  
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
18  
ORDERING INFORMATION  
(Order by Full Part Number)  
63P737  
MCM  
63P819  
XX  
X
X
Motorola Memory Prefix  
Part Number  
Blank = Trays, R = Tape and Reel  
Speed (166 = 166 MHz, 150 = 150 MHz,  
133 = 133 MHz)  
Package (TQ = TQFP, ZP = PBGA)  
Full Part Numbers — MCM63P737TQ166  
MCM63P737TQ166R MCM63P737TQ150R MCM63P737TQ133R  
MCM63P737ZP166 MCM63P737ZP150 MCM63P737ZP133  
MCM63P737ZP166R MCM63P737ZP150R MCM63P737ZP133R  
MCM63P737TQ150  
MCM63P737TQ133  
MCM63P819TQ166  
MCM63P819TQ166R MCM63P819TQ150R MCM63P819TQ133R  
MCM63P819ZP166 MCM63P819ZP150 MCM63P819ZP133  
MCM63P819ZP166R MCM63P819ZP150R MCM63P819ZP133R  
MCM63P819TQ150  
MCM63P819TQ133  
MCM63P737•MCM63P819  
19  
MOTOROLA FAST SRAM  
PACKAGE DIMENSIONS  
TQ PACKAGE  
TQFP  
CASE 983A–01  
4X  
e
0.20 (0.008) H A–B  
D
2X 30 TIPS  
e/2  
0.20 (0.008) C A–B  
D
–D–  
80  
51  
B
B
50  
81  
–X–  
E/2  
X=A, B, OR D  
–A–  
–B–  
VIEW Y  
BASE  
METAL  
E1  
E
PLATING  
b1  
E1/2  
c1  
c
31  
100  
1
30  
b
D1/2  
D/2  
M
S
S
0.13 (0.005)  
C A–B  
D
D1  
D
SECTION B–B  
NOTES:  
2X 20 TIPS  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
0.20 (0.008) C A–B  
D
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF  
LEAD AND IS COINCIDENT WITH THE LEAD  
WHERE THE LEAD EXITS THE PLASTIC BODY AT  
THE BOTTOM OF THE PARTING LINE.  
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED  
AT DATUM PLANE –H–.  
A
q2  
0.10 (0.004) C  
–H–  
5. DIMENSIONS D AND E TO BE DETERMINED AT  
SEATING PLANE –C–.  
–C–  
SEATING  
PLANE  
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD  
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25  
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO  
INCLUDE MOLD MISMATCH AND ARE  
DETERMINED AT DATUM PLANE –H–.  
7. DIMENSION b DOES NOT INCLUDE DAMBAR  
PROTRUSION. DAMBAR PROTRUSION SHALL  
NOT CAUSE THE b DIMENSION TO EXCEED 0.45  
(0.018).  
q3  
VIEW AB  
S
0.05 (0.002)  
S
q1  
R2  
MILLIMETERS  
INCHES  
MIN  
–––  
DIM MIN  
MAX  
MAX  
0.063  
0.006  
0.057  
0.015  
0.013  
0.008  
0.006  
0.25 (0.010)  
A
A1  
A2  
b
b1  
c
c1  
D
D1  
E
E1  
e
L
L1  
L2  
S
R1  
R2  
q
–––  
0.05  
1.35  
0.22  
0.22  
0.09  
0.09  
1.60  
GAGE PLANE  
0.15 0.002  
1.45 0.053  
0.38 0.009  
0.33 0.009  
0.20 0.004  
0.16 0.004  
A2  
L2  
L
R1  
A1  
22.00 BSC  
20.00 BSC  
16.00 BSC  
14.00 BSC  
0.65 BSC  
0.866 BSC  
q
0.787 BSC  
0.630 BSC  
0.551 BSC  
0.026 BSC  
0.030  
0.039 REF  
0.020 REF  
L1  
VIEW AB  
0.45  
1.00 REF  
0.50 REF  
0.20  
0.75 0.018  
––– 0.008  
–––  
–––  
0.008  
7
–––  
13  
0.08  
0.08  
0
––– 0.003  
0.20 0.003  
7
–––  
13  
0
0
11  
11  
_
_
_
_
_
_
_
q1  
q2  
q3  
0
11  
11  
_
_
_
_
_
13  
13  
_
_
MCM63P737•MCM63P819  
MOTOROLA FAST SRAM  
20  
ZP PACKAGE  
7 x 17 BUMP PBGA  
CASE 999–02  
0.20  
4X  
119X  
b
B
D
M
0.3  
A B C  
A
E
C
NOTES:  
M
0.15  
1. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
7
6 5 4 3 2 1  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
2. ALL DIMENSIONS IN MILLIMETERS.  
3. DIMENSION b IS THE MAXIMUM SOLDER BALL  
DIAMETER MEASURED PARALLEL TO DATUM A.  
4. DATUM A, THE SEATING PLANE, IS DEFINED BY  
THE SPHERICAL CROWNS OF THE SOLDER  
BALLS.  
D1  
D2  
MILLIMETERS  
DIM MIN  
MAX  
2.40  
0.70  
1.70  
1.00  
A
A1  
A2  
A3  
D
–––  
0.50  
1.30  
0.80  
16X e  
22.00 BSC  
20.32 BSC  
D1  
6X  
e
E2  
D2 19.40 19.60  
E1  
E
E1  
14.00 BSC  
7.62 BSC  
TOP VIEW  
BOTTOM VIEW  
E2 11.90 12.10  
b
e
0.60  
1.27 BSC  
0.90  
0.25 A  
0.35 A  
A3  
A2  
0.20 A  
A
SEATING  
PLANE  
SIDE VIEW  
A1  
A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and  
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola  
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”  
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of  
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other  
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury  
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola  
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
Motorola was negligent regarding the design or manufacture of the part. Motorola and  
Opportunity/Affirmative Action Employer.  
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal  
Mfax is a trademark of Motorola, Inc.  
How to reach us:  
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;  
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488  
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,  
– US & Canada ONLY 1-800-774-1848 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong.  
JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,  
Motorola Fax Back System  
– http://sps.motorola.com/mfax/  
852-26629298  
HOME PAGE: http://motorola.com/sps/  
CUSTOMER FOCUS CENTER: 1-800-521-6274  
MCM63P737/D  
◊

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