MCM64Z836TQ225 [MOTOROLA]
ZBT SRAM, 256KX36, 2.6ns, CMOS, PQFP100, TQFP-100;
| 型号： | MCM64Z836TQ225 |
| 厂家： | 
MOTOROLA |
| 描述： | ZBT SRAM, 256KX36, 2.6ns, CMOS, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总31页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM64Z836/D
SEMICONDUCTOR TECHNICAL DATA
MCM64Z836
MCM64Z918
Product Proposal
256K x 36 and 512K x 18
Bit Pipelined ZBT RAM
Synchronous Fast Static RAM
The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide
Zero Bus Turnaround . The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM64Z836 (organized as
256K words by 36 bits) and the MCM64Z918 (organized as 512K words by 18
bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-
nology. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in communication applications. Synchronous design allows precise cycle
control with the use of an external positive–edge–triggered clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
TQ PACKAGE
TQFP
CASE 983A–01
ZP PACKAGE
PBGA
CASE 999–02
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled
through positive–edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Forreadcycles, pipelinedSRAMoutputdataistemporarilystoredbyanedge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
•
•
2.5 V LVTTL and LVCMOS Compatible
MCM64Z836/918–225 = 2.6 ns Access/4.4 ns Cycle (225 MHz)
MCM64Z836/918–200 = 3.2 ns Access/5 ns Cycle (200 MHz)
MCM64Z836/918–166 = 3.6 ns Access/6 ns Cycle (166 MHz)
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Sleep Mode (ZZ)
Two–Cycle Deselect
Byte Write Control
ADV Controlled Burst
•
•
•
•
•
•
•
•
IEEE 1149–1 Sample Only JTAG
100–Pin TQFP and 119–Bump PBGA Packages
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
6/2/99
Motorola, Inc. 1999
LOGIC BLOCK DIAGRAM
LBO
SA
BURST
ADDRESS
COUNTER
ADDRESS
REGISTER
MEMORY
ARRAY
DATA–IN
REGISTER
K
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CK
CONTROL
LOGIC
K
CKE
DATA–IN
REGISTER
SE1
SE2
SE3
CONTROL
REGISTER
ADV
SW
CONTROL
LOGIC
K
DATA–OUT
REGISTER
SBx
G
ZZ
36 OR 18
DQ
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
2
MCM64Z836 PIN ASSIGNMENTS
1
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
B
C
D
E
DQc
DQc
DQc
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
V
SA
SA
NC
SA
SA
V
DDQ
DDQ
2
3
4
5
6
7
8
9
NC
SE2
SA
SA
SA
ADV
SA
SA
SE3
SA
NC
V
V
V
V
DDQ
DDQ
SS
NC
V
NC
V
DD
SS
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
DQc
DQc
DQc
DQc
DQc
V
NC
SE1
G
V
DQb DQb
DQb DQb
SS
SS
SS
SS
SS
SS
V
V
V
V
F
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
SS
V
DQb
V
DDQ
DDQ
V
DDQ
DQc
DQc
DDQ
G
DQb
DQb
DQc
DQc
DQc
SBc
SA
SBb
DQb DQb
DQb DQb
H
V
V
V
V
V
DD
DD
SS
DD
DD
DQc
V
SW
V
SS
SS
J
K
L
V
V
DQd
DQd
V
V
NC
V
NC
V
V
DDQ
DD
SS
DDQ
DD
DD
DD
ZZ
DQa
DQa
DQd
DQd
V
CK
V
DQa DQa
DQa DQa
SS
SS
DQd
DQd SBd
NC
SBa
V
V
V
V
DDQ
DDQ
SS
M
N
P
V
SS
V
DQd
V
CKE
V
DQa
V
DDQ
DDQ
DQd
DQd
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQa
DQa
DQd
DQd
SA
V
SA1
SA0
V
DQa DQa
DQa DQa
SS
SS
SS
SS
DD
V
V
V
V
V
SS
SS
DDQ
R
T
DDQ
DQd
DQd
DQd
V
LBO
V
V
SA
NC
NC
DD
DD
DQa
DQa
DQa
NC
NC
SA
SA
SA
ZZ
U
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
TMS
TDI
TCK
TDO TRST V
DDQ
DDQ
100–PIN TQFP
TOP VIEW
119–BUMP PGBA
TOP VIEW
Not to Scale
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
3
MCM64Z836 TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
87
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
CKE
DQx
Input
I/O
Clock Enable: Disables the CK input when CKE is high.
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86
31
G
Input
Input
Asynchronous Output Enable.
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49,
50, 81, 82, 83, 99, 100
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
37, 36
SA0, SA1
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b,
c, d) in conjunction with SW. Has no effect on read cycles.
98
97
92
88
SE1
SE2
SE3
SW
Input
Input
Input
Input
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
64
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
14, 15, 16, 41, 65, 66, 91
4, 11, 20, 27, 54, 61, 70, 77
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
V
DDQ
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
38, 39, 42, 43, 84
NC
—
No Connection: There is no connection to the chip.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
4
MCM64Z836 PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
4B
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
4K
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
4M
CKE
DQx
Input
I/O
Clock Enable: Disables the CK input when CKE is high.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
4F
3R
G
Input
Input
Asynchronous Output Enable.
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 3T, 4T, 5T
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
5L, 5G, 3G, 3L
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b,
c, d) in conjunction with SW. Has no effect on read cycles.
4E
2B
6B
4H
SE1
SE2
SE3
SW
Input
Input
Input
Input
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
4U
TCK
Input
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to V
or V
.
SS
DD
3U
5U
2U
6U
TDI
TDO
TMS
TRST
Boundary Scan Pin, Test Data In.
Output Boundary Scan Pin, Test Data Out.
Input
Input
Boundary Scan Pin, Test Mode Select.
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to V
.
SS
7T
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4C, 2J, 4J, 6J, 1R, 4R, 5R
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
DDQ
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
V
SS
4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 7R,
1T, 2T, 6T
NC
—
No Connection: There is no connection to the chip.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
5
MCM64Z918 PIN ASSIGNMENTS
1
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A
B
C
D
E
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SA
NC
NC
V
SA
SA
NC
SA
SA
V
DDQ
DDQ
2
3
4
5
6
7
8
9
NC
SE2
SA
SA
SA
ADV
SA
SA
SE3
SA
NC
V
V
V
V
NC
DDQ
DDQ
SS
V
NC
V
NC
SS
DD
NC
NC
DQb
NC
NC
DQb
NC
V
NC
SE1
G
V
DQa
NC
NC
DQa
DQa
DQa
SS
SS
SS
SS
SS
SS
DQb
DQb
V
V
V
V
V
V
DQa
F
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
SS
V
DQa
V
DDQ
DDQ
V
DDQ
DQb
DQb
DDQ
G
DQa
DQa
NC
DQb
NC
SBb
SA
NC
DQa
SS
SS
H
V
V
V
V
V
DD
DD
SS
DD
DD
DQb
V
SW
DQa
NC
SS
J
K
L
V
V
V
NC
V
NC
V
V
DD
DDQ
DD
DD
DD
DDQ
V
DQb
DQb
ZZ
DQa
SS
NC
DQb
NC
V
CK
NC
V
NC
DQa
NC
DQa
SS
SS
SS
SS
SS
SS
DQa
V
V
DQb
V
V
V
V
SBa
NC
DDQ
DDQ
SS
M
N
P
V
V
SS
V
DQb
NC
CKE
SA1
SA0
V
V
DQb
DQb
DQb
NC
DQa
DQa
NC
DDQ
SS
DDQ
DQb
V
V
DQa
NC
NC
SS
SS
DD
NC
NC
DQb
SA
DQa
NC
ZZ
V
V
V
SS
SS
DDQ
R
T
V
DDQ
NC
NC
NC
V
LBO
SA
V
V
SA
DD
DD
NC
NC
NC
NC
SA
NC
SA
SA
U
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
V
TMS
TDI
TCK
TDO TRST V
DDQ
DDQ
100–PIN TQFP
TOP VIEW
119–BUMP PGBA
TOP VIEW
Not to Scale
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
6
MCM64Z918 TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
87
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
CKE
DQx
Input
I/O
Clock Enable: Disables the CK input when CKE is high.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86
31
G
Input
Input
Asynchronous Output Enable.
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
32, 33, 34, 35, 44, 45, 46, 47, 48, 49,
50, 80, 81, 82, 83, 99, 100
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
37, 36
SA0, SA1
Synchronous Burst Address Inputs: The two LSBs of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in
conjunction with SW. Has no effect on read cycles.
98
97
92
88
SE1
SE2
SE3
SW
Input
Input
Input
Input
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
64
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
14, 15, 16, 41, 65, 66, 91
4, 11, 20, 27, 54, 61, 70, 77
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
V
DDQ
5, 10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
V
SS
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39,
42, 43, 51, 52, 53, 56, 57, 75, 78,
79, 84, 95, 96
NC
—
No Connection: There is no connection to the chip.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
7
MCM64Z918 PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
4B
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
4K
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
4M
CKE
DQx
Input
I/O
Clock Enable: Disables the CK input when CKE is high.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
4F
3R
G
Input
Input
Asynchronous Output Enable.
LBO
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in
conjunction with SW. Has no effect on read cycles.
4E
2B
6B
4H
SE1
SE2
SE3
SW
Input
Input
Input
Input
Synchronous Chip Enable: Active low to enable chip.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
4U
TCK
Input
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to V
or V
.
SS
DD
3U
5U
2U
6U
TDI
TDO
TMS
TRST
Boundary Scan Pin, Test Data In.
Output Boundary Scan Pin, Test Data Out.
Input
Input
Boundary Scan Pin, Test Mode Select.
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to V
.
SS
7T
ZZ
Input
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4C, 2J, 4J, 6J, 1R, 4R, 5R
V
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
DD
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
DDQ
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N,
3P, 5P
V
SS
NC
4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K,
6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P,
7R, 1T, 4T
—
No Connection: There is no connection to the chip.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
8
TRUTH TABLE
SA0 –
SAx
Input
Command Code
CK
L–H
L–H
L–H
CKE
E
X
SW
X
SBx
X
ADV
Next Operation
Notes
1, 2
1
0
0
X
0
0
X
X
V
Hold
H
D
False
True
X
X
Deselect
1, 2
0
V
Load Address, New Write
W
1, 2, 3,
4, 5
L–H
L–H
0
0
True
X
1
X
0
1
V
X
Load Address, New Read
R
B
1, 2
V (W)
X (R, D)
Burst
X
1, 2, 4,
6, 7
Continue
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deselect cycle.
ASYNCHRONOUS TRUTH TABLE
Operation
Read
ZZ
L
G
L
I/O Status
Data Out (DQx)
High–Z
Read
L
H
X
X
X
Write
L
High–Z
Deselected
Sleep
L
High–Z
H
High–Z
WRITE TRUTH TABLE
SBc
SBd
(See Note 1)
(See Note 1)
Cycle Type
SW
H
L
SBa
X
SBb
X
Read
X
H
H
L
X
H
H
H
L
Write Byte a
L
H
Write Byte b
L
H
L
Write Byte c (See Note 1)
Write Byte d (See Note 1)
Write All Bytes
L
H
H
L
H
H
H
L
L
L
L
L
NOTE:
1. Valid only for x36.
LINEAR BURST ADDRESS TABLE (LBO = V
)
SS
1st Address (External)
X . . . X00
2nd Address (Internal)
X . . . X01
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = V
)
DD
2nd Address (Internal)
1st Address (External)
X . . . X00
3rd Address (Internal)
X . . . X10
4th Address (Internal)
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X01
X . . . X11
X . . . X10
X . . . X10
X . . . X00
X . . . X01
X . . . X11
X . . . X01
X . . . X00
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
9
INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
INPUT
COMMAND
CODE
D
B
W
B
R
B
H
CONTINUE
DESELECT
BURST
WRITE
BURST
READ
DESELECT
NEW WRITE
NEW READ
HOLD
CK
CKE
E
FALSE
TRUE
VALID
TRUE
VALID
SA0 – SAx
ADV
SW
SBX
VALID
VALID
NOTE: Cycles are named for their control inputs, not for data I/O state.
MCM64Z836•MCM64Z918
10
MOTOROLA FAST SRAM
B
B
BURST
READ
BURST
WRITE
D
D
W
W
R
R
B
B
D
D
NEW
READ
NEW
WRITE
R
R
W
W
B
R
W
DESELECT
D
KEY:
CURRENT
STATE (n)
NEXT
STATE (n + 1)
TRANSITION
ƒ
NOTES:
1. Input command codes (D, W, R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
INPUT
COMMAND
CODE
Figure 1. ZBT RAM State Diagram
STATE
CK
n
n + 1
n + 2
n + 3
COMMAND
CODE
ƒ
DQ
CURRENT
STATE
NEXT
STATE
Figure 2. State Definitions for ZBT RAM State Diagram
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
11
INTERMEDIATE
D
B
HIGH–Z
R
W
INTERMEDIATE
INTERMEDIATE
D
W
R
D
B
B
W
DATA OUT
(Q VALID)
HIGH–Z
(DATA IN)
INTERMEDIATE
INTERMEDIATE
R
INTERMEDIATE
KEY:
INTERMEDIATE
STATE (n + 1)
CURRENT
STATE (n)
NEXT STATE
(n + 2)
TRANSITION
TRANSITION
NOTES:
ƒ
1. Inputcommand codes (D, W, R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
INPUT
COMMAND
CODE
Figure 3. Data I/O State Diagram
STATE
n
n + 1
n + 2
n + 3
CK
COMMAND
CODE
ƒ
DQ
STATE NAME
CURRENT
STATE
INTERMEDIATE
STATE
NEXT
STATE
Figure 4. State Definitions for I/O State Diagrams
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
12
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 2.5 V ± 5%, T = 0 to 70°C Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to V
= 0 V)
SS
Parameter
Symbol
Min
Typ
2.5
2.5
—
Max
2.625
2.625
0.7
Unit
V
Supply Voltage
V
DD
2.375
2.375
– 0.3
1.7
I/O Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage (I
V
DDQ
V
V
IL
V
V
IH
—
V
+ 0.3
V
DDQ
= 8 mA)
V
—
—
0.7
—
V
OL
OL
Output High Voltage (I
= – 8 mA)
V
OH
1.7
—
V
OH
V
IH
V
SS
V
– 1.0 V
SS
20% t
(MIN)
KHKH
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
—
Typ
—
Max
± 1
Unit
Notes
Input Leakage Current (0 V ≤ V ≤ V
in
)
I
µA
µA
1
DD
lkg(I)
Output Leakage Current (0 V ≤ V ≤ V
in
)
I
—
—
± 1
DDQ
lkg(O)
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both V and V
I
I
I
–225
–200
–166
—
—
—
—
—
—
300
290
280
mA
2, 3, 4
DDA
DDA
DDA
DD
DDQ
CMOS Standby Supply Current (Device Deselected, Freq = 0,
= Max, V = Max, All Inputs Static at CMOS Levels)
I
—
—
10
mA
mA
5, 6
SB2
V
DD
Sleep Mode Supply Current (Device Deselected, Freq = Max,
= Max, All Other Inputs Static at CMOS Levels,
DDQ
I
—
—
TBD
1, 5, 6
ZZ
V
DD
ZZ ≥ V
– 0.2 V)
DD
Clock Running (Device Deselected, Freq = Max, V
All Inputs Toggling at CMOS Levels)
= Max,
I
I
I
–225
–200
–166
—
—
—
—
—
—
100
100
90
mA
mA
5, 7
6
DD
SB4
SB4
SB4
Hold Supply Current (Device Selected, Freq = Max,
= Max, V = Max, CKE ≥ V – 0.2 V,
I
—
—
15
DD1
V
DD
DDQ
DD
All Inputs Static at CMOS Levels)
NOTES:
1. LBO and ZZ pins have an internal pullup and will exhibit leakage currents of ± 5 µA.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the Truth Table.
6. CMOS levels for I/Os are V ≤ V
7. TTL levels for I/Os are V ≤ V or ≥ V
IT IL
+ 0.2 V or ≥ V
. TTL levels for other inputs are V ≤ V or ≥ V .
IH2 in IL
– 0.2 V. CMOS levels for other inputs are V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V.
DD
IT
SS
DDQ
SS
IH
CAPACITANCE (f = 1.0 MHz, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Min
—
Typ
4
Max
5
Unit
pF
Input Capacitance
C
in
Input/Output Capacitance
C
—
7
8
pF
I/O
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
13
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 2.5 V ± 5%, T = 0 to 70°C Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . 1 ns (20% to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V
Output Load . . . . . . . . . . . . . . See Figure 6 Unless Otherwise Noted
R
Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
θJA
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM64Z836–225
MCM64Z918–225
225 MHz
MCM64Z836–200
MCM64Z918–200
200 MHz
MCM64Z836–166
MCM64Z918–166
166 MHz
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
4.4
1.7
1.7
—
Max
—
Min
5
Max
—
—
—
3
Min
6
Max
—
Cycle Time
t
KHKH
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
t
—
2
2.4
2.4
—
—
0.8
0.7
0
—
3
3
KHKL
KLKH
KHQV
t
—
2
—
t
2.6
2.6
—
—
—
0.8
0.7
0
3.6
3.6
—
Output Enable to Output Valid
Clock High to Output Active
Output Hold Time
t
—
3
GLQV
t
0.8
0.7
0
—
—
—
3
4, 5
4
KHQX1
t
—
—
KHQX
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
t
—
—
4, 5
4, 5
4, 5
GLQX
GHQZ
t
—
2.3
2.4
—
—
1
—
1
3.5
3
t
0.8
2.5
—
KHQZ
ADKH
Setup Times:
Hold Times:
NOTES:
Address
ADV
Data In
t
1.3
1.3
1.2
1.3
1.3
1.3
1.3
1.3
1.2
1.3
1.3
1.3
1.3
1.3
1.2
1.3
1.3
1.3
—
t
t
LVKH
DVKH
Write
t
WVKH
Chip Enable
Clock Enable
t
t
EVKH
CVKH
Address
ADV
Data In
t
t
0.5
—
0.5
—
0.5
—
ns
KHAX
KHLX
t
KHDX
Write
t
KHWX
Chip Enable
Clock Enable
t
t
KHEX
KHCX
1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low, SE2 high, and SB3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V /2. In some
DDQ
designexercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC test conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at ± 200 mV from steady state.
OUTPUT
Z
= 50 Ω
0
R
= 50 Ω
L
1.25 V
Figure 6. AC Test Loads
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
14
t
KHKH
t
t
KLKH
KHKL
CK
t
AVKH
t
t
KHAX
SA0 – SAx
t
t
WVKH
WVKH
KHWX
SW
t
t
KHWX
SBx
E
t
EVKH
KHEX
t
LVKH
t
t
KHLX
ADV
CKE
t
CVKH
KHCX
G
t
GLQX
t
t
GLQV
GHQZ
DQ
Q
t
DVKH
t
KHDX
DQ
DQ
D
t
t
KHQV
KHQX
t
t
KHQZ
KHQX1
Q
Q
NOTE: E is true if SE1 = SE3 = low and SE2 = high.
t
t
,t
,andt
onlyapplyifGistoggled.IfGistiedlow
GLQX GLQV
GHQZ
, and t
, t
apply.
KHQX KHQV
KHQZ
Figure 7. AC Timing Parameter Definitions
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
15
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
16
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
17
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
18
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
19
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
20
APPLICATION INFORMATION
SLEEP MODE
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of any
write signal is not allowed. If a write operation occurs during
these periods, the memory array may be corrupted. Validity
of data out from the RAM can not be guaranteed immediately
after ZZ is asserted (prior to being in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep
A sleep mode feature, the ZZ pin, has been implemented
on the MCM64Z836 and MCM64Z918. It allows the system
designer to place the RAM in the lowest possible power
condition by asserting ZZ. The sleep mode timing diagram
shows the different modes of operation: Normal Operation,
No READ/WRITE Allowed, and Sleep Mode. Each mode has
its own set of constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
current (I ). All inputs are allowed to toggle — the RAM will
ZZ
times prior to sleep and t
nanoseconds after re-
not be selected and perform any reads or writes. However, if
ZZREC
covering from sleep. Clock (K) must also meet cycle high and
low times during these periods. Two cycles prior to sleep, ini-
tiation of either a read or write operation is not allowed.
inputs toggle, the I (max) specification will not be met.
ZZ
Note: It is invalid to go from stop clock mode directly into
sleep mode.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
21
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
TAPs operation) and can be expected to function in a manner
that does not conflict with the operation of devices with IEEE
Standard 1149.1 compliant TAPs. The TAP operates using a
3.3 V tolerant logic level signaling.
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TRST should be tied low and TCK,
TDI, and TMS should be pulled through a resistor to 3.3 V.
TDO should be left unconnected.
TAP DC OPERATING CHARACTERISTICS
(T = 0 to 70°C, Unless Otherwise Noted)
A
Symbol
Min
Max
Unit
Notes
Parameter
Input Logic Low
Input Logic High
Input Leakage Current
Output Logic Low
Output Logic High
NOTES:
V
1
– 0.5
2
0.8
3.6
± 10
0.4
—
V
V
IL
V
IH
1
I
—
µA
V
1
2
lkg
V
OL
1
—
V
OH
1
2.4
V
1. 0 V ≤ V ≤ V
in
for all logic input pins.
DDQ
2. For V
= 0.4 V, 14 mA ≤ I
≤ 28 mA.
OL
OL
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
22
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(T = 0 to 70°C, Unless Otherwise Noted)
A
AC TEST CONDITIONS
Parameter
Value
1.5
Unit
V
Input Timing Reference Level
Input Pulse Levels
0 to 3.0
1
V
Input Rise/Fall Time (20% to 80%)
Output Timing Reference Level
V/ns
V
1.5
Output Load (See Figure 6 Unless Otherwise Noted)
—
—
TAP CONTROLLER TIMING
Parameter
Symbol
Min
60
25
25
1
Max
—
Unit
Notes
TCK Cycle Time
t
ns
ns
ns
ns
ns
ns
THTH
TCK Clock High Time
TCK Clock Low Time
TDO Access Time
TRST Pulse Width
Setup Times
t
—
TH
t
—
TL
t
t
10
—
TLQV
TSRT
40
Capture
TDI
t
5
5
5
—
1
1
CS
t
t
DVTH
MVTH
TMS
Hold Times
NOTE:
Capture
TDI
t
13
14
14
—
ns
CH
t
t
THDX
THMX
TMS
1. t
CS
and t
CH
define the minimum pauses in RAM I/O transitions to assure accurate pad data capture.
TAP CONTROLLER TIMING DIAGRAM
t
THTH
t
TLTH
TEST CLOCK
(TCK)
t
THTL
t
THMX
t
MVTH
TEST MODE SELECT
(TMS)
t
THDX
t
DVTH
TEST DATA IN
(TDI)
t
TLQV
TEST DATA OUT
(TDO)
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
23
MCM64Z836 BOUNDARY SCAN ORDER
Bit No.
1
Signal Name
SA
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Signal Name
SBa
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
SA
SEb
3
SA
SBc
4
SA
SBd
5
SA
SE2
6
SA
SE1
7
SA
SA
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
SA
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SA
V
DD
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
LBO
SA
SA
SA
ADV
G
SA
SA
CKE
SW
SA
SA1
SA0
CK
SE3
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
24
MCM64Z918 BOUNDARY SCAN ORDER
Bit No.
1
Signal Name
SA
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal Name
CK
Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
SA
SE3
3
SA
SBa
4
SA
SBb
5
SA
SB2
6
SA
SE1
7
SA
SA
8
DQa
DQa
DQa
DQa
ZZ
SA
9
DQb
DQb
DQb
DQb
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DQa
DQa
DQa
DQa
DQa
SA
V
DD
DQb
DQb
DQb
DQb
DQb
LBO
SA
SA
SA
SA
SA
ADV
G
SA
SA
CKE
SW
SA1
SA0
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
25
BOUNDARY SCAN REGISTER
TEST ACCESS PORT PINS
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 0) reserved for density
upgrade address pins. There are a total of 67 bits in the case
of the x36 device and 48 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state.
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will not produce the same result as a
logic 1 input level (not IEEE 1149.1 compliant).
The Bump/Bit Scan Order table describes which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (refer to Figure 9). An undriven TDI pin will not pro-
duce the same result as a logic 1 input level (not IEEE 1149.1
compliant).
IDENTIFICATION (ID) REGISTER
The ID register is a 32–bit register that is loaded with a de-
vice and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (refer to Figure 9). Output changes in re-
sponse to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO.
TRST — TAP RESET
The TRST is an asynchronous input that resets the TAP
controller and preloads the instruction register with the
IDCODE command. This type of reset does not affect the
operation of the system logic. The reset affects test logic
only.
ID Register Presence Indicator
Bit No.
Value
0
1
TEST ACCESS PORT REGISTERS
OVERVIEW
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1–1990
Bit No. 11
Value
10
9
8
7
6
5
4
3
2
1
The various TAP registers are selected (one at a time) via
the sequences of 1s and 0s input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift regis-
ters that capture serial input data on the rising edge of TCK
and push serial data out on the subsequent falling edge of
TCK. When a register is selected, it is “placed” between the
TDI and TDO pins.
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
Value
17
16
15
14
13
12
x
x
x
x
x
x
Device Width
Bit No.
INSTRUCTION REGISTER
22
21
0
20
1
19
0
18
0
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are 3 bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The parallel outputs of the
instruction register are automatically preloaded with the
IDCODE instruction when TRST is asserted or whenever the
controller is placed in the test–logic–reset state. The two
least significant bits of the serial instruction register are
loaded with a binary “or” pattern in the capture–IR state.
256K x 36
512K x 18
Device Depth
Bit No.
0
0
0
0
1
1
27
0
26
0
25
1
24
1
23
0
256K x 36
512K x 18
Revision Number
Bit No.
0
0
1
1
1
BYPASS REGISTER
31
30
29
28
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
Value
0
0
0
0
Figure 8. ID Register Bit Meanings
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
26
possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metast-
able state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup, plus hold
TAP CONTROLLER INSTRUCTION SET
OVERVIEW
There are two classes of instructions defined in the IEEE
Standard 1149.1–1990; the standard (public) instructions
and device specific (private) instructions. Some public
instructions, are mandatory for IEEE 1149.1 compliance.
Optional public instructions must be implemented in pre-
scribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully imple-
mented. The TAP on this device may be used to monitor all
input and I/O pads, but can not be used to load address,
data, or control signals into the RAM or to preload the I/O
buffers. In other words, the device will not perform IEEE
1149.1 EXTEST, INTEST, or the preload portion of the
SAMPLE/PRELOAD command.
time (t
plus t ). The RAMs clock inputs need not be
CS
CH
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins. Be-
cause the PRELOAD portion of the command is not im-
plemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at TRST assertion and any time the con-
troller is placed in the test–logic–reset state.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION
The BYPASS instruction is loaded in the instruction regis-
ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE–Z
If the HIGH–Z instruction is loaded in the instruction regis-
ter, all DQ pins are forced to an inactive drive state (High–Z)
and the bypass register is connected between TDI and TDO
when the TAP controller is moved to the shift–DR state.
SAMPLE/PRELOAD
THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
out of the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
NO OP
Do not use these instructions; they are reserved for future
use.
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
27
STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES
Instruction
IDCODE
Code*
001**
010
Description
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
HIGH–Z
Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins
to High–Z. NOT IEEE 1149.1 COMPLIANT.
BYPASS
011
100
Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1
COMPLIANT.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT.
*Instruction codes expressed in binary, MSB on left, LSB on right.
**Default instruction automatically loaded when TRST asserted or in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
NO OP
Code*
000
Description
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
NO OP
NO OP
NO OP
101
110
111
* Instruction codes expressed in binary, MSB on left, LSB on right.
TEST–LOGIC
RESET
1
0
1
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
1
0
0
0
CAPTURE–IR
0
1
1
CAPTURE–DR
0
SHIFT–DR
1
SHIFT–IR
1
0
0
1
1
EXIT1–DR
0
EXIT1–IR
0
PAUSE–DR
1
PAUSE–IR
1
0
0
0
0
EXIT2–DR
1
EXIT2–IR
1
UPDATE–IR
0
UPDATE–DR
1
0
1
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 9. TAP Controller State Diagram
MCM64Z836•MCM64Z918
28
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
64Z836
64Z918
MCM
XX
X
X
Motorola Memory Prefix
Part Number
Blank = Trays, R = Tape and Reel
Speed (225 = 225 MHz, 200 = 200 MHz,
166 = 166 MHz)
Package (TQ = TQFP, ZP = PBGA)
Full Part Numbers — MCM64Z836TQ225
MCM64Z836TQ225R
MCM64Z836TQ200 MCM64Z836TQ166
MCM64Z836TQ200R
MCM64Z918TQ200
MCM64Z918TQ200R
MCM64Z836TQ166R
MCM64Z918TQ166
MCM64Z918TQ166R
MCM64Z918TQ225
MCM64Z918TQ225R
MCM64Z836ZP225
MCM64Z836ZP225R
MCM64Z918ZP225
MCM64Z918ZP225R
MCM64Z836ZP200
MCM64Z836ZP200R
MCM64Z918ZP200
MCM64Z918ZP200R
MCM64Z836ZP166
MCM64Z836ZP166R
MCM64Z918ZP166
MCM64Z918ZP166R
MCM64Z836•MCM64Z918
29
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
e
4X
80
0.20 (0.008)
H
A–B
D
2X 30 TIPS
e/2
0.20 (0.008)
C
A–B
D
–D–
51
B
B
50
81
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
b1
E1/2
31
100
c1
c
1
30
b
D1/2
D/2
M
S
S
D1
0.13 (0.005)
C
A–B
D
D
SECTION B–B
2X 20 TIPS
0.20 (0.008)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
C
A–B
D
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
A
2
3
0.10 (0.004)
C
–H–
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
–C–
SEATING
PLANE
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
VIEW AB
S
0.05 (0.002)
S
1
MILLIMETERS
INCHES
MIN
0.25 (0.010)
DIM
A
A1
A2
b
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
GAGE PLANE
–––
0.002
0.053
0.009
0.009
0.004
0.004
R2
A2
0.05
1.35
0.22
0.22
0.09
0.09
b1
c
L2
L
R1
A1
c1
D
22.00 BSC
0.866 BSC
D1
E
E1
e
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
L1
VIEW AB
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
1
2
3
0
11
11
–––
13
13
0
11
11
–––
13
13
MCM64Z836•MCM64Z918
MOTOROLA FAST SRAM
30
ZP PACKAGE
7 x 17 BUMP PBGA
CASE 999–02
0.20
4X
119X
b
B
D
M
0.3
A
A
B C
E
C
NOTES:
M
0.15
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
D1
D2
MILLIMETERS
K
L
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
MIN
–––
0.50
1.30
0.80
MAX
2.40
0.70
1.70
1.00
M
N
P
R
T
16X e
U
22.00 BSC
20.32 BSC
19.40 19.60
14.00 BSC
7.62 BSC
6X
e
E2
E1
BOTTOM VIEW
TOP VIEW
11.90
0.60
1.27 BSC
12.10
0.90
e
0.25
A
A
A3
A2
0.35
0.20
A
A
SEATING
PLANE
SIDE VIEW
A1
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
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