MCM67A618FN10 [MOTOROLA]
64K x 18 Bit Asychronous/Latched Address Fast Static RAM; 64K ×18位台异步/锁存地址快速静态RAM
| 型号： | MCM67A618FN10 |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 18 Bit Asychronous/Latched Address Fast Static RAM |
| 文件： | 总12页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM67A618/D
SEMICONDUCTOR TECHNICAL DATA
MCM67A618
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAM
The MCM67A618 is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits, fabricated with Motorola’s high–
performance silicon–gate BiCMOS technology. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in-
put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup-
ported by multiple power pins.
FN PACKAGE
PLASTIC
CASE 778–02
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17
(the upper bits).
Six pair of power and ground pins have been utilized and placed on the pack-
age for maximum performance.
The MCM67A618 will be available in a 52–pin plastic leaded chip carrier
(PLCC).
This device is ideally suited for systems that require wide data bus widths,
cache memory, and tag RAMs.
PIN ASSIGNMENT
7
6
5
4
3
2
1
52 51 50 49 48 47
46 DQ8
DQ9
DQ10
8
9
45
44
43
DQ7
DQ6
V
10
11
CC
V
V
SS
CC
42
41
40
DQ11
DQ12
DQ13
12
13
14
V
SS
DQ5
DQ4
39
38
DQ14
15
16
DQ3
DQ2
V
SS
37
36
35
34
V
17
18
19
V
CC
SS
DQ15
DQ16
V
DQ1
DQ0
CC
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Access Times: 10/12/15 ns Max
Byte Writeable via Dual Write Enables
Separate Data Input Latch for Simplified Write Cycles
Address and Chip Enable Input Latches
Common Data Inputs and Data Outputs
Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
DQ17
20
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
AL . . . . . . . . . . . . . . . . . . . . . . Address Latch
DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Higher Byte Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . . Data Input/Output
High Board Density 52–Lead PLCC Package
V
V
. . . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
Allpowersupplyandgroundpinsmustbecon-
nected for proper operation of the device.
REV 4
5/95
Motorola, Inc. 1994
BLOCK DIAGRAM
A0 – A15
16
OUTPUT
BUFFER
DQ0 – DQ17
LATCH
16
18
18
MEMORY ARRAY
64K x 18
18
9
9
WRITE AMP
CONTROL
LATCH
18
E
LATCH
AL
LW
UW
G
DL
TRUTH TABLE
Supply
Current
I/O
Status
E
H
L
L
L
L
L
L
L
L
LW
X
X
X
H
H
L
UW
X
AL*
DL*
G
X
X
X
L
Mode
X
L
X
X
X
X
X
L
Deselected Cycle
I
High–Z
—
SB
CC
CC
CC
CC
CC
CC
CC
CC
X
Read or Write Using Latched Addresses
Read or Write Using Unlatched Addresses
Read Cycle
I
I
I
I
I
I
I
I
X
H
X
X
X
X
X
X
—
H
H
L
Data Out
High–Z
High–Z
High–Z
High–Z
High–Z
H
X
X
X
X
Read Cycle
Write Both Bytes Using Latched Data In
Write Both Bytes Using Unlatched Data In
Write Cycle, Lower Byte
L
L
H
X
X
L
H
L
H
Write Cycle, Lower Byte
*E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup
*and hold times for falling edge of DL.
NOTE: This truth table shows the application of each function. Combinations of these functions are valid.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0)
This device contains circuitry to protect the
inputs against damage due to high static
voltagesor electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
V
CC
– 0.5 to 7.0
for Any
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Pin Except V
CC
Output Current (per I/O)
I
mA
± 30
out
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
Power Dissipation
P
1.6
W
°C
°C
°C
D
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to + 70
T
A
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM67A618
2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to V
= 0 V)
SS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
4.75
2.2
Max
Unit
V
V
CC
5.25
V
IH
V
V
+ 0.3**
CC
Input Low Voltage
V
IL
0.8
V
– 0.5*
** V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL
IL
+ 0.3 V dc; V (max) = V
** V (max) = V
+ 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IH CC
IH
CC
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
Unit
µA
Input Leakage Current (All Inputs, V = 0 to V
in CC
)
I
lkg(I)
Output Leakage Current (G = V
IH
)
I
—
µA
lkg(O)
AC Standby Current (G = V , I
= 0 mA, All Inputs = V and V
IL
I
I
I
—
290
280
265
mA
IH out
IH,
CCA10
CCA12
CCA15
V
IL
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ t min)
IH AVAV
AC Standby Current (E = V , I
= 0 mA, All Inputs = V and V
IL
I
—
—
95
mA
mA
IH out
IH,
SB1
V
IL
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ t min)
IH AVAV
CMOS Standby Current (E ≥ V
– 0.2, All Inputs ≥ V
– 0.2 V or
I
20
CC CC
SB2
≤ 0.2 V, f = f
max
)
Output Low Voltage (I
OL
= + 8.0 mA)
= – 4.0 mA)
V
—
0.4
3.3
V
V
OL
Output High Voltage (I
OH
V
OH
2.4
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
Input Capacitance (All Pins Except DQ0 – DQ17)
Input/Output Capacitance (DQ0 – DQ17)
Symbol
Typ
4
Max
5
Unit
pF
C
in
C
6
8
pF
I/O
MCM67A618
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
ASYNCHRONOUS READ CYCLE TIMING (See Notes 1 and 2)
MCM67A618–10
MCM67A618–12
MCM67A618–15
Parameter
Read Cycle Times
Access Times:
Symbol
Min
Max
Min
Max
Min
Max
Unit
ns
Notes
t
10
—
12
—
15
—
3
4
AVAV
ns
Address Valid to Output Valid
E Low to Output Valid
Output Enable Low to Output Valid
Output Hold from Address Change
Output Buffer Control:
t
—
—
—
10
10
5
—
—
—
12
12
6
—
—
—
15
15
7
AVQV
t
t
ELQV
GLQV
t
4
—
4
—
4
—
ns
ns
AXQX
5
E Low to Output Active
G Low to Output Active
E High to Output High–Z
G High to Output High–Z
t
t
t
3
1
2
2
—
—
5
3
1
2
2
—
—
6
3
1
2
2
—
—
7
ELQX
GLQX
EHQZ
GHQZ
t
5
6
7
Power Up Time
NOTES:
t
0
—
0
—
0
—
ns
ELICCA
1. AL and DL are equal to V for all asynchronous cycles.
IH
2. Both Write Enable signals (LW, UW) are equal to V for all read cycles.
IH
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t
is less than t
ELQX
and t
GHQZ
is less than t for a given device.
GLQX
EHQZ
AC TEST LOADS
+ 5 V
480
Ω
OUTPUT
255
OUTPUT
Ω
R
= 50
Ω
5 pF
Z
= 50 Ω
L
0
V
= 1.5 V
L
Figure 1A
Figure 1B
MCM67A618
4
MOTOROLA FAST SRAM
ASYNCHRONOUS READ CYCLES
AL (ADDRESS
LATCH)
A (ADDRESS)
A1
A2
A3
t
AVAV
E
(CHIP ENABLE)
t
t
ELQV
AVQV
t
t
t
EHQZ
AXQX
ELQX
Q (DATA OUT)
Q(A1)
Q(A2)
Q(A3)
t
t
GLQX
GHQZ
t
GLQV
G
(OUTPUT ENABLE)
LW, UW
(WRITE ENABLE)
DL
(DATA LATCH)
MCM67A618
MOTOROLA FAST SRAM
5
ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM67A618–10
MCM67A618–12
MCM67A618–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
ns
Notes
Write Cycle Times
Setup Times:
t
10
—
12
—
15
—
4
AVAV
Address Valid to End of Write
Address Valid to E High
Address Valid to W Low
Address Valid to E Low
DataValid to W High
t
t
t
t
9
9
0
0
5
5
—
—
—
—
—
—
10
10
0
0
6
—
—
—
—
—
—
13
13
0
0
7
—
—
—
—
—
—
ns
AVWH
AVEH
AVWL
AVEL
t
t
DVWH
Data Valid E High
6
7
DVEH
Hold Times:
W High to Address Invalid
E High to Address Invalid
W High to Data Invalid
E High to Data Invalid
t
t
0
0
0
0
—
—
—
—
0
0
0
0
—
—
—
—
0
0
0
0
—
—
—
—
ns
ns
WHAX
EHAX
t
t
WHDX
EHDX
Write Pulse Width: Write Pulse Width (G Low)
Write Pulse Width (G High)
Write Pulse Width
t
t
t
9
8
9
9
9
—
—
—
—
—
10
9
10
10
10
—
—
—
—
—
13
12
13
13
13
—
—
—
—
—
WLWH
WLWH
5
6
5, 6
WLEH
Enable to End of Write
Enable to End of Write
t
ELWH
t
ELEH
Output Buffer Control: W High to Output Active
W Low to Output High–Z
t
t
3
0
—
5
3
0
—
6
3
0
—
9
ns
7
7, 8
WHQX
WLQZ
NOTES:
1. W (write) refers to either one or both byte write enables LW and UW.
2. AL and DL are equal to V for all asynchronous cycles.
IH
3. Both Write Enables must be equal to V for all address transitions.
IH
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes high coincident with or before W goes high the output will remain in a high impedance state.
6. If E goes low coincident with or after W goes low the output will remain in a high impedance state.
7. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t is less than t for a given device.
WLQZ
WHQX
8. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
MCM67A618
6
MOTOROLA FAST SRAM
ASYNCHRONOUS WRITE CYCLE
AL (ADDRESS
LATCH)
A1
A2
A3
A4
A (ADDRESS)
t
t
t
t
AVEH
AVAV
AVWH
EHAX
t
AVEL
t
ELEH
E
(CHIP ENABLE)
t
t
AVWL
ELWH
t
t
t
WLEH
WHAX
WLWH
LW, UW
(WRITE ENABLE)
t
t
EHDX
WHDX
t
t
DVEH
DVWH
D(A1)
D(A2)
D(A3)
D(A4)
DATA–IN
DL
(DATA LATCH)
t
t
WLQZ
WHQX
Q (DATA OUT)
G
(OUTPUT ENABLE)
MCM67A618
7
MOTOROLA FAST SRAM
LATCHED READ CYCLE TIMING (See Notes 1 and 2)
MCM67A618–10
MCM67A618–12
MCM67A618–15
Parameter
Read Cycle Times
Access Times:
Symbol
Min
Max
Min
Max
Min
Max
Unit
ns
Notes
t
10
—
12
—
15
—
3
AVAV
ns
Address Valid to Output Valid
E Low to Output Valid
AL High to Output Valid
Output Enable Low to Output Valid
t
t
—
—
—
—
10
10
10
5
—
—
—
—
12
12
12
6
—
—
—
—
15
15
15
7
AVQV
ELQV
3
4
t
ALHQV
t
GLQV
Setup Times:
ns
Address Valid to AL Low
E Valid to AL Low
Address Valid to AL High
E Valid to AL High
t
t
t
t
2
2
0
0
—
—
—
—
2
2
0
0
—
—
—
—
2
2
0
0
—
—
—
—
4
4
AVALL
EVALL
AVALH
EVALH
Hold Times:
Output Hold:
ns
ns
4
AL Low to Address Invalid
AL Low to E Invalid
t
t
2
2
—
—
2
2
—
—
3
3
—
—
ALLAX
ALLEX
Address Invalid to Output Invalid
AL High to Output Invalid
t
4
4
—
—
4
4
—
—
4
4
—
—
AXQX
t
t
ALHQX1
Address Latch Pulse Width
Output Buffer Control:
t
5
—
5
—
5
—
ns
ns
ALHALL
5
E Low to Output Active
t
3
1
3
2
2
2
—
—
—
5
5
5
3
1
3
2
2
2
—
—
—
6
6
6
3
1
3
2
2
2
—
—
—
9
9
7
ELQX
t
GLQX
G Low to Output Active
AL High to Output Active
E High to Output High–Z
AL High to Output High–Z
G High to Output High–Z
ALHQX2
t
EHQZ
t
t
ALHQZ
GHQZ
NOTES:
1. Both Write Enable Signals (LW, UW) are equal to V for all read cycles.
IH
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data
latch (DL).
5. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t
a given device.
is less than t
and t
is less than t
and t
is less than t
for
EHQZ
ELQX
ALHQZ
ALHQX2
GHQZ
GLQX
MCM67A618
MOTOROLA FAST SRAM
8
LATCHED READ CYCLES
AL (ADDRESS
LATCH)
t
ALLAX
t
ALHALL
t
AVALH
t
AVALL
A (ADDRESS)
A1
A2
A3
t
t
AVAV
ALLEX
t
t
EVALH
EVALL
E
(CHIP ENABLE)
t
t
ALHQV
t
t
ELQV
AVQV
t
t
ALHQZ
EHQZ
t
t
ALHQX1
ELQX
AXQX
Q (DATA OUT)
Q(A1)
Q(A2)
Q(A2)
Q(A3)
t
ALHQX2
t
GHQZ
t
GLQX
t
GLQV
G
(OUTPUT ENABLE)
LW, UW
(WRITE ENABLE)
DL
(DATA LATCH)
MCM67A618
9
MOTOROLA FAST SRAM
LATCHED WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM67A618–10
MCM67A618–12
MCM67A618–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Times:
t
10
—
12
—
15
—
ns
4
AVAV
Address Valid to Address Valid
Setup Times:
ns
Address Valid to End of Write
Address Valid to End of Write
E Valid to AL Low
t
t
9
9
2
2
0
0
0
0
0
2
5
5
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
10
2
2
0
0
0
0
0
2
6
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
13
2
2
0
0
0
0
0
2
7
7
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AVWH
AVEH
t
t
EVALL
AVALL
Address Valid to AL Low
E Valid to AL High
Address Valid to AL High
AL High to W Low
Address Valid to W Low
Address Valid to E Low
Data Valid to DL Low
Data Valid to W High
Data Valid to E High
DL High to W High
t
t
EVALH
AVALH
t
ALHWL
t
AVWL
AVEL
t
t
t
t
DVDLL
DVWH
DVEH
t
DLHWH
DL High to E High
t
6
7
DLHEH
Hold Times:
ns
AL Low to E High
AL Low to Address Invalid
DL Low to Data Invalid
W High to Address Invalid
E High to Address Invalid
W High to Data Invalid
E High to Data Invalid
W High to DL High
t
2
2
2
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
2
2
2
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
3
3
3
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
4
4
ALLEH
t
t
t
ALLAX
DLLDX
WHAX
EHAX
WHDX
EHDX
t
t
t
t
t
WHDLH
EHDLH
WHALH
E High to DL High
W High to AL High
t
Write Pulse Width:
ns
AL High to W High
Write Pulse Width (G Low)
Write Pulse Width (G High)
Write Pulse Width
t
t
t
9
9
8
9
9
9
—
—
—
—
—
—
10
10
9
10
10
10
—
—
—
—
—
—
13
13
12
13
13
13
—
—
—
—
—
—
5
ALHWH
WLWH
WLWH
t
6
7
6, 7
WLEH
Enable to End of Write
Enable to End of Write
t
ELWH
t
ELEH
Address Latch Pulse Width
Output Buffer Control:
t
5
—
5
—
5
—
ns
ns
4
ALHALL
W High to Output Active
W Low to Output High–Z
t
t
3
0
—
5
3
0
—
6
3
0
—
9
8
8, 9
WHQX
WLQZ
NOTES:
1. W refers to either one or both byte write enables LW and UW.
2. A write occurs during the overlap of E low and W low.
3. Both Write Enables must be equal to V for all address transitions.
IH
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of address latch (AL) and data
latch (DL).
6. If E goes high coincident with or before W goes high the output will remain in a high impedance state.
7. If E goes low coincident with or after W goes low the output will remain in a high impedance state.
8. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, t
9. If G goes low coincident with or after W goes low the output will remain in a high impedance state.
is less than t for a given device.
WLQZ
WHQX
MCM67A618
10
MOTOROLA FAST SRAM
LATCHED WRITE CYCLES
AL (ADDRESS
LATCH)
t
t
AVALL
ALHALL
t
ALLAX
A (ADDRESS)
A1
A2
A3
A4
t
AVALH
t
t
t
AVEH
EVALL
t
AVAV
t
WHAX
t
t
EHAX
AVEL
ALLEH
t
EVALH
t
ELEH
E
(CHIP ENABLE)
t
t
t
t
ELWH
ALHWH
AVWL
WHALH
t
t
t
AVWH
t
WLWH
WLEH
ALHWL
LW, UW
(WRITE ENABLE)
t
t
t
DVWH
DLHEH
t
EHDX
t
WHDX
DVEH
DATA–IN
D(A1)
D(A2)
D(A3)
D(A4)
t
t
WHDLH
DVDLL
t
t
EHDLH
DLHWH
t
DLLDX
DL
(DATA LATCH)
t
WHQX
t
WLQZ
Q (DATA OUT)
ORDERING INFORMATION
(Order by Full Part Number)
MCM 67A618 XX XX
Motorola Memory Prefix
Part Number
Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns)
Package (FN = PLCC)
Full Part Numbers — MCM67A618FN10 MCM67A618FN12 MCM67A618FN15
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67A618
11
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
M
S
S
B
0.007 (0.180)
T L
–M
N
Y BRK
-N-
M
S
S
0.007 (0.180)
T
L –M
N
U
D
D
-L-
-M-
52
LEADS
ACTUAL
Z
W
(NOTE 1)
52
1
G1
X
S
S
S
0.010 (0.250)
0.007 (0.180)
T
L –M
L –M
N
V
VIEW D-D
M
S
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
T
L –M
L –M
N
N
Z
M
R
M
S
S
H
T
N
C
K1
E
K
0.004 (0.100)
SEATING
PLANE
(NOTE 1)
52
-T-
G
J
M
S
S
F
0.007 (0.180)
T
L –M
N
VIEW S
VIEW S
G1
S
S
S
0.010 (0.250)
T
L –M
N
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
20.19
20.19
4.57
A
B
C
E
0.785
0.785
0.165
0.090
0.013
0.795
0.795
0.180
0.110
0.019
19.94
19.94
4.20
2.29
2.79
F
0.33
0.48
G
H
J
K
R
U
V
W
X
Y
0.050 BSC
1.27 BSC
0.026
0.032
—
—
0.756
0.756
0.048
0.048
0.056
0.020
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
—
0.81
—
—
19.20
19.20
1.21
1.21
1.42
0.50
0.020
0.025
0.750
0.750
0.042
0.042
0.042
—
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
Z
G1
K1
2°
10
°
2°
10°
0.710
0.040
0.730
—
18.04
1.02
18.54
—
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
CODELINE TO BE PLACED HERE
MCM67A618/D
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