MCM67H618BFN12 [MOTOROLA]
64K x 18 Bit BurstRAM Synchronous Fast Static RAM; 64K ×18位BurstRAM同步快速静态RAM
| 型号： | MCM67H618BFN12 |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM |
| 文件： | 总12页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM67H618B/D
SEMICONDUCTOR TECHNICAL DATA
MCM67H618B
Advance Information
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
The MCM67H618B is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
7
6
5
4
3
2
1 52 51 50 49 48 47
46 DQ8
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–
edge–triggered noninverting registers.
DQ9
DQ10
8
9
10
11
45 DQ7
44 DQ6
V
V
CC
SS
Bursts can be initiated with either address status processor (ADSP)
or address status cache controller (ADSC) input pins. Subsequent
burst addresses can be generated internally by the MCM67H618B
(burst sequence imitates that of the i486 and Pentium) and controlled
by the burst address advance (ADV) input pin. The following pages pro-
vide more detailed information on burst controls.
43
42
V
V
CC
SS
DQ11 12
DQ12 13
DQ13 14
DQ14 15
41 DQ5
40 DQ4
39 DQ3
38 DQ2
V
16
17
SS
CC
Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.
V
37
36
V
V
SS
CC
DQ15 18
DQ16 19
DQ17 20
35 DQ1
34 DQ0
21 22 23 24 25 26 27 28 29 30 31 32 33
Dual write enables (LW and UW) are provided to allow individually
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
ADSP Disabled with Chip Enable (E) — Supports Address Pipelining
V
V
. . . . . . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground
CC
SS
All power supply and ground pins must be con-
nected for proper operation of the device.
i486 and Pentium are trademarks of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
7/15/97
Motorola, Inc. 1997
BLOCK DIAGRAM (See Note)
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
′
Q0
Q1
K
A0
16
64K x 18
MEMORY
ARRAY
A1
CLR
A1
ADSC
ADSP
A1 – A0
2
ADDRESS
REGISTER
A2 – A15
A0 – A15
18
9
9
16
WRITE
REGISTER
UW
LW
DATA–IN
REGISTERS
ENABLE
REGISTER
OUTPUT
BUFFER
E
9
9
G
9
9
DQ0 – DQ8
DQ9 – DQ17
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC)
is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by
asserting ADSP, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or
UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and
ADSC are high, ADSP is ignored — the external address is not registered in this case.
When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A15 – A2
A15 – A2
A15 – A2
A15 – A2
A1
A1
A1
A1
A0
A0
A0
A0
NOTE: The burst wraps around to its initial state upon
completion.
MCM67H618B
2
MOTOROLA FAST SRAM
SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
E
H
L
ADSP
ADSC
ADV
X
UW or LW
K
Address Used
N/A
Operation
X
L
L
X
L
X
X
L
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Deselected
X
External Address
External Address
External Address
Next Address
Next Address
Current Address
Current Address
Next Address
Next Address
Current Address
Current Address
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
L
H
H
H
H
H
H
X
X
X
X
X
L
L
X
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
H
H
NOTES:
1. X means Don’t Care.
2. All inputs except G must meet setup and hold times for the low–to–high transition of clock (K).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
Read
G
L
I/O Status
Data Out
Read
H
X
X
High–Z
Write
High–Z — Data In
High–Z
Deselected
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, G must be high before the input data
required setup time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normalprecautions be taken to avoid application
of any voltage higher than maximum rated volt-
ages to this high–impedance circuit.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
V
CC
– 0.5 to + 7.0
for Any Pin
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Except V
CC
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
Output Current (per I/O)
Power Dissipation
I
± 30
mA
W
out
P
1.6
D
Temperature Under Bias
Ambient Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to +70
°C
°C
°C
T
A
T
– 55 to + 125
stg
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM67H618B
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to V
= 0 V)
SS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
4.75
2.2
Max
Unit
V
V
CC
5.25
V
IH
V
+ 0.3**
V
CC
Input Low Voltage
V
IL
– 0.5*
0.8
V
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.
IH IH
CC
CC
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
TBD
Unit
µA
Input Leakage Current (All Inputs, V = 0 to V
in
)
I
lkg(I)
CC
Output Leakage Current (G = V
)
I
—
µA
IH
lkg(O)
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max)
MCM67H618B–9
MCM67H618B–10
MCM67H618B–12
I
—
mA
CCA
CMOS Standby Supply Current (Device Deselected, Freq = 0, V
= Max,
I
—
—
TBD
TBD
mA
mA
CC
– 0.2 V)
SB2
All Inputs Static at CMOS Levels V ≤ V
in
+ 0.2 V or ≥ V
CC
SS
Clock Running (Device Deselected, Freq = Max, V
= Max,
I
CC
SB4
All Inputs Toggling at CMOS Levels V ≤ V
in
+ 0.2 V or ≥ V
– 0.2 V)
CC
SS
Output Low Voltage (I
= + 8.0 mA)
V
—
0.4
3.3
V
V
OL
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
OH
NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 and Pentium
bus cycles.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
4
Max
5
Unit
pF
Input Capacitance
C
in
Input/Output Capacitance
C
6
8
pF
I/O
MCM67H618B
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM67H618B–9
MCM67H618B–10
MCM67H618B–12
Min
15
—
—
6
Max
—
9
Min
16.6
—
—
6
Max
—
10
5
Min
20
—
—
6
Max
—
12
6
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
KHKH
Clock Access Time
t
5
KHQV
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
t
5
GLQV
t
t
—
—
—
6
—
—
—
7
—
—
—
7
KHQX1
3
3
3
KHQX2
t
0
0
0
GLQX
t
—
3
—
3
—
3
6
7
GHQZ
t
6
7
7
KHQZ
Clock High Pulse Width
t
5
—
—
—
5
—
—
—
6
—
—
—
KHKL
KLKH
AVKH
Clock Low Pulse Width
t
5
5
6
Setup Times:
Hold Times:
NOTES:
Address
t
2.5
2.5
2.5
Address Status
Data In
t
t
ADSVKH
t
t
DVKH
Write
WVKH
ADVVKH
Address Advance
Chip Enable
t
EVKH
Address
Address Status
Data In
t
0.5
—
0.5
—
0.5
—
ns
7
KHAX
t
t
KHADSX
t
t
KHDX
Write
KHWX
KHADVX
Address Advance
Chip Enable
t
KHEX
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage. This parameter is sampled rather than 100% tested. At any given voltage and
temperature, t
max is less than t
min for a given device and from device to device.
KHQZ
KHQZ1
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP
or ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising
edges of K when the chip is enabled. Chip enable must be asserted at each rising edge of clock for the device (when ADSC is low) to remain
enabled.
OUTPUT
Z
= 50 Ω
0
R
= 50 Ω
L
V
= 1.5 V
L
Figure 1. Test Load
MCM67H618B
5
MOTOROLA FAST SRAM
MCM67H618B
6
MOTOROLA FAST SRAM
MCM67H618B
7
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLE (E Low, ADSC High)
t
KHKH
K
t
t
KHKL
KLKH
t
t
KHADSX
ADSVKH
ADSP
t
t
KHAX
AVKH
ADDRESS
A1
A2
A3
t
t
t
WVKH
KHWX
LW, UW
t
ADVVKH
KHADVX
ADV
G
t
t
t
DVKH
KHDX
GLQV
t
KHQV
DATA IN
D(A2)
t
t
KHQX2
t
t
GHQZ
KHQX1
GLQX
DATA OUT
Q(A3)
Q(A3 + 1)
Q(A3 + 2)
Q(A1)
READ
WRITE
BURST READ
MCM67H618B
8
MOTOROLA FAST SRAM
APPLICATION EXAMPLE
DATA BUS
DATA
ADDRESS BUS
ADDRESS
16
72
CLOCK
Pentium
ADDR
ADDR
DATA
K
CLK
NA
K
ADSC
W
CACHE
CONTROL
LOGIC
MCM67H618BFN9
G
E
ADV
ADSP
ADS
CONTROL
512K Byte Burstable, Secondary Cache
Using Four MCM67H618BFN9s with a 66 MHz Pentium
Figure 2.
MCM67H618B
9
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
67H618B XX XX
Motorola Memory Prefix
Part Number
Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)
Package (FN = PLCC)
Full Part Numbers — MCM67H618BFN9 MCM67H618BFN10 MCM67H618BFN12
MCM67H618B
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
M
S
S
0.007 (0.18)
T L–M
N
B
Y BRK
–N–
M
S
S
0.007 (0.18)
T L–M
N
U
D
Z
–M–
W
–L–
D
G1
52
1
X
S
S
S
0.010 (0.25)
T L–M
N
V
VIEW D–D
NOTES:
M
M
S
S
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE
TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED
AT DATUM –T–, SEATING PLANE.
0.007 (0.18)
0.007 (0.18)
T L–M
T L–M
N
A
R
Z
S
S
N
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
E
C
0.004 (0.100)
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE
BURRS AND INTERLEAD FLASH, BUT INCLUDING
ANY MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
–T– SEATING
J
G
PLANE
VIEW S
G1
S
S
S
0.010 (0.25)
T L–M
N
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
M
S
S
H
0.007 (0.18)
0.007 (0.18)
T L–M
N
INCHES
MILLIMETERS
K1
K
DIM
A
B
C
E
MIN
MAX
0.795
0.795
0.180
0.110
0.019
MIN
19.94
19.94
4.20
2.29
0.33
MAX
20.19
20.19
4.57
2.79
0.48
0.785
0.785
0.165
0.090
0.013
M
S
S
T L–M
N
F
F
G
H
J
K
R
U
V
W
X
Y
0.050 BSC
1.27 BSC
VIEW S
0.026
0.020
0.025
0.750
0.750
0.042
0.042
0.042
–––
0.032
–––
–––
0.756
0.756
0.048
0.048
0.056
0.020
10
0.66
0.51
0.64
19.05
19.05
1.07
1.07
1.07
–––
0.81
–––
–––
19.20
19.20
1.21
1.21
1.42
0.50
10
Z
2
2
G1
K1
0.710
0.040
0.730
–––
18.04
1.02
18.54
–––
MCM67H618B
11
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
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ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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