MCM6929AWJ8 [MOTOROLA]
256K x 4 Bit Fast Static Random Access Memory; 256K ×4位高速静态随机存取存储器
| 型号： | MCM6929AWJ8 |
| 厂家： | 
MOTOROLA |
| 描述： | 256K x 4 Bit Fast Static Random Access Memory |
| 文件： | 总8页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM6929A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6929A
Advance Information
256K x 4 Bit Fast Static Random
Access Memory
The MCM6929A is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
PIN ASSIGNMENT
NC
A
A
A
A
A
A
G
1
2
32
31
30
29
28
27
•
•
•
•
•
•
•
Single 3.3 V Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: 8, 10, 12, 15 ns
Center Power and I/O Pins for Reduced Noise
Fully 3.3 V BiCMOS
A
3
A
4
A
5
E
6
DQ
DQ
V
7
26
25
24
23
22
21
20
V
8
DD
SS
V
V
DD
BLOCK DIAGRAM
9
SS
DQ
DQ
A
10
A
A
A
W
A
11
V
DD
VSS
A
12
13
14
A
A
A
A
A
MEMORY
19
18
ROW
DECODER
MATRIX
512 ROWS x 512 x 4
COLUMNS
A
A
A
A
A
A
A
15
16
NC
NC
17
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
DQ
COLUMN I/O
INPUT
DATA
CONTROL
COLUMN DECODER
V
V
. . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . Ground
DQ
DD
SS
A
A
A
A
A
A
A
A
A
NC . . . . . . . . . . . . . . . . . . No Connection
E
W
G
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
REV1
2/26/97
Motorola, Inc. 1997
TRUTH TABLE (X = Don’t Care)
E
H
L
G
X
H
L
W
X
H
H
L
Mode
Not Selected
Output Disabled
Read
V
Current
Output
High–Z
High–Z
Cycle
—
DD
I
, I
SB1 SB2
I
I
I
—
DDA
DDA
DDA
L
D
Read Cycle
Write Cycle
out
L
X
Write
High–Z
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol
Power Supply Voltage
Voltage Relative to V
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
thatnormal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to these high–impedance cir-
cuits.
This BiCMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
andtransverse air flow of at least500linearfeet
per minute is maintained.
Value
– 0.5 to + 4.6
– 0.5 to V + 0.5
Unit
V
V
V
DD
for Any Pin Except
V , V
in out
SS
DD
V
DD
Output Current
I
± 30
mA
W
out
Power Dissipation
P
D
0.6
Temperature Under Bias
Operating Temperature
T
– 10 to + 85
0 to + 70
°C
°C
°C
bias
T
A
Storage Temperature — Plastic
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V +10%, – 5% T = 0 to 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.135
2.2
Typ
3.3
—
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
DD
3.6
V
IH
V
V
+ 0.3**
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
*V (min) = –0.5 V dc; V (min) = –2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
DD
IH IH
DD
DC CHARACTERISTICS
Parameter
Symbol
Min
—
Max
± 1.0
± 1.0
0.4
Unit
µA
µA
V
Input Leakage Current (All Inputs, V = 0 to V
)
I
lkg(I)
in
DD
Output Leakage Current (E = V , V
IH out
= 0 to V
)
I
—
DD
lkg(O)
Output Low Voltage (I
= + 8.0 mA)
V
OL
—
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
—
V
OH
MCM6929A
2
MOTOROLA FAST SRAM
POWER SUPPLY CURRENTS (See Note 1)
6929A–8
6929A–10
6929A–12
6929A–15
Parameter
Symbol
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Unit
Notes
AC Active Supply Current
I
—
—
—
—
150
—
—
—
—
130
—
—
—
—
120
—
—
—
—
110
mA
2, 3, 4
DDA
(I
out
= 0 mA) (V
= max, f = f
)
max
DD
Active Quiescent Current
(E = V , V = max, f = 0 MHz)
I
80
50
20
80
45
20
80
40
20
80
35
20
mA
mA
mA
DD2
IL DD
AC Standby Current
(E = V , V = max, f = f
I
2, 3, 4
SB1
SB2
)
max
IH DD
CMOS Standby Current
(V = max, f = 0 MHz,
I
DD
E ≥ V
V
– 0.2 V,
DD
≤ V
+ 0.2 V, or ≥ V – 0.2 V)
DD
in
NOTES:
1. Typical current = 25°C @ 3.3 V.
2. Reference AC Operating Conditions and Characteristics for input and timing (V /V , t /t , pulse level 0 to 3.0 V, V = 3.0 V).
SS
IH IL r f
IH
3. All addresses transition simultaneously low (LSB) and then high (MSB).
4. Data states are all zero.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
—
Max
Unit
pF
Address Input Capacitance
Control Pin Input Capacitance
Input/Output Capacitance
C
C
6
6
8
in
in
—
pF
C
—
pF
I/O
MCM6929A
3
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V + 10%, – 5%, T = 0 to +70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1 and 2)
6929A–8
6929A–10
Min Max
10
6929A–12
Min Max
12
6929A–15
Min Max
15
Parameter
Read Cycle Time
Symbol
Min
8
Max
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
—
—
—
3
AVAV
Address Access Time
t
—
—
—
3
—
—
—
3
10
10
5
—
—
—
3
12
12
6
—
—
—
3
15
15
7
AVQV
Enable Access Time
t
8
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
t
t
4
—
—
—
4
—
—
—
5
—
—
—
6
—
—
—
7
t
3
3
3
3
4,5,6
4,5,6
4,5,6
4,5,6
ELQX
GLQX
EHQZ
GHQZ
t
t
0
0
0
0
—
—
—
—
—
—
—
—
t
4
5
6
7
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
device to device.
max < t
min, and t
GHQZ
max < t min, both for a given device and from
GLQX
EHQZ
ELQX
5. Transition is measured 200 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = V , G = V ).
IL IL
8. Addresses valid prior to or coincident with E going low.
TIMING LIMITS
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a mini-
mum since the system must supply at least that much
time. On the other hand, responses from the memory
are specified from the device point of view. Thus, the
access time is shown as a maximum since the device
never provides data later than that time.
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
MCM6929A
4
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 7)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Note 8)
t
AVAV
A (ADDRESS)
t
AVQV
t
ELQV
E (CHIP ENABLE)
t
EHQZ
t
ELQX
G (OUTPUT ENABLE)
t
t
GHQZ
GLQV
t
GLQX
Q (DATA OUT)
DATA VALID
MCM6929A
5
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6929A–8
Min Max
6929A–10
6929A–12
6929A–15
Parameter
Write Cycle Time
Symbol
Min
10
0
Max
Min
12
0
Max
—
Min
15
0
Max
—
Unit
ns
Notes
t
8
0
8
7
8
—
—
—
—
—
—
—
—
—
—
3
AVAV
Address Setup Time
t
—
—
ns
AVWL
Address Valid to End of Write
Address Valid to End of Write, G High
Write Pulse Width
t
t
9
10
9
—
12
10
12
—
ns
AVWH
AVWH
8
—
—
ns
t
t
,
9
10
—
—
ns
WLWH
WLEH
Write Pulse Width, G High
t
t
,
7
—
8
—
9
—
10
—
ns
WLWH
WLEH
Data Valid to End of Write
Data Hold Time
t
t
4
0
—
—
4
5
0
—
—
5
6
0
—
—
6
7
0
—
—
7
ns
ns
ns
ns
ns
DVWH
WHDX
Write Low to Data High–Z
Write High to Output Active
t
—
3
—
3
—
3
—
3
4,5,6
4,5,6
WLQZ
t
—
—
—
—
—
—
—
—
WHQX
Write Recovery Time
NOTES:
t
0
0
0
0
WHAX
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
max < t
min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLEH
t
WLWH
W (WRITE ENABLE)
D (DATA IN)
t
t
AVWL
t
WHDX
DVWH
DATA VALID
HIGH–Z
t
WLQZ
HIGH–Z
Q (DATA OUT)
t
WHQX
MCM6929A
6
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
6929A–8
Min Max
6929A–10
6929A–12
6929A–15
Parameter
Write Cycle Time
Symbol
Min
10
0
Max
Min
12
0
Max
Min
15
0
Max
Unit
ns
Notes
t
8
0
7
7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
AVAV
Address Setup Time
t
ns
AVEL
Address Valid to End of Write
Enable to End of Write
t
8
9
10
10
ns
AVEH
t
t
,
8
9
ns
4,5
ELEH
ELWH
Data Valid to End of Write
Data Hold Time
t
4
0
0
—
—
—
5
0
0
—
—
—
6
0
0
—
—
—
7
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
t
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
t
AVAV
A (ADDRESS)
t
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
t
EHAX
AVEL
ELWH
W (WRITE ENABLE)
t
t
EHDX
DVEH
D (DATA IN)
DATA VALID
HIGH–Z
Q (DATA OUT)
MCM6929A
7
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32–LEAD
400 MIL SOJ
CASE 857A–02
F 32 PL
S
S
S
0.17 (0.007)
T
B
A
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
32
1
17
16
32 PL
D
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.
S
S
S
0.17 (0.007)
T
A
B
A
NOTE 3
DETAIL Z
S
S
S
0.17 (0.007)
T
B
INCHES
MILLIMETERS
-A-
DIM
A
B
C
D
E
MIN
MAX
0.830
0.405
0.148
0.020
0.098
0.032
MIN
20.83
10.03
3.26
0.41
2.24
0.67
MAX
21.08
10.29
3.75
0.50
2.48
P
0.820
0.395
0.128
0.016
0.088
0.026
L
G
-B-
C
F
0.81
E
G
K
L
0.050 BSC
1.27 BSC
0.10 (0.004)
0.035
0.045
0.89
1.14
SEATING
PLANE
K
-T-
0.025 BSC
0.64 BSC
S RADIUS
DETAIL Z
R
N
P
R
S
0.030
0.435
0.365
0.030
0.045
0.445
0.375
0.040
0.76
11.05
9.27
0.77
1.14
11.30
9.52
1.01
S
S
S
0.25 (0.010)
T
A
B
NOTE 3
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6929A WJ XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (8 = 8 ns, 10 = 10 ns, 12 = 12 ns, 15 = 15 ns)
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6929AWJ8
MCM6929AWJ8R
MCM6929AWJ10
MCM6929AWJ10R
MCM6929AWJ12
MCM6929AWJ12R
MCM6929AWJ15
MCM6929AWJ15R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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MCM6929A/D
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