MCM69D618TQ8 [MOTOROLA]
64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM; 64K ×18位同步双I / O ，双SRAM地址
| 型号： | MCM69D618TQ8 |
| 厂家： | 
MOTOROLA |
| 描述： | 64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM |
| 文件： | 总14页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MCM69D618/D
SEMICONDUCTOR TECHNICAL DATA
MCM69D618
64K x 18 Bit Synchronous
Dual I/O, Dual Address SRAM
TheMCM69D618isa1M–bitstaticrandomaccessmemory, organizedas64K
words of 18 bits. It features common data input and data output buffers and
incorporates input and output registers on–board with high speed SRAM.
The MCM69D618 allows the user to concurrently perform reads, writes, or
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports
(AX, AY) determine the read or write locations for their respective data ports
(DQX, DQY).
TQ PACKAGE
100 LEAD TQFP
CASE 983A–01
The synchronous design allows for precise cycle control with the use of an
external single clock (K). All signal pins except output enables (GX, GY) are
registered on the rising edge of clock (K).
The pass–through feature allows data to be passed from one port to the other,
in either direction. The PTX input must be asserted to pass data from port X to
port Y. The PTY will likewise pass data from port Y to port X. A pass–through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols are followed. If
both ports are read, the reads occur normally. If one port is written and the other
is read, the read from the array will occur before the data is written. If both ports
are written, only the data on DQY will be written to the array.
•
•
•
•
•
Single 3.3 V ± 5% Power Supply
Fast Access Times: 6/8 ns Max
Throughput of 1.49 Gigabits/Second
Single Clock Operation
Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers
On–Chip
•
•
•
•
•
•
•
•
•
83 MHz Maximum Clock Frequency
Self Timed Write
Two Bi–Directional Data Buses
Can be Configured as Separate I/O
Pass–Through Feature
Asynchronous Output Enables (GX, GY)
LVTTL Compatible I/O
Concurrent Reads and Writes
100–Pin TQFP Package
Suggested Applications
— ATM
— Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches
— Shared Memory
Product Family Configurations
Part
Number
Dual
Address
Single
Address
Dual
I/O
Separate
I/O
Configuration
32K x 36
V
DD
MCM69D536
MCM69D618
MCM67Q709A
MCM67Q909
NOTES:
Note 1
Note 1
Note 2
Note 2
3.3 V
3.3 V
5.0 V
5.0 V
64K x 18
128K x 9
512K x 9
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
REV 5
1/16/98
Motorola, Inc. 1998
BLOCK DIAGRAM
16
16
ADDRESS
REGISTER
ADDRESS
REGISTER
AX
AY
64K x 18 ARRAY
WRITE X
REGISTER
WRITE Y
REGISTER
WX
WRITE
DRIVER
SENSE
AMPS
SENSE
AMPS
WRITE
DRIVER
WY
PTX
REGISTER
PTY
REGISTER
PTX
PTY
PASS–THROUGH
DATA IN
REGISTER
OUTPUT
REGISTER
OUTPUT
REGISTER
DATA IN
REGISTER
K
K
ENABLE
REG 1
E1
E2
ENABLE
REG 2
DQX
DQY
GX
GY
MCM69D618
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
V
1
DD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
AY15
V
2
SS
V
SS
3
4
V
DQX9
DD
DQY9
DQX10
DQY10
DQX8
DQY8
5
6
7
DQX7
DQY7
V
DD
V
V
SS
8
9
10
SS
DQX11
DQY11
DQX12
DQY12
V
DD
DQX6
11
12
13
14
15
DQY6
DQX5
V
DQY5
DD
V
V
SS
SS
DQY13
DQX13
DQY14
DQX14
V
DD
16
17
DQY4
DQX4
65
64
63
18
19
20
DQY3
DQX3
V
DD
62
61
V
SS
V
SS
DQY15
DQX15
21
22
23
24
25
26
V
60
59
58
DD
DQY2
DQX2
DQY1
DQX1
DQY16
DQX16
57
56
V
DD
V
V
SS
55
54
53
52
51
SS
DQY17
V
27
28
29
DD
DQX17
AY5
AX5
DQY0
DQX0
AY14
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MCM69D618
3
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
40, 38, 36, 34, 32, 30, 100, 98, 85,
83, 42, 44, 46, 48, 50, 81
AX0 –
AX15
Input
Address Port X. Never allow floating addresses for inputs AX0 – AX15.
A pullup resistor is needed.
39, 37, 35, 33, 31, 29, 99, 97, 84, 82,
43, 45, 47, 49, 51, 80
AY0 –
AY15
Input
I/O
Address Port Y. Never allow floating addresses for inputs AY0 – AY15.
A pullup resistor is needed.
52, 56, 58, 62, 64, 69, 71, 75, 77,
3, 5, 9, 11, 16, 18, 22, 24, 28
DQX0 –
DQX17
Data Input/Output Port X.
53, 57, 59, 63, 65, 68, 70, 74, 76,
4, 6, 10, 12, 15, 17, 21, 23, 27
DQY0 –
DQY17
I/O
Data Input/Output Port Y.
90
91
92
E1
E2
GX
Input
Input
Input
Synchronous Chip Enable: Active low.
Synchronous Chip Enable: Active high.
Asynchronous Output Enable Port X Input:
Low — enables output buffers (DQXx pins).
High — DQXx pins are high impedance.
93
96
GY
K
Input
Input
Asynchronous Output Enable Port Y Input:
Low — enables output buffers (DQYx pins).
High — DQYx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except G.
86
PTX
PTY
WX
Input
Input
Input
Input
Pass–Through Port X.
87
Pass–Through Port Y.
88
Synchronous Write Enable Port X.
Synchronous Write Enable Port Y.
89
WY
1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95
2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94
V
Supply + 3.3 V Power Supply.
Supply Ground.
DD
V
SS
MCM69D618
4
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 5)
Input at t Clock
n
E1
H
X
L
E2
X
WX
X
WY
X
PTX
X
PTY
X
Operation
Deselected
Operation Number
1
2
3
4
5
6
7
8
L
X
X
X
X
Deselected
H
H
H
H
H
H
0
X
X
X
Write X Port
L
X
0
X
X
Write Y Port
L
X
X
0
X
Pass–Through X to Y
Pass–Through Y to X
Read X
L
X
X
X
0
L
1
X
1
1
L
X
1
1
1
Read Y
NOTES:
1. GX/GY must be controlled to avoid bus contention issues during write and pass–through cycles.
2. Operation numbers 3 – 6 can be used in any combination.
3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.
4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
t
t
n + 1
n
K
VALID
ADDRESS & CONTROL
PIPELINED READ ACCESS
VALID
DATA INPUT D
PASS–THROUGH
DATA OUTPUT Q
VALID
ABSOLUTE MAXIMUM RATINGS (See Note)
This is a synchronous device. All synchro-
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
nousinputsmustmeetspecifiedsetupandhold
times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
V
DD
– 0.5 to + 4.6
for Any Pin
V , V
in out
– 0.5 to V
DD
+ 0.5
V
SS
Except V
DD
Output Current
I
± 20
TBD
mA
W
out
Power Dissipation
P
D
Temperature Under Bias
Operating Temperature
T
bias
– 10 to + 85
0 to + 70
°C
°C
°C
T
A
Storage Temperature — Plastic
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
MCM69D618
5
MOTOROLA FAST SRAM
PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Rating
Symbol
TQFP
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
R
40
25
°C/W
2
θJA
Junction to Board (Bottom)
Junction to Case (Top)
NOTES:
R
R
17
9
°C/W
°C/W
3
4
θJB
θJC
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
3.135
2.0
Max
Unit
V
V
DD
3.465
V
IH
V
+ 0.5**
V
DD
Input Low Voltage
V
– 0.5*
—
0.8
V
IL
Input Leakage Current (All Inputs, V = 0 to V
)
I
± 1.0
± 1.0
µA
µA
mA
in
DD
lkg(I)
Output Leakage Current (E = V , V
IH out
= 0 to V
)
I
—
DD
lkg(O)
AC Supply Current (I
= 0 mA) (V
= max, f = f
)
MCM69D618–6 ns
MCM69D618–8 ns
I
DDA
—
—
300
300
out
DD
max
CMOS Standby Supply Current (Deselected, Clock (K)
Cycle Time ≥ t
MCM69D618–6 ns
, All Inputs Toggling at CMOS Levels MCM69D618–8 ns
I
—
—
100
100
mA
SB1
KHKH
+ 0.2 V or ≥ V
V
≤ V
– 0.2 V)
in
SS
DD
= + 8.0 mA)
Output Low Voltage (I
V
—
0.4
V
V
OL
OL
Output High Voltage (I
= – 4.0 mA)
V
2.4
V
DD
OH
OH
*V ≥ –1.5 V for t ≤ t
/2.
/2.
KHKH
IL
KHKH
**V ≤ V
IH
+ 1.0 V for t ≤ t
DD
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to + 70°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Max
Unit
pF
Address and Data Input Capacitance
Control Pin Input Capacitance
Output Capacitance
C
C
6
6
8
in
in
pF
C
pF
out
MCM69D618
6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 5%, T = 0 to 70°C, Unless Otherwise Noted)
DD
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
MCM69D618–6
MCM69D618–8
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
12
—
4
Max
—
6
Min
15
—
6
Max
—
8
Cycle Time
t
1
KHKH
Clock Access Time
t
KHQV
Clock Low Pulse Width
t
—
—
—
—
5
—
—
—
—
5
KLKH
Clock High Pulse Width
t
4
6
KHKL
Clock High to Data Output Active
Clock High to Data Output Invalid
Clock High to Data Output High–Z
Output Enable Low to Data Output Valid
Output Enable Low to Data Output Low–Z
Output Enable High to Data Output High–Z
t
t
0
0
KHQX1
2
2
KHQX2
t
t
t
—
—
0
—
—
0
2
KHQZ
GLQV
GLQX
GHQZ
6
8
—
—
8
t
—
2.5
5
—
3
2
3
Setup Times:
Hold Times:
NOTES:
AWR0 – AWR14
ARD0 – ARD14
t
—
—
AVKH
AVKH
WVKH
t
t
W
PT
E1, E2
D0 – D35
t
PTVKH
t
t
EVKH
DVKH
AWR0 – AWR14
ARD0 – ARD14
W
t
t
0.5
—
1
—
ns
3
3
3
3
3
KHAX
KHAX
t
KHWX
PT
E1, E2
D0 – D35
t
KHPTX
KHEX
KHDX
t
t
3, 4
1. All read and write cycles are referenced from K.
2. This parameter is sampled and not 100% tested.
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
4. t
clock edge.
minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising
KHDX
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
MCM69D618
7
MOTOROLA FAST SRAM
READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH)
t
KHKH
t
t
KHKL
KLKH
K
t
AVKH
t
KHAX
1
2
3
4
5
6
7
8
9
AX
GX
PORT X
t
GLQV
t
KHQV
t
GHQZ
t
KHQX1
Q(1)
Q(2)
Q(3)
Q(5)
Q(6)
Q(7)
DQX
t
GLQX
t
EVKH
E
t
KHEX
12
13
14
15
16
6
7
19
20
AY
GY
PORT Y
t
KHQZ
Q(12)
Q(13)
Q(14)
Q(16)
Q(6)
Q(7)
DQY
t
KHQV
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.
MCM69D618
8
MOTOROLA FAST SRAM
WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH)
t
t
t
KHKL
KHKH
KLKH
K
1
2
3
4
5
6
7
8
9
AX
t
KHWX
t
WVKH
WX
PORT X
GX
t
t
KHDX
DVKH
D(2)
D(3)
D(4)
D(8)
D(9)
DQX
E
12
13
14
5
6
18
19
20
AY
15
WY
PORT Y
GY
D(14)
D(15)
D(5)
D(6)
D(18)
D(19)
DQY
PORT Y TAKES PRECEDENCE
OVER PORT X WHEN AX = AY
AND WRITING BOTH PORTS.
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.
MCM69D618
9
MOTOROLA FAST SRAM
WRITE TO PORT X AND PASS–THROUGH TO PORT Y (See Note)
t
t
t
KHKL
KHKH
KLKH
K
AX
1
2
3
4
5
6
7
8
9
WX
PORT X
GX
t
t
PTVKH
KHPTX
PTX
t
t
DVKH
KHDX
D(2)
D(3)
D(X)
D(Y)
D(6)
DQX
E
12
13
14
16
17
18
19
20
AY
15
WY
GY
PORT Y
PTY
t
KHQV
t
KHQZ
t
KHQX2
D(3)
D(X)
D(17)
DQY
D(Y)
E Low = E1 Low and E2 High. E High = E1 High or E2 Low.
NOTE: The timing diagram is valid for the opposite case as well, i.e., writing to Port Y and passing through to Port X.
MCM69D618
10
MOTOROLA FAST SRAM
COMBINATION READ/WRITE WITH SAME ADDRESS ON EACH PORT
t
t
t
KHKL
KHKH
KLKH
K
TRY TO
WRITE
TRY TO
WRITE
READ
1
READ
READ
READ
2
READ
READ
3
1
2
AX
WX
GX
PORT X
D(ABC)
D(DEF)
Q(PQR)
Q(XYZ)
Q(JKL)
DQX
READ
1
READ
2
READ
3
WRITE
2
READ
READ
3
WRITE
1
WRITE
2
AY
WY
GY
PORT Y
D(PQR)
D(XYZ)
Q(PQR)
D(JKL)
Q3
Q(JKL)
DQY
PORT Y TAKES PRECEDENCE
OVER PORT X WHEN AX = AY
AND WRITING BOTH PORTS.
PTX = PTY = high.
D(Value) = Value is the input to the data port.
Q(Value) = Value is the output from the data port.
MCM69D618
11
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 69D618 XX XX
X
Motorola Memory Prefix
Part Number
Shipping Method (R = Tape and Reel,
Blank = Rails)
Speed (6 = 6ns, 8 = 8 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM69D618TQ6
MCM69D618TQ8
MCM69D618TQ6R MCM69D618TQ8R
MCM69D618
12
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQFP PACKAGE
100 PIN
CASE 983A–01
4X
80
e
0.20 (0.008)
H
A–B
D
2X 30 TIPS
e/2
0.20 (0.008)
C
A–B
D
–D–
51
50
81
B
B
–X–
E/2
X=A, B, OR D
–A–
–B–
VIEW Y
E1
E
BASE
METAL
PLATING
E1/2
b1
31
100
1
30
c1
c
D1/2
D/2
b
D1
D
M
S
S
0.13 (0.005)
C
A–B
D
2X 20 TIPS
0.20 (0.008)
SECTION B–B
C
A–B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED AT
DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018).
A
2
3
0.10 (0.004)
C
–H–
–C–
SEATING
PLANE
VIEW AB
S
0.05 (0.002)
S
1
0.25 (0.010)
MILLIMETERS
INCHES
MIN
GAGE PLANE
R2
A2
DIM
A
A1
A2
b
b1
c
c1
D
MIN
–––
MAX
1.60
0.15
1.45
0.38
0.33
0.20
0.16
MAX
0.063
0.006
0.057
0.015
0.013
0.008
0.006
–––
0.002
0.053
0.009
0.009
0.004
0.004
0.05
1.35
0.22
0.22
0.09
0.09
L2
L
R1
A1
L1
22.00 BSC
0.866 BSC
D1
E
E1
e
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.787 BSC
0.630 BSC
0.551 BSC
0.026 BSC
VIEW AB
L
0.45
1.00 REF
0.50 REF
0.75
0.018
0.039 REF
0.020 REF
0.030
L1
L2
S
R1
R2
0.20
–––
–––
0.20
7
0.008
–––
–––
0.008
7
0.08
0.08
0
0.003
0.003
0
1
2
3
0
11
11
–––
13
13
0
11
11
–––
13
13
MCM69D618
13
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
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How to reach us:
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P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
– US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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