MCM69L737AZP9.5 [MOTOROLA]
4M Late Write LVTTL; 4M后写入LVTTL型号: | MCM69L737AZP9.5 |
厂家: | MOTOROLA |
描述: | 4M Late Write LVTTL |
文件: | 总20页 (文件大小:215K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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by MCM69L737A/D
SEMICONDUCTOR TECHNICAL DATA
MCM69L737A
MCM69L819A
Advance Information
4M Late Write LVTTL
The MCM69L737A/819A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L819A
organized as 256K words by 18 bits, and the MCM69L737A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is available at the falling edge of the CK
clock.
ZP PACKAGE
PBGA
CASE 999–01
The RAM uses LVTTL 3.3 V inputs and outputs.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V + 10%, – 5% Operation
LVTTL 3.3 V I/O (V
Register to Latch Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 organization
MCM69L737A/819A–8.5 = 8.5 ns
MCM69L737A/819A–9 = 9 ns
)
DDQ
MCM69L737A/819A–9.5 = 9.5 ns
Sleep Mode Operation (ZZ Pin)
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
•
•
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
8/15/97
Motorola, Inc. 1997
FUNCTIONAL BLOCK DIAGRAM
DATA IN
REGISTER
ADDRESS
REGISTERS
MEMORY
ARRAY
SA
DQ
DATA OUT
LATCH
SW
SW
REGISTERS
CONTROL
LOGIC
SBx
CK
G
SS
SS
REGISTERS
PIN ASSIGNMENTS
TOP VIEW
MCM69L737A
MCM69L819A
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
A
B
C
D
E
V
SA
NC
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
SA
V
V
SA
NC
SA
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
V
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
SA
V
NC
NC
V
SA
NC
NC
DD
DD
DQc
DQc
DQc
DQc
DQc
V
NC
V
DQb DQb
DQb DQb
DQb
NC
NC
DQb
NC
V
NC
SS
G
V
DQa
NC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
SS
G
V
V
V
V
V
V
V
V
DQa
F
F
V
DQb
V
V
DQa
NC
V
DDQ
DDQ
DDQ
DDQ
G
G
DQc
DQc SBc
NC
NC
SBb
DQb DQb
DQb DQb
NC
DQb SBb
NC
NC
NC
DQa
H
H
DQc
DQc
V
V
DQb
V
DQa
NC
SS
SS
SS
J
K
L
J
K
L
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD DDQ
V
V
V
V
V
NC
NC
DDQ
DD
DD
DD DDQ
DQd
DQd
V
CK
V
DQa DQa
DQa DQa
NC
DQb
V
CK
CK
V
NC
DQa
NC
SS
SS
SS
SS
DQb
NC
V
SBa
DQa
DQd
DQd SBd
CK
SW
SA
SA
SBa
SS
M
N
P
M
N
P
V
DQd
DQd
DQd
V
V
V
V
V
V
DQa
V
V
DQb
NC
V
V
V
SW
SA
SA
V
V
V
NC
DQa
NC
V
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DQd
DQa DQa
DQa DQa
DQb
NC
DQd
NC
DQb
DQa
NC
ZZ
R
T
R
T
NC
NC
SA
NC
V
V
V
SA
NC
NC
NC
ZZ
NC
NC
SA
SA
V
V
V
SA
SA
NC
DD
DD
SS
DD
SA
TDI
DD
NC
TCK
SS
SA
TDO
SA
SA
SA
U
U
V
TMS
TDI
TCK
TDO
V
V
TMS
V
DDQ
DDQ
DDQ
DDQ
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
2
MCM69L737A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
CK
Type
Input
Input
I/O
Description
4K
4L
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
Synchronous Data I/O.
CK
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
4F
G
Input
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
TDI
Input
Input
Test Clock (JTAG).
Test Data In (JTAG).
3U
5U
TDO
TMS
ZZ
Output Test Data Out (JTAG).
2U
7T
Input
Input
Test Mode Select (JTAG).
Enables sleep mode.
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
Supply Core Power Supply.
DD
V
DDQ
Supply Output Power Supply: provides operating power for output buffers.
Supply Ground.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G,
4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U
NC
—
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
3
MCM69L819A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
CK
Type
Input
Input
I/O
Description
4K
4L
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
Synchronous Data I/O.
CK
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
4F
G
Input
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
TDI
Input
Input
Test Clock (JTAG).
Test Data In (JTAG).
3U
5U
TDO
TMS
ZZ
Output Test Data Out (JTAG).
2U
7T
Input
Input
Test Mode Select (JTAG).
Enables sleep mode.
4C, 2J, 4J, 6J, 4R, 3R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
Supply Core Power Supply.
DD
V
DDQ
Supply Output Power Supply: provides operating power for output buffers.
Supply Ground.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
NC
—
No Connection: There is no connection to the chip.
Note: 3J and 5J are tied common.
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
4
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V , See Note 1)
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
Rating
Core Supply Voltage
Symbol
Value
Unit
V
DD
– 0.5 to + 4.6
V
Output Supply Voltage
Voltage On Any Pin
V
– 0.5 to V
+ 0.5
V
V
DDQ
DD
V
– 0.5 to V
+ 0.5
in
in
DD
Input Current (per I/O)
Output Current (per I/O)
Power Dissipation (See Note 2)
Operating Temperature
Temperature Under Bias
I
± 50
mA
mA
W
I
± 70
—
out
P
D
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
T
A
0 to + 70
°C
°C
°C
T
– 10 to + 85
bias
Storage Temperature
NOTES:
T
stg
– 55 to + 125
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposuretohigherthanrecommendedvoltagesforextended
periods of time could affect device reliability.
2. Powerdissipationcapabilitywillbedependentuponpackagecharacteristicsanduse
environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
53
38
22
14
5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2
Junction to Ambient (Still Air)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board (Bottom)
Junction to Case (Top)
R
θJA
R
θJA
R
θJA
R
θJB
R
θJC
Single Layer Board
Four Layer Board
1, 2
3
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K CLK
L – H
L – H
L – H
L – H
L – H
L – H
L – H
L – H
X
ZZ
L
SS
L
SW
H
L
SBa
X
SBb
X
SBc
X
SBd
X
DQ (n)
DQ (n+1)
Mode
D
0–35
X
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
out
L
L
L
H
H
H
High–Z
D
0–8
in
L
L
L
H
L
H
H
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
D
9–17
in
L
L
L
H
H
L
H
D
18–26
27–35
0–35
in
in
L
L
L
H
H
H
L
D
L
L
L
L
L
L
L
D
in
L
L
L
H
H
H
H
High–Z
X
L
H
X
X
X
X
X
X
X
H
X
X
X
X
High–Z
Sleep Mode
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Typical Typical Typical
–8.5
–9
—
—
–9.5
Parameter
Core Power Supply Voltage
Symbol
Min
3.15
3.15
Max
3.6
Unit
V
Notes
V
DD
—
—
Output Driver Supply Voltage
Active Power Supply Current
V
—
—
3.6
V
DDQ
DD1
(x18)
(x36)
I
I
—
—
320
370
320
370
300
350
480
550
mA
5
Quiescent Active Power
Supply Current
—
180
180
180
250
mA
6, 10
DD2
Active Standby Power Supply Current
I
I
—
—
170
150
170
150
170
150
250
230
mA
mA
7
SB1
Quiescent Standby Power
Supply Current
8, 10
SB2
Sleep Mode Power Supply Current
NOTES:
I
—
30
30
30
50
mA
9, 10
SB3
1. AlldatasheetparametersspecifiedtofullrangeofV
unlessotherwisenoted. AllvoltagesarereferencedtovoltageappliedtoV bumps.
SS
DD
2. Supply voltage applied to V
3. Supply voltage applied to V
connections.
DD
connections.
DDQ
4. All power supply currents measured with outputs open or deselected.
5. V
6. V
7. V
8. V
9. V
= V
= V
= V
= V
= V
(max), t
(max), t
(max), t
(max), t
(max), t
= t
KHKH KHKH
(min), SS registered active, 50% read cycles.
= dc, SS registered active.
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
KHKH
KHKH KHKH
= t
(min), SS registered inactive.
= dc, SS registered inactive, ZZ low.
= dc, SS registered inactive, ZZ high.
– 200 mV.
KHKH
KHKH
10. 200 mV ≥ V ≥ V
in
DDQ
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
2.0
Max
+ 0.3
DD
Unit
V
Notes
DC Input Logic High
V
(dc)
(dc)
V
IH
DC Input Logic Low
V
– 0.3
—
0.8
± 5
± 8
V
1
2
2
IL
Input Leakage Current
I
µA
µA
V
lkg
Clock Input Leakage Current
Clock Input Signal Voltage
I
—
clkg
V
in
– 0.3
0.2
V
V
+ 0.3
DD
Clock Input Differential Voltage
Clock Input Common Mode Voltage Range (See Figure 3)
V
DIF
V
CM
(dc)
(dc)
+ 0.6
V
3
4
DD
1.1
2.1
V
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% t
(e.g., 2 ns at a clock cycle time of 10 ns).
KHKH
2. 0 V ≤ V ≤ V
in
for all pins.
DDQ
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
DC OUTPUT CHARACTERISTICS
Parameter
Symbol
Min
– 1.0
—
Max
1.0
0.4
—
Unit
µA
V
Notes
Output Leakage Current
Output Low Voltage
I
lkg
V
OL
1
2
Output High Voltage
NOTES:
V
OH
2.4
V
1. I
2. I
= 8.0 mA.
= – 8.0 mA.
OL
OH
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0°C ≤ T ≤ 70°C, Periodically Sampled Rather Than 100% Tested)
A
Characteristic
Symbol
Typ
4
Max
Unit
pF
Input Capacitance
C
5
8
5
in
Input/Output Capacitance
CK, CK Capacitance
C
7
pF
I/O
CK
C
4
pF
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
6
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
Clock Input Pulse Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.1 V
READ/WRITE CYCLE TIMING (See Note 1)
MCM69L737A–8.5
MCM69L819A–8.5
MCM69L737A–9
MCM69L819A–9
MCM69L737A–9.5
MCM69L819A–9.5
Parameter
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
8
Max
—
Min
8
Max
—
Min
9
Max
—
—
—
9.5
4
Cycle Time
t
KHKH
Clock High Pulse Width
t
3.2
3.2
—
—
3.2
3.2
—
—
3.6
3.6
—
KHKL
KLKH
KHQV
Clock Low Pulse Width
t
—
—
Clock High to Output Valid
t
8.5
3.5
—
9
Clock Low to Output Valid
t
—
—
3.5
—
—
KLQV
Clock Low to Output Hold
t
0.5
1
0.5
1
0.5
1
—
—
4
2
KLQX
Clock Low to Output Low–Z
Clock High to Output High–Z
Output Enable Low to Output Low–Z
Output Enable Low to Output Valid
Output Enable to Output Hold
Output Enable High to Output High–Z
t
—
—
2, 3
2, 3
KLQX1
t
t
t
1
3.5
—
1
3.5
—
1
KHQZ
GLQX
GLQV
0.5
—
0.5
—
0.5
—
—
4
3.5
—
3.5
—
t
0.5
—
0.5
—
0.5
—
—
4
GHQX
t
3.5
—
3.5
—
2, 3
GHQZ
Setup Times:
Hold Times:
NOTES:
Address
t
t
0.5
0.5
0.5
—
AVKH
DVKH
Data In
Chip Select
Write Enable
t
SVKH
t
WVKH
Address
Data In
Chip Select
Write Enable
t
t
1
—
1
—
1
—
ns
KHAX
KHDX
t
KHSX
t
KHWX
1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., t ) or at frequencies that exceed the applied K clock frequency.
KHKL
2. This parameter is sampled, and not 100% tested.
3. Measured at ± 200 mV from steady state.
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
7
TIMING LIMITS
V
/2
DDQ
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirementsarespecifiedfromtheexternalsystem
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as amaximum
since the device never provides data later than that
time.
50
Ω
DEVICE
UNDER
TEST
50
Ω
Figure 1. AC Test Load
V
OH
V
SS
50%
100%
20% t
KHKH
Figure 2. Undershoot Voltage
V
DDQ
V
TR
CROSSING POINT
V
DIF
V
*
CM
V
CP
V
SS
*V
, the Common Mode Input Voltage, equals V
CM TR
– ((V
TR
– V )/2).
CP
Figure 3. Differential Inputs/Common Mode Input Voltage
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
8
REGISTER LATCH READ–WRITE–READ CYCLES
t
t
KHKL
KHKH
CK
SA
t
t
AVKH
KLKH
t
KHAX
A1
A0
A2
t
A3
A4
SVKH
t
KHSX
SS
t
WVKH
t
KHWX
SW
SBx
G
t
KLQX
Q1
t
t
KHQV
KHQZ
t
t
DVKH
t
t
KLQV
t
KHQZ
KLQX1
Q4
t
KHDX
KLQX1
DQ
Q0
READ
D2
WRITE
Q3
READ
READ
READ
DESELECT (HIGH–Z)
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
9
REGISTER LATCH READ–WRITE–READ CYCLES
(G Controlled)
CK
A0
A1
A2
A3
A4
SA
SS
SW
SBx
G
t
GLQV
t
t
GHQX
GLQX
t
GHQZ
DQ
Q0
READ
Q1
READ
D2
Q3
READ DESELECT (HIGH–Z)
Q4
READ
WRITE
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
10
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
(V ). Reads of all bytes proceed normally and write cycles,
SS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
falling edge of the current cycle, the output latch becomes
transparent and data is available. The output data is latched
on the rising edge of the next clock. The output data is avail-
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable in-
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
able at the output at t
or t
whichever is later.
KLQV
is the internal latency of the device. During this same
KHQV
t
KHQV
cycle a new read address can be applied to the address pins.
A write cycle can occur on the next cycle as long as t
KHQZ
are met. Read cycles may follow write cycles im-
and t
DVKH
mediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers immediately. SW low deselects the output
drivers immediately (on the same cycle). Output selecting via
a low on SS and high on SW at a rising CK clock has its ef-
LATE WRITE
The write address is sampled on the first rising edge of
clock and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
fect on the output drivers at t
. Output drive is also con-
KLQX
trolled directly by output enable, G. G is an asynchronous
input. No clock edges are required to enable or disable the
output with G.
Output data will be valid the latter of t
, t
, or
GLQV KHQV
t
. Outputs will begin driving at t
. Outputs will
inthecaseof
KLQV
KLQX1
holdpreviousdatauntilt
t
ort
KLQX, GHQX KHQZ
POWER UP AND INITIALIZATION
a write following a read.
The following supply voltage application sequence is
recommended: V , V , then V
. Please note, per the
SS DD
DDQ
AbsoluteMaximumRatingstable,V
WRITE AND BYTE WRITE FUNCTIONS
isnottoexceedV
DDQ
DD
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
+ 0.5 V, whatever the instantaneous value of V . Once
DD
supplies have reached specification levels, a minimum dwell
of 1.0 ms with C/K clock inputs cycling is required before
beginning normal operations.
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
11
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
1149.1 compliant TAPs. The TAP operates using conven-
tional JEDEC Standard 8–1B Low Voltage (3.3 V) TTL/
CMOS logic level signaling.
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for 1149.1 compliance. Certain functions have been modified
or eliminated because their implementation places extra
delays in the RAMs critical speed path. Nevertheless, the
RAM supports the standard TAP controller architecture. (The
TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with Standard
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP Controller without interfering with normal op-
eration of the device, TCK must be tied to V
to preclude
SS
mid level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to V
nected.
through a 1 k resistor. TDO should be left uncon-
DD
TAP DC OPERATING CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Parameter
Symbol
Min
2.0
– 0.3
—
Max
V + 0.3
DD
Unit
V
Note
Logic Input Logic High
Logic Input Logic Low
Logic Input Leakage Current
CMOS Output Logic Low
CMOS Output Logic High
TTL Output Logic Low
TTL Output Logic High
NOTES:
V
IH
1
V 1
IL
0.8
± 5
0.2
—
V
I
µA
V
1
2
3
4
5
lkg
V 1
OL
—
V 1
OH
V
– 0.2
V
DD
V 2
OL
—
0.4
—
V
V 2
OH
2.4
V
1. 0 V ≤ V ≤ V
2. I 1 ≤ 100 µA. Sampled, not 100% tested.
OL
for all logic input pins.
in
DDQ
3.
I
1 ≤ 100 µA. Sampled, not 100% tested.
OH
OL
4. I 2 ≤ 8 mA.
5.
I
2 ≤ 8 mA.
OH
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
12
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0°C ≤ T ≤ 70°C, Unless Otherwise Noted)
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Test Load . . . . . . 50 Ω Parallel Terminated T–line with 20 pF
Receiver Input Capacitance
Test Load Termination Supply Voltage (V ) . . . . . . . . . . . . . . . 1.5 V
T
TAP CONTROLLER TIMING
Parameter
Symbol
Min
100
40
40
10
10
10
10
10
10
0
Max
—
—
—
—
—
—
—
—
—
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
THTH
Clock High Time
Clock Low Time
TMS Setup
t
THTL
t
TLTH
t
t
MVTH
THMX
TMS Hold
TDI Valid to TCK High
TCK High to TDI Don’t Care
Capture Setup
t
DVTH
THDX
t
t
1
1
CS
Capture Hold
t
CH
TCK Low to TDO Unknown
TCK Low to TDO Valid
NOTES:
t
t
TLQX
—
TLOV
1. t + t
CS CH
defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
AC TEST LOAD
1.5 V
50
Ω
DEVICE
UNDER
TEST
50
Ω
20 pF
TAP CONTROLLER TIMING DIAGRAM
t
THTH
t
TLTH
TEST CLOCK
(TCK)
t
THTL
t
THMX
t
MVTH
TEST MODE SELECT
(TMS)
t
THDX
t
DVTH
TEST DATA IN
(TDI)
t
t
TLQV
TLQX
TEST DATA OUT
(TDO)
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
13
BOUNDARY SCAN REGISTER
TEST ACCESS PORT PINS
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a log-
ic one input level.
TDI — TEST DATA IN (INPUT)
The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (refer to Figure 5, TAP Controller State Diagram). An
undriven TDI pin will produce the same result as a logic one
input level.
IDENTIFICATION (ID) REGISTER
TDO — TEST DATA OUT (OUTPUT)
The ID Register is a 32–bit register that is loaded with a
device and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
Output that is active depending on the state of the TAP
state machine (refer to Figure 5, TAP Controller State Dia-
gram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO.
TRST — TAP RESET
This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic reset state is entered while TMS
is held high for five rising edges of TCK. Power on reset cir-
cuitry is included internally. This type of reset does not affect
the operation of the system logic. The reset affects test logic
only.
ID Register Presence Indicator
Bit No.
Value
0
1
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1 – 1990
TEST ACCESS PORT REGISTERS
OVERVIEW
Bit No. 11
Value
10
9
8
7
6
5
4
3
2
1
The various TAP registers are selected (one at a time) via
the sequences of ones and zeros input to the TMS pin as the
TCK is strobed. Each of the TAPs registers are serial shift
registers that capture serial input data on the rising edge of
TCK and push serial data out on subsequent falling edge of
TCK. When a register is selected it is “placed” between the
TDI and TDO pins.
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
Value
17
16
15
14
13
12
x
x
x
x
x
x
Device Width
Configuration
128K x 36
Bit No.
Value
Value
22
0
21
20
1
19
0
18
0
INSTRUCTION REGISTER
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction regis-
ter is automatically preloaded with the IDCODE instruction at
power–up or whenever the controller is placed in test–logic–
reset state.
0
0
256K x 18
0
0
1
1
Device Depth
Configuration
Bit No.
Value
Value
27
0
26
0
25
1
24
0
23
1
128K x 36
256K x 18
0
0
1
1
0
Revision Number
BYPASS REGISTER
Bit No.
Value
31
30
29
28
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
x
x
x
x
Figure 4. ID Register Bit Meanings
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
14
MCM69L737A Bump/Bit Scan Order
MCM69L819A Bump/Bit Scan Order
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
1
M2
SA
5R
4P
4T
6R
5T
7T
6P
7P
6N
7N
6M
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SA
NC
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4G
4H
4M
3L
1
M2
SA
5R
6T
4P
6R
5T
7T
7P
6N
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
SBb
NC
3G
4D
4E
4G
4H
4M
2K
1L
2
2
3
SA
SA
3
SA
SS
4
SA
SA
4
SA
NC
5
SA
SA
5
SA
NC
6
ZZ
SA
6
ZZ
SW
DQb
DQb
DQb
DQb
DQb
SA
7
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
SBa
CK
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
SBc
NC
7
DQa
DQa
DQa
DQa
SBa
CK
8
8
9
9
2M
1N
2P
3T
2R
4N
2T
3R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7K
5L
4L
7L
CK
4K
4F
6H
7G
6F
7E
6D
6A
6C
5C
5A
6B
5B
3B
2B
3A
3C
2C
2A
1D
2E
2G
1H
SA
6K
7K
5L
G
SA
DQa
DQa
DQa
DQa
DQa
SA
SA
M1
4L
CK
4K
4F
5G
7H
6H
7G
6G
6F
7E
6E
7D
6D
6A
6C
5C
5A
6B
5B
SS
G
NC
SBb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SA
NC
SW
SBd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
SA
SA
SA
1K
2K
1L
SA
NC
SA
2L
SA
2M
1N
2N
1P
2P
3T
2R
4N
3R
NC
SA
SA
SA
SA
SA
SA
DQb
DQb
DQb
DQb
SA
SA
NC
SA
35
SA
M1
NOTES:
1. TheNC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. In scan mode, differential inputs CK and CK are referenced to each other and must be at opposite logic levels for reliable operation.
3. M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. M1 and M2 must be driven to within 100 mV of a V
DD
or V
supply rail to ensure consistent results.
SS
4. ZZ must remain at V during boundary scan to ensure consistent results.
IL
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
15
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture setup plus hold
TAP CONTROLLER INSTRUCTION SET
OVERVIEW
time (t
plus t ). The RAMs clock inputs need not be
CS
CH
There are two classes of instructions defined in Standard
1149.1–1990; the standard (public) instructions, and device
specific (private) instructions. Some public instructions, are
mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implement-
ed. The TAP on this device may be used to monitor all input
and I/O pads, but can not be used to load address, data, or
control signals into the RAM or to preload the I/O buffers. In
other words, the device will not perform IEEE 1149.1
EXTEST, INTEST, or the preload portion of the SAMPLE/
PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state,
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins. Be-
cause the PRELOAD portion of the command is not im-
plemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore, this
device is not IEEE 1149.1 compliant. Nevertheless, this
RAMs TAP does respond to an all zeros instruction, as
follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in
response to the SAMPLE/PRELOAD instruction described
above, except the RAM outputs are forced to High–Z any
time the instruction is loaded.
IDCODE
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
The BYPASS instruction is loaded in the instruction regis-
ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
SAMPLE/PRELOAD
If the SAMPLE–Z instruction is loaded in the instruction
register, all RAM outputs are forced to an inactive drive state
(High–Z) and the boundary scan register is connected be-
tween TDI and TDO when the TAP controller is moved to the
shift–DR state.
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the Instruction register, moving the TAP controller
into the capture–DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK), it is
possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e., in a metast-
able state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results can not be
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NOOP
Do not use these instructions; they are reserved for future
use.
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
16
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
EXTEST
Code*
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM outputs to High–Z state. NOT IEEE 1149.1 COMPLIANT.
IDCODE
001**
100
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
010
Places bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM output drivers to High–Z state.
*Instruction codes expressed in binary, MSB on left, LSB on right.
**Default instruction automatically loaded at power–up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
NO OP
Code*
011
Description
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
NO OP
NO OP
101
110
* Instruction codes expressed in binary, MSB on left, LSB on right.
TEST–LOGIC
RESET
1
0
1
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
1
0
0
0
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–DR
1
SHIFT–IR
1
0
0
1
1
EXIT1–DR
0
EXIT1–IR
0
PAUSE–DR
1
PAUSE–IR
1
0
0
0
0
EXIT2–DR
1
EXIT2–IR
1
UPDATE–DR
UPDATE–IR
1
0
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MCM69L737A•MCM69L819A
17
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
69L737A
MCM
69L819A XX
X
X
Motorola Memory Prefix
Part Number
R = Tape and Reel, Blank = Tray
Speed (8.5 = 8.5 ns, 9 = 9 ns,
9.5 = 9.5 ns)
Package (ZP = PBGA)
Full Part Numbers — MCM69L737AZP8.5
MCM69L819AZP8.5
MCM69L737AZP9
MCM69L819AZP9
MCM69L737AZP9.5
MCM69L819AZP9.5
MCM69L737AZP9.5R
MCM69L819AZP9.5R
MCM69L737AZP8.5R MCM69L737AZP9R
MCM69L819AZP8.5R MCM69L819AZP9R
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
18
PACKAGE DIMENSIONS
ZP PACKAGE
7 X 17 BUMP PBGA
CASE 999–01
NOTES:
0.20 (0.008)
4X
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
–W–
2. CONTROLLING DIMENSION: MILLIMETER.
PIN 1A
IDENTIFIER
7
6
5
4
3 2 1
MILLIMETERS
MIN MAX
14.00 BSC
22.00 BSC
INCHES
MIN MAX
0.551 BSC
0.866 BSC
A
B
C
D
E
F
G
H
J
DIM
A
B
C
D
E
–––
0.60
0.50
1.30
2.40
–––
0.024
0.020
0.051
0.094
0.90
0.70
1.70
0.035
0.028
0.067
B
–L–
S
P
F
K
L
G
K
N
P
1.27 BSC
0.050 BSC
M
N
P
R
T
0.80
11.90
19.40
1.00
12.10
19.60
0.031
0.469
0.764
0.039
0.476
0.772
16X G
R
S
7.62 BSC
20.32 BSC
0.300 BSC
0.800 BSC
U
119X
D
N
6X
G
S
S
S
S
0.30 (0.012)
0.10 (0.004)
T
T
W
L
R
TOP VIEW
BOTTOM VIEW
0.25 (0.010)
T
F
0.35 (0.014)
T
0.15 (0.006)
T
C
–T–
K
SIDE VIEW
E
MCM69L737A•MCM69L819A
MOTOROLA FAST SRAM
19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
Customer Focus Center: 1–800–521–6274
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609
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Motorola Fax Back System
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/
MCM69L737A/D
◊
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