MCM69R736ZP5 [MOTOROLA]
Cache SRAM, 128KX36, 2.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119;
| 型号： | MCM69R736ZP5 |
| 厂家： | 
MOTOROLA |
| 描述： | Cache SRAM, 128KX36, 2.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119 信息通信管理 静态存储器 |
| 文件： | 总20页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MCM69R736/D
SEMICONDUCTOR TECHNICAL DATA
MCM69R736
MCM69R818
Advance Information
4M Late Write HSTL
The MCM69R736/818 is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R818
organized as 256K words by 18 bits, and the MCM69R736 organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.
ZP PACKAGE
PBGA
CASE 999–01
TheRAMusesHSTLinputsandoutputs. Theadjustableinputtrip–point(V
)
ref
and output voltage (V
) gives the system designer greater flexibility in
optimizing system performance.
DDQ
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
•
•
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V ± 5% Operation
HSTL – I/O (JEDEC Standard JESD8–6 Class I and Class II Compatible)
HSTL – User Selectable Input Trip–Point
HSTL – Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x 18 or x 36 organization
MCM69R736/818–5 = 5 ns
MCM69R736/818–6 = 6 ns
MCM69R736/818–7 = 7 ns
•
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 17 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
5/3/96
Motorola, Inc. 1996
FUNCTIONAL BLOCK DIAGRAM
DATA IN
REGISTER
ADDRESS
REGISTERS
MEMORY
ARRAY
SA
DQ
DATA OUT
REGISTER
SW
SW
REGISTERS
CONTROL
LOGIC
SBx
CK
G
SS
SS
REGISTERS
PIN ASSIGNMENTS
TOP VIEW
MCM69R736
MCM69R818
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
A
B
C
D
E
V
SA
NC
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
SA
V
V
SA
NC
SA
SA
SA
SA
NC
NC
SA
SA
SA
SA
NC
V
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
SA
V
NC
NC
V
SA
NC
NC
DD
DD
DQc
DQc
DQc
DQc
DQc
V
ZQ
V
DQb DQb
DQb DQb
DQb
NC
NC
DQb
NC
V
ZQ
SS
G
V
DQa
NC
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
SS
G
V
V
V
V
V
V
V
V
DQa
F
F
V
DQb
V
V
DQa
NC
V
DDQ
DDQ
DDQ
DDQ
G
G
DQc
DQc SBc
DQc
NC
NC
SBb
DQb DQb
DQb DQb
NC
DQb SBb
NC
NC
DQa
H
H
DQc
V
V
DQb
NC
V
DQa
NC
SS
SS
SS
J
K
L
J
K
L
V
V
V
V
V
V
V
DDQ
DD
DQd
DQd SBd
ref
DD
ref
DD DDQ
V
V
V
V
V
V V
DD DDQ
DDQ
DD
ref
SS
SS
DD
ref
DQd
V
CK
V
DQa DQa
DQa DQa
NC
DQb
V
V
CK
CK
V
NC
DQa
NC
SS
SS
SS
DQb
NC
SBa
DQa
DQd
CK
SW
SA
SA
SBa
M
N
P
M
N
P
V
DQd
DQd
DQd
V
V
V
V
V
V
DQa
V
V
DQb
NC
V
V
V
SW
SA
SA
V
V
V
NC
DQa
NC
V
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DDQ
SS
SS
SS
SS
SS
SS
DDQ
DQd
DQa DQa
DQa DQa
DQb
NC
DQd
NC
NC
NC
DQb
DQa
NC
R
T
R
T
NC
NC
SA
NC
V
V
V
SA
NC
NC
NC
NC
SA
SA
V
V
V
SA
SA
NC
SS
DD
DD
SS
DD
NC
TCK
DD
SA
TDO
SA
SA
SA
SA
NC
U
U
V
TMS
TDI
TCK
TDO
V
V
TMS
TDI
V
DDQ
DDQ
DDQ
DDQ
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
2
MCM69R736 PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
Description
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
4K
4L
CK
CK
SW
Input
Input
Input
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
4M
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
SS
Input
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4F
2U
3U
4U
5U
4D
G
Input
Input
Input
Input
Output Enable: Asynchronous pin, active low.
Test Mode Select (JTAG).
Test Data In (JTAG).
TMS
TDI
TCK
TDO
ZQ
Test Clock (JTAG).
Output Test Data Out (JTAG).
Input
I/O
Programmable Output Impedance: Programming pin.
Synchronous Data I/O.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
3J, 5J
V
Supply Input Reference: provides reference voltage for input buffers.
Supply Core Power Supply.
ref
4C, 2J, 4J, 6J, 4R, 5R
V
DD
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
Supply Output Power Supply: provides operating power for output buffers.
Supply Ground.
DDQ
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
4G, 4H, 1R, 7R, 1T, 2T, 6T, 7T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
3
MCM69R818 PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
Description
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
4K
4L
CK
CK
SW
Input
Input
Input
Address, data in and control input register clock. Active high.
Address, data in and control input register clock. Active low.
4M
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
5L, 3G
(a), (b)
SBx
SS
Input
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
2U
3U
4U
5U
4D
4F
TMS
TDI
TCK
TDO
ZQ
Input
Input
Input
Test Mode Select (JTAG).
Test Data In (JTAG).
Test Clock (JTAG).
Output Test Data Out (JTAG).
Input
Input
I/O
Programmable Output Impedance: Programming pin.
G
Output Enable: Asynchronous pin, active low.
Synchronous Data I/O.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
3J, 5J
V
Supply Input Reference: provides reference voltage for input buffers.
Supply Core Power Supply.
ref
4C, 2J, 4J, 6J, 4R, 5R
V
DD
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
V
Supply Output Power Supply: provides operating power for output buffers.
Supply Ground.
DDQ
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
V
SS
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 7T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
4
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
)
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
Rating
Core Supply Voltage
Symbol
Value
Unit
V
DD
– 0.5 to + 4.6
V
Output Supply Voltage
Voltage On Any Pin
V
DDQ
– 0.5 to V
V
V
DD + 0.5
V
in
– 0.5 to V
+ 0.5
DD
Input Current (per I/O)
Output Current (per I/O)
Power Dissipation
I
in
± 50
mA
mA
W
I
± 70
—
out
P
D
This devicecontainscircuitrythatwillensure
the output devices are in High–Z at power up.
Temperature Under Bias*
Operating Temperature*
Storage Temperature
T
—
°C
°C
°C
bias
T
J
20 to +110
– 55 to + 125
T
stg
*
Power dissipation capability will be dependent upon package characteristics and
use environment. See enclosed thermal impedance data.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Rating
Symbol
Max
25
Unit
°C/W
°C/W
°C/W
Notes
Junction to Ambient (@ 1 m/s)
Junction to Balls (Bottom)
Junction to Case (Top)
NOTES:
R
θJA
R
θJB
R
θJC
2
3
4
12
10
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(T = 20 to 110 °C, Unless Otherwise Noted)
J
RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Parameter Symbol
Min
3.1
1.4
Max
3.6
Unit
V
Notes
Core Power Supply Voltage
Output Driver Supply Voltage
Active Power Supply Current
V
DD
V
1.6
V
DDQ
DD1
(x18)
(x36)
I
600
700
mA
5
Quiescent Active Power Supply Current
Active Standby Power Supply Current
Quiescent Standby Power Supply Current
I
TBD
TBD
TBD
mA
mA
mA
6
7
8
DD2
I
SB1
SB2
I
NOTES:
1. AlldatasheetparametersspecifiedtofullrangeofV
unlessotherwisenoted. AllvoltagesarereferencedtovoltageappliedtoV bumps.
SS
DD
2. Supply voltage applied to V
3. Supply voltage applied to V
connections.
DD
connections when using the RAM in push–pull output configuration.
DDQ
4. All power supply currents measured with outputs open or deselected.
5. V
6. V
7. V
8. V
= V
= V
= V
= V
(max), t
(max), t
(max), t
(max), t
= t
(min), SS registered active, 50% read cycles.
DD
DD
DD
DD
DD
DD
DD
DD
KHKH KHKH
KHKH
= dc, SS registered active.
= t
(min), SS registered active.
KHKH KHKH
= dc, SS registered inactive.
KHKH
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
+ 0.1
Max
+ 0.3
Unit
V
Notes
DC Input Logic High
V
(dc)
(dc)
(dc)
V
ref
V
IH
DDQ
DC Input Logic Low
V
– 0.3
0.6
V
– 0.1
V
1
2
3
IL
ref
1.1
± 5
Input Reference DC Voltage
Input Leakage Current
V
ref
V
I
—
µA
V
lkg(1)
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage Range
V
in
– 0.3
0.1
V
V
+ 0.3
DDQ
V
DIF
V
CM
(dc)
(dc)
+ 0.6
V
4
DDQ
0.68
1.1
V
Note 5,
Fig. 2
Clock Input Crossing Point Voltage Range
V
X
0.68
1.1
V
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% t
2. Although considerable latitude in the selection of the nominal dc value (i.e. rms value) of V is supported, the peak to peak ac component
(e.g. 2 ns at a clock cycle time of 10 ns).
KHKH
ref
superimposed on V may not exceed 5% of the dc component of V
.
ref ref
for all pins.
3. 0 V ± V ± V
in DDQ
4. Minimum instantaneous differential input voltage required for differential input clock operation.
5. Maximum rejectable common mode input voltage variation.
DC OUTPUT BUFFER CHARACTERISTICS – PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(T = 20 to 110 °C, ZQ = I
(out) (RQ)) (See Notes 5 and 6)
ZQ
Parameter
J
Symbol
Min
Max
V /2 +0.025
DDQ
Unit
V
Notes
Output Logic Low
Output Logic High
V
OL
V
V
/2 – 0.025
/2 – 0.025
1
2
3
4
DDQ
V
OH
V
DDQ
/2 + 0.025
V
DDQ
Light Load Output Logic Low
Light Load Output Logic High
V 1
OL
V
SS
0.2
V
V
OH
1
V
– 0.2
V
DDQ
V
DDQ
NOTES:
1.
2. | I
I
= (V
| = (V
DDQ
/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.
/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.
OL
DDQ
OH
I = ≤ 100 µΑ
OL
3.
4. | I
| ≤ 100 µA
OH
5. The impedance controlled mode is expected to be used in point–to–point applications, driving high impedance inputs.
6. The ZQ pin is connected through RQ to V
for the controlled impedance mode.
SS
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
6
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER OPERATION
vate the outputs, such as deselect cycles.
Impedance updates occur approximately every 32 clock
cycles (CK clock). All clock cycles are counted. For example,
after 32 + 1 contiguous read cycles have occurred, an im-
pedance update will occur the next time SS is high or SW is
low at the rising edge of CK clock.
The output impedance is programmed by a resistor (RQ)
attached between the ZQ pin and V . RQ’s value is five
SS
times the programmed impedance. For example, 250 Ω is re-
quired for an output impedance of 50 Ω.
Impedance updates occur early in cycles that do not acti-
DC OUTPUT BUFFER CHARACTERISTICS – MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(T = 20 to 110 °C, ZQ = V ) (See Notes 5 and 6)
J
DD
Parameter
Symbol
Min.
Max.
Unit
V
Notes
Output Logic Low
Output Logic High
V 2
OL
V
SS
0.4
1
2
3
4
V
2
3
V
V
– 0.4
V
DDQ
V
OH
DDQ
Light Load Output Logic Low
Light Load Output Logic High
V
V
SS
0.2
V
OL
V
OH
3
– 0.2
V
DDQ
V
DDQ
NOTES:
1.
2. | I
I
≤ 20 mA
|≤ 20 mA
OL
OH
I ≤ 100 µA
OL
3.
4. | I
|≤ 100 µA
OH
5. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class II.
6. The ZQ pin is connected to V
DD
to enable the minimum impedance mode.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 20 to 110 °C, Periodically Sampled Rather Than 100% Tested)
J
Characteristic
Symbol
Typ
5
Max
Unit
pF
Input Capacitance
C
5
8
7
in
Input/Output Capacitance
CK, CK Capacitance
C
6
pF
I/O
CK
C
6
pF
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(T = 20 to 110°C, Unless Otherwise Noted)
J
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
ZQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω
READ/WRITE CYCLE TIMING (See Note 3)
MCM69R736–5 MCM69R736–6 MCM69R736–7
MCM69R818–5 MCM69R818–6 MCM69R818–7
Parameter
Symbol
Min
5
Max
—
Min
6
Max
—
—
—
—
3
Min
7
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
KHKH
Clock High Pulse Width
t
2
—
2.4
2.4
1
2.8
2.8
1
—
KHKL
Clock Low Pulse Width
t
2
—
—
KLKH
Clock High to Output Low–Z
Clock High to Output Valid
Clock High to Output Hold
Clock High to Output High–Z
Output Enable Low to Output Low–Z
Output Enable Low to Output Valid
Output Enable to Output Hold
Output Enable High to Output High–Z
Setup Times:
t
1
—
—
2
1
1
2
2
1
1
2
KHQX1
t
—
1
2.5
—
—
1
—
1
3.5
—
KHQV
KHQX
t
—
3
t
t
t
0
2.5
—
0
0
3.25
—
KHQZ
GLQX
GLQV
0.5
—
0.5
—
0.5
0.5
—
0.5
—
0.5
—
3
0.5
—
0.5
—
0.5
2.5
—
3.5
—
t
—
3
GHQX
t
2.5
—
3.5
—
GHQZ
Address
Data In
Chip Select
Write Enable
t
t
—
AVKH
DVKH
t
SVKH
t
WVKH
Hold Times:
NOTES:
Address
Data In
Chip Select
Write Enable
t
t
1
—
1
—
1
—
ns
KHAX
KHDX
t
KHSX
t
KHWX
1. Tested per AC Test Load diagram. See Figure 1A.
2. Measured at ± 200 mV from steady state. See Figure 1B.
3. In no case may control input signals (e.g. SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g. t ) or at frequencies that exceed the applied K clock frequency.
KHKL
AC TEST LOADS
TIMING LIMITS
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
requireit). Ontheotherhand, responsesfrom
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
0.75 V
0.75 V
V
/2
DDQ
V
/2
DDQ
V
V
ref
ref
50
Ω
50
Ω
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
50
Ω
Ω
250
Ω
250
5 pF
ZQ
ZQ
Figure 1A
Figure 1B
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
8
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Note
AC Input Logic High
AC Input Logic Low
V
(ac)
(ac)
V +200 mV
ref
Fig. 3
IH
V
V –200 mV
ref
Note 1,
Fig. 1, 3
IL
Input Reference Peak to Peak ac Voltage
Clock Input Differential Voltage
V
(ac)
(ac)
5% V (dc)
ref
2
3
ref
V
400 mV
V
+600 mV
dif
DDQ
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% t
2. Although considerable latitude in the selection of the nominal dc value (i.e. rms value) of V is supported, the peak to peak ac component
(e.g. 2 ns at a clock cycle time of 10 ns).
KHKH
ref
superimposed on V may not exceed 5% of the dc component of V
.
ref ref
3. Minimum instantaneous differential input voltage required for differential input clock operation.
V
OH
V
SS
50%
100%
20% t
KHKH
Figure 1. Undershoot Voltage
V
DDQ
VTR
CROSSING POINT
V
dif
VCM*
VCP
V
SS
* VCM , the Common Mode Input Voltage, equals VTR–((VTR–VCP)/2).
Figure 2. Differential Inputs/ Common Mode Input Voltage
V (ac)
IH
V
ref
V (ac)
IL
Figure 3. Differential Inputs/ Common Mode Input Voltage
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
9
REGISTER/REGISTER READ–WRITE–READ CYCLES
t
t
KHKH
KHKL
CK
SA
SS
t
t
AVKH
t
KLKH
KHAX
A0
A1
A2
A3
A4
t
SVKH
t
KHSX
t
WVKH
t
KHWX
SW
SBx
G
V
IL
t
t
KHQX1
t
t
KHQZ
KHQV
t
t
KHDX
KHQX
t
KHQX
Q1
DVKH
DQx
Q–1
Q0
D2
Q3
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
10
REGISTER/REGISTER READ–WRITE–READ
(G Controlled)
t
t
KHKH
KHKL
CK
SA
t
t
AVKH
t
KLKH
KHAX
A0
A1
A2
A3
A4
SS
V
IL
SW
SBx
G
t
t
GLQV
GLQX
t
GHQZ
t
GHQX
DQx
Q–1
Q0
Q1
D2
Q3
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
11
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
LATE WRITE
The write address is sampled on the first rising edge of
clock and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to assure coherent op-
eration. This occurs in all cases whether there is a byte write
or a full word is written.
the output register and available at the outputs at t
ing this same cycle a new read address can be applied to the
address pins.
. Dur-
KHQV
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of the CK clock has its effect on
the output drivers after the next rising edge of the CK clock.
SW low deselects the output drivers immediately (on the
same cycle). Output drive is also controlled directly by output
enable, G. No clock edges are required to generate output
disable with G. G asynchronously enables the output drivers.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer imped-
ance by terminating the ZQ pin to V
through a precision
SS
resistor (RQ). The value of RQ is five times the output imped-
ance desired. For example, 250 Ω resistor will give an output
impedance of 50 Ω.
Impedance updates occur early in cycles that do not acti-
vate the outputs, such as deselect cycles, i.e. SW, SS, but
not G. In all cases impedance updates are transparent to the
user and do not produce access time “push–outs” or other
anomalous behavior in the RAM.
Output data will be valid the latter of t
and t
.
GLQV
. Outputs will hold pre-
KHQV
Outputs will begin driving at t
KHQX1
.
vious data until t
or t
KHQX
GHQX
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing pa-
rameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
The output buffers can also be programmed in a minimum
impedance configuration. The output buffers have an output
impedance similar to standard LVTTL outputs but maintain
V
and V as the maximum output voltages.
DDQ
SS
POWER UP AND INITIALIZATION
(V ). Reads of all bytes proceed normally and write cycles,
The following supply voltage application sequence is
SS
activated via a low on SW, and the rising edge of the CK
clock, write the entire RAM I/O width. This way the designer
is spared having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable in-
puts in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simulta-
neously read one byte and write another at the same ad-
dress. A write cycle initiated with none of the byte write
recommended: V , V
Absolute Maximum Ratings table, V
then V
. Please note, per the
is not to exceed
SS DD,
DDQ
DDQ
V
+0.5 V, whatever the instantaneous value of V . Once
DD
DD
supplies have reached specification levels, a minimum dwell
of 1.0 µs with CK clock inputs cycling is required before
beginning normal operations. At power up the output
impedance will be set at approximately 50 Ω, however, in
order to match the programmed impedance the part requires
deselect cycles to occur.
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
12
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
1149.1 compliant TAPs. The TAP operates using convention-
al JEDEC Standard 8–1B Low Voltage (3.3 V) TTL / CMOS
logic level signaling.
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for 1149.1 compliance. Certain functions have been modified
or eliminated because their implementation places extra de-
lays in the RAMs critical speed path. Nevertheless, the RAM
supports the standard TAP controller architecture. (The TAP
controller is the state machine that controls the TAPs opera-
tion) and can be expected to function in a manner that does
not conflict with the operation of devices with Standard
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP Controller without interfering with normal op-
eration of the device, TCK must be tied to V
to preclude
SS
mid level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to V
nected.
through a 1 k resistor. TDO should be left uncon-
DD
TAP DC OPERATING CHARACTERISTICS
(T = 20 to 110°C, Unless Otherwise Noted)
J
Parameter
Symbol
Min
Max
V + 0.3
DD
Unit
V
Note
Logic Input Logic High
Logic Input Logic Low
V
IH
1
2.0
– 0.3
—
V 1
IL
0.8
± 5
0.2
—
V
Logic Input Leakage Current
CMOS Output Logic Low
CMOS Output Logic High
TTL Output Logic Low
I
µA
V
1
2
3
4
5
lkg
V 1
OL
—
V
OH
1
V
– 0.2
V
DD
V 2
OL
—
0.4
—
V
TTL Output Logic High
V
OH
2
2.4
V
NOTES:
1. 0 V± V ± V
for all logic input pins.
= 0.2 V. Sampled, not 100% tested.
–0.2 V. Sampled, not 100% tested.
in
DDQ
2.
3. |I
4.
I
1 ≥ 100 µA @ V
OL OL
1| ≥ 100 µA @ V
OH
DDQ
= 0.4 V
I
2 ≥ 8 mA @ V
OL OL
5. |I 2| ≥ 8 mA @ V
= 2.4 V
OH
OH
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
13
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(T = 20 to 110°C, Unless Otherwise Noted)
J
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Output Test Load . . . . . . 50 Ω Parallel Terminated T–line with 20 pF
Receiver Input Capacitance
Test Load Termination Supply Voltage (V ) . . . . . . . . . . . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
T
TAP CONTROLLER TIMING
Parameter
Cycle Time
Symbol
Min
100
40
40
10
10
10
10
10
10
0
Max
—
—
—
—
—
—
—
—
—
—
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
THTH
Clock High Time
t
THTL
Clock Low Time
t
TLTH
TMS Setup
t
t
MVTH
THMX
TMS Hold
TDI Valid to TCK High
TCK High to TDI Don’t Care
Capture Setup
t
DVTH
THDX
t
t
1
1
CS
Capture Hold
t
CH
TCK Low to TDO Unknown
TCK Low to TDO Valid
NOTES:
t
t
TLQX
—
TLOV
1. t defines the minimum pause in RAM I/O pad transitions to assure accurate pad data capture.
+ t
CS CH
AC TEST LOAD
1.5 V
50
Ω
DEVICE
UNDER
TEST
50
Ω
20 pF
TAP CONTROLLER TIMING DIAGRAM
t
THTH
t
TLTH
TEST CLOCK
(TCK)
t
THTL
t
THMX
t
MVTH
TEST MODE SELECT
(TMS)
t
THDX
t
DVTH
TEST DATA IN
(TDI)
t
t
TLQV
TLQX
TEST DATA OUT
(TDO)
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
14
TEST ACCESS PORT PINS
TCK – TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
BOUNDARY SCAN REGISTER
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic 1) reserved for density
upgrade address pins. There are a total of 70 bits in the case
of the x36 device and 51 bits in the case of the x18 device.
The boundary scan register, under the control of the TAP
controller, is loaded with the contents of the RAMs I/O ring
when the controller is in capture–DR state and then is placed
between the TDI and TDO pins when the controller is moved
to shift–DR state. Several TAP instructions can be used to
activate the boundary scan register.
TMS – TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a log-
ic one input level.
TDI – TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (refer to Figure 5 TAP Controller State Diagram). An
undriven TDI pin will produce the same result as a logic one
input level.
The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
IDENTIFICATION (ID) REGISTER
The ID Register is a 32 bit register that is loaded with a de-
vice and vendor specific 32 bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32 bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
TDO – TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (refer to Figure 5 TAP Controller State Dia-
gram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO.
TRST – TAP RESET
This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic reset state is entered while TMS
is held high for five rising edges of TCK. Power on reset cir-
cuitry is included internally. This type of reset does not affect
the operation of the system logic. The reset affects test logic
only.
ID Register Presence Indicator
Bit #
0
1
Value
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1 – 1990
TEST ACCESS PORT REGISTERS
OVERVIEW
Bit #
11
10
9
8
7
6
5
4
3
2
1
The various TAP registers are selected (one at a time) via
the sequences of ones and zeros input to the TMS pin as the
TCK is strobed. Each of the TAPs registers are serial shift
registers that capture serial input data on the rising edge of
TCK and push serial data out on subsequent falling edge of
TCK. When a register is selected it is “placed” between the
TDI and TDO pins.
Value
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit #
Value
17
16
15
14
13
12
x
x
x
x
x
x
Device Width
Configuration
128Kx36
Bit #
Value
Value
22
0
21
20
1
19
0
18
0
INSTRUCTION REGISTER
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction regis-
ter is automatically preloaded with the IDCODE instruction at
power–up or whenever the controller is placed in test–logic–
reset state.
0
0
256Kx18
0
0
1
1
Device Depth
Configuration
Bit #
Value
Value
27
0
26
0
25
1
24
0
23
1
128Kx36
256Kx18
0
0
1
1
0
Revision Number
BYPASS REGISTER
Bit #
31
30
29
28
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
Value
x
x
x
x
Figure 4. ID Register Bit Meanings
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
15
MCM69R736 Bump/Bit Scan Order
MCM69R818 Bump/Bit Scan Order
BIT
#
Signal
Name
Bump
ID
Bit
#
Signal
Name
Bump
ID
Bit
#
Signal
Name
Bump
ID
Bit
#
Signal
Name
Bump
ID
1
M2
SA
5R
4P
4T
6R
5T
7T
6P
7P
6N
7N
6M
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SA
NC
3B
2B
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
4D
4E
4G
4H
4M
3L
1
M2
SA
5R
6T
4P
6R
5T
7T
7P
6N
6L
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
SBb
ZQ
3G
4D
4E
4G
4H
4M
2K
1L
2
2
3
SA
SA
3
SA
SS
4
SA
SA
4
SA
NC
5
SA
SA
5
SA
NC
6
NC
SA
6
NC
SW
DQb
DQb
DQb
DQb
DQb
SA
7
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
SBa
CK
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
SBc
ZQ
7
DQa
DQa
DQa
DQa
SBa
CK
8
8
9
9
2M
1N
2P
3T
2R
4N
2T
3R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7K
5L
4L
7L
CK
4K
4F
6H
7G
6F
7E
6D
6A
6C
5C
5A
6B
5B
3B
2B
3A
3C
2C
2A
1D
2E
2G
1H
SA
6K
7K
5L
G
SA
DQa
DQa
DQa
DQa
DQa
SA
SA
M1
4L
CK
4K
4F
5G
7H
6H
7G
6G
6F
7E
6E
7D
6D
6A
6C
5C
5A
6B
5B
SS
G
NC
SBb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SA
NC
SW
SBd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
SA
SA
SA
1K
2K
1L
SA
NC
SA
2L
SA
2M
1N
2N
1P
2P
3T
2R
4N
3R
NC
SA
SA
SA
SA
SA
SA
DQb
DQb
DQb
DQb
SA
SA
NC
SA
35
SA
M1
NOTES:
1. TheNC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic 1. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. CK, CK, are sampled individually. CK is not simply a forced compliment of the CK input. In scan mode these differential inputs are referenced
to V , not each other.
ref
3. M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. M1 and M2 must be driven to within 100 mV of a V
DD
or V
supply rail to assure consistent results.
SS
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
16
TAP Controller Instruction Set
expected. RAM input signals must be stabilized for long
enough to meet the TAPs input data capture set–up plus hold
OVERVIEW
time (t
plus t ). The RAMs clock inputs need not be
CS
CH
There are two classes of instructions defined in the Stan-
dard 1149.1–1990; the standard (public) instructions, and de-
vice specific (private) instructions. Some public instructions,
are mandatory for 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the
1149.1 conventions, it is not 1194.1 compliant because some
of the mandatory instructions are not fully implemented. The
TAP on this device may be used to monitor all input and I/O
pads, but cannot be used to load address, data or control sig-
nals into the RAM or to preload the I/O buffers. In other
words, the device will not perform Standard 1149.1 EXTEST,
INTEST or the preload portion of the SAMPLE / PRELOAD
command.
When the TAP controller is placed in capture–IR state the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state
the instruction register is placed between TDI and TDO. In
this state the desired instruction is serially loaded through the
TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins. Be-
cause the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the
update–DR state with the SAMPLE / PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not Standard
1149.1 compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic 0s.
EXTEST is not implemented in this device. Therefore this
device is not 1149.1 compliant. Nevertheless, this RAMs TAP
does respond to an all zeros instruction, as follows. With the
EXTEST (000) instruction loaded in the instruction register
the RAM responds just as it does in response to the
SAMPLE / PRELOAD instruction described above, except
the RAM outputs are forced to high–Z any time the
instruction is loaded.
IDCODE
STANDARD (PUBLIC) INSTRUCTIONS
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
BYPASS
The BYPASS instruction is loaded in the instruction regis-
ter when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
THE DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
SAMPLE/PRELOAD
If the SAMPLE–Z instruction is loaded in the instruction
register, all RAM outputs are forced to an inactive drive state
(high–Z) and the boundary scan register is connected be-
tween TDI and TDO when the TAP controller. is moved to the
shift–DR state.
Sample/preload is a Standard 1149.1 mandatory public
instruction. When the sample / preload instruction is loaded
in the Instruction register, moving the TAP controller into the
capture–DR state loads the data in the RAMs input and I/O
buffers into the boundary scan register. Because the RAM
clock(s) are independent from the TAP clock (TCK) it is pos-
sible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable
state). Although allowing the TAP to sample metastable in-
puts will not harm the device, repeatable results cannot be
THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NOOP
Do not use these instructions, they are reserved for future
use.
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
17
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM outputs to High–Z state. *NOT 1149.1 COMPLIANT*
IDCODE
001**
100
Preloads ID register and places it between TDI and TDO.
Does not affect RAM operation.
SAMPLE / PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement 1149.1 Preload function. * NOT 1149.1 COMPLIANT *
BYPASS
111
010
Places bypass register between TDI and TDO.
Does not affect RAM operation.
SAMPLE–Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM output drivers to High–Z.
*Instruction codes expressed in binary, MSB on left, LSB on right.
**Default instruction automatically loaded at power–up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
NO OP
Code*
011
Description
Do not use these instructions, they are reserved for future use.
Do not use these instructions, they are reserved for future use.
Do not use these instructions, they are reserved for future use.
NO OP
101
NO OP
110
*Instruction codes expressed in binary, MSB on left, LSB on right.
TEST–LOGIC
RESET
1
0
1
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
1
0
0
0
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–DR
1
SHIFT–IR
1
0
0
1
1
EXIT1–DR
0
EXIT1–IR
0
PAUSE–DR
1
PAUSE–IR
1
0
0
0
0
EXIT2–DR
1
EXIT2–IR
1
UPDATE–DR
UPDATE–IR
1
0
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
18
ORDERING INFORMATION
(Order by Full Part Number)
69R736
MCM
69R818
XX
X
X
R = Tape and Reel, Blank = Tray
Speed (5 = 5 ns, 6 = 6 ns, 7 = 7 ns)
Package (ZP = PBGA)
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM69R736ZP5
MCM69R818ZP5
MCM69R736ZP6
MCM69R818ZP6
MCM69R736ZP7
MCM69R818ZP7
MCM69R736ZP5R MCM69R736ZP6R MCM69R736ZP7R
MCM69R818ZP5R MCM69R818ZP6R MCM69R818ZP7R
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM69R736•MCM69R818
MOTOROLA FAST SRAM
19
PACKAGE DIMENSIONS
ZP PACKAGE
7 X 17 BUMP PBGA
CASE 999–01
0.20 (0.008)
4X
A
-W-
PIN 1A
IDENTIFIER
-T-
0.15 (0.006)
0.25 (0.010)
T
T
0.35 (0.014)
T
NOTES:
B
-L-
P
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
MILLIMETERS
MIN MAX
14.00 BSC
22.00 BSC
INCHES
MIN MAX
0.551 BSC
0.866 BSC
DIM
A
B
C
D
E
–––
0.60
0.50
1.30
2.40
–––
0.024
0.020
0.051
0.094
N
0.90
0.70
1.70
0.035
0.028
0.067
TOP VIEW
F
G
K
N
P
R
S
1.27 BSC
0.050 BSC
0.80
11.90
19.40
1.00
12.10
19.60
0.031
0.469
0.764
0.039
0.476
0.772
R
6X
G
7.62 BSC
20.32 BSC
0.300 BSC
0.800 BSC
U
T
K
F
R
P
N
M
L
K
J
H
G
F
E
C
16X G
S
SIDE VIEW
E
D
C
B
A
1
2 3 4 5 6 7
119X
D
BOTTOM VIEW
S
S
S
0.30 (0.012)
0.10 (0.004)
T
T
W
L
S
How to reach us:
USA / EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MCM69R736/D
◊
相关型号：
MCM69R736ZP5R
Cache SRAM, 128KX36, 2.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R736ZP6R
Cache SRAM, 128KX36, 3ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MOTOROLA
MCM69R737AZP5R
128KX36 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
NXP
©2020 ICPDF网 联系我们和版权申明