MCM72F7ADG10_技术文档

Order this document

by MCM72F6A/D

SEMICONDUCTOR TECHNICAL DATA

MCM72F6A

MCM72F7A

512KB and 1MB Synchronous

Fast Static RAM Module

The MCM72F6A (512KB) is configured as 64K x 72 bits and the MCM72F7A

(1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual–

in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit

flow–through BurstRAMs.

168–LEAD DIMM

CASE 1115J–01

TOP VIEW

Address (A), data inputs (DQ, DP), and all control signals except output enable

(G) are clock (K) controlled through positive–edge–triggered noninverting reg-

isters.

1

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature provides increased timing flexibility for incoming

signals. Synchronous byte write (W) allows writes to either individual bytes or to

both bytes.

11

•

Single 3.3 V + 10%, – 5% Power Supply

Plug and Pin Compatibility with 2MB and 4MB

Multiple Clock Pins for Reduced Loading

All Inputs and Outputs are LVTTL Compatible

Byte Write Capability

Fast SRAM Access Times: 9/10/12 ns

Decoupling Capacitors for Each Fast Static RAM

High Quality Multi–Layer FR4 PWB With Separate Power and Ground

Planes

40

41

•

Amp Connector, Part Number: 390064–4

5 V Tolerant on All Pins (Inputs and I/Os)

168–Pin DIMM Module

84

1/29/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM72F6A•MCM72F7A

1

MCM72F6A BLOCK DIAGRAM

64K x 18

SE1

G

64K x 18

SE1

G

64K x 18

SE1

G

64K x 18

SE1

G

E0

G0

A0 – A15

ADSP

W0

A0 – A15

ADSC

A0 – A15

ADSC

A0 – A15

ADSC

A0 – A15

ADSC

W2

W4

W6

SBa

SBb

SBa

SBb

SBa

SBb

SBa

SBb

W1

K0

W3

K1

W5

K2

W7

K3

K

SE2

ADV

ADSP

V

SGW

DD

SW

LBO

SE3

LBO

SE3

LBO

SE3

LBO

SE3

V

SS

DQa0 – DQa7

DQa8

DQa0 – DQa7

DQa8

DQa0 – DQa7

DQa8

DQa0 – DQa7

DQa8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

DQ0 – DQ7

DP0

DQ16 – DQ23

DP2

DQ32 – DQ39

DP4

DQ48 – DQ55

DP6

DQ8 – DQ15

DP1

DQ24 – DQ31

DP3

DQ40 – DQ47

DP5

DQ56 – DQ63

DP7

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

2

MCM72F7A BLOCK DIAGRAM

64K x 18

SE1

64K x 18

SE1

64K x 18

SE1

64K x 18

SE1

E0

G0

G

A0 – A15

ADSP

A0 – A15

ADSC

A0 – A15

ADSC

A0 – A15

ADSC

A0 – A15

ADSC

W0

W2

W4

W6

SBa

SBb

SBa

SBb

SBa

SBb

SBa

SBb

W1

K0

W3

K1

W5

K2

W7

K3

K

DQa0 – DQa7

DQa8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

DQb0 – DQb7

DQb8

SE2

ADV

ADSP

SGW

V

DD

SW

LBO

SE3

LBO

SE3

LBO

SE3

LBO

SE3

V

SS

DQ0 – DQ7

DQ16 – DQ23

DQ32 – DQ39

DQ48 – DQ55

DP0

DQ8 – DQ15

DP1

DP2

DQ24 – DQ31

DP3

DP4

DQ40 – DQ47

DP5

DP6

DQ56 – DQ63

DP7

64K x 18

A0 – A15

ADSC

64K x 18

A0 – A15

ADSC

64K x 18

A0 – A15

ADSC

64K x 18

A0 – A15

ADSC

SBa

SBb

SBa

SBb

SBa

SBb

SBa

SBb

K

DQb8

DQb0 – DQb7

DQa8

DQa0 – DQa7

SE2

ADV

ADSP

SGW

ADSP

SGW

ADSP

SGW

ADSP

SGW

V

DD

SW

LBO

SE3

SE1

LBO

SE3

SE1

LBO

SE3

SE1

LBO

SE3

SE1

V

SS

E1

G1

G

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

3

PIN ASSIGNMENT

168–LEAD DIMM

TOP VIEW

V

DQ63

DQ62

85

86

87

88

89

90

91

92

93

94

V

SS

1

2

3

4

5

6

7

8

9

10

SS

DP7

DQ61

V

DD

SS

DQ60

DQ58

DQ59

DQ57

V

DP6

SS

DQ56

DQ55

DQ54

V

DD

V

SS

DQ53

DQ51

95

96

97

98

99

DQ52

DQ50

V

SS

DQ48

DQ47

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

V

SS

DQ49

DP5

V

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

V

DD

SS

DQ46

DQ44

DQ45

DQ43

V

SS

DQ41

DP4

SS

DQ42

DQ40

DQ19 41

42

DQ17 43

DP1 44

125 DQ18

126

127 DQ16

128 DQ15

V

SS

V

SS

V

SS

DD

DQ39

DQ37

DQ38

DQ36

45

129

V

SS

DD

V

SS

DQ34

DQ32

SS

DQ14 46

DQ12 47

130 DQ13

131 DQ11

DQ35

DQ33

48

132

V

SS

V

SS

K3

SS

K2

DQ10 49

DQ8 50

133 DQ9

134 DP0

V

DP3

V

SS

51

135

V

DD

SS

DQ31

DQ29

DQ7 52

DQ5 53

136 DQ6

137 DQ4

DQ30

V

DD

SS

54

138

V

SS

DQ28

DQ26

DQ27

DQ25

DQ3 55

DQ1 56

139 DQ2

140 DQ0

V

DP2

SS

57

NC 58

NC 59

141

V

SS

DD

DQ24

DQ23

142 NC

143 NC

DQ22

V

DQ21

V

SS

DD

DQ20

60

NC 61

A14 62

144

V

SS

145 A15

146 A13

V

63

A12 64

A10 65

147

DD

SS

148 A11

149 A9

V

66

A8 67

A6 68

150

SS

151 A7

152 A5

V

69

153

SS

DD

A4 70

A2 71

A0 72

154 A3

155 A1

156 ADSP

V

73

K1 74

75

W7 76

W5 77

157

158 K0

159

160 W6

161 W4

V

SS

V

SS

V

78

W3 79

162

163 W2

V

SS

80

81

82

83

84

164

165

166

167

168

W1

W0

V

SS

G1

DD

G0

E0

E1

V

SS

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

4

PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

72, 155, 71, 154, 70, 152,

68, 151, 67, 149, 65, 148,

64, 146, 62, 145

A0 – A15

Input

Synchronous Address Inputs: These inputs are registered and must meet

setup and hold times.

156

ADSP

Input

I/O

Synchronous Addresss Status Controller: Initiates read, write, or chip

deselect cycle.

134, 44, 121, 31,

105, 15, 92, 86

DP0 – DP7

DQ0 – DQ63

Synchronous Parity Data Inputs/Outputs.

140, 56, 139, 55, 137, 53,

136, 52, 50, 133, 49, 131,

47, 130, 46, 128, 127, 43,

125, 41, 124, 40, 122, 38,

37, 119, 35, 118, 34, 116,

32, 115, 111, 27, 110, 26,

108, 24, 107, 23, 21, 104,

20, 102, 18, 101, 17, 99,

98, 14, 96, 12, 95, 11, 93,

9, 8, 90, 6, 89, 5, 87, 3, 2

Synchronous Data Inputs/Outputs.

167, 83

E0, E1

G0, G1

Input

Synchronous Chip Enable: Active low to enable chip. Negated high —

deselects chip when ADSP is asserted. E1 is only used on 1MB module.

166, 82

Asynchronous Output Enable Input:

Low — enables output buffer.

High — DQx pins are high impedance.

G1 is only used on 1MB module.

158, 74, 113, 29

K0 – K3

Input

Clock: This signal registers the address, data in, and all control signals

except G0 and G1.

164, 80, 163, 79, 161,

77, 160, 76

W0 – W7

Synchronous Byte Write Inputs.

4, 16, 33, 45, 57, 69, 94,

106, 123, 135, 147, 165

V

Supply

Power Supply: 3.3 V + 10%, – 5%. Must be connected on all modules.

Ground.

DD

1, 7, 10, 13, 19, 22, 25, 28,

30, 36, 39, 42, 48, 51, 54, 60,

63, 66, 73, 75, 78, 81, 84, 85,

88, 91, 97, 100, 103, 109,

112, 114, 117, 120, 126, 129,

132, 138, 141, 144, 150, 153,

157, 159, 162, 168

V

SS

58, 59, 61, 142, 143

NC

No Connection: There is no connection to the chip.

DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)

Next Cycle

Deselect

Begin Read

Read

Address Used

None

Ex

1

ADSP

Gx

X

0

DQx

High–Z

DQ

WRITE

X

0

1

0

1

External Address

Current

0

Read

Write

X

0

1

High–Z

DQ

Read

Current

0

Begin Write

Write

External

X

High–Z

Current

X

NOTES:

1. X = don’t care, 1 = logic high, 0 = logic low.

2. Write is defined as any Wx low.

3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

) following G going low.

GLQX

4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

also remain negated at the completion of the write cycle to ensure proper write data hold times.

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

5

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

= 0 V)

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

applicationof any voltage higher thanmaximum

rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been

designed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established.

Rating

Symbol

Value

Unit

V

Power Supply Voltage

V

DD

– 0.5 to + 4.6

– 0.5 to + 6.0

± 20

Voltage Relative to V

V , V

in out

V

SS

Output Current (per I/O)

Power Dissipation

I

mA

W

out

MCM72F6A

MCM72F7A

P

D

4.6

9.2

Temperature Under Bias

Storage Temperature

T

bias

– 10 to + 85

°C

This device contains circuitry that will ensure

the output devices are in High–Z at power up.

T

stg

– 55 to + 125

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(V

= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)

DD

A

RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to V

= 0 V)

SS

Parameter

Supply Voltage (Operating Voltage Range)

Input High Voltage

Symbol

Min

3.135

2.0

Max

3.6

Unit

V

DD

V

IH

5.5**

0.8

V

Input Low Voltage

V

IL

– 0.5*

V

*V ≥ – 2.0 V for t ≤ t

**V ≤ 6 V for t

IH KHKH

/2.

IL

KHKH

/2.

DC CHARACTERISTICS

Parameter

Symbol

Min

—

Max

± 1.0

0.4

Unit

µA

V

Input Leakage Current (0 V ≤ V ≤ V

in

)

I

lkg(I)

DD

Output Leakage Current (0 V ≤ V ≤ V

in

)

I

—

DD

lkg(O)

Output Low Voltage (I

= + 8.0 mA)

V

OL

—

OL

Output High Voltage (I

= – 4.0 mA)

V

OH

2.4

—

V

OH

POWER SUPPLY CURRENTS

Parameter

AC Supply Current (Device Selected, All Outputs Open,

Cycle Time ≥ t min)

Symbol

Min

Max

Unit

MCM72F6ADG9

MCM72F6ADG10

MCM72F6ADG12

MCM72F7ADG9

MCM72F7ADG10

MCM72F7ADG12

I

—

900

860

840

1800

1720

1680

mA

DDA

KHKH

CMOS Standby Supply Current (Deselected,

Clock (K) Cycle Time ≥ t , All Inputs Toggling at

MCM72F6ADG9

MCM72F6ADG10

MCM72F6ADG12

MCM72F7ADG9

MCM72F7ADG10

MCM72F7ADG912

I

—

440

400

380

880

800

760

mA

SB1

KHKH

+ 0.2 V or ≥ V

CMOS Levels V ≤ V

– 0.2 V)

in

SS

DD

Clock Running Supply Current (Deselected,

Clock (K) Cycle Time ≥ t , All Other Inputs

MCM72F6ADG9

MCM72F6ADG10/12

MCM72F7ADG9

I

160

140

320

280

SB2

KHKH

Held to Static CMOS Levels V ≤ V

+ 0.2 V

in

SS

or ≥ V

– 0.2 V)

MCM72F7ADG10/12

DD

MCM72F6A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

Symbol

Typ

Max

Unit

Input Capacitance

I/O Capacitance

W, K

Other Inputs

C

—

16

36

pF

in

C

—

19

pF

I/O

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

6

MCM72F7A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

Symbol

Typ

Max

Unit

Input Capacitance

I/O Capacitance

W, K

E, G

Other Inputs

C

—

22

36

60

pF

in

C

—

28

pF

I/O

MASS (Periodically Sampled Rather Than 100% Tested)

Parameter

Max

16

Unit

g

MCM72F6A

MCM72F7A

20

g

AC OPERATING CONDITIONS AND CHARACTERISTICS

(V

= 3.3 V + 10%, – 5%, T = 0 to 70°C, Unless Otherwise Noted)

DD

A

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V

Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted

DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM72F6A–9

MCM72F7A–9

MCM72F6A–10

MCM72F7A–10

MCM72F6A–12

MCM72F7A–12

Parameter

Symbol

Unit

ns

Notes

Min

12

4

Max

—

9

Min

15

5

Max

—

10

5

Min

16.6

6

Max

—

12

6

Cycle Time

t

KHKH

Clock High Pulse Width

t

KHKL

KLKH

KHQV

Clock Low Pulse Width

t

4

5

6

Clock Access Time

t

—

0

—

0

—

0

Output Enable to Output Valid

Clock High to Output Active

Clock High to Output Change

Output Enable to Output Active

Output Disable to Q–High–Z

Clock High to Q–High–Z

t

5

GLQV

t

—

5

—

5

—

6

5

KHQX1

KHQX2

3

t

0

5

GLQX

t

—

3

—

3

—

3

5, 6

GHQZ

t

5

6

KHQZ

Setup Times

Hold Times:

NOTES:

Address

ADSP

Data In

t

2.5

—

2.5

—

2.5

—

AVKH

ADKH

DVKH

Write

Chip Enable

t

WVKH

t

EVKH

Address

ADSP, ADSC, ADV

Data In

t

0.5

—

0.5

—

0.5

—

ns

KHAX

t

KHADX

KHDX

KHWX

t

KHEX

t

Write

Chip Enable

t

1. In setup and hold times, write refers to any Wx low.

2. Chip Enable is defined as Ex low, whenever ADSP is asserted.

3. All read and write cycle timings are referenced from K or G.

4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

5. This parameter is sampled and not 100% tested.

6. Measured at ± 200 mV from steady state.

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

7

TIMING LIMITS

The table of timing values shows either a minimum or a

maximumlimit for each parameter. Input requirements are

specified from the external system point of view. Thus, ad-

dress setup time is shown as a minimum since the system

must supply at least that much time (even though most

devices do not require it). On the other hand, responses

from the memory are specified from the device point of

view. Thus, the access time is shown as a maximum since

the device never provides data later than that time.

Z

= 50

Ω

0

OUTPUT

50

Ω

V

= 1.5 V

L

Figure 1. AC Test Load

READ/WRITE CYCLES

t

KLKH

KHKH

KHKL

K

Ax

A

B

C

D

E

F

G

ADSP

E

W

G

t

GHQZ

D(D)

t

KHQV

KHQX2

Q(C)

GLQV

GLQX

Q(n)

Q(A)

Q(B)

D(E)

D(F)

Q(G)

DQx

t

KHQX1

KHQZ

DESELECTED

READ

WRITES

READ

ORDERING INFORMATION

(Order by Full Part Number)

MCM

72F

X

A

XX

Motorola Memory Prefix

Part Number

Speed (9 = 9 ns, 10 = 10 ns, 12 = 12 ns)

Package (DG = Gold Pad DIMM)

Module Revision

Memory Size (6A = 512KB, 7A = 1 MB)

Full Part Numbers — MCM72F6ADG9

MCM72F7ADG9

MCM72F6ADG10

MCM72F7ADG10

MCM72F6ADG12

MCM72F7ADG12

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

8

PACKAGE DIMENSIONS

168–LEAD DIMM

CASE 1115J–01

D1

M

0.15 (0.006)

A B C

E

C

L

(DATUM PLANE C)

D5

A1

NOTE 4

COMPONENT

AREA

A

1

84

10

11

40 41

E2

NOTE 5

VIEW C

D4

VIEW B

D6

D4

A

E1 NOTE 6

D3

VIEW C

M

0.016 (0.4)

D2 /2

B

VIEW D

D2

FRONT VIEW

SIDE VIEW

94

95

85

168

COMPONENT

AREA

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

BACK VIEW

2. CONTROLLING DIMENSION: INCH.

3. CARD THICKNESS APPLIES ACROSS TABS AND

INCLUDES PLATING AND/OR METALLIZATION.

4. DIMENSIONS E AND A1 DEFINE A

DOUBLE–SIDED MODULE.

R

A5

5. DIMENSION E2 DEFINES OPTIONAL

SINGLE–SIDED MODULE

6. STRAIGHTNESS CALLOUT APPLIES TO TAB

AREA ONLY.

7. D5 DIMENSION DEFINES SLOT END AND EDGE

OF COMPONENT AREA.

C

K

M

0.004 (0.1)

A B C

K

INCHES

MILLIMETERS

DIM

A

MIN

1.095

0.390

MAX

1.105

–––

MIN

27.81

9.90

MAX

28.07

–––

M

0.004 (0.1)

A B C

VIEW A

A1

A2

A3

A4

A5

b

D1

D2

D3

D4

D5

D6

e

VIEW B

0.118 BSC

0.700 BSC

3.00 BSC

17.78 BSC

0.154

0.161

0.128

0.041

3.90

3.00

0.95

4.10

3.25

1.05

2X A4

0.004 (0.1)

168X b

R

0.118

0.037

5.245

M

0.004 (0.1)

A

B

C

M

A

B C

5.255 133.22 133.48

5.014 BSC

1.700 BSC

0.250 BSC

0.118 –––

0.125 BSC

0.050 BSC

127.35 BSC

43.18 BSC

6.35 BSC

168X L1

3.00

3.175 BSC

1.27 BSC

–––

1

168X L

2X A3

2X A2

E

–––

0.046

–––

0.075

0.100

–––

0.200

–––

1.17

–––

1.90

2.54

–––

4.00

1.37

2.70

2.10

–––

E1

E2

K

L

L1

P

0.054

0.148

0.083

–––

0.010

0.122

162X

e

84

VIEW D

0.25

3.10

2X

P

0.114

2.90

M

0.004 (0.1)

A

B C

VIEW C

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

9

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola

datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and

Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Mfax is a trademark of Motorola, Inc.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,

P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488

Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Motorola Fax Back System

– US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/

CUSTOMER FOCUS CENTER: 1-800-521-6274

MCM72F6A/D

◊

MCM72F6A•MCM72F7A

MOTOROLA FAST SRAM

10


型号：	MCM72F7ADG10
厂家：	MOTOROLA
描述：	512KB and 1MB Synchronous Fast Static RAM Module 512KB和1MB同步快速静态RAM模块
文件：	总10页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCM72F7ADG10 [MOTOROLA]

相关型号：

MCM72F7ADG12

MCM72F7ADG9

MCM72F7DG10

MCM72F7DG12

MCM72F7DG9

MCM72F8

MCM72F8DG12

MCM72F8DG8

MCM72F8DG9

MCM72F9DG12

MCM72F9DG8

MCM72F9DG9