MMSF5P02HD [MOTOROLA]
SINGLE TMOS POWER MOSFET 8.7 AMPERES 20 VOLTS; 单TMOS功率MOSFET 8.7安培20伏型号: | MMSF5P02HD |
厂家: | MOTOROLA |
描述: | SINGLE TMOS POWER MOSFET 8.7 AMPERES 20 VOLTS |
文件: | 总12页 (文件大小:211K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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by MMSF5P02HD/D
SEMICONDUCTOR TECHNICAL DATA
Medium Power Surface Mount Products
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
8.7 AMPERES
20 VOLTS
MiniMOS devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process. These
miniature surface mount MOSFETs feature ultra low R
and true
DS(on)
R
= 0.03 OHM
DS(on)
logic level performance. They are capable of withstanding high energy in
the avalanche and commutation modes and the drain–to–source diode
has a very low reverse recovery time. MiniMOS devices are designed for
use in low voltage, high speed switching applications where power
efficiency is important. Typical applications are dc–dc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage transients.
D
CASE 751–05, Style 13
SO–8
G
•
•
•
•
•
•
•
•
Ultra Low R Provides Higher Efficiency and Extends Battery Life
DS(on)
S
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Source
Source
Source
Gate
I
Specified at Elevated Temperature
DSS
Avalanche Energy Specified
Top View
Mounting Information for SO–8 Package Provided
DEVICE MARKING
ORDERING INFORMATION
Device
S5P02H
Reel Size
Tape Width
12 mm embossed tape
Quantity
4000 units
MMSF5P02HDR2
13″
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola, Inc. 1997
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Negative sign for P–Channel devices omitted for clarity
Rating
Symbol
Max
20
Unit
V
Drain–to–Source Voltage
V
DSS
Drain–to–Gate Voltage (R
GS
= 1.0 MΩ)
V
DGR
20
V
Gate–to–Source Voltage — Continuous
V
GS
± 8.0
V
1 inch SQ.
FR–4 or G–10 PCB
Thermal Resistance — Junction to Ambient
R
50
2.5
20
8.7
7.0
43.5
°C/W
Watts
mW/°C
A
THJA
D
Total Power Dissipation @ T = 25°C
P
A
Linear Derating Factor
I
Drain Current — Continuous @ T = 25°C
D
A
I
D
A
A
10 seconds
Continuous @ T = 70°C
Pulsed Drain Current
A
(1)
I
DM
Minimum
FR–4 or G–10 PCB
Thermal Resistance — Junction to Ambient
R
80
1.56
12.5
6.9
5.5
35
°C/W
Watts
mW/°C
A
THJA
D
Total Power Dissipation @ T = 25°C
P
A
Linear Derating Factor
I
Drain Current — Continuous @ T = 25°C
D
A
I
D
A
A
10 seconds
Continuous @ T = 70°C
Pulsed Drain Current
A
(1)
I
DM
T , T
Operating and Storage Temperature Range
– 55 to 150
°C
J
stg
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
1000
(V
DD
= 20 Vdc, V
= 4.5 Vdc, Peak I = 19 Apk, L = 5.5 mH, R = 25
)
GS
L
G
(1) Repetitive rating; pulse width limited by maximum junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(V = 0 Vdc, I = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0)
(1) (3)
V
Vdc
(BR)DSS
20
—
—
10
—
—
GS
D
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
(V
DS
(V
DS
= 16 Vdc, V
= 16 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
1.0
25
GS
GS
J
Gate–Body Leakage Current (V
GS
= ± 8.0 Vdc, V
DS
= 0)
I
—
—
100
nAdc
Vdc
GSS
(1)
ON CHARACTERISTICS
Gate Threshold Voltage
(Cpk ≥ 2.0)
(1) (3)
(1) (3)
V
GS(th)
(V
DS
= V , I = 0.25 mAdc)
GS
0.7
—
0.9
2.6
1.4
—
D
Threshold Temperature Coefficient (Negative)
mV/°C
mΩ
Static Drain–to–Source On–Resistance
(Cpk ≥ 2.0)
R
DS(on)
(V
GS
(V
GS
= 4.5 Vdc, I = 6.4 Adc)
—
—
22
35
30
45
D
= 2.5 Vdc, I = 5.1 Adc)
D
On–State Drain Current
I
A
D(on)
(V
DS
(V
DS
≤ 5.0 V, V
≤ 5.0 V, V
= 4.5 V)
= 2.5 V)
10
5.0
—
—
—
—
GS
GS
Forward Transconductance (V
= 9.0 Vdc, I = 6.4 Adc)
(1)
g
FS
14
18
—
Mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
1400
925
1960
1300
520
iss
(V
= 16 Vdc, V
= 0 Vdc,
DS
DD
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Transfer Capacitance
C
370
rss
(2)
SWITCHING CHARACTERISTICS
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
19
28
40
55
ns
d(on)
(V
= 6.0 Vdc, I = 1.0 Adc,
Rise Time
D
t
r
V
R
= 4.5 Vdc,
= 6.0 Ω) (1)
GS
G
Turn–Off Delay Time
Fall Time
t
130
90
200
150
38
d(off)
t
f
Gate Charge
See Figure 8
Q
T
Q
1
Q
2
Q
3
27.3
3.4
12
nC
—
(V
DS
= 6.0 Vdc, I = 6.4 Adc,
D
GS
V
= 4.5 Vdc) (1)
—
8.0
—
SOURCE–DRAIN DIODE CHARACTERISTICS
(1)
Forward On–Voltage
V
Vdc
ns
SD
(I = 2.5 Adc, V
= 0 Vdc) (1)
= 0 Vdc, T = 125°C)
S
GS
—
—
0.77
0.6
1.2
—
(I = 2.5 Adc, V
S
GS
J
Reverse Recovery Time
See Figure 15
t
—
—
—
—
95
35
180
—
rr
t
a
(I = 2.5 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs) (1)
S
GS
S
t
60
—
b
Reverse Recovery Stored Charge
Q
0.151
—
µC
RR
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
C
=
pk
3 x SIGMA
(4) Repetitive rating; pulse width limited by maximum junction temperature.
Motorola TMOS Power MOSFET Transistor Device Data
3
TYPICAL ELECTRICAL CHARACTERISTICS
12
10
12
V
=
GS
8
2.3 V
2.5 V
V
≥ 10 V
DS
T
= 25°C
10
8.0
6.0
4.0
J
2.7 V
3.1 V
3.7 V
4.5 V
8.0
6.0
4.0
2.1 V
100°C
25°C
1.9 V
1.7 V
T
= –55
2.0
°C
J
2.0
0
2.0
0
0
0.5
1.0
1.5
2.0
1.0
1.5
2.5
3.0
12
20
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.06
0.06
T
= 25°C
J
I
T
= 6.4 A
= 25°C
D
J
2.5 V
0.04
0.02
0
0.04
0.02
0
V
= 4.5 V
GS
0
2.0
4.0
6.0
8.0
10
0
2.0
4.0
I , DRAIN CURRENT (AMPS)
D
6.0
8.0
10
V
, GATE–TO–SOURCE (VOLTS)
GS
Figure 3. On–Resistance versus Drain Current
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.0
1.5
1.0
1000
100
V
= 0 V
T
= 125°C
GS
J
V
= 4.5 V
GS
= 5.1 A
I
D
100°C
25°C
10
0.5
0
1.0
–50
–25
0
25
50
75
100
C)
125
150
0
4.0
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
8.0
12
16
T , JUNCTION TEMPERATURE (
°
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
6000
4000
2000
0
C
iss
T
V
= 25°C
J
= 0 V
GS
C
rss
C
iss
C
oss
C
rss
–10
0
10
20
V
V
DS
GS
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
Figure 7. Capacitance Variation
Motorola TMOS Power MOSFET Transistor Device Data
5
5.0
10
1000
T
= 25°C
= 1.0 A
J
QT
I
D
8.0
6.0
4.0
4.0
3.0
2.0
V
V
= 6.0 V
= 4.5 V
DD
GS
t
t
d(off)
V
V
DS
GS
f
100
Q1
Q2
t
r
T
= 25°C
= 6.4 A
J
2.0
0
1.0
0
I
D
t
d(on)
Q3
4.0
10
1.0
0
8.0
12
16
20
24
28
10
, GATE RESISTANCE (OHMS)
100
Q
G
, TOTAL GATE CHARGE (nC)
R
G
Figure 8. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
di/dts. The diode’s negative di/dt during t is directly con-
a
trolled by the device clearing the stored charge. However,
the positive di/dt during t is an uncontrollable diode charac-
b
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of t /t serves
b a
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
vice, therefore it has a finite reverse recovery time, t , due to
rr
the storage of minority carrier charge, Q , as shown in the
RR
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
(shorter t ), have less stored charge and a softer reverse re-
rr
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
diode with short t and low Q
these losses.
specifications to minimize
rr
RR
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
7.0
6.0
T
V
= 25°C
J
= 0 V
5.0
4.0
3.0
2.0
GS
1.0
0
0.4
0.5
0.6
0.7
0.8
0.9
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus
Current
6
Motorola TMOS Power MOSFET Transistor Device Data
di/dt = 300 A/µs
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t )
rr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curve (Figure
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
12) defines the maximum simultaneous drain–to–source vol-
tage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (T ) of
C
25°C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the pro-
cedures discussed in AN569, “Transient Thermal Resistance
– General Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded, and that the transition
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
time (t , t ) does not exceed 10 µs. In addition the total power
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
averaged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
equal the values indicated.
100
1000
V
= 20 V
V
= 25 V
= 4.5 V
= 19 Apk
GS
SINGLE PULSE
= 25
DS
V
I
GS
L
1 ms
T
°C
800
600
400
200
0
C
L = 5.5 mH
10
1.0
0.1
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
25
50
75
100
125
C)
150
0.1
1.0
10
100
T , STARTING JUNCTION TEMPERATURE (
°
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
Motorola TMOS Power MOSFET Transistor Device Data
7
TYPICAL ELECTRICAL CHARACTERISTICS
10
1
D = 0.5
0.2
0.1
0.1
Normalized to θja at 10s.
0.05
0.02
0.01
0.0163
Ω
0.0652
Ω
0.1988
Ω
0.6411
Ω
0.9502 Ω
Chip
0.01
0.0307 F
0.1668 F
1.0E+00
0.5541 F
1.9437 F
72.416 F
Ambient
SINGLE PULSE
1.0E–04
0.001
1.0E–05
1.0E–03
1.0E–02
1.0E–01
t, TIME (s)
1.0E+01
1.0E+02
1.0E+03
Figure 14. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 15. Diode Reverse Recovery Waveform
8
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO–8 POWER DISSIPATION
The power dissipation of the SO–8 is a function of the input
pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
the equation for an ambient temperature T of 25°C, one can
calculate the power dissipation of the device which in this case
is 1.6 Watts.
A
determined by T
, the maximum rated junction
J(max)
temperature of the die, R
150°C – 25°C
, the thermal resistance from the
θJA
P
=
= 1.6 Watts
D
80°C/W
devicejunctiontoambient;andtheoperatingtemperature,T .
Using the values provided on the data sheet for the SO–8
A
package, P can be calculated as follows:
D
The 80°C/W for the SO–8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 1.6 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad .
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.
T
– T
A
J(max)
R
P
=
D
θJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola TMOS Power MOSFET Transistor Device Data
9
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. Taken together, these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
16 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
typeofsolderused, andthetypeofboardorsubstratematerial
being used. This profile shows temperature versus time. The
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
205
PEAK AT
SOLDER JOINT
° TO 219°C
200
°
C
C
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
160°C
150°C
150°
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
100
°
C
C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 16. Typical Solder Heating Profile
10
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
NOTES:
–A–
J
1. DIMENSIONS A AND B ARE DATUMS AND T IS A
DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DIMENSIONS ARE IN MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
6. DIMENSION D DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
1
5
4
–B–
M
G
MILLIMETERS
DIM
A
B
C
D
MIN
4.80
3.80
1.35
0.35
0.40
MAX
5.00
4.00
1.75
0.49
1.25
–T–
SEATING
PLANE
F
G
J
K
M
P
R
1.27 BSC
8X D
0.18
0.10
0
0.25
0.25
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
STYLE 13:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
CASE 751–05
SO–8
ISSUE P
Motorola TMOS Power MOSFET Transistor Device Data
11
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
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MMSF5P02HD/D
◊
相关型号:
MMSF7N03ZR2
Power Field-Effect Transistor, 7.5A I(D), 30V, 0.03ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET
MOTOROLA
MMSF7P03HDR2
Power Field-Effect Transistor, 7A I(D), 30V, 0.035ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, CASE 751-05, SO-8
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