MPC555PB [MOTOROLA]
This document provides an overview of the MPC555 microcontroller, including a block diagram showing the major modular components and sections that lis; 本文档提供了MPC555微控制器的概览，包括显示主要的模块化组件和型材的LIS框图
| 型号： | MPC555PB |
| 厂家： | 
MOTOROLA |
| 描述： | This document provides an overview of the MPC555 microcontroller, including a block diagram showing the major modular components and sections that lis |
| 文件： | 总12页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Brief
MPC555PB/D
Rev. 3, 2/2003
MPC555 Product Brief
This document provides an overview of the MPC555 microcontroller, including a block
diagram showing the major modular components and sections that list the major features. The
MPC555 member of the Motorola MPC500 RISC Microcontroller family.
Table 1. MPC555 Features
Device
Flash
Code Compression
MPC555
448 Kbytes
Code compression not supported
1
Introduction
The MPC555 device offers the following features:
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PowerPC™ core with floating-point unit
26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM
448 Kbytes Flash EEPROM with 5-V programming
5-V I/O system
Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B
controller
modules (TouCANTM
)
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50-channel timer system: dual time processor units (TPU3), modular I/O system
(MIOS1)
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32 analog inputs: dual queued analog-to-digital converters (QADC64)
Submicron HCMOS (CDR1) technology
272-pin plastic ball grid array (PBGA) packaging
40-MHz operation, -40 °C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C
for the suffix A device)
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32-bit architecture (PowerPC ISA architecture compliant)
Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz
Fully static, low power operation
Integrated double-precision floating-point unit
Precise exception model
Block Diagram
Extensive system development support
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— On-chip watchpoints and breakpoints
— Program flow tracking
— BDM on-chip emulation development interface
1.1 Block Diagram
Figure 1 is a block diagram of the MPC555.
256 Kbytes
Flash
192 Kbytes
Flash
Burst
Interface
U-bus
E-bus
USIU
RCPU
10 Kbytes
SRAM
16 Kbytes
SRAM
L2U
L-bus
UIMB
QADC
QADC
QSMCM
TouCAN
IMB3
TPU3
DPTRAM
TPU3
TouCAN
MIOS1
Figure 1. MPC555 Block Diagram
1.2 Key Features
The MPC555 key features are explained in the following sections.
1.2.1 Four-Bank Memory Controller
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Works with SRAM, EPROM, Flash EEPROM, and other peripherals
Byte write enables
32-bit address decodes with bit masks
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Key Features
1.2.2 U-Bus System Interface Unit (USIU)
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Clock synthesizer
Power management
Reset controller
MPC555 decrementer and time base
Real-time clock register
Periodic interrupt timer
Hardware bus monitor and software watchdog timer
Interrupt controller that supports up to eight external and eight internal interrupts
IEEE 1149.1 JTAG test access port
External bus interface
— 24 address pins, 32 data pins
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Supports 5V inputs, provides 3.3-V outputs
1.2.3 Flexible Memory Protection Unit
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Four instruction regions and four data regions
4-Kbyte to 16-Mbyte region size support
Default attributes available in one global entry
Attribute support for speculative accesses
1.2.4 448-Kbyte Flash EEPROM Memory
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One 256-Kbyte and one 192-Kbyte module
Page read mode
Block (32-Kbyte) erasable
External 4.75-V to 5.25-V program and erase power supply
1.2.5 26-Kbytes of Static RAM
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One 16-Kbyte and one 10-Kbyte module
Fast (one-clock) access
Keep-alive power
Soft defect detection (SDD)
1.2.6 General-Purpose I/O Support
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Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode
Nine general-purpose I/O pins in MIOS1 unit
Many peripheral pins can be used for general-purpose I/O when not used for primary function
5-V tolerant inputs/outputs
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Key Features
1.2.7 Two Time Processor Units (TPU3)
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Each TPU3 module provides these features:
— A dedicated micro-engine operates independently of the RCPU
— 16 independent programmable channels and pins
— Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare
register and a 16-bit comparator
— Nine pre-programmed timer functions are available
— Any channel can perform any time function
— Each timer function can be assigned to more than one channel
— Two timer count registers with programmable prescalers
— Each channel can be synchronized to one or both counters
— Selectable channel priority levels
— 5-V tolerant inputs/outputs
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6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode
1.2.8 18-Channel Modular I/O System (MIOS1)
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Ten double action submodules (DASM)
Eight dedicated PWM sub-modules (PWMSM)
Two 16-bit modulus counter submodules (MCSM)
Two parallel port I/O submodules (PIOSM)
5-V tolerant inputs/outputs
1.2.9 Two Queued Analog-to-Digital Converter Modules
(QADC64)
Each QADC provides:
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Up to 16 analog input channels, using internal multiplexing
Up to 41 total input channels, using internal and external multiplexing
10-bit A/D converter with internal sample/hold
Typical conversion time of 10 µs (100,000 samples per second)
Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger/level gate
— Software command
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64 result registers
Output data that is right- or left-justified, signed or unsigned
5-V reference and range
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Key Features
1.2.10 Two CAN 2.0B Controller Modules (TouCAN)
Each TouCAN provides these features:
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Full implementation of CAN protocol specification, version 2.0A and 2.0B
Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
Global mask register for message buffers 0 to 13
Independent mask registers for message buffers 14 and 15
Programmable transmit-first scheme: lowest ID or lowest buffer number
16-bit free-running timer for message time-stamping
Low power sleep mode with programmable wake-up on bus activity
Programmable I/O modes
Maskable interrupts
Independent of the transmission medium (external transceiver is assumed)
Open network architecture
Multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode with programmable wakeup on bus activity
1.2.11 Queued Serial Multi-Channel Module (QSMCM)
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Queued serial peripheral interface (QSPI)
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— 160-byte queue buffer
— Programmable transfer length: from 8 to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock divided by 4
— Four programmable peripheral-select pins support up to 16 devices
— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals
(e.g., – serial A/D converters, I/O latches, etc.)
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Two serial communications interfaces (SCI). Each SCI offers these features:
— UART mode provides NRZ format and half-or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1 only)
— Advanced error detection and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or
a new address byte is received
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete
inputs, allowing realization of a low-speed serial protocol
MOTOROLA
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Key Features
2
MPC555 Address Map
The internal memory map is shown in Figure 2.
0x00 0000
CMF Flash A
0x2F C000
Kbytes
256
USIU Control Registers
0x04 0000
1
Kbyte
CMF Flash B
Kbytes
192
0x2F C800
0x2F C840
FLASH Module A (64 bytes)
FLASH Module B (64 bytes)
0x06 FFFF
0x07 0000
0x2F C880
Reserved for Flash
(2.6 Mbytes - 16 Kbytes)
Reserved for USIU
BFFF
0x 2F
0x 2F 000
C
U SI U & F lash
16 Kbytes
Control
0x 2F
FFFF
IMB3 Address Space
0x 30 0000
UIMB Interface &
IMB3 Modules
(32 Kbytes)
0x30 0000
0x30 2000
DPTRAM Control
(12 bytes)
Reserved (8180 bytes)
7
FFF
0x 30
0x 30 8000
DPTRAM (6 Kbytes)
Reserved for IMB3
(480 Kbytes)
Reserved (2 Kbytes)
0x30 4000
0x30 4400
0x30 4800
0x30 4C00
TPU3_A (1 Kbyte)
TPU3_B (1 Kbyte)
QADC_A (1 Kbyte)
0x37 FFFF
0x 38 0000
SR A M C on t r ol A
QADC_B (1 Kbyte)
(
8
bytes)
0x30 5000
0x 38 0008
0x 38 0010
QSMCM (4 Kbytes)
SR A M C on t r ol B
(
8
ytes)
b
0x30 6000
0x30 7080
MIOS1 (4 Kbytes)
Reserved
(485.98 Kbytes)
TouCAN_A (1 Kbyte)
TouCAN_B (1 Kbyte)
Reserved (1920 bytes)
0x30 7480
0x30 7884
0x 3F 9800
0x 3F C000
SRAM A
(10 Kbytes)
0x30 7F80
0x30 7FFF
SRAM B
(16 Kbytes)
UIMB Registers
(128 bytes)
0x 3F
FFFF
Figure 2. MPC555 Internal Memory Map
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Key Features
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MPC555 Pinout Diagram
Figure 3 shows the pinout for the MPC555.
Figure 3. MPC555 Pinout Diagram
MOTOROLA
MPC555ProductBrief
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Key Features
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Supporting Documentation List
This list contains references to currently available and planned documentation.
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MPC555 User’s Manual (MPC555UM/AD)
RCPU Reference Manual (RCPURM/AD)
Board Strategies for Ensuring Optimum Frequency Synthesizer Performance (AN1282/D)
Using the MIOS on the MPC555 Evaluation Board (AN1778/D)
Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX
Family (AN1821/D)
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Non-Volatile Memory Technology Overview (AN1837/D)
Designing Expansion Boards for the Motorola EVB555/ETAS ES200 (AN2001/D)
MPC555 Interrupts (AN2109/D)
EMC Guidelines for MPC500-Based Automotive Powertrain Systems (AN2127/D)
Nexus Standard Specification (non-Motorola document)
Nexus Web Site: http://www.nexus5001.org/
IEEE 1149.1 Specification (non-Motorola document)
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Revision History
Table 2. Revision History
Revision Number
Substantive Changes
Date of Release
2
2.1
3
Existing Document.
September 2001
11 December 2002
11 February 2003
Added temperature range for suffix A device.
Updated template and formats.
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© Motorola, Inc. 2003
MPC555PB/D
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