MPC7410RX400LE [MOTOROLA]

32-BIT, 400MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360;


型号：	MPC7410RX400LE
厂家：	MOTOROLA
描述：	32-BIT, 400MHz, RISC PROCESSOR, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 时钟外围集成电路
文件：	总73页 (文件大小：873K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Advance Information

MPC7410EC

Rev. 2, 10/2003

MPC7410 RISC

Microprocessor

Hardware Speciﬁcations

The MPC7410 is a PowerPC™ microprocessor. The MPC7410 is a reduced instruction set

computing (RISC) microprocessor that implements the PowerPC instruction set architecture.

This document describes pertinent electrical and physical characteristics of the MPC7410. For

functional characteristics of the processor, refer to the MPC7410 RISC Microprocessor User’s

Manual.

This document contains the following topics:

Topic

Page

Section 1.1, “Overview”

Section 1.2, “Features”

Section 1.3, “General Parameters”

Section 1.4, “Electrical and Thermal Characteristics”

Section 1.5, “Pin Assignments”

Section 1.6, “Pinout Listings”

Section 1.7, “Package Description”

Section 1.8, “System Design Information”

Section 1.9, “Document Revision History”

Section 1.10, “Ordering Information”

To locate any published errata or updates for this document, refer to the web site at

http://www.motorola.com/semiconductors.

Overview

1.1 Overview

The MPC7410 is the second implementation of the fourth generation (G4) microprocessors from Motorola.

The MPC7410 implements the full PowerPC 32-bit architecture and is targeted at both computing and

embedded systems applications.

Some comments on the MPC7410 with respect to the MPC750:

•

The MPC7410 adds an implementation of the new AltiVec™ technology instruction set.

The MPC7410 includes signiﬁcant improvements in memory subsystem (MSS) bandwidth and

offers an optional, high-bandwidth MPX bus interface.

•

The MPC7410 adds full hardware-based multiprocessing capability, including a ﬁve-state cache

coherency protocol (four MESI states plus a ﬁfth state for shared intervention).

The MPC7410 is implemented in a next generation process technology for core frequency

improvement.

The MPC7410 ﬂoating-point unit has been improved to make latency equal for double- and

single-precision operations involving multiplication.

•

The completion queue has been extended to eight slots.

There are no other signiﬁcant changes to scalar pipelines, decode/dispatch/completion mechanisms,

or the branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch,

execute, complete/writeback).

Some comments on the MPC7410 with respect to the MPC7400:

•

The MPC7410 adds conﬁgurable direct-mapped SRAM capability to the L2 cache interface.

The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements

a 19th L2 address pin (L2ASPARE on the MPC7400) in order to support additional address range.

•

The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.

Figure 1 shows a block diagram of the MPC7410.

1.2 Features

This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major

features of the MPC7410 are as follows:

•

Branch processing unit

— Four instructions fetched per clock

— One branch processed per cycle (plus resolving two speculations)

— Up to one speculative stream in execution, one additional speculative stream in fetch

— 512-entry branch history table (BHT) for dynamic prediction

— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating

branch delay slots

Dispatch unit

— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to eight independent units (system, branch, load/store, ﬁxed-point

unit 1, ﬁxed-point unit 2, ﬂoating-point, AltiVec permute, AltiVec ALU)

— Serialization control (predispatch, postdispatch, execution serialization)

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Features

Figure 1. MPC7410 Block Diagram

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Features

•

Decode

— Register ﬁle access

— Forwarding control

— Partial instruction decode

•

Completion

— Eight-entry completion buffer

— Instruction tracking and peak completion of two instructions per cycle

— Completion of instructions in program order while supporting out-of-order instruction

execution, completion serialization, and all instruction ﬂow changes

•

Fixed point units (FXUs) that share 32 GPRs for integer operands

— Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical

— Single-cycle arithmetic, shifts, rotates, logical

— Multiply and divide support (multi-cycle)

— Early out multiply

Three-stage ﬂoating-point unit and a 32-entry FPR ﬁle

— Support for IEEE-754 standard single- and double-precision ﬂoating-point arithmetic

— Three-cycle latency, one-cycle throughput (single- or double-precision)

— Hardware support for divide

— Hardware support for denormalized numbers

— Time deterministic non-IEEE mode

•

System unit

— Executes CR logical instructions and miscellaneous system instructions

— Special register transfer instructions

AltiVec unit

— Full 128-bit data paths

— Two dispatchable units: vector permute unit and vector ALU unit.

— Contains its own 32-entry 128-bit vector register ﬁle (VRF) with 6 renames

— The vectorALU unit is further subdivided into the vector simple integer unit (VSIU), the vector

complex integer unit (VCIU), and the vector ﬂoating-point unit (VFPU).

— Fully pipelined

•

Load/store unit

— One-cycle load or store cache access (byte, half word, word, double word)

— Two-cycle load latency with 1-cycle throughput

— Effective address generation

— Hits under misses (multiple outstanding misses)

— Single-cycle unaligned access within double-word boundary

— Alignment, zero padding, sign extend for integer register ﬁle

— Floating-point internal format conversion (alignment, normalization)

— Sequencing for load/store multiples and string operations

— Store gathering

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Features

— Executes the cache and TLB instructions

— Big- and little-endian byte addressing supported

— Misaligned little-endian supported

— Supports FXU, FPU, and AltiVec load/store trafﬁc

— Complete support for all four architecture AltiVec DST streams

Level 1 (L1) cache structure

•

— 32K, 32-byte line, eight-way set-associative instruction cache (iL1)

— 32K, 32-byte line, eight-way set-associative data cache (dL1)

— Single-cycle cache access

— Pseudo least-recently-used (LRU) replacement

— Data cache supports AltiVec LRU and transient instructions algorithm

— Copy-back or write-through data cache (on a page-per-page basis)

— Supports all PowerPC memory coherency modes

— Nonblocking instruction and data cache

— Separate copy of data cache tags for efﬁcient snooping

— No snooping of instruction cache except for ICBI instruction

Level 2 (L2) cache interface

•

— Internal L2 cache controller and tags; external data SRAMs

— 512K, 1M, and 2-Mbyte two-way set-associative L2 cache support

— Copy-back or write-through data cache (on a page basis, or for all L2)

— 32-byte (512-K), 64-byte (1-M), or 128-byte (2-M) sectored line size

— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register)

late write synchronous BurstRAMs

— Supports direct-mapped mode for 256K, 512K, 1M, or 2-Mbyte of SRAM (either all, half, or

none of L2 SRAM must be conﬁgured as direct-mapped)

— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported

— 64-bit data bus which also supports 32-bit bus mode

— Selectable interface voltages of 1.8 and 2.5 V

Memory management unit

•

— 128-entry, two-way set-associative instruction TLB

— 128-entry, two-way set-associative data TLB

— Hardware reload for TLBs

— Four instruction BATs and four data BATs

— Virtual memory support for up to 4 exabytes (2 ) of virtual memory

— Real memory support for up to 4 gigabytes (2 ) of physical memory

— Snooped and invalidated for TLBI instructions

•

Efﬁcient data ﬂow

— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide

— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF

— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s

— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Features

— Up to seven outstanding, out-of-order transactions on the bus

— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same

line

— Store miss merging for multiple store misses to the same line. Only coherency action taken (that

is, address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).

— Two-entry ﬁnished store queue and four-entry completed store queue between load/store unit

and dL1

— Separate additional queues for efﬁcient buffering of outbound data (castouts, write throughs,

etc.) from dL1 and L2

•

Bus interface

— MPX bus extension to 60x processor interface

— Mode-compatible with 60x processor interface

— 32-bit address bus

— 64-bit data bus

— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,

8x, 9x supported

— Selectable interface voltages of 1.8, 2.5, and 3.3 V

Power management

•

— Low-power design with thermal requirements very similar to MPC740 and MPC750

— Low-voltage processor core

— Selectable interface voltages can reduce power in output buffers

— Three static power saving modes: doze, nap, and sleep

— Dynamic power management

•

Testability

— LSSD scan design

— IEEE 1149.1 JTAG interface

— Array built-in self test (ABIST)—factory test only

— Redundancy on L1 data arrays and L2 tag arrays

Reliability and serviceability

— Parity checking on 60x and L2 cache buses

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

General Parameters

1.3 General Parameters

The following list provides a summary of the general parameters of the MPC7410:

Technology

Die size

0.18 µm CMOS, six-layer metal

6.32 mm × 8.26 mm (52 mm )

Transistor count

Logic design

Packages

10.5 million

Fully static

Surface mount 360 ceramic ball grid array (CBGA)

Surface mount 360 high coefﬁcient of thermal expansion

ceramic ball grid array (HCTE)

Core power supply

I/O power supply

1.8 V ± 100 mV DC (nominal; see Table 3 for recommended

operating conditions)

1.8 V ± 100 mV DC or

2.5 V ± 100 mV

3.3 V ± 165 mV (system bus only)

(input thresholds are conﬁguration pin selectable)

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

1.4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical speciﬁcations and thermal characteristics for the MPC7410.

1.4.1 DC Electrical Characteristics

The tables in this section describe the MPC7410 DC electrical characteristics. Table 1 provides the absolute

maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Maximum Value

Unit

Notes

Core supply voltage

PLL supply voltage

–0.3 to 2.1

–0.3 to 3.6

–0.3 to 2.8

L2 DLL supply voltage

Processor bus supply voltage

L2 bus supply voltage

Input voltage

L2AV

3, 6

L2OV

Processor bus

L2 bus

–0.3 to OV + 0.2 V

2, 5

–0.3 to L2OV + 0.2 V

JTAG signals

–0.3 to OV + 0.2 V

Storage temperature range

Rework temperature

Notes:

–55 to 150

260

°C

stg

rwk

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: V must not exceed OV or L2OV by more than 0.2 V at any time including during power-on reset.

3. Caution: L2OV /OV must not exceed V /AV /L2AV by more than 2.0 V at any time including during

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

4. Caution: V /AV /L2AV must not exceed L2OV /OV by more than 0.4 V at any time including during

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

5. V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6. MPC7410RXnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV and have a maximum

value OV of –0.3 to 2.8 V.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410.

(L2)OV

+ 20%

+ 5%

(L2)OV

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of t (OV

)

SYSCLK

or t

(L2OV

)

L2CLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7410 provides several I/O voltages to support both compatibility with existing systems and

migration to future systems. The MPC7410 core voltage must always be provided at nominal voltage (see

Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are

provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. Voltage

must be provided to the L2OV power pins even if the interface is not used. The input voltage threshold

for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL at the negation

of the signal HRESET. These signals must remain stable during part operation and cannot change. The

output voltage will swing from GND to the maximum voltage applied to the OV or L2OV power pins.

Table 2. Input Threshold Voltage Setting

Processor Bus Input

Threshold is Relative to:

L2 Bus Input Threshold is

Relative to:

BVSEL Signal

L2VSEL Signal

Notes

1.8 V

2.5 V

3.3 V

1.8 V

2.5 V

1, 2

1, 4, 5

HRESET

2.5 V

¬HRESET

Not Supported

Notes:

1. Caution: The input threshold selection must agree with the OV /L2OV voltages supplied.

2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals

change state together. This is the preferred method for selecting this mode of operation.

3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used.

4. Default voltage setting if left unconnected (internal pulled-up). MPC7410RXnnnLE (Rev 1.4) and later only.

Previous revisions do not support 3.3 V OV , the default voltage setting if left unconnected is 2.5 V.

5. MPC7410RXnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV , having BVSEL = 1

selects the 2.5-V threshold.

6. MPC7410RXnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. (¬HRESET is

the inverse of HRESET.)

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Table 3 provides the recommended operating conditions for the MPC7410.

Table 3. Recommended Operating Conditions

Recommended

Value

Characteristic

Core supply voltage

Symbol

Unit

Notes

1.8 V ± 100 mV

2.5 V ± 100 mV

3.3 V ± 165 mV

PLL supply voltage

L2 DLL supply voltage

L2AV

Processor bus supply

voltage

BVSEL = 0

BVSEL = HRESET

BVSEL = ¬HRESET or

BVSEL = 1

2, 3

L2 bus supply voltage

Input voltage

L2VSEL = 0

L2OV

1.8 V ± 100 mV

2.5 V ± 100 mV

L2VSEL = HRESET or

L2VSEL = 1

Processor bus and

JTAG signals

GND to OV

L2 bus

GND to L2OV

0 to 105

Die-junction temperature

°C

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. MPC7410RXnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV and have a

recommended OV value of 2.5 V ± 100 mV for BVSEL = 1.

3. MPC7410RXnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET.

Table 4 provides the package thermal characteristics for the MPC7410.

Table 4. Package Thermal Characteristics

Value

Characteristic

Symbol

MPC7410

HCTE

CBGA

Unit

Notes

MPC7410

CBGA

Junction-to-ambient thermal resistance, natural convection,

single-layer (1s) board

°C/W

1, 2

1, 3

Junction-to-ambient thermal resistance, natural convection,

four-layer (2s2p) board

JMA

Junction-to-ambient thermal resistance, 200 ft/min airﬂow,

single-layer (1s) board

Junction-to-ambient thermal resistance, 400 ft/min airﬂow,

single-layer (1s) board

Junction-to-ambient thermal resistance, 200 ft/min airﬂow,

1, 3

four-layer (2s2p) board

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 4. Package Thermal Characteristics (continued)

Value

Characteristic

Symbol

MPC7410

HCTE

CBGA

Unit

Notes

MPC7410

CBGA

Junction-to-ambient thermal resistance, 400 ft/min airﬂow,

°C/W

JMA

four-layer (2s2p) board

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Notes:

°C/W

< 0.1

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airﬂow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of R

for the part is less

θJC

than 0.1˚C/W.

Note: Refer to Section 1.8.8, “Thermal Management Information,” for more details about thermal management.

Table 5 provides the DC electrical characteristics for the MPC7410.

Table 5. DC Electrical Speciﬁcations

At recommended operating conditions (see Table 3)

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit

Notes

Input high voltage (all inputs except

SYSCLK)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

0.65 × (L2)OV

1.7

(L2)OV + 0.2

2, 3, 8

(L2)OV + 0.2

2.0

OV + 0.3

Input low voltage (all inputs except

SYSCLK)

–0.3

1.5

0.35 × (L2)OV

2, 8

0.2 × (L2)OV

0.8

SYSCLK input high voltage

SYSCLK input low voltage

OV + 0.2

2.0

OV + 0.2

2.4

OV + 0.3

–0.3

0.2

0.4

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Table 5. DC Electrical Speciﬁcations (continued)

At recommended operating conditions (see Table 3)

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit

Notes

Input leakage current,

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

—

µA

2, 3,

6, 7

= L2OV /OV

DD DD

High-Z (off-state) leakage current,

= L2OV /OV

µA

2, 3,

5, 7

TSI

Output high voltage, I = –6 mA

(L2)OV – 0.45

—

1.7

2.4

—

Output low voltage, I = 6 mA

0.45

0.4

6.0

—

Capacitance, V = 0 V, f = 1 MHz

—

3, 4, 7

Notes:

1. Nominal voltages; see Table 3 for recommended operating conditions.

2. For processor bus signals, the reference is OV while L2OV is the reference for the L2 bus signals.

3. Excludes factory test signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV and L2OV , or both OV and L2OV must vary in the same

direction (for example, both OV and L2OV vary by either +5% or –5%).

6. Measured at max OV /L2OV

7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.

8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see V /V /V /V /CV /CV DC limits of

IL IH OL OH

1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by

the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR

or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,

there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a

SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET.

Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST

or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 6 provides the power consumption for the MPC7410.

Table 6. Power Consumption for MPC7410

Processor (CPU) Frequency

450 MHz

Unit

Notes

400 MHz

500 MHz

Full-On Mode

4.7

Typical

4.2

9.5

5.3

1, 3

1, 2

Maximum

10.7

11.9

Doze Mode

Nap Mode

Maximum

4.3

1.35

1.3

4.8

5.3

1.65

1.6

1.5

Sleep Mode

1.45

Sleep Mode—PLL and DLL Disabled

Typical

600

1.1

600

1.1

600

1.1

Maximum

Notes:

1. These values apply for all valid processor bus and L2 bus ratios.The values do not include I/O supply power (OV

and L2OV ) or PLL/DLL supply power (AV and L2AV ). OV and L2OV power is system dependent, but

is typically <10% of V power. Worst case power consumption for AV = 15 mW and L2AV = 15 mW.

2. Maximum power is measured at 105°C and V = 1.8 V while running an entirely cache-resident, contrived

sequence of instructions which keep the execution units, including AltiVec, maximally busy.

3. Typical power is an average value measured at 65°C and V = 1.8 V in a system while running typical

benchmarks.

1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7410. After fabrication, functional parts

are sorted by maximum processor core frequency, see Section 1.4.2.1, “ClockAC Speciﬁcations,” and tested

for conformance to the AC speciﬁcations for that frequency. The processor core frequency is determined by

the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum

processor core frequency; see Section 1.10, “Ordering Information.”

1.4.2.1

Clock AC Speciﬁcations

Table 7 provides the clock AC timing speciﬁcations as deﬁned in Figure 3.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Table 7. Clock AC Timing Speciﬁcations

At recommended operating conditions (see Table 3)

Maximum Processor Core Frequency

400 MHz 450 MHz 500 MHz

Characteristic

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

Processor frequency

VCO frequency

350

700

400

800

133

350

700

450

900

133

350

700

500

1000

133

MHz

core

VCO

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle

SYSCLK

7.5

—

7.5

—

7.5

—

and t

0.5

ns/V

KHKL SYSCLK

measured at OV /2

SYSCLK jitter

Internal PLL-relock time

Notes:

—

±150

100

—

±150

100

—

±150

100

µs

1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK

(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or

minimum operating frequencies.Refer to the PLL_CFG[0:3] signal description in Section 1.8.1, “PLL Conﬁguration,”

for valid PLL_CFG[0:3] settings.

2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a

result, the 0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the

3.3-V bus interface. Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from

0.2 to 1.2 V) in 0.5 ns for the 1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change

(from 0.4 to 2.4 V) in 1 ns.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time

required for PLL lock after a stable V and SYSCLK are reached during the power-on reset sequence. This

speciﬁcation also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also

note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the

power-on reset sequence.

Figure 3 provides the SYSCLK input timing diagram.

SYSCLK

KHKL

SYSCLK

VM = Midpoint Voltage (OV /2)

Figure 3. SYSCLK Input Timing Diagram

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

1.4.2.2

Processor Bus AC Speciﬁcations

Table 8 provides the processor bus AC timing speciﬁcations for the MPC7410 as deﬁned in Figure 4 and

Figure 5. Timing speciﬁcations for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC

Speciﬁcations.”

Table 8. Processor Bus AC Timing Speciﬁcations

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

Input setup

1.0

—

IVKH

Input hold

IXKH

Output valid times:

5, 6

ARTRY, SHD0, SHD1

All other outputs

—

3.0

2.3

3.0

KHTSV

KHARV

KHOV

Output hold times:

ARTRY, SHD0, SHD1

All other outputs

0.5

—

KHTSX

KHARX

KHOX

SYSCLK to output enable

0.5

—

KHOE

SYSCLK to output high impedance (all except

ABB/AMON(0), ARTRY/SHD, DBB/DMON(0), SHD0,

SHD1)

3.5

KHOZ

SYSCLK to ABB/AMON(0), DBB/DMON(0) high

impedance after precharge

—

3, 7, 9

3, 8, 9

KHABPZ

SYSCLK

Maximum delay to ARTRY, SHD0, SHD1 precharge

KHARP

SYSCLK

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Table 8. Processor Bus AC Timing Speciﬁcations (continued)

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

SYSCLK to ARTRY, SHD0, SHD1 high impedance after

precharge

—

3, 8, 9

KHARPZ

SYSCLK

Notes:

1. All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output speciﬁcations are measured from the midpoint of the rising edge of SYSCLK to the

midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and

output timings are measured at the pin; time-of-ﬂight delays must be added for trace lengths, vias, and connectors

in the system.

2. The symbology used for timing speciﬁcations herein follows the pattern of t

for inputs and

(signal)(state)(reference)(state)

for outputs. For example, t

symbolizes the time input signals (I) reach the valid state

(reference)(state)(signal)(state)

IVKH

(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

symbolizes the

KHOV

time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read

as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)— note the position of

the reference and its state for inputs—and output hold time can be read as the time from the rising edge (KH) until

the output went invalid (OX).

3. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by

SYSCLK

the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. Includes mode select signals: BVSEL, EMODE, L2VSEL. See Figure 5 for mode select timing with respect to

HRESET.

5. All other output signals are composed of the following— A[0:31], AP[0:3], TT[0:4], TS, TBST, TSIZ[0:2], GBL, WT,

CI, DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.

6. Output valid time is measured from 2.4 to 0.8 V which may be longer than the time required to discharge from V

to 0.8 V.

7. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are

asserted low then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width

for ABB or DBB is 0.5 × t , that is, less than the minimum t period, to ensure that another master

SYSCLK

asserting ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold

timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed

by design.

8. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period

immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it

low. Any master asserting it low in the ﬁrst clock following AACK will then go to high-Z for one clock before

precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY

is 1.0 t

; that is, it should be high-Z as shown in Figure 6 before the ﬁrst opportunity for another master to

SYSCLK

assert ARTRY. Output valid and output hold timing are tested for the signal asserted. Output valid time is tested for

precharge. The high-Z behavior is guaranteed by design.

9. Guaranteed by design and not tested.

Figure 4 provides the AC test load for the MPC7410.

Z = 50 Ω

Output

OV /2

R = 50 Ω

Figure 4. AC Test Load

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 5 provides the mode select input timing diagram for the MPC7410. The mode select inputs are

sampled twice, once before and once after HRESET negation.

SYSCLK

HRESET

Mode Signals

First sample

Second sample

VM = Midpoint Voltage (OV /2)

Figure 5. Mode Input Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7410.

SYSCLK

IXKH

IVKH

All Inputs

KHOV

KHOX

All Outputs

(Except TS, ABB,

ARTRY, DBB)

khoe

KHOZ

All Outputs

(Except TS, ABB,

ARTRY, DBB)

KHABPZ

KHTSV

KHTSX

TS,

KHTSV

ABB/AMON(0),

DBB/DMON(0)

KHARPZ

KHARV

KHARP

ARTRY,

SHD0,

SHD1

KHARX

VM = Midpoint Voltage (OV /2)

Figure 6. Input/Output Timing Diagram

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

1.4.2.3

L2 Clock AC Speciﬁcations

The L2CLK frequency is programmed by the L2 Conﬁguration Register (L2CR[4:6]) core-to-L2 divisor

ratio. See Table 14 for example core and L2 frequencies at various divisors. Table 9 provides the potential

range of L2CLK output AC timing speciﬁcations as deﬁned in Figure 7.

The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the

L2SYNC_IN input of the MPC7410 to synchronize L2CLK_OUT at the SRAM with the processor’s

internal clock. L2CLK_OUT at the SRAM can be offset forward or backward in time by shortening or

lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Motorola Application Note AN1794/D,

Backside L2 Timing Analysis for the PCB Design Engineer.

The minimum L2CLK frequency in Table 9 is speciﬁed by the maximum delay of the internal DLL. The

variable-tap DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and

L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase-aligned with the next core clock

(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below

this minimum, or the L2CLK_OUT signals provided for SRAM clocking will not be phase-aligned with the

MPC7410 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 9 is the core frequency divided by one. Very few L2

SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to

provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK

frequency for any application of the MPC7410 will be a function of the AC timings of the MPC7410, the

AC timings for the SRAM, bus loading, and printed-circuit board trace length.

Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a

socketed part on a functional tester at the maximum frequencies in Table 9. Therefore, functional operation

and AC timing information are tested at core-to-L2 divisors of two or greater.

L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK

multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC

timings in Table 10 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN

is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of

L2CLK_OUTA and L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since

in a closed loop system L2SYNC_IN is held in phase-alignment with the internal L2CLK, the signals in

Table 10 are referenced to this signal rather than the not-externally-visible internal L2CLK. During

manufacturing test, these times are actually measured relative to SYSCLK.

Table 9. L2CLK Output AC Timing Speciﬁcations

At recommended operating conditions (see Table 3)

400 MHz

450 MHz

500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

L2CLK frequency

133

2.5

400

7.5

133

2.5

400

7.5

133

2.5

400

7.5

MHz

1, 4

L2CLK

L2CLK cycle time

L2CLK

L2CLK duty cycle

CHCL L2CLK

Internal DLL-relock time

DLL capture window

640

—

640

—

640

—

L2CLK

L2CLK_OUT

—

L2CSKW

output-to-output skew

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Table 9. L2CLK Output AC Timing Speciﬁcations (continued)

At recommended operating conditions (see Table 3)

400 MHz

450 MHz

500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

L2CLK_OUT output jitter

—

±150

—

±150

—

±150

Notes:

1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core

frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their

respective maximum or minimum operating frequencies. The maximum L2CLK frequency will be system

dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL-relock time is speciﬁed in terms of L2CLKs. The number in the table must be multiplied by the period of

L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. This adds more delay to each tap of

the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward

or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between

L2SYNC_IN and the internal L2CLK.This number must be comprehended in the L2 timing analysis.The input jitter

on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already

comprehended in the AC timing and does not have to be considered in the L2 timing analysis.

The L2CLK_OUT timing diagram is shown in Figure 7.

L2 Single-Ended Clock Mode

L2CF

L2CR

L2CLK

CHCL

L2CLK_OUTA

L2CLK_OUTB

L2CSKW

L2SYNC_OUT

L2 Differential Clock Mode

L2CLK

CHCL

L2CLK_OUTB

L2CLK_OUTA

L2SYNC_OUT

VM = Midpoint Voltage (L2OV /2)

Figure 7. L2CLK_OUT Output Timing Diagram

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

1.4.2.4

L2 Bus AC Speciﬁcations

Table 10 provides the L2 bus interfaceAC timing speciﬁcations for the MPC7410 as deﬁned in Figure 8 and

Figure 9 for the loading conditions described in Figure 10.

Table 10. L2 Bus Interface AC Timing Speciﬁcations

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

L2SYNC_IN rise and fall time

Setup times: Data and parity

Input hold times: Data and parity

Valid times:

and t

—

1.5

—

1.0

—

L2CR

L2CF

DVL2CH

DXL2CH

L2CHOV

0.0

3, 4

All outputs when L2CR[14–15] = 00

—

2.5

2.9

3.5

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

Output hold times

L2CHOX

L2CHOZ

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

0.4

0.8

1.2

1.6

—

L2SYNC_IN to high impedance:

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

—

2.0

2.5

3.0

3.5

Notes:

1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV

2. All input speciﬁcations are measured from the midpoint of the signal in question to the midpoint voltage of the rising

edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.

3. All output speciﬁcations are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint

of the signal in question.The output timings are measured at the pins. All output timings assume a purely resistive

50-Ω load (see Figure 10).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous

BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15]

= 10 is recommended.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 8 shows the L2 bus input timing diagrams for the MPC7410.

L2CF

L2CR

L2SYNC_IN

DVL2CH

DXL2CH

L2 Data and

Data Parity

Inputs

VM = Midpoint Voltage (L2OV /2)

Figure 8. L2 Bus Input Timing Diagrams

Figure 9 shows the L2 bus output timing diagrams for the MPC7410.

L2SYNC_IN

All Outputs

L2DATA Bus

L2CHOV

L2CHOX

L2CHOZ

VM = Midpoint Voltage (L2OV /2)

Figure 9. L2 Bus Output Timing Diagrams

Figure 10 provides the AC test load for L2 interface of the MPC7410.

Output

L2OV /2

Z = 50 Ω

R = 50 Ω

Figure 10. AC Test Load for the L2 Interface

1.4.2.5

IEEE 1149.1 AC Timing Speciﬁcations

Table 11 provides the IEEE 1149.1 (JTAG) AC timing speciﬁcations as deﬁned in Figure 12 through

Figure 15.

Table 11. JTAG AC Timing Speciﬁcations (Independent of SYSCLK)

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

TCK cycle time

33.3

—

MHz

TCLK

TCK clock pulse width measured at OV /2

—

JHJL

TCK rise and fall times

and t

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

Table 11. JTAG AC Timing Speciﬁcations (Independent of SYSCLK) (continued)

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TRST assert time

Input setup times:

—

TRST

Boundary-scan data

TMS, TDI

—

DVJH

IVJH

Input hold times:

Valid times:

Boundary-scan data

TMS, TDI

—

DXJH

IXJH

Boundary-scan data

TDO

JLDV

JLOV

TCK to output high impedance:

Boundary-scan data

TDO

4, 5

JLDZ

JLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 11). Time-of-ﬂight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC7410.

Output

OV /2

Z = 50 Ω

R = 50 Ω

Figure 11. Alternate AC Test Load for the JTAG Interface

Figure 12 provides the JTAG clock input timing diagram.

TCLK

JHJL

TCLK

VM = Midpoint Voltage (OV /2)

Figure 12. JTAG Clock Input Timing Diagram

Figure 13 provides the TRST timing diagram.

TRST

VM = Midpoint Voltage (OV /2)

Figure 13. TRST Timing Diagram

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Electrical and Thermal Characteristics

Figure 14 provides the boundary-scan timing diagram.

TCK

DVJH

DXJH

Boundary

Data Inputs

Input

Data Valid

JLDV

JLDX

Boundary

Data Outputs

Output Data Valid

JLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

Figure 14. Boundary-Scan Timing Diagram

Figure 15 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

IVJH

IXJH

Input

Data Valid

JLOV

JLOX

Output Data Valid

JLOZ

TDO

Output Data Valid

VM = Midpoint Voltage (OV /2)

Figure 15. Test Access Port Timing Diagram

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Pin Assignments

1.5 Pin Assignments

Figure 16 (in part A) shows the pinout for both the MPC7410, 360 CBGA and 360 HCTE packages as

viewed from the top surface. Part B shows the side proﬁle of the package to indicate the direction of the top

surface view.

Part A

10 11 12 13 14 15 16 17 18 19

Not to Scale

Part B

View

Substrate Assembly

Encapsulant

Die

Figure 16. Pinout of the MPC7410, 360 CBGA and 360 HCTE Packages

as Viewed from the Top Surface

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pinout Listings

1.6 Pinout Listings

Table 12 provides the pinout listing for the MPC7410, 360 CBGA and 360 HCTE packages.

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

A[0:31]

A13, D2, H11, C1, B13, F2, C13, E5, D13, G7,

F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1,

G2, F3, J7, M3, H3, J2, J6, K3, K2, L2

High

I/O

BVSEL

AACK

ABB

Low

High

Low

—

Input

Output

I/O

BVSEL

12, 16

AP[0:3]

ARTRY

C4, C5, C6, C7

I/O

Input

Output

Input

Low

High

BVSEL

N/A

BVSEL

1, 3, 8,

9, 14

CHK

K11

Low

High

Low

High

Input

I/O

BVSEL

2, 8, 9

CKSTP_IN

CKSTP_OUT

CLK_OUT

DBB

Input

Output

Input

I/O

12, 16

DBG

DH[0:31]

W12, W11, V11, T9, W10, U9, U10, M11, M9, P8,

W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7,

R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5

DL[0:31]

M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11,

V13, U12, P12, T13, W13, U13, V10, W8, T11,

U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2

High

I/O

BVSEL

DP[0:7]

DRDY

L1, P2, M2, V2, M1, N2, T3, R1

High

Low

I/O

BVSEL

Output

Input

6, 8, 13

DBWO

DTI[0]

DTI[1:2]

EMODE

H6, G1

High

Low

Input

BVSEL

5, 10, 13

7, 10

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

Signal Name

GBL

Pin Number

Active

I/O

I/F Select

Notes

Low

—

I/O

—

BVSEL

N/A

GND

D10, D14, D16, D4, D6, E12, E8, F4, F6, F10,

F14, F16, G9, G11, H5, H8, H10, H12, H15, J9,

J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5,

M8, M10, M12, M15, N9, N11, P4, P6, P10, P14,

P16, R8, R12, T4, T6, T10, T14, T16

HIT

Low

High

Output

Input

BVSEL

L2VSEL

6, 8

HRESET

INT

C11

Input

L1_TSTCLK

L2ADDR[0:16]

Input

L17, L18, L19, M19, K18, K17, K15, J19, J18,

J17, J16, H18, H17, J14, J13, H19, G18

Output

L2ADDR[17:18] K19,W19

High

—

Output

Input

L2VSEL

L2AV

L13

P17

N15

L16

L2CE

Low

High

Output

I/O

L2VSEL

L2CLK_OUTA

L2CLK_OUTB

L2DATA[0:63]

U14, R13, W14, W15, V15, U15, W16, V16, W17,

V17, U17, W18, V18, U18, V19, U19, T18, T17,

R19, R18, R17, R15, P19, P18, P13, N14, N13,

N19, N17, M17, M13, M18, H13, G19, G16, G15,

G14, G13, F19, F18, F13, E19, E18, E17, E15,

D19, D18, D17, C18, C17, B19, B18, B17, A18,

A17, A16, B16, C16, A14, A15, C15, B14, C14,

E13

L2DP[0:7]

V14, U16, T19, N18, H14, F17, C19, B15

High

—

I/O

—

L2VSEL

N/A

L2OV

D15, E14, E16, H16, J15, L15, M16, K13, P15,

R14, R16, T15, F15

L2SYNC_IN

L14

High

Input

Output

Input

L2VSEL

BVSEL

N/A

L2SYNC_OUT M14

L2_TSTCLK

L2VSEL

A19

Input

1, 3, 8,

9, 14

L2WE

N16

G17

Low

High

Low

Output

Input

L2VSEL

BVSEL

L2ZZ

LSSD_MODE

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

MCP

B11

Low

—

Input

—

BVSEL

N/A

D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4,

P5, R4, R6, R9, R11, T5, T8, T12

PLL_CFG[0:3]

QACK

QREQ

RSRV

SHD0

SHD1

SMI

A4, A5, A6, A7

High

Low

—

Input

Output

I/O

BVSEL

I/O

5, 8

A12

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

E10

Low

High

Low

High

Low

High

Low

High

Low

TBEN

TBST

TCK

A11

B10

TDI

TDO

TEA

TMS

TRST

A10

TSIZ[0:2]

TT[0:4]

A9, B9, C9

Output

I/O

C10, D11, B12, C12, F11

I/O

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

G8, G10, G12, J8, J10, J12, L8, L10, L12, N8,

N10, N12

—

N/A

Notes:

1. OV

supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE,

L2WE, and L2ZZ); L2OV supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7],

and L2SYNC_OUT) and the L2 control signals; and V supplies power to the processor core and the PLL and

DLL (after ﬁltering to become AV and L2AV , respectively). These columns serve as a reference for the

nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin conﬁgurations of Table 2 and

the voltage supplied. For actual recommended value of V or supply voltages, see Table 3.

2. These are test signals for factory use only and must be pulled up to OV for normal machine operation.

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either

OV , GND, HRESET, or ¬HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The

default selection, if L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports

3.3-, 2.5-, and 1.8-V options. The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to

Table 2 for supported BVSEL and L2VSEL settings.

4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or

during sleep mode and must adhere to the internal PLL-relock time requirement.

5. Ignored input in 60x bus mode.

6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.

7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for

MPX bus mode.

8. Uses one of nine existing no connects in the MPC750 360 BGA package.

9. Internal pull up on die. Pulled-up signals are V based.

10. Reuses MPC750 DRTRY, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).

11. The VOLTDET pin position on the MPC750 360 CBGA package is now an L2OV pin on the MPC7410

360 CBGA package.

12. Output only for MPC7410, was I/O for MPC750.

13. MPX bus mode only.

14. If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a

pull-down resistance less than 250 Ω should be used.

15. MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles

to guarantee that it is latched by the processor.

16. In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a

requirement of the MPX bus protocol and may not be available on future products.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Package Description

1.7 Package Description

The following sections provide the package parameters and mechanical dimensions for both the MPC7410,

360 CBGA and 360 HCTE packages.

1.7.1 Package Parameters for the MPC7410

The package parameters are as provided in the following list. The package types are the 25 × 25 mm,

360-lead ceramic ball grid array package (CBGA) or the 25 × 25 mm, 360-lead high coefﬁcient of thermal

expansion CBGA package (HCTE).

Package outline

Interconnects

25 × 25 mm

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

2.65 mm

Pitch

Minimum module height

Maximum module height

Ball diameter

3.20 mm

0.89 mm (35 mil)

1.7.2 Mechanical Dimensions for the MPC7410

Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410,

360 CBGA and 360 HCTE packages.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Package Description

0.2

Millimeters

DIM

MIN

MAX

A1 CORNER

2.72

0.80

1.10

—

3.20

1.00

1.30

0.60

0.90

0.93

C6-2

C6-1

12X

C1-1

C1-2

C5-1

C5-2

0.15 A

0.25 A

0.82

C4-1

0.35 A

C4-2

25.00 BSC

L2 L1

10.0 typ.

6.32

C2-2

C2-1

1.27 BSC

25.00 BSC

12.6 typ.

8.26

12X

0.2

C3-1

C3-2

0.89 BSC

3.2 BSC

0.68 BSC

6.56

9 10 111213141516 171819

8.13

8.61

7.04

Package

Caps

Value

Voltage

µF

Reference

C1-1

C1-2

C2-1

C2-2

C3-1

C3-2

C4-1

C4-2

C5-1

C5-2

C6-1

C6-2

L2OV_DD

GND

0.01

L2OV_DD

GND

0.01

360X

V_DD

0.3 C A B

GND

0.15

NOTES:

OV_DD

GND

1. DIMENSIONING ANDTOLERANCING

PER ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. TOP SIDE A1 CORNER INDEX IS A

METALIZED FEATURE WITH

OV_DD

GND

V_DD

VARIOUS SHAPES.BOTTOM SIDE A1

CORNER IS DESIGNATED WITH A

BALL MISSING FROM THE ARRAY.

GND

Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,

360 CBGA and 360 HCTE Packages

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC7410.

1.8.1 PLL Conﬁguration

The MPC7410 PLL is conﬁgured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the

PLL conﬁguration signals set the internal CPU and VCO frequency of operation. The PLL conﬁguration

for the MPC7410 is shown in Table 13 for example frequencies. In this example, shaded cells represent

settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with

the minimum and maximum core frequencies listed in Table 8.

Table 13. MPC7410 Microprocessor PLL Conﬁguration

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_CFG

Bus-to-

Core

Multiplier Multiplier

Core-to

VCO

[0:3]

Bus

33.3 MHz 50 MHz 66.6 MHz 75 MHz 83.3 MHz 100 MHz 133 MHz

0100

0110

1000

2.5x

400

(800)

1110

1010

0111

1011

1001

1101

0101

0010

0001

1100

0000

3.5x

350

(700)

465

(930)

400

(800)

4.5x

375

(750)

450

(900)

375

(750)

416

(833)

500

(1000)

5.5x

366

(733)

412

(825)

458

(916)

400

(800)

450

(900)

500

(1000)

6.5x

433

(866)

488

(967)

350

(700)

466

(933)

7.5x

375

(750)

500

(1000)

400

(800)

450

(900)

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

Table 13. MPC7410 Microprocessor PLL Conﬁguration (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_CFG

[0:3]

Bus-to-

Core

Multiplier Multiplier

Core-to

VCO

Bus

33.3 MHz 50 MHz 66.6 MHz 75 MHz 83.3 MHz 100 MHz 133 MHz

0011

1111

PLL off/bypass

PLL off

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

PLL off, no core clocking occurs

Notes:

1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL conﬁgurations may select bus, core,

or VCO frequencies which are not useful, not supported, or not tested for by the MPC7410; see Section 1.4.2.1,

“Clock AC Speciﬁcations,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the

bus mode is set for 1:1 mode operation. This mode is intended for factory use and third-party emulator tool

development only.

Note: The AC timing speciﬁcations given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7410 regardless of the SYSCLK input.

5. PLL-off mode should not be used during chip power-up sequencing.

The MPC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock

frequency of the MPC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop

(DLL) circuit and should be routed from the MPC7410 to the external RAMs. A separate clock output,

L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin

L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking

of the internal latches in the L2 bus interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register.

Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the

frequency of the MPC7410 core, and the phase adjustment range that the L2 DLL supports. Table 14 shows

various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum

L2 frequency target is 133 MHz. Sample core-to-L2 frequencies for the MPC7410 is shown in Table 14. In

this example, shaded cells represent settings that, for a given core frequency, result in L2 frequencies that

do not comply with the minimum and maximum L2 frequencies listed in Table 10.

Table 14. Sample Core-to-L2 Frequencies

Core Frequency

÷1

÷1.5

÷2

÷2.5

÷3

÷3.5

÷4

(MHz)

350

366

400

433

450

350

366

400

—

233

244

266

288

300

175

183

200

216

225

140

147

160

173

180

—

133

144

150

—

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Table 14. Sample Core-to-L2 Frequencies (continued)

Core Frequency

(MHz)

÷1

÷1.5

÷2

÷2.5

÷3

÷3.5

÷4

466

500

—

311

333

233

250

186

200

155

166

133

143

—

Note: The core and L2 frequencies are for reference only. Some examples may

represent core or L2 frequencies which are not useful, not supported, or not tested

for by the MPC7410; see Section 1.4.2.3, “L2 Clock AC Speciﬁcations,” for valid

L2CLK frequencies.The L2CR[L2SL] bit should be set for L2CLK frequencies less

than 150 MHz.

1.8.2 PLL and DLL Power Supply Filtering

The AV and L2AV power signals are provided on the MPC7410 to supply power to the PLL and DLL,

respectively.

On systems that use the MPC7410 CBGA device, the L2AV ﬁlter should implement the circuit shown in

Figure 18. The AV

Figure 19.

ﬁlter on the MPC7410 CBGA device should implement the circuit shown in

On systems that use the MPC7410 HCTE device, the AV

implement the circuit shown in Figure 18.

and L2AV

input signals should both

The circuit shown below should be placed as close as possible to the AV pin to minimize noise coupled

from nearby circuits. A separate circuit should be placed as close as possible to the L2AV pin. It is often

possible to route directly from the capacitors to the AV pin, which is on the periphery of the 360 CBGA

footprint, without the inductance of vias. The L2AV

proportionately less critical.

pin may be more difﬁcult to route, but is

It is the recommendation of Motorola, that systems that implement the AV

ﬁlter shown in Figure 19

design in the pads for the removed capacitors (shown in Figure 18), to provide for the possible

reintroduction of the ﬁlter in Figure 18. This would be necessary in case there is a planned transition to the

HCTE package of the MPC7410.

10 Ω

AV (or L2AV

)

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 18. PLL Power Supply Filter Circuit #1

51 Ω

Capacitor

Pad Sites

GND

Figure 19. PLL Power Supply Filter Circuit #2

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

1.8.3 Decoupling Recommendations

Due to the MPC7410 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7410 can generate transient power surges and high frequency noise in its power

supply, especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the MPC7410 system, and the MPC7410 itself requires a clean, tightly regulated source of

power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each

, OV , and L2OV pin of the MPC7410. It is also recommended that these decoupling capacitors

DD DD

receive their power from separate V , (L2)OV , and GND power planes in the PCB, utilizing short

traces to minimize inductance.

These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations, where

connections are made along the length of the part.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the V , L2OV , and OV planes, to enable quick recharging of the smaller chip capacitors.

These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick

response time necessary. They should also be connected to the power and ground planes through two vias

to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).

1.8.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level through a resistor. Unused active low inputs should be tied to OV . Unused active high inputs should

be connected to GND. All NC (no connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , L2OV , and GND pins of the

MPC7410. Note that power must be supplied to L2OV even if the L2 interface of the MPC7410 will not

be used; the remainder of the L2 interface may be left unterminated.

1.8.5 Output Buffer DC Impedance

The MPC7410 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure

Z , an external resistor is connected from the chip pad to OV or GND. Then, the value of each resistor is

varied until the pad voltage is OV /2 (see Figure 20).

The output impedance is the average of two components, the resistances of the pull-up and pull-down

devices. When data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the

pad equals (L2)OV /2. R then becomes the resistance of the pull-down devices. When data is held high,

SW1 is closed (SW2 is open), and R is trimmed until the voltage at the pad equals (L2)OV /2. R then

becomes the resistance of the pull-up devices. R and R are designed to be close to each other in value.

Then, Z = (R + R )/2.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Figure 20 describes the driver impedance measurement circuit described above.

SW2

SW1

Pad

Data

OGND

Figure 20. Driver Impedance Measurement Circuit

Alternately, the following is another method to determine the output impedance of the MPC7410. A voltage

source, V

, is connected to the output of the MPC7410, as in Figure 21. Data is held low, the voltage

force

source is set to a value that is equal to (L2)OV /2, and the current sourced by V

is measured. The

force

voltage drop across the pull-down device, which is equal to (L2)OV /2, is divided by the measured current

to determine the output impedance of the pull-down device, R . Similarly, the impedance of the pull-up

device is determined by dividing the voltage drop of the pull-up, (L2)OV /2, by the current sank by the

pull-up when the data is high and V

is equal to (L2)OV /2. This method can be employed with either

force

empirical data from a test setup or with data from simulation models, such as IBIS.

R and R are designed to be close to each other in value. Then, Z = (R + R )/2. Figure 21 describes the

alternate driver impedance measurement circuit.

(L2)OV

BGA

Data

force

OGND

Figure 21. Alternate Driver Impedance Measurement Circuit

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°,

65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus

voltage.

Table 15. Impedance Characteristics

= 1.8 V, OV = 2.5 V, T = 0° – 105°C

Impedance

Processor Bus

L2 Bus

Symbol

Unit

41.5–54.3

37.3–55.3

42.7–54.1

39.3–50.0

Ω

1.8.6 Pull-Up Resistor Requirements

The MPC7410 requires pull-up resistors (1 kΩ–5 kΩ) on several control pins of the bus interface to maintain

the control signals in the negated state after they have been actively negated and released by the MPC7410

or other bus masters. These pins are: TS, ARTRY, SHDO, SHD1.

Four test pins also require pull-up resistors (100 Ω−1 kΩ). These pins are CHK, L1_TSTCLK,

L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to

OV for normal machine operation.

If pull-down resistors are used to conﬁgure BVSEL or L2VSEL, the resistors should be less than 250 Ω (see

Table 12). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and

pull-down resistors (1 kΩ or less) are recommended to conﬁgure these signals in order to protect against

erroneous switching due to ground bounce, power supply noise or noise coupling.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ–5 kΩ) if it is

used by the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor

(1 kΩ–5 kΩ) to prevent erroneous assertions of this signal.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and

may, therefore, ﬂoat in the high-impedance state for relatively long periods of time. Since the MPC7410

must continually monitor these signals for snooping, this ﬂoat condition may cause excessive power draw

by the input receivers on the MPC7410 or by other receivers in the system. These signals can be pulled up

through weak (10-kΩ) pull-up resistors by the system, address bus driven mode can be enabled (see the

MPC7410 RISC Microporcessor Family Users’ Manual for more information on this mode), or these

signals may be otherwise driven by the system during inactive periods of the bus to avoid this additional

power draw. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI, WT, and

GBL.

In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction

while not driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on

GBL. Note that the MPC7410 will only snoop transactions when GBL is asserted.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore,

do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require

pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The

data bus signals are: DH[0:31], DL[0:31], and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is disabled through

HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and

should be left unconnected by the system. If parity checking is disabled through HID0, and parity generation

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

is not required by the MPC7410 (note that the MPC7410 always generates parity), then all parity pins may

be left unconnected by the system.

The L2 interface does not normally require pull-up resistors.

1.8.7 JTAG Conﬁguration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 speciﬁcation, but is provided on all processors that implement the PowerPC architecture.

While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more

reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.

Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,

simply tying TRST to HRESET is not practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated

hardware and debugging software) to access and control the internal operations of the processor. The COP

interface connects primarily through the JTAG port of the processor, with some additional status monitoring

signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control

the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,

power supply failures, or push-button switches, then the COP reset signals must be merged into these signals

with logic.

The arrangement shown in Figure 22 allows the COP port to independently assert HRESET or TRST, while

ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,

TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset

signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While

Motorola recommends that the COP header be designed into the system as shown in Figure 22, if this is not

possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need

to be wired onto the system in debug situations.

The COP header shown in Figure 22 adds many beneﬁts—breakpoints, watchpoints, register and memory

examination/modiﬁcation, and other standard debugger features are possible through this interface—and

can be as inexpensive as an unpopulated footprint for a header to be added when needed.

The COP interface has a standard header for connection to the target system, based on the 0.025"

square-post 0.100" centered header assembly (often called a Berg header). The connector typically has

pin 14 removed as a connector key.

There is no standardized way to number the COP header shown in Figure 22; consequently, many different

pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then

left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter

clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in

Figure 22 is common to all known emulators.

The QACK signal shown in Figure 22 is usually connected to the PCI bridge chip in a system and is an input

to the MPC7410 informing it that it can go into the quiescent state. Under normal operation this occurs

during a low-power mode selection. In order for COP to work, the MPC7410 must see this signal asserted

(pulled down). While shown on the COP header, not all emulator products drive this signal. If the product

does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products

implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can

be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the

pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

populate both in a system. To preserve correct power-down operation, QACK should be merged via logic

so that it also can be driven by the PCI bridge.

SRESET

From Target

SRESET

HRESET

Board Sources HRESET

(if any)

QACK

10 kΩ

HRESET

SRESET

0 Ω

TRST

VDD_SENSE

10 kΩ

2 kΩ

CHKSTP_OUT

10 kΩ

Key

11 12

KEY

10 kΩ

CHKSTP_IN

TMS

No Pin

CHKSTP_IN

TMS

TDO

TDI

COP Connector

Physical Pin Out

TDO

TDI

TCK

QACK

2 kΩ

10 kΩ

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7410. Connect

pin 5 of the COP header to OV with a 10-kΩ pull-up resistor.

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-Ω isolation reisistor.

6. The COP port and target board should be able to independently assert HRESET and TRST to the

processor in order to fully control the processor as shown above.

Figure 22. COP Connector Diagram

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.8.8 Thermal Management Information

This section provides thermal management information for the MPC7410 for air-cooled applications.

Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and

thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the

package by several methods—adhesive, spring clip to holes in the printed-circuit board or package, and

mounting clip and screw assembly; see Figure 23. This spring force should not exceed 5.5 pounds of force.

Note that care should be taken to avoid focused forces being applied to die corners and/or edges when

mounting heat sinks.

CBGA Package

Heat Sink

Clip

Adhesive or

Thermal Interface Material

Printed-Circuit Board

Option

Figure 23. Package Exploded Cross-Sectional View with Several Heat Sink Options

The board designer can choose between several types of heat sinks to place on the MPC7410. There are

several commercially-available heat sinks for the MPC7410 provided by the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

603-224-9988

408-749-7601

800-347-4572

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

Tyco Electronics

Chip Coolers

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

800-522-6752

603-635-5201

Wakeﬁeld Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakeﬁeld.com

Ultimately, the ﬁnal selection of an appropriate heat sink depends on many factors, such as thermal

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

1.8.8.1 Internal Package Conduction Resistance

For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance

paths are as follows:

•

The die junction-to-case (or top-of-die for exposed silicon) thermal resistance

•

The die junction-to-ball thermal resistance

Figure 24 depicts the primary heat transfer path for a package with an attached heat sink mounted to a

printed-circuit board.

Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink

attach material (or thermal interface material), and ﬁnally to the heat sink where it is removed by forced-air

convection.

Since the silicon thermal resistance is quite small, for a ﬁrst-order analysis, the temperature drop in the

silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective

thermal resistances are the dominant terms.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

Note the internal versus external package resistance.

Figure 24. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

1.8.8.2 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the

thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 25 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,

graphite/oil, ﬂoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

The use of thermal grease signiﬁcantly reduces the interface thermal resistance. That is, the bare joint results

in a thermal resistance approximately seven times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see

Figure 23). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers

the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal

interface material depends on many factors—thermal performance requirements, manufacturability, service

temperature, dielectric properties, cost, etc.

Figure 25 describes the thermal performance of selected thermal interface materials.

Silicone Sheet (0.006”)

Bare Joint

Floroether Oil Sheet (0.007”)

Graphite/Oil Sheet (0.005”)

Synthetic Grease

1.5

0.5

Contact Pressure (psi)

Figure 25. Thermal Performance of Select Thermal Interface Material

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

System Design Information

The board designer can choose between several types of thermal interface. Heat sink adhesive materials

should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment

shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive

materials provided by the following vendors:

Chomerics, Inc.

781-935-4850

77 Dragon Court

Woburn, MA 01888-4014

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

800-248-2481

Midland, MI 48686-0997

Internet: www.dow.com

Shin-Etsu MicroSi, Inc

10028 S. 51st St.

Phoenix, AZ 85044

888-642-7674

888-246-9050

Internet: www.microsi.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

1.8.8.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (θ + θ + θ ) × P

int

where:

T is the die-junction temperature

T is the inlet cabinet ambient temperature

T is the air temperature rise within the computer cabinet

θ is the junction-to-case thermal resistance

is the adhesive or interface material thermal resistance

int

θ is the heat sink base-to-ambient thermal resistance

P is the power dissipated by the device

During operation the die-junction temperatures (T ) should be maintained less than the value speciﬁed in

Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air

temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air

temperature (T ) may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the

range of 5° to 10°C. The thermal resistance of the thermal interface material (θ ) is typically about 1°C/W.

int

Assuming a T of 30°C, a T of 5°C, a CBGA package θ = 0.03, and a power consumption (P ) of 5.0 W,

the following expression for T is obtained:

Die-junction temperature: T = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θ ) × 5.0 W

For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θ ) versus airﬂow

velocity is shown in Figure 26.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

System Design Information

Assuming an air velocity of 0.5 m/s, we have an effective R of 7°C/W, thus

T = 30°C + 5°C + (0.03°C/W + 1.0°C/W + 7°C/W) × 5.0 W,

resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating

temperature of the component.

Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, The Bergquist Company, IERC, Chip

Coolers, and Wakeﬁeld Engineering offer different heat sink-to-ambient thermal resistances, and may or

may not need airﬂow.

Thermalloy #2328B Pin-Fin Heat Sink

(25 × 28 × 15 mm)

0.5

1.5

2.5

3.5

Approach Air Velocity (m/s)

Figure 26. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airﬂow Velocity

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common

ﬁgure-of-merit used for comparing the thermal performance of various microelectronic packaging

technologies, one should exercise caution when only using this metric in determining thermal management

because no single parameter can adequately describe three-dimensional heat ﬂow. The ﬁnal die-junction

operating temperature, is not only a function of the component-level thermal resistance, but the system-level

design and its operating conditions. In addition to the component's power consumption, a number of factors

affect the ﬁnal operating die-junction temperature—airﬂow, board population (local heat ﬂux of adjacent

components), heat sink efﬁciency, heat sink attach, heat sink placement, next-level interconnect technology,

system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today's

microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,

and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models

for the board, as well as, system-level designs.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Document Revision History

1.9 Document Revision History

Table 16 provides a revision history for this hardware speciﬁcation.

Table 16. Document Revision History

Rev. No.

Substantive Change(s)

Initial release.

Minor updates.

0.1

0.2

Corrected Section 1.3—technology from 0.13 µm to 0.18 µm.

Updated Table 7—adds power consumption numbers; adds note on estimated decrease w/o AltiVec.

Updated Table 8—adds minimun values for processor frequency and VCO frequency.

Updated Table 9—input setup, output valid times, output hold times, SYSCLK to output high impedance.

Updated Table 11—L2SYNC_IN to high impedance.

Updated Figure 17—mechanical dimensions, adds capacitor pad dimensions.

Added 3.3 V support on the processor bus (BVSEL).

0.3

Table 7—update typical and maximum power numbers for full-on mode in. Removed note 4. Reworded

notes 2 and 3.

Table 9, Note 2—removed reference to application note.

Figure 17—corrected side view datum A to be datum C.

Section 1.8.7—added CI and WT to transfer attribute signals requiring pull-ups.

Section 1.8.7—added 1-kΩ pull-up recommendation to GBL when GBL is not connected.

Table 2— added pull-down resistance necessary for internally pulled-up voltage select pins. Added

3.3-V support for BVSEL.

Table 13—added note 14 for BVSEL, L2VSEL, and TRST pins to address pull-down resistance

necessary for these internally pulled-up pins to recognize a low signal.

Table 6—lowered 2.5V CV from 2.2 to 2.0V to be compatible withV of the MPC107.Added support

for 3.3-V processor bus.

Table 15—modiﬁed note 1, use L2CR[L2SL] for L2CLK frequency less than 150 MHz.

Table 8—revised note 2 discussing for 3.3-V bus voltage support.

Table 14—added note 5, do not use PL off during power-up sequence.

Table 1—update output hold times (t

L2CHOX

1.0

Section 1.3 and Table 3—revised OV

from 3.3 V ± 100 mV to 3.3 V ± 165 mV.

Table 13—removed unsupported PLL conﬁgurations.

Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus support.

Table 13—revised note 3 to include emulator tool development.

Table 14—removed unsupported Core-to-L2 example frequencies.

Section 1.8.8—updated heat sink vendors list.

Section 1.8.8.2—updated interface vendors list.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Document Revision History

Table 16. Document Revision History (continued)

Rev. No.

Substantive Change(s)

Table 1—updated voltage sequencing requirements notes 3 and 4.

Table 4—Updated/added thermal characteristics.

Table 5—removed table and TAU related information, TAU is no longer supported.

Table 6—updated I and I

leakage current specs.

TSI

Section 1.8.3—removed section.

Section 1.10—reformatted section.

Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and

TS to control signals needing pull-ups. Added pull-up resistor value recomendation for L1_TSTCLK,

L2_TSTCLK, and LSSD_MODE factory test signals.

Section 1.8.7—revised text regarding connection of TRST. Combined Figure 22, Figure 23, and Table

17, into Figure 21.

Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of

350 MHz.

Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OV

Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V

Table 5—added note 8 regarding DC voltage limits for JTAG signals.

Internal release.

1.1

Table 12—added note 16 for ABB/AMON and DBB/DMON signal clariﬁcation.

Table 12—changed CHK note 4 reference to note 2, signal is for factory test only. Changed previous

note 4 (CHK related) to now provide additional PLL info.

Table 1—modiﬁed maximum value for OV from –0.3 to 3.465 to now be –0.3 to 3.6 and L2OV from

–0.3 to 2.6 to now be –0.3 to 2.8. Modiﬁed note 6, OV for revisions prior to Rev. 1.4 have maximum

value for OV of –0.3 to 2.8.

Table 8—removed note 12. L2_TSTCLK is for factory use only (see Table 12, note 2).

Section 1.10.2—revised section to include nomenclature tables for part markings not covered by this

spec.

Figure 2—added that under/overshoot for L2OV references t

while OV references t

L2CLK

SYSCLK

Table 4—added HCTE package (HX package descriptor) thermal characteristics.

Section 1.5—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same pin assignments.

Section 1.6—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same pinout listings.

Section 1.7—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same package parameters and dimensions.

Table 17—added HCTE package (HX package descriptor) to part numbering nomenclature.

Table 21—added MPC7410THXnnnLE extended temperature HCTE package part numbers and part

number speciﬁcation document reference.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Document Revision History

Table 16. Document Revision History (continued)

Rev. No.

Substantive Change(s)

Public release, includes Rev 1.1 changes.

Section 1.7.2—added package capacitor values.

Section 1.8.6—added recommendation that strong pull-up/down resistors be used on the

PLL_CFG[0:3] signals.

Table 8—removed mode input setup and hold times. These inputs adhere to the general input setup

and hold speciﬁcations.

Figure 5—revised mode input diagram to show sample points around HRESET negation.

Section 1.3—added HCTE package description.

Figure 22—added note 6 to emphasize that COP emulator and target board need to be able to drive

HRESET and TRST independently to the CPU.

Section 1.8.2—revised section for HCTE package. Added text and ﬁgure for AV ﬁlter for the CBGA

package.

Section 1.8.6—removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST

from snooped transfer attribute list. TBST is an output and is not snooped.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Ordering Information

1.10 Ordering Information

Ordering information for the parts fully covered by this speciﬁcation document is provided in

Section 1.10.1, “Part Numbers Addressed by This Speciﬁcation.” Section 1.10.2, “Part Numbers Not Fully

Addressed by This Document,” lists the part numbers which do not fully conform to the speciﬁcations of

this document. These special part numbers require an additional document called a part number

speciﬁcation.

1.10.1 Part Numbers Addressed by This Speciﬁcation

Table 17 provides the Motorola part numbering nomenclature for the MPC7410 Note that the individual part

numbers correspond to a maximum processor core frequency. For available frequencies, contact your local

Motorola sales ofﬁce. In addition to the processor frequency, the part numbering scheme also includes an

application modiﬁer which may specify special application conditions. Each part number also contains a

revision code which refers to the die mask revision number.

Table 17. Part Numbering Nomenclature

MPC 7410

nnn

Product

Code

Part

Identiﬁer

Processor

Frequency

Application

Modiﬁer

Package

Revision Level

MPC

7410

RX = CBGA

HX = HCTE

400

450

500

L: 1.8 V ± 100 mV C: 1.2; PVR = 800C 1102

0° to 105°C

D: 1.3; PVR = 800C 1103

E: 1.4; PVR = 800C 1104

Notes:

1. See Section 1.7, “Package Description,” for more information on available package types and Table 4 for more

information on thermal characteristics.

2. Processor core frequencies supported by parts addressed by this speciﬁcation only. Not all parts described in this

speciﬁcation support all core frequencies. Additionally, parts addressed by part number speciﬁcations may support

other maximum core frequencies.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Ordering Information

1.10.2 Part Numbers Not Fully Addressed by This Document

Parts with application modiﬁers or revision levels not fully addressed in this speciﬁcation document are

described in separate part number speciﬁcations which supplement and supersede this document, as

described in the following tables.

Table 18. Part Numbers Address by MPC7410RXnnnPx Series Part Numbers Speciﬁcations

MPC 7410

nnn

Product

Code

Part

Identiﬁer

Processor

Frequency

Application

Modiﬁer

Package

RX = CBGA

Revision Level

MPC

7410

450

500

550

P: 2.0 V ± 50 mV

C: 1.2; PVR = 800C 1102

D: 1.3; PVR = 800C 1103

0° to 65°C

E: 1.4; PVR = 800C 1104

Notes: Document order numbers:

1. MPC7410PCPNS.

2. MPC7410PDPNS.

3. MPC7410PEPNS.

Table 19. Part Numbers Address by MPC7410RXnnnNE Part Numbers Speciﬁcation

MPC 7410

nnn

Revision Level

Product

Code

Part

Identiﬁer

Processor

Frequency

Application

Modiﬁer

Package

MPC

7410

RX = CBGA

400

450

500

N: 1.5 V ± 50 mV

E: 1.4; PVR = 800C 1104

Note: Document order number: MPC7410NEPNS.

Table 20. Part Numbers Address by MPC7410TRXnnnNE Part Numbers Speciﬁcation

MPC 7410

nnn

Product

Code

Part

Identiﬁer

Process

Descriptor

Processor

Frequency

Application

Modiﬁer

Package

Revision Level

MPC

7410

T: –40° to 105°C RX = CBGA

400

450

N: 1.5 V ±50 mV

E: 1.4; PVR = 800C 1104

Note: Document order number: MPC7410TRXNEPNS.

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Ordering Information

Table 21. Part Numbers Address by MPC7410TRXnnnLE and MPC7410THXnnnLE

Part Numbers Speciﬁcations

MPC 7410

nnn

Product

Code

Part

Identiﬁer

Process

Descriptor

Processor

Frequency

Application

Modiﬁer

Package

Revision Level

MPC

7410

T: –40 to 105°C RX = CBGA

400

450

500

L: 1.8 V ± 100 mV E: 1.4; PVR = 800C 1104

HX = HCTE

Notes: Document order number:

1. MPC7410TRXLEPNS.

2. MPC7410THXLEPNS.

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

Ordering Information

1.10.3 Part Marking

Parts are marked as the example shown in Figure 27.

MPC7410

RXnnnLE

MMMMMM

ATWLYYWWA

7410

CBGA

Notes:

MMMMMM is the 6-digit mask number.

ATWLYYWWA is the traceability code.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

Figure 27. Part Marking for BGA Device

MPC7410 RISC Microprocessor Hardware Speciﬁcations

MOTOROLA

Ordering Information

THIS PAGE INTENTIONALLY LEFT BLANK

MOTOROLA

MPC7410 RISC Microprocessor Hardware Speciﬁcations

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USA/EUROPE/LOCATIONS NOT LISTED:

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P.O. Box 5405, Denver, Colorado 80217

1-480-768-2130

(800) 521-6274

JAPAN:

Motorola Japan Ltd.

SPS, Technical Information Center

3-20-1, Minami-Azabu Minato-ku

Tokyo 106-8573 Japan

Information in this document is provided solely to enable system and software implementers to use

Motorola products.There are no express or implied copyright licenses granted hereunder to design

or fabricate any integrated circuits or integrated circuits based on the information in this document.

81-3-3440-3569

ASIA/PACIFIC:

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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

Motorola reserves the right to make changes without further notice to any products herein.

Motorola makes no warranty, representation or guarantee regarding the suitability of its products

for any particular purpose, nor does Motorola assume any liability arising out of the application or

use of any product or circuit, and speciﬁcally disclaims any and all liability, including without

limitation consequential or incidental damages. “Typical” parameters which may be provided in

Motorola data sheets and/or speciﬁcations can and do vary in different applications and actual

performance may vary over time. All operating parameters, including “Typicals” must be validated

for each customer application by customer’s technical experts. Motorola does not convey any

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MPC7410 : Host Processor

Page Contents:

The MPC7410 Host Processor is a high-performance, low-power, 32-bit PowerPC processor combined

with a full 128-bit implementation of Motorola's AltiVec™ technology. This creates a microprocessor ideal

for leading-edge computing, embedded network control, and signal processing applications. The

MPC7410 offers the high-bandwidth MPX bus with minimized signal setup times and reduced idle cycles

to increase maximum operating frequency to over 100 MHz, in addition to increased address and data bus

bandwidth. To maintain compatibility for existing designs, the MPC7410 also supports the 60x bus

protocol. MPC7410 microprocessors offer single-cycle double precision floating-point performance, full

symmetric multi-procesing (SMP) capabilities, and support for up to 2MB of backside L2 cache. While the

MPC7410 is software-compatible with existing MPC603e, MPC740, and MPC750 microprocessors, to

utilize the full potential of the AltiVec technology changes to existing source code is required.

Features

Documentation

Tools

Applications

Orderable Parts

Related Links

Other Info:

FAQs

3rd Party Design Help

Training

Product Picture

Block Diagram

3rd Party Tool

Vendors

MPC7410 Features

3rd Party Trainers

Rate this Page

Superscalar Microprocessor

MPC7410 microprocessors feature a high-frequency, superscalar PowerPC processor core, capable of

issuing three instructions per clock cycle (two instructions + branch) into eight independent execution

units:

Submit

Care to Comment?

●

Two integer units and Double-precision floating-point unit

Vector permute unit

Vector arithmetic logic unit

Load/store unit and System unit

Branch processing unit

MPX Bus Interface

MPC7410 microprocessors support the MPX bus protocol with 64-bit data bus and 32-bit address bus.

Support is included for burst, split, pipelined and out-of-order transactions, in addition to data streaming,

and data intervention (in SMP systems). The interface provides snooping for data cache coherency. The

MPC7410 implements the MERSI cache coherency protocol for multiprocessing support in hardware,

allowing access to system memory for additional caching bus masters, such as DMA devices.

Power Management

MPC7410 microprocessors feature a low-power 1.8-volt design with three power-saving user-

programmable modes -- nap, doze (with bus snoop) and sleep -- which progressively reduce the power

drawn by the processor. The MPC7410 also provides a thermal assist unit and instruction cache throttling

for software-controllable thermal management.

Cache and MMU Support

The MPC7410 microprocessor has separate 32-Kbyte, physically addressed instruction and data caches.

Both caches feature cache locking and are eight-way set-associative. The MPC7410 microprocessor's

dedicated L2 cache interface with on-chip L2 tags features a very fast (up to core speed, 1:1) interface to

memory, instruction-only or data-only modes, and parity checking on L2 data. The L2 data bus has both

32-bit and 64-bit modes, which can also be configured as private memory. The MPC7410 microprocessor

contains separate memory management units (MMUs) for instructions and data, supporting 4 Petabytes

(252) of virtual memory and 4 Gigabytes (232) of physical memory. The MPC7410 also has four

instruction block address translation (iBAT) and four data block address translation (dBAT) registers.

AltiVec Technology

The AltiVec technology expands the capabilities of Motorola's fourth generation processors by providing

leading-edge, general purpose processing performance while concurrently addressing high-bandwidth

data processing and algorithmic-intensive computations in a single-chip solution. AltiVec technology:

●

Meets the computational demands of networking infrastructure such as echo cancellation

equipment, and basestation processing.

●

Enables faster, more secure encryption methods optimized for the SIMD processing model.

Provides compelling performance for multimedia-oriented desktop computers, desktop publishing,

and digital video processing.

●

Enables real-time processing of the most demanding data streams (MPEG-2 encode, continuous

speech recognition, real-time high-resolution 3D memory for additional caching bus masters, such

as DMA devices.)

Return to Top

MPC7410 Documentation

Documentation

Application Note

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

AN1794/D

AN1795/D

AN1809

AN1812/D

AN2077

AN2097

AN2106/D

AN2114/D

AN2115/D

AN2161

AN2180

AN2203/D

AN2273

AN2424/D

AN2435

Backside L2 Timing Analysis for PCB Design Engineers

Designing PowerPC(TM) MPC7400 Systems

87 0.2 5/22/2003

97 1.1 6/05/2003

MOTOROLA

pdf

Minimal Boot Sequence for Executing Compiled C

Programs on PowerPC(TM) Devices

MOTOROLA

pdf

11/11/2003

270 1.2

Common Footprint for the MPC750, MPC755, MPC7400, MOTOROLA

and MPC7410 Application Note

12/17/2001

pdf

283

Design Checklist for Motorola PowerPC(TM)

Microprocessors

MOTOROLA

11/11/2003

309 1.6

PowerPC(TM) 60X Bus Implementation Differences

PowerPC(TM) MPX Bus Implementation Differences

135 0.3 8/06/2003

76 0.1 6/05/2003

158 2.1 6/03/2003

151 2.1 6/03/2003

95 0.1 8/04/2003

Complex Fixed-Point Fast Fourier Transform Optimization MOTOROLA

for Altivec(TM)

Complex Floating Point Fast Fourier Transform

Optimization for AltiVec(TM)

MOTOROLA

Outstanding Data Tenures on the MPX Bus

Cache Latencies of the 7451

87 0.2 8/04/2003

1152

MPC7450 RISC Microprocessor Family Software

Optimization Guide

7/30/2002

Building an NFS DHCP/BOOTP Server for Use with

Sandpoint and MVP Linux

1.1 6/10/2003

12/20/2002

MPC7410 and MPC7450: Comparison and Compatibility

Thermal Solutions for PowerPC(TM) Processors

194

125

7/28/2003

MOTOROLA

11/11/2003

9/30/2003

AN2436

AN2491

AN2540

AN2581

Specifying Power Consumption

pdf

225 0.2

Simplified Mnemonics for PowerPC Instructions

524

Synchronizing Instructions for PowerPC(TM) Instruction

Set Architecture

0.1 7/03/2003

AltiVec Performance Enhancement in a Multiprocessing

Environment

10/10/2003

341

Data Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7410 RISC Microprocessor Hardware

Specifications

MOTOROLA

pdf

616

10/03/2003

MPC7410EC

2.0

MPC7410 Part Number Specifications for the

RXxxxNE Series

MOTOROLA

pdf

10/21/2002

MPC7410NEPNS

MPC7410PCPNS

MPC7410PDPNS

MPC7410PEPNS

MPC7410 Part Number Specifications for the

RXxxxPC Series

MOTOROLA

pdf

229

10/21/2002

MPC7410 Part Number Specifications for the

RXxxxPD Series

MOTOROLA

pdf

157

10/21/2002

MPC7410 Part Number Specifications for the

RXxxxPE Series

MOTOROLA

pdf

10/21/2002

MPC7410 Part Number Specification for the

MPC7410THXnnnLE Series

MOTOROLA

pdf

10/03/2003

10/21/2002

MPC7410THXLEPNS

MPC7410TRXLEPNS/D

MPC7410 Part Number Specification for the

MPC7410TRXnnnLE Series

MOTOROLA

pdf

MPC7410TRXNEPNS/D

MPC7410 Part Number Specification for the

MPC7410TRXnnnNE Series

MOTOROLA

pdf

112

1.1 5/28/2003

Errata - Click here for important errata information

Size

Date Last

Modified

Order

Availability

Name

Vendor ID Format

Rev #

MPC7410CE

MPC7410 RISC Microprocessor Chip Errata MOTOROLA

pdf

156

10/20/2003

Fact Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

160

2/20/2003

ALTIVECFACT/D

ALTIVECWP

AltiVec Fact Sheet

Motorola's AltiVec Technology

MOTOROLA

pdf

171

1/01/1998

4/08/2002

2/17/2003

MPC7410 Fact Sheet High Performance, Low-Power 32- MOTOROLA

Bit RISC Microprocessor

MPC7410FACT/D

pdf

PPCSALESFACT/D

MOTOROLA

234

PowerPC Processors At-A-Glance

Packaging Information

Date Last

Modified

Order

Availability

Name

Vendor ID Format Size K Rev #

PBGAPRES

PBGA Packaging Customer Tutorial

TBGA Packaging Customer Tutorial

MOTOROLA

pdf

1923

1784

8/05/2003

TBGAPRESPKG

Product Brief

Size Rev Date Last

Order

Name

Vendor ID Format

pdf

Modified Availability

MPC7410TS/D

MPC7410 RISC Microprocessor Technical Summary MOTOROLA

311

10/04/2000

Product Change Notices

Size

Date Last

Modified

Order

Availability

Name

Vendor ID Format

Rev #

PCN8657

FC CBGA HIGH TEMP REFLOW CAPABLITY MOTOROLA htm

3/19/2003

Reference Manual

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

3893

ALTIVECPEM/D

ALTIVECPIM_D

MPC7410UM

AltiVec Technology Programming Environments Manual

AltiVec Technology Programming Interface Manual

MPC7410 RISC Microprocessor Users Manual

2.0 2/28/2002

MOTOROLA

pdf

6/01/1999

MOTOROLA

pdf

11/18/2002

Errata to MPC7410 RISC Microprocessor Users Manual MOTOROLA

Rev. 1

MPC7410UMAD

MPCBUSIF/AD

MPCFPE32B/AD

MPCFPE32BAD/AD

pdf

8/29/2003

The Bus Interface for 32-Bit Microprocessors that

Implement the PowerPC Architecture

MOTOROLA

916

3/31/1997

Programming Environments Manual for 32-Bit

Implementations of the PowerPC Architecture

MOTOROLA

6909

12/21/2001

Errata to MPCFPE32B, Programming Environments

Manual for 32-Bit Implementations of the Power PC

Architecture, Rev. 2

MOTOROLA

10/11/2002

1/01/1996

pdf

PowerPC Microprocessor Family: The Programmer's

Pocket Reference Guide

MPCPRGREF/D

375

Reliability and Quality Information

Size Rev Date Last

Order

Availability

Name

Vendor ID Format

Modified

FPCREPORT

FRCALC

Board Level Failure Prediction Calculation Report MOTOROLA

pdf

Component Level Failure Rate Calculation

MPC7410 Reliability and Qualification Data

MOTOROLA

MPC7410QI

Reports or Presentations

Size Rev Date Last

Order

Availability

Name

Vendor ID Format

Modified

9/21/1999

2/10/2003

ALTIVECPR

AltiVec Technology Presentation

MOTOROLA

pdf

PPCCPUSUMM

Motorola Host and Integrated Processor Summary MOTOROLA

Roadmap

Size

Date Last

Modified

Order

Availability

Name

Vendor ID Format

pdf

Rev #

PPCRMAP

Motorola Host Processor Strategy Roadmap MOTOROLA

122

11/30/2001

Selector Guide

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

11/11/2003

SG2000CR

Application Selector Guide Index and Cross-Reference.

Supporting Information

Size Rev Date Last

Order

Availability

Name

Vendor ID Format

pdf

Modified

PPCPVR

Motorola Host Processor Version Register Settings MOTOROLA

16 10/17/2003

White Paper

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

G4WP

G4 Architecture White Paper

1/23/2001

5/01/1996

Motorola PowerPC 603 and PowerPC 604 RISC

Microprocessor: The C4/Ceramic-Ball-Grid Array

Interconnect Technology

MPC603OVERALLWP/D

MOTOROLA

pdf

112

Thermal Management of a C4/Ceramic-Ball-Grid

Array: The Motorola PowerPC 603 and PowerPC

604 RISC Microprocessors

MPC603THERMALWP/D

MPC74XXMBUSWP_D

MOTOROLA

pdf

5/01/1996

MOTOROLA

pdf

11/20/2003

Memory Bus Throughput of the MPC74xx

95 1.1

Return to Top

MPC7410 Tools

Hardware Tools

Board Testers

Name

Vendor ID

Format

Size K

Rev #

Order Availability

SCANPLUS

CORELIS

ScanPlus

Emulators/Probes/Wigglers

Name

Vendor ID

ABATRON

CORELIS

Format Size K Rev #

Order Availability

BDI1000/BDI2000

10200A

BDI1000/BDI2000

NetICE-R option 2/2M

PROBE

GREENHILLS

WINDRIV

Green Hills Probe & Slingshot

visionICE II

VISIONICE

VISIONPROBE

WPICE

WINDRIV

visionPROBE II

WINDRIV

WIND®POWER ICE

Evaluation/Development Boards and Systems

Size Rev

Order

Availability

Name

Vendor ID Format

MOTOROLA

SANDPOINTX3

Sandpoint X3 Evaluation System - Motherboard

PPCEVAL-SP3-

7410

MOTOROLA

Sandpoint X3 Motherboard with Altimus X3 MPC7410 PMC Module

Models

BSDL

Size Rev

Order

Availability

Name

Vendor ID Format

MOTOROLA txt

MPC7410R1CBSDL

MPC7410 BSDL for Rev. 1.2 and above of Silicon

Bus Functional Models

Name

Vendor ID

Format Size K Rev # Order Availability

tar 1185 1.6

MPC7400 Bus Functional Model

(07/16/2002)

MPC7400BFM

MOTOROLA

Full Functional Models

Name

Vendor ID Format Size K Rev #

Order Availability

EP100

EUREKA

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

EP201

EP300

EP433

ES100

IBIS

Size Rev

Order

Availability

Name

Vendor ID Format

MPC7410, All Revisions, 360 CBGA Package, 2.5V I/O, 2.5V MOTOROLA

L2 IBIS

103

MPC7410AIBIS

MPC7410BIBIS

MPC7410CIBIS

MPC7410DIBIS

MPC7410EIBIS

MPC7410FIBIS

MPC7410PAIBIS

MPC7410PBIBIS

MPC7410PCIBIS

MPC7410PDIBIS

MPC7410PEIBIS

MPC7410PFIBIS

txt

0.1

MPC7410, All Revisions, 360 CBGA Package, 2.5V I/O, 1.8V MOTOROLA

L2 IBIS

100

0.1

MPC7410, All Revisions,360 CBGA Package, 1.8V I/O, 2.5V MOTOROLA

L2 IBIS

99 0.1

95 0.1

MPC7410, All Revisions,360 CBGA Package, 1.8V I/O, 1.8V MOTOROLA

L2 IBIS

MPC7410, All Revisions,360 CBGA Package, 3.3V I/O, 2.5V MOTOROLA

L2 IBIS

109

0.1

MPC7410, All Revisions,360 CBGA Package, 3.3V I/O, 1.8V MOTOROLA

L2 IBIS

105

0.1

MPC7410, All Revisions,360 PBGA Package, 2.5V I/O, 2.5V

L2 IBIS

MOTOROLA

111

0.1

MPC7410, All Revisions,360 PBGA Package, 2.5V I/O, 1.8V

L2 IBIS

102

0.1

MPC7410, All Revisions,360 PBGA Package, 1.8V I/O, 2.5V

L2 IBIS

101

0.1

MPC7410, All Revisions,360 PBGA Package, 1.8V I/O, 1.8V

L2 IBIS

97 0.1

MPC7410, All Revisions,360 PBGA Package, 3.3V I/O, 2.5V

L2 IBIS

111

0.1

MPC7410, All Revisions,360 PBGA Package, 3.3V I/O, 1.8V

L2 IBIS

107

0.1

Timing Models

Name

Vendor ID

Format Size K Rev # Order Availability

SimG4 Timing Model (for Linux)

(01/2002)

MPC7400LINTIME

MPC7400SOLTIME

MOTOROLA

310

279

1.3.2

1.3.1

SimG4 Timing Model (for Solaris)

(01/2002)

MOTOROLA

Software

Application Software

Application Development Framework

Name

Vendor ID Format Size K Rev # Order Availability

NPMGMT

KENATI

NP Management Application Framework

DINK32

Name

Vendor ID

Format Size K Rev # Order Availability

DINK32

ROM-Based Debug Monitor, R13.1.1

MOTOROLA

Board Support Packages

Name

Vendor ID Format Size K Rev #

Order Availability

ARC-MOT-MQXBSP

ARC

MQX Board Support Packages

NP Linux

NPLINUX

KENATI

Device Drivers

Name

Vendor ID

KENATI

Format

Size K

Rev #

Order Availability

NPLINUX

NP Linux

Operating Systems

Size Rev

Order

Availability

Name

Vendor ID Format

ARC-MOT-MQX

ARC

Precise/MQX? Real Time Operating System

ARC-MOT-

OSCHANGER

OS Changer

INTEGRITY

INTEGRITY® is a secure, royalty-free Real-Time Operating System

intended for use in embedded systems that require maximum

reliability.

INTEGRITY

GREENHILLS

JAL100

JAL200

NPLINUX

JALUNA

KENATI

Jaluna-1

Jaluna-2

NP Linux

Protocol Stacks

Name

Vendor ID

ARC

Format Size K Rev #

Order Availability

ARC-MOT-IPSHIELD

IPShield Security Solution

Precise/RTCS

CMX TCP/IP

ARC-MOT-RTCS

CMX TCP/IP

NPSTACK

ARC

CMX

KENATI

NP Network Stack

Software Tools

Code Translation

Name

Vendor ID

MICROAPL

Format Size K Rev #

Order Availability

PA68K-PPC

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

PA86-PPC

Compilers

Size Rev

Order

Availability

Name

Vendor ID

Format

CWEPPC

METROWERKS

CodeWarrior Development Studio for PowerPC ISA

CodeWarrior Development Studio. Linux Application Edition for

PowerPC

CWLINPPC

ARC-MOT-

COMPILER

ARC

MetaWare C/C++ Compiler Tool Suite

MULTI

COMPILER

GREENHILLS

WINDRIV

MULTI Compiler For PowerPC

Diab C/C++ Compiler

DIAB

Debuggers

Size Rev

Order

Availability

Name

Vendor ID

Format

CodeWarrior Development Studio. Linux Application Edition for

PowerPC

CWLINPPC

METROWERKS

ARC-MOT-

DEBUGGER

ARC

SeeCode C/C++ Debugger

MULTI Debugger

POWERPC

DEBUGGER

GREENHILLS

IDE (Integrated Development Environment)

Size Rev

Order

Availability

Name

Vendor ID

Format

CodeWarrior Development Studio. Linux Application Edition for

PowerPC

CWLINPPC

METROWERKS

IC-SW-OPR

WPIDE

ISYS

winIDEA

WINDRIV

WIND®POWER IDE

Models

Instruction Set Simulator

Name

Vendor ID

Format Size K Rev #

Order Availability

MPC7410 Generic Library ISS

(04/07/2003)

MPC7410GENISS

MOTOROLA

2293

1489

1.12.17

MPC7410 Standalone ISS

(04/07/2003)

MPC7410ISS

MOTOROLA

Return to Top

Applications

Networking and Communications

Access

Cable Modem Termination System

Return to Top

Orderable Parts Information

Budgetary

Price

QTY 1000+

($US)

Tape

and

Reel

Additional

Info

Order

Availability

Life Cycle Description (code)

PartNumber

Package Info

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

MPC7410HX400LE

MPC7410HX450LE

MPC7410HX500LE

MPC7410RX400LE

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

MPC7410RX400NE

MPC7410RX450LE

MPC7410RX450NE

MPC7410RX500LE

MPC7410TRX400LE

MPC7410TRX400NE

MPC7410TRX450LE

MPC7410TRX450NE

MPC7410TRX500LE

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

FCCBGA 360

25SQ*3.2P1.27

PRODUCT STABLE

GROWTH/MATURITY(3)

NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.

Return to Top

Related Links

C-Port™ Network Processors

Networking

PowerPC™ Processors

PowerQUICC™ Communication Processors

AltiVec Technology

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Motorola > Semiconductors > Products > 32-Bit Embedded Processors > PowerPC™ Processors > MPC7XXX, MPC7XX and

MPC6XX Host Processors > MPC7410

spacer

MPC7410 : Host Processor

Page Contents:

Features

The MPC7410 Host Processor is a high-performance, low-power, 32-bit PowerPC processor

combined with a full 128-bit implementation of Motorola's AltiVec™ technology. This creates a

microprocessor ideal for leading-edge computing, embedded network control, and signal processing

applications. The MPC7410 offers the high-bandwidth MPX bus with minimized signal setup times

and reduced idle cycles to increase maximum operating frequency to over 100 MHz, in addition to

increased address and data bus bandwidth. To maintain compatibility for existing designs, the

MPC7410 also supports the 60x bus protocol. MPC7410 microprocessors offer single-cycle double

precision floating-point performance, full symmetric multi-procesing (SMP) capabilities, and

support for up to 2MB of backside L2 cache. While the MPC7410 is software-compatible with

existing MPC603e, MPC740, and MPC750 microprocessors, to utilize the full potential of the

AltiVec technology changes to existing source code is required.

Parametrics

Documentation

Tools

Applications

Orderable Parts

Related Links

Other Info:

FAQs

Literature Services

3rd Party Design

Help

Link

Product Picture

Link

Block Diagram

Training

3rd Party Tool

Vendors

MPC7410 Features

3rd Party Trainers

Rate this Page

Superscalar Microprocessor

MPC7410 microprocessors feature a high-frequency, superscalar PowerPC processor core, capable

of issuing three instructions per clock cycle (two instructions + branch) into eight independent

execution units:

Submit

Care to Comment?

●

Two integer units and Double-precision floating-point unit

Vector permute unit

Vector arithmetic logic unit

Load/store unit and System unit

Branch processing unit

MPX Bus Interface

MPC7410 microprocessors support the MPX bus protocol with 64-bit data bus and 32-bit address

bus. Support is included for burst, split, pipelined and out-of-order transactions, in addition to data

streaming, and data intervention (in SMP systems). The interface provides snooping for data cache

coherency. The MPC7410 implements the MERSI cache coherency protocol for multiprocessing

support in hardware, allowing access to system memory for additional caching bus masters, such as

DMA devices.

Power Management

MPC7410 microprocessors feature a low-power 1.8-volt design with three power-saving user-

programmable modes -- nap, doze (with bus snoop) and sleep -- which progressively reduce the

power drawn by the processor. The MPC7410 also provides a thermal assist unit and instruction

cache throttling for software-controllable thermal management.

Cache and MMU Support

The MPC7410 microprocessor has separate 32-Kbyte, physically addressed instruction and data

caches. Both caches feature cache locking and are eight-way set-associative. The MPC7410

microprocessor's dedicated L2 cache interface with on-chip L2 tags features a very fast (up to core

speed, 1:1) interface to memory, instruction-only or data-only modes, and parity checking on L2

data. The L2 data bus has both 32-bit and 64-bit modes, which can also be configured as private

memory. The MPC7410 microprocessor contains separate memory management units (MMUs) for

instructions and data, supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of

physical memory. The MPC7410 also has four instruction block address translation (iBAT) and four

data block address translation (dBAT) registers.

AltiVec Technology

The AltiVec technology expands the capabilities of Motorola's fourth generation processors by

providing leading-edge, general purpose processing performance while concurrently addressing high-

bandwidth data processing and algorithmic-intensive computations in a single-chip solution. AltiVec

technology:

●

Meets the computational demands of networking infrastructure such as echo cancellation

equipment, and basestation processing.

●

Enables faster, more secure encryption methods optimized for the SIMD processing model.

Provides compelling performance for multimedia-oriented desktop computers, desktop

publishing, and digital video processing.

●

Enables real-time processing of the most demanding data streams (MPEG-2 encode,

continuous speech recognition, real-time high-resolution 3D memory for additional caching

bus masters, such as DMA devices.)

Return to Top

MPC7410 Parametrics

Core

Operating

Voltage

(Spec)

(V)

Junction

Operating

Temperature

(Max)

Operating

Frequency

(Max)

Power

Dissipation

(Typ)

Power

Dissipation

(Max)

I/O Operating Ambient

CPU Performance

(Max)

Voltage

(Max)

(V)

Temp

(Min)

(oC)

(MIPS)

(MHz)

(W)

(oC)

2.92,

3.29,

4.2,

4.7,

5.3

6.6,

7.43,

9.5,

10.7,

11.9

968,

1089,

1210

400,

450,

500

1.5,

1.8

-40,

3.3

105

L1 Cache Instructional L1 Cache Data L2 Cache External

External Bus Speed

(Max)

Bus Interface

Package Description

(KByte)

(MHz)

60x,

MPX

2000

133

FCCBGA 360 25SQ*3.2P1.27

Link

View expanded set of parameters

Return to Top

MPC7410 Documentation

Documentation

Application Note

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

Backside L2 Timing Analysis for PCB Design

Engineers

AN1794/D

AN1795/D

AN1809

AN1812/D

AN2077

AN2097

AN2106/D

AN2114/D

AN2115/D

AN2161

AN2180

AN2203/D

AN2273

AN2424/D

AN2435

AN2436

AN2491

AN2540

pdf 87 0.2 5/22/2003

pdf 97 1.1 6/05/2003

MOTOROLA

Designing PowerPC(TM) MPC7400 Systems

Minimal Boot Sequence for Executing Compiled C MOTOROLA

Programs on PowerPC(TM) Devices

11/11/2003

pdf 270 1.2

Common Footprint for the MPC750, MPC755,

MPC7400, and MPC7410 Application Note

MOTOROLA

12/17/2001

pdf 283

Design Checklist for Motorola PowerPC(TM)

Microprocessors

11/11/2003

pdf 309 1.6

PowerPC(TM) 60X Bus Implementation

Differences

pdf 135 0.3 8/06/2003

pdf 76 0.1 6/05/2003

pdf 158 2.1 6/03/2003

pdf 151 2.1 6/03/2003

pdf 95 0.1 8/04/2003

PowerPC(TM) MPX Bus Implementation

Differences

Complex Fixed-Point Fast Fourier Transform

Optimization for Altivec(TM)

Complex Floating Point Fast Fourier Transform

Optimization for AltiVec(TM)

Outstanding Data Tenures on the MPX Bus

Cache Latencies of the 7451

pdf 87 0.2 8/04/2003

1152

MPC7450 RISC Microprocessor Family Software MOTOROLA

Optimization Guide

pdf

7/30/2002

Building an NFS DHCP/BOOTP Server for Use

with Sandpoint and MVP Linux

MOTOROLA

pdf 213 1.1 6/10/2003

12/20/2002

MPC7410 and MPC7450: Comparison and

Compatibility

pdf 194

Thermal Solutions for PowerPC(TM) Processors

Specifying Power Consumption

pdf 125

7/28/2003

11/11/2003

pdf 225 0.2

pdf 524

Simplified Mnemonics for PowerPC Instructions

9/30/2003

Synchronizing Instructions for PowerPC(TM)

Instruction Set Architecture

pdf 67 0.1 7/03/2003

AltiVec Performance Enhancement in a

Multiprocessing Environment

MOTOROLA

10/10/2003

AN2581

pdf 341

Data Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7410 RISC Microprocessor Hardware MOTOROLA

Specifications

947

pdf

5/14/2004

MPC7410EC

MPC7410 Part Number Specifications for MOTOROLA

the RXxxxNE Series

10/21/2002

MPC7410NEPNS

MPC7410PCPNS

pdf 96

MPC7410 Part Number Specifications for MOTOROLA

the RXxxxPC Series

229

157

10/21/2002

pdf

MPC7410 Part Number Specifications for MOTOROLA

the RXxxxPD Series

10/21/2002

MPC7410PDPNS

MPC7410 Part Number Specifications for MOTOROLA

the RXxxxPE Series

10/21/2002

MPC7410PEPNS

pdf 71

pdf 52

pdf 76

MPC7410 Part Number Specification for the MOTOROLA

MPC7410THXnnnLE Series

10/03/2003

10/21/2002

MPC7410THXLEPNS

MPC7410TRXLEPNS/D

MPC7410TRXNEPNS/D

MPC7410 Part Number Specification for the MOTOROLA

MPC7410TRXnnnLE Series

MPC7410 Part Number Specification for the MOTOROLA

MPC7410TRXnnnNE Series

112

pdf

1.1 5/28/2003

Errata - Click here for important errata information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7410 RISC Microprocessor Chip Errata MOTOROLA pdf 193 15 5/13/2004

MPC7410CE

Fact Sheets

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

160

2/20/2003

1/01/1998

4/08/2002

2/17/2003

ALTIVECFACT

ALTIVECWP

AltiVec Fact Sheet

Motorola's AltiVec Technology

MOTOROLA

pdf

171

MPC7410 Fact Sheet High Performance, Low- MOTOROLA

Power 32-Bit RISC Microprocessor

MPC7410FACT/D

PPCSALESFACT/D

pdf 35

234

MOTOROLA

PowerPC Processors At-A-Glance

pdf

Packaging Information

Date Last

Modified

Order

Availability

Name

Vendor ID Format Size K Rev #

PBGAPRES

PBGA Packaging Customer Tutorial MOTOROLA pdf 1923

TBGA Packaging Customer Tutorial MOTOROLA pdf 1784

8/05/2003

TBGAPRESPKG

Product Brief

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MPC7410 RISC Microprocessor Technical

Summary

MOTOROLA

pdf

311

10/04/2000

MPC7410TS/D

Product Change Notices

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

PCN8657

PCN9224

PCN9383

PCN9842

FC CBGA HIGH TEMP REFLOW CAPABLITY

htm 14

htm 62

htm 14

3/19/2003

NEW TRAY FOR 25 X 25 FLIPCHIP BGA

PACKAGE

MOTOROLA

10/14/2003

11/24/2003

4/30/2004

MPC7410 TEST PLATFORM TRANSFER.

CHANGE ON NITRO VOL/VOH TEST

CONDITIONS

htm

Reference Manual

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

AltiVec Technology Programming

Environments Manual

MOTOROLA

pdf

3893

ALTIVECPEM/D

ALTIVECPIM

2.0 2/28/2002

AltiVec Technology Programming Interface

Manual

MOTOROLA

pdf

6/01/1999

The Bus Interface for 32-Bit Microprocessors MOTOROLA

that Implement the PowerPC Architecture

2527

MPC60XBUSRM

MPC7410UM

pdf

0.1 1/14/2004

MPC7410 RISC Microprocessor Users Manual MOTOROLA

7772

11/18/2002

Errata to MPC7410 RISC Microprocessor

Users Manual Rev. 1

MOTOROLA

MPC7410UMAD

MPCFPE32B/AD

pdf 69

8/29/2003

Programming Environments Manual for 32-Bit MOTOROLA

Implementations of the PowerPC Architecture

6909

12/21/2001

pdf

Errata to MPCFPE32B, Programming

Environments Manual for 32-Bit

Implementations of the Power PC Architecture,

Rev. 2

MOTOROLA

10/11/2002

MPCFPE32BAD/AD

pdf 40

Reliability and Quality Information

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

FPCREPORT

FRCALC

MPC7410QI

Board Level Failure Prediction Calculation Report

Component Level Failure Rate Calculation

MPC7410 Reliability and Qualification Data

pdf 84

pdf 21

pdf 13

MOTOROLA

Reports or Presentations

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

726

9/21/1999

ALTIVECPR

PPCCPUSUMM

AltiVec Technology Presentation

Motorola Host and Integrated Processor Summary

MOTOROLA

pdf

2/10/2003

Roadmap

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

Freescale High-Performance PowerPC Processors

Roadmap

4/26/2004

PPCRMAP

pdf 27

Selector Guide

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

Application Selector Guide Index and Cross-

Reference.

12/29/2003

SG2000CR

pdf 46

Supporting Information

Size Rev Date Last

Order

Name

Vendor ID Format

Modified Availability

MOTOROLA

pdf

4/05/2004

PPCPVR

Motorola Host Processor Version Register Settings

White Paper

Size Rev Date Last

Order

Name

Vendor ID Format

MOTOROLA

Modified Availability

G4WP

G4 Architecture White Paper

pdf 53

1/23/2001

5/01/1996

Motorola PowerPC 603 and PowerPC 604

RISC Microprocessor: The C4/Ceramic-

Ball-Grid Array Interconnect Technology

MOTOROLA

112

MPC603OVERALLWP/D

pdf

Thermal Management of a C4/Ceramic-

Ball-Grid Array: The Motorola PowerPC MOTOROLA

603 and PowerPC 604 RISC

Microprocessors

MPC603THERMALWP/D

MPC74XXMBUSWP_D

pdf 86

5/01/1996

Memory Bus Throughput of the MPC74xx MOTOROLA

103

11/24/2003

pdf

1.1

Return to Top

MPC7410 Tools

Hardware Tools

Board Testers

Size Rev

Order

Name

Vendor ID Format

# Availability

SCANPLUS

CORELIS

ScanPlus

µMaster 4031

Functional Test and Debug Solutions for boards carrying

Motorola™ and IBM® PowerPC™ processors with COP debug

port (740, 750, 750DD2, 750DD3, 755, 603e, 8240, 8250A,

8255A, 8260A, 8264A, 8265A, 8266A, 7400, 7410, etc.)

4000-994020-

001

INTLTEST

Emulators/Probes/Wigglers

Size Rev

Order

Name

Vendor ID Format

# Availability

BDI1000/BDI2000

Abatron develops and produces high-quality, high-speed

BDM and JTAG Debug Tools (BDI Family) for software

development environments from leading vendors.

BDI1000/BDI2000

ABATRON

10200A

PROBE

CORELIS

NetICE-R option 2/2M

GREENHILLS

Green Hills Probe & Slingshot

µMaster 4031

Functional Test and Debug Solutions for boards carrying

Motorola™ and IBM® PowerPC™ processors with COP

debug port (740, 750, 750DD2, 750DD3, 755, 603e, 8240,

8250A, 8255A, 8260A, 8264A, 8265A, 8266A, 7400, 7410,

etc.)

4000-994020--001

INTLTEST

VISIONICE

VISIONPROBE

WPICE

WINDRIV

visionICE II

visionPROBE II

WIND®POWER ICE

Evaluation/Development Boards and Systems

Size Rev

Order

Name

Vendor ID Format

# Availability

PPCEVAL-SP3-

7410

Sandpoint X3 Motherboard with Altimus X3 MPC7410 PMC

Module

MOTOROLA

SANDPOINTX3

MOTOROLA

Sandpoint X3 Evaluation System - Motherboard

Models

BSDL

Size Rev

Order

Name

Vendor ID Format

# Availability

MOTOROLA

txt

MPC7410R1CBSDL

MPC7410 BSDL for Rev. 1.2 and above of Silicon

Bus Functional Models

Name

Vendor ID

Format Size K Rev # Order Availability

gz 1175 1.7

MPC7400 Bus Functional Model

(01/05/2004)

MPC7400BFM

MOTOROLA

Full Functional Models

Name

Vendor ID Format Size K Rev # Order Availability

EP100

EP201

EP300

EP433

ES100

EUREKA

PowerPC Bus Slave

PowerPC Bus Master

PowerPC Bus Arbiter

PowerPC-PCI Bridge

PowerPC System Controller

IBIS

Size Rev

Order

Name

Vendor ID Format

# Availability

MPC7410, All Revisions, 360 CBGA Package, 2.5V

I/O, 2.5V L2 IBIS

MOTOROLA

103

MPC7410AIBIS

MPC7410BIBIS

MPC7410CIBIS

MPC7410DIBIS

MPC7410EIBIS

MPC7410FIBIS

MPC7410PAIBIS

MPC7410PBIBIS

MPC7410PCIBIS

MPC7410PDIBIS

MPC7410PEIBIS

MPC7410PFIBIS

txt

0.1

MPC7410, All Revisions, 360 CBGA Package, 2.5V

I/O, 1.8V L2 IBIS

100

0.1

MPC7410, All Revisions,360 CBGA Package, 1.8V

I/O, 2.5V L2 IBIS

99 0.1

95 0.1

MPC7410, All Revisions,360 CBGA Package, 1.8V

I/O, 1.8V L2 IBIS

MPC7410, All Revisions,360 CBGA Package, 3.3V

I/O, 2.5V L2 IBIS

109

0.1

MPC7410, All Revisions,360 CBGA Package, 3.3V

I/O, 1.8V L2 IBIS

105

0.1

MPC7410, All Revisions,360 PBGA Package, 2.5V

I/O, 2.5V L2 IBIS

111

0.1

MPC7410, All Revisions,360 PBGA Package, 2.5V

I/O, 1.8V L2 IBIS

102

0.1

MPC7410, All Revisions,360 PBGA Package, 1.8V

I/O, 2.5V L2 IBIS

101

0.1

MPC7410, All Revisions,360 PBGA Package, 1.8V

I/O, 1.8V L2 IBIS

97 0.1

MPC7410, All Revisions,360 PBGA Package, 3.3V

I/O, 2.5V L2 IBIS

111

0.1

MPC7410, All Revisions,360 PBGA Package, 3.3V

I/O, 1.8V L2 IBIS

107

0.1

Timing Models

Name

Vendor ID Format Size K Rev # Order Availability

SimG4 Timing Model (for Linux)

(01/2002)

MPC7400LINTIME

MPC7400SOLTIME

MOTOROLA

310 1.3.2

279 1.3.1

SimG4 Timing Model (for Solaris)

(01/2002)

Software

Application Software

Application Development Framework

Name

Vendor ID Format Size K Rev # Order Availability

KENATI

NPMGMT

NP Management Application Framework

DINK32

Name

Vendor ID Format Size K Rev # Order Availability

DINK32

ROM-Based Debug Monitor, R13.1.1

MOTOROLA

Board Support Packages

Name

Vendor ID

KENATI

Format

Size K

Rev #

Order Availability

NPLINUX

NP Linux

Device Drivers

Name

Vendor ID

KENATI

Format

Size K

Rev #

Order Availability

NPLINUX

NP Linux

Libraries

Vendor

Size Rev

Order

Name

KwikPeg GUI

Format

# Availability

KADAK's KwikPeg Graphical User Interface (GUI) is derived from

PEG, a professional, high-quality graphic system created by Swell

Software, Inc. to enable you, the embedded system developer, to

easily add graphics to your products.

PN311-1

KADAK

Operating Systems

Size Rev

Order

Name

Vendor ID Format

# Availability

ARC-OS Changer

Provides developers the freedom to migrate from either

ARC-MOT-

ARC

ENEA

OSCHANGER pSOSystem or VxWorks to MQX RTOS while reusing an

existing code base

DPP.7XXX.KRN

OSE Real-Time Operating System

ThreadX

RTOS. Royalty-free real-time operating system (RTOS) for

embedded applications. ThreadX is small, fast, and royalty-

free making it ideal for high-volume electronic products.

THREADX

EXPRESSLOG

MorphOS

MorphOS is designed around the concept of shared resources

and the ability to build up applications using shared system

components. MorphOS is not unix based.

MORPHOS

GENESI

INTEGRITY

INTEGRITY? is a secure, royalty-free Real-Time Operating

System intended for use in embedded systems that require

maximum reliability.

INTEGRITY

JAL100

GREENHILLS

JALUNA

Jaluna-1

JAL200

JALUNA

KADAK

KENATI

Jaluna-2

AMX PPC32

AMX is a full featured RTOS for the PowerPC family. AMX

has been tested on the EST SBC8260, Embedded Planet RPX

Lite MPC823 and Motorola Ultra 603, MBX860, MPC860

ADS and MPC860 FADS.

PX382-1

NPLINUX

NP Linux

Protocol Stacks

Size Rev

Order

Name

Vendor ID Format

# Availability

AnviMSTP

Avnisoft's AvniMSTP is a completely portable ANSI C compliant

implementation of the IEEE 802.1s MSTP. It is implemented on

top of, and includes the AvniPORT platform abstraction layer to

simplify integration with target platforms.

MSTP

AVNISOFT

CMX

CMX TCP/IP

PN713-1

CMX TCP/IP

KwikNet

The KwikNet TCP/IP Stack enables you to add networking

features to your products with a minimum of time and expense.

KwikNet is a compact, high performance stack built with

KADAK's characteristic simplicity, flexibility and reliability.

KADAK

KENATI

NPSTACK

NP Network Stack

Software Tools

Code Translation

Name

Vendor ID

MICROAPL

Format Size K Rev #

Order Availability

PA68K-PPC

PortAsm/68K for PowerPC

PortAsm/86 for PowerPC

PA86-PPC

Compilers

Size Rev

Order

Name

Vendor ID

Format

# Availability

CWEPPC

METROWERKS

CodeWarrior Development Studio for PowerPC ISA

CodeWarrior Development Studio. Linux Application

Edition for PowerPC

CWLINPPC

ARC-MOT-

COMPILER

MetaWare C/C++ Compiler Tool Suite

Optimized compiler for Motorola processors

ARC

MULTI

COMPILER

GREENHILLS

WINDRIV

MULTI Compiler For PowerPC

Diab C/C++ Compiler

DIAB

Debuggers

Name

Vendor ID

Format Size K Rev # Order Availability

MetaWare SeeCode Debugger

C/C++ Debugger

ARC-MOT-DEBUGGER

POWERPC DEBUGGER

ARC

GREENHILLS

MULTI Debugger

IDE (Integrated Development Environment)

Name

Vendor ID

GREENHILLS

ISYS

Format Size K Rev #

Order Availability

MULTI

IC-SW-OPR

WPIDE

MULTI

winIDEA

WINDRIV

WIND®POWER IDE

Models

Instruction Set Simulator

Name

Vendor ID

Format Size K Rev # Order Availability

MPC7410 Generic Library ISS

(04/07/2003)

MPC7410GENISS

MPC7410ISS

MOTOROLA

2293 1.12.17

1489 1.12.17

MPC7410 Standalone ISS

(04/07/2003)

Return to Top

Applications

Networking and Communications

Access

Cable Modem Termination System

Return to Top

Orderable Parts Information

Budgetary

Price

QTY

1000+

($US)

Application/

Qualification

Tier

Tape

and

Reel

Pb-Free

Terminations

Package

Description

Part Number

Status

Info Order

FCCBGA 360

25SQ*3.2P1.27

No Longer

Manufactured

MPC7410HX400LE

MPC7410HX450LE

MPC7410HX500LE

MPC7410RX400LE

MPC7410RX400NE

FCCBGA 360

25SQ*3.2P1.27

Available

FCCBGA 360

25SQ*3.2P1.27

COMMERCIAL,

INDUSTRIAL

Available

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

MPC7410RX450LE

MPC7410RX450NE

MPC7410RX500LE

MPC7410THX400LE

MPC7410THX450LE

MPC7410THX500LE

MPC7410TRX400LE

MPC7410TRX400NE

MPC7410TRX450LE

MPC7410TRX450NE

MPC7410TRX500LE

Available

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

No Longer

Manufactured

FCCBGA 360

25SQ*3.2P1.27

No Longer

Manufactured

FCCBGA 360

25SQ*3.2P1.27

Available

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

FCCBGA 360

25SQ*3.2P1.27

NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.

Return to Top

Related Links

Link

C-Port™ Network Processors

Networking

PowerPC™ Processors

PowerQUICC™ Communication Processors

AltiVec Technology

Return to Top

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MPC7410RX400LE [MOTOROLA]

相关型号：

MPC7410RX400NE

MPC7410RX400NE

MPC7410RX400NE

MPC7410RX450LC

MPC7410RX450LD

MPC7410RX450LE

MPC7410RX450NE

MPC7410RX450NE

MPC7410RX450TE

MPC7410RX500LD

MPC7410RX500LE

MPC7410RX500NE