MPC8241LZQ166D [MOTOROLA]
32-BIT, 166MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357;
| 型号： | MPC8241LZQ166D |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 166MHz, RISC PROCESSOR, PBGA357, 25 X 25 MM, 1.27 MM HEIGHT, PLASTIC, BGA-357 |
| 文件： | 总64页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MPC8241EC
Rev. 7, 5/2004
MPC8241
Integrated Processor
Hardware Specifications
The MPC8241 combines a MPC603e PowerPC™ core microprocessor with a PCI bridge. The
PCI support on the MPC8241 allows system designers to use peripherals that are already
designed for the PCI and other standard interfaces to design systems rapidly. The MPC8241
also integrates a high-performance memory controller that supports various types of ROM and
SDRAM. The MPC8241 is the second of a family of products that provides system-level
support for industry standard interfaces with a MPC603e processor core.
This document describes pertinent electrical and physical characteristics of the MPC8241,
which is based on the MPC8245 design. For information about functional characteristics of
the processor, refer to the MPC8245 Integrated Processor User’s Manual (MPC8245UM).
This document contains the following topics:
Topic
Page
Section 1, “Overview”
1
Section 2, “Features”
3
Section 3, “General Parameters”
Section 4, “Electrical and Thermal Characteristics”
Section 5, “Package Description”
Section 6, “PLL Configuration”
Section 7, “System Design Information”
Section 8, “Document Revision History”
Section 9, “Ordering Information”
5
6
34
42
47
57
59
To locate any published errata or updates for this document, refer to the web site at
http://www.motorola.com/semiconductors.
1 Overview
The MPC8241 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar MPC603e core, as shown in Figure 1.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
MPC8241
Processor Core Block
(64-Bit) Two-Instruction Fetch
Additional Features:
Processor
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Branch
Processing
Unit
PLL
Instruction
Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
Floating-
Integer
Unit
(IU)
Load/Store
Point
Unit
Unit
(LSU)
(FPU)
(SRU)
64-Bit
Instruction
Data
MMU
MMU
16-Kbyte
Data
Cache
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
Peripheral Logic Block
Address
Message
Unit
Data Bus
Data (64-Bit)
Data Path
(32- or 64-Bit)
with 8-Bit Parity
or ECC
(32-Bit)
ECC Controller
(with I2O)
Central
Memory
Controller
Memory/ROM/
Port X Control/Address
Control
Unit
DMA
Controller
Performance
Monitor
SDRAM_SYNC_IN
SDRAM Clocks
PCI_SYNC_IN
I2C
I2C
Controller
DLL
Peripheral Logic
PLL
PIC
5 IRQs/
16 Serial
Interrupts
Interrupt
Controller/
Timers
Configuration
Registers
PCI Bus
Interface Unit
DUART
Address
Translator
PCI
Arbiter
Watchpoint
Facility
Fanout PCI Bus
Buffers
Clocks
OSC_IN
32-Bit
Five
PCI Interface Request/Grant
Pairs
Figure 1. MPC8241 Block Diagram
2
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
2
memory controller, DMA controller, PIC interrupt controller, a message unit (and I O interface), and an I C
2
controller. The processor core is a full-featured, high-performance processor with floating-point support,
memory management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power management features.
The integration reduces the overall packaging requirements and the number of discrete devices required for
an embedded system.
The MPC8241 contains an internal peripheral logic bus that interfaces the processor core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade performance for power
consumption. The processor core is clocked from a separate PLL that is referenced to the peripheral logic
PLL, allowing the microprocessor and the peripheral logic block to operate at different frequencies while
maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory
data bus width) and a 32-bit address bus along with control signals that enable the interface between the
processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8241 memory
space are passed to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic serve the general purposes of a variety of embedded applications.
The MPC8241 can be used as either a PCI host or PCI agent controller.
2 Features
Major features of the MPC8241 are as follows:
•
Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and a branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—entire cache or on a per-way basis up to three of four ways
— Dynamic power management—supports 60x nap, doze, and sleep modes
Peripheral logic
•
— Peripheral logic bus
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Supports full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Supports up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
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MPC8241 Integrated Processor Hardware Specifications
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3
Features
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/Port X space
– Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or
64-bit)
– Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data
path
– Port X: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Some internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/Port X not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I O message interface
2
2
— I C controller with full master/slave support that accepts broadcast messages
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers with cascade
— Two (dual) universal asynchronous receiver/transmitters (UARTs)
4
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
System level performance monitor facility
•
•
Debug features
— Memory attribute and PCI attribute signals
— Debug address signals
— MIV signal: marks valid address and data bus cycles on the memory bus
— Programmable input and output signals with watchpoint capability
— Error injection/capture on data path
— IEEE 1149.1 (JTAG)/test interface
3 General Parameters
The following list provides a summary of the general parameters of the MPC8241:
Technology
Die size
0.25 µm CMOS, five-layer metal
2
49.2 mm
Transistor count
Logic design
Packages
4.5 million
Fully static
Surface-mount 357 (thick substrate and thick mold cap)
plastic ball grid array (PBGA)
Core power supply
I/O power supply
1.8 V ± 100 mV DC (nominal; see Table 2 for details
and recommended operating conditions)
3.0 to 3.6 V DC
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
Electrical and Thermal Characteristics
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8241.
4.1 DC Electrical Characteristics
This section covers ratings, conditions, and other characteristics.
4.1.1 Absolute Maximum Ratings
This section describes the MPC8241 DC electrical characteristics. Table 1 provides the absolute maximum
ratings.
Table 1. Absolute Maximum Ratings
Characteristic 1
Symbol
Range
Unit
Supply voltage—CPU core and peripheral logic
VDD
–0.3 to 2.1
–0.3 to 3.6
V
V
Supply voltage—memory bus drivers
PCI and standard I/O buffers
GVDD_OVDD
Supply voltage—PLLs
Supply voltage—PCI reference
Input voltage 2
AVDD/AVDD
2
–0.3 to 2.1
–0.3 to 5.4
–0.3 to 3.6
0 to 105
V
V
LVDD
Vin
V
Operational die-junction temperature range
Storage temperature range
Notes:
Tj
°C
°C
Tstg
–55 to 150
1. Table 2 provides functional and tested operating conditions. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability
or cause permanent damage to the device.
2. PCI inputs with LVDD = 5 V ± 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5 V DC.
6
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8241.
Table 2. Recommended Operating Conditions 1
Recommended
Value
Characteristic
Symbol
Unit
Notes
Supply voltage
VDD
1.8 ± 100 mV
3.3 ± 0.3
V
V
2
2
I/O buffer supply for PCI and standard; supply voltages
for memory bus drivers
GVDD_OVDD
CPU PLL supply voltage
PLL supply voltage—peripheral logic
PCI reference
AVDD
1.8 ± 100 mV
1.8 ± 100 mV
5.0 ± 5%
2
2
AVDD
2
V
V
LVDD
4, 5, 6
5, 6, 7
4, 7
8
3.3 ± 0.3
V
Input voltage
PCI inputs
Vin
0 to 3.6 or 5.75
0 to 3.6
V
All other inputs
V
Die-junction temperature
Tj
0 to 105
°C
Notes:
1. Motorola has tested these operating conditions and recommends them. Proper device operation outside of these
conditions is not guaranteed.
2. Caution: GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on
reset. Note that GVDD_OVDD pins are all shorted together: This limit may be exceeded for a maximum of 20 ms
during power-on reset and power-down sequences. Connections should not be made to individual PWRRING pins.
3. Caution: VDD/AVDD/AVDD2 must not exceed GVDD_OVDD by more than 0.6 V at any time, including during
power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
4. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0 V DC power supply.
5. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on reset.
This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
6. Caution: LVDD must not exceed GVDD_OVDD by more than 3.0 V at any time, including during power-on reset. This
limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
7. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3 V DC power supply.
8. Caution: Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at
all times including during power-on reset. Input voltage (Vin) must not be greater than GVDD_OVDD by more than
0.6 V at all times including during power-on reset.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
7
Electrical and Thermal Characteristics
Figure 2 shows supply voltage sequencing and separation cautions.
LVDD @ 5 V
5 V
See Note 1
6
5
3.3 V
2 V
6
GVDD_OVDD/(LVDD @ 3.3 V - - - -)
5
2
3
VDD/AVDD/AVDD
2
100 µs
PLL
VDD Stable
Relock
Time 3
0
HRST_CPU and
Time
6
HRST_CTRL
Asserted 255
PLL
External Memory
Power Supply Ramp Up 2
Reset
Clock Cycles 3
Configuration Pins
9 External Memory
Clock Cycles Setup Time 4
HRST_CPU and
HRST_CTRL
Maximum Rise Time Must be Less Than
One External Memory Clock Cycle 5
VM = 1.4 V
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. See Cautions section of Table 2 for additional information about this topic.
3. Refer to Table 8 for additional information on PLL relock and reset signal assertion timing requirements.
4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements.
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN.
clock cycle for the device to be in the nonreset state.
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation
of HRST_CTRL and HRST_CPU negate in order to be latched.
Figure 2. Supply Voltage Sequencing and Separation Cautions
8
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 shows the undershoot and overshoot voltage of the MPC8241memory interface.
4 V
GVDD_OVDD + 5%
GVDD_OVDD
VIH
GND/GNDRING
GND/GNDRING – 0.3 V
VIL
GND/GNDRING – 1.0 V
Not to Exceed 10%
of tSDRAM_CLK
Figure 3. Overshoot/Undershoot Voltage
Figure 4 and Figure 5 show the undershoot and overshoot voltage of the MPC8241 PCI interface for 3.3-
and 5-V signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 4. Maximum AC Waveforms for 3.3-V Signaling
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
9
Electrical and Thermal Characteristics
11 ns
(Min)
+11 V
0 V
Overvoltage
Waveform
11 V p-to-p
(Min)
4 ns
(Max)
4 ns
(Max)
62.5 ns
+5.25 V
Undervoltage
Waveform
10.75 V p-to-p
(Min)
–5.5 V
Figure 5. Maximum AC Waveforms for 5-V Signaling
4.1.3 DC Electrical Characteristics
Table 3 provides the DC electrical characteristics for the MPC8241 at recommended operating conditions.
Table 3. DC Electrical Specifications
Characteristics
Conditions
Symbol
Min
Max
Unit Notes
Input high voltage
PCI only, except
PCI_SYNC_IN
VIH
0.65 ×
LVDD
V
V
V
1
GVDD_OVDD
Input low voltage
Input high voltage
PCI only, except
PCI_SYNC_IN
VIL
VIH
—
0.3 × GVDD_OVDD
All other pins, including
PCI_SYNC_IN
2.0
3.3
(GVDD_OVDD = 3.3 V)
Input low voltage
All inputs, including
PCI_SYNC_IN
VIL
GND/GNDRING
—
0.8
V
2
3
Input leakage current
for pins using DRV_PCI @ LVDD = 4.75 V
driver
0.5 V ≤ Vin ≤ 2.7 V
IL
±70
µA
Input leakage currentall LVDD = 3.6 V
IL
—
2.4
—
±10
—
µA
V
3
4
4
others
GVDD_OVDD ≤ 3.465 V
Output high voltage
I
OH = driver dependent
VOH
(GVDD_OVDD = 3.3 V)
Output low voltage
IOL = driver dependent
(GVDD_OVDD = 3.3 V)
VOL
0.4
V
10
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Table 3. DC Electrical Specifications (continued)
Characteristics
Conditions
Symbol
Min
Max
Unit Notes
Capacitance
Notes:
Vin = 0 V, f = 1 MHz
Cin
—
16.0
pF
1. See Table 17 for pins with internal pull-up resistors.
2. All grounded pins are connected together.
3. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is
measured for nominal GVDD_OVDD/LVDD and VDD or both GVDD_OVDD/LVDD and VDD must vary in the same
direction.
4. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with
that pin as listed in Table 17.
4.1.4 Output Driver Characteristics
Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values
are preliminary estimates from an IBIS model and are not tested.
Table 4. Drive Capability of MPC8241 Output Pins 5, 6
ProgrammableOutput
Driver Type
Impedance
Supply Voltage
IOH
IOL
Unit
Notes
(Ω)
DRV_STD_MEM
20 (default)
GVDD_OVDD = 3.3 V
36.6
18.6
12.0
6.1
18.0
9.2
mA
mA
mA
mA
mA
mA
mA
2, 4
2, 4
1, 3
1, 3
2, 4
2, 4
2, 4
40
20
DRV_PCI
12.4
6.3
40 (default)
6 (default)
20
DRV_MEM_CTRL
DRV_PCI_CLK
DRV_MEM_CLK
89.0
36.6
18.6
42.3
18.0
9.2
40
Notes:
1. For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolating
between the 0.3- and 0.4-V table entries current values which corresponds to the PCI VOH = 2.97 = 0.9 ×
GVDD_OVDD (GVDD_OVDD = 3.3 V) where table entry voltage = GVDD_OVDD – PCI VOH
.
2. For all others with GVDD_ OVDD = 3.3 V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the
0.9-V table entry which corresponds to the VOH = 2.4 V where table entry voltage = GVDD_OVDD – VOH
.
3. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V = PCI VOL = 0.1 ×
GVDD_OVDD (GVDD_OVDD = 3.3 V) by interpolating between the 0.3- and 0.4-V table entries.
4. For all others with GVDD_OVDD = 3.3 V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the
0.4-V table entry.
5. See driver bit details for output driver control register (0x73) in the MPC8245 Integrated Processor User’s Manual.
6. See Chip Errata No. 19 in the MPC8245/MPC8241 Integrated Processor Chip Errata.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
11
Electrical and Thermal Characteristics
4.1.5 Power Characteristics
Table 5 provides preliminary estimated power consumption data for the MPC8241.
Table 5. Preliminary Power Consumption
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Mode
Unit
Notes
33/66/
133
33/66/
166
33/66/
200
33/100/ 66/100/
66/66/
266
66/133/
266
200
200
Typical
Max—CFP
Max—INT
Doze
0.7
0.8
0.8
0.5
0.2
0.2
0.8
1.0
0.9
0.6
0.2
0.2
1.0
1.2
1.0
0.7
0.3
0.2
1.0
1.3
1.2
0.8
0.4
0.2
1.0
1.3
1.2
0.8
0.4
0.3
1.5
1.9
1.6
1.0
0.4
0.2
1.8
2.1
1.8
1.3
0.7
0.4
W
W
W
W
W
W
1, 5
1, 2
1, 3
1, 4, 6
1, 4, 6
1, 4, 6
Nap
Sleep
I/O Power Supplies 7
Minimum
500
Mode
Maximum
Unit
Notes
GVDD_OVDD
1130
mW
8
Notes:
1. The values include VDD, AVDD, and AVDD2 but do not include I/O supply power.
2. Maximum—FP power is measured at VDD = 1.9 V with dynamic power management enabled while running an
entirely cache-resident, looping, floating-point multiplication instruction.
3. Maximum—INT power is measured at VDD = 1.9 V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at VDD = 1.9 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at VDD = AVDD = 1.8 V, GVDD_OVDD = 3.3 V where a nominal FP value, a nominal INT
value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit
boundaries to local memory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW, guaranteed by design, but not tested.
8. The typical maximum GVDD_OVDD value resulted from the MPC8241 operating at the fastest frequency
combination of 66:133:266 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating
ones and zeros to PCI memory and on 64-bit boundaries to local memory.
12
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
4.2 Thermal Characteristics
Table 6 provides the package thermal characteristics for the MPC8241. To obtain more information, see
Section 7.7, “Thermal Management Information.”
Table 6. Thermal Characterization Data
Value 7
Value 7
Thermal Test Board
Description
(166- and
200-MHz
Parts)
Rating
Symbol
(266-MHz
Part)
Unit
Notes
Junction-to-ambient
natural convection
Single-layer board (1s)
Four-layer board (2s2p)
Single-layer board (1s)
Four-layer board (2s2p)
Four-layer board (2s2p)
Single-layer board (1s)
RθJA
RθJMA
RθJMA
RθJMA
RθJB
38
25
31
22
17
28
20
22
17
11
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
Junction-to-ambient
natural convection
Junction-to-ambient
(@200 ft/min)
Junction-to-ambient
(@200 ft/min)
Junction-to-board
(bottom)
Junction-to-case (top)
RθJC
8
2
7
2
°C/W
°C/W
5
6
Junction-to-package top Natural convection
ΨJT
Notes:
1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and EIA/JESD51-2 with the board horizontal.
3. Per EIA/JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per EIA/JESD51-2.
7. Note that the 166- and 200-MHz parts are in a two-layer package and the 266-MHz part is in a four-layer package,
which causes the two package types to have different thermal characterization data.
4.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC8241. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Table 7 and tested for conformance to the AC
specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN)
clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency. See Section 9, “Ordering Information.”
Table 7 provides the operating frequency information for the MPC8241 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V.
DD
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13
Electrical and Thermal Characteristics
Table 7. Operating Frequency
166 MHz
200 MHz
266 MHz
Characteristic
VDD/AVDD/AVDD2 = 1.8 ± 100 mV
Unit
Min
Max
Min
Max
Min
Max
Processor frequency
(CPU)
100
166
100
200
100
266
MHz
Memory bus frequency
PCI input frequency
33
83
33
100
33
133
MHz
MHz
25–66
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configuration,” for valid
PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
4.3.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in
Section 4.3.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths
indicated in Table 4. Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled
number items listed in Table 8.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V
DD
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1
Frequency of operation (PCI_SYNC_IN)
25
—
40
6
66
2.0
60
MHz
ns
%
2, 3 PCI_SYNC_IN rise and fall times
1
4
PCI_SYNC_IN duty cycle measured at 1.4 V
PCI_SYNC_IN pulse width high measured at 1.4 V
PCI_SYNC_IN pulse width low measured at 1.4 V
PCI_SYNC_IN jitter
5a
5b
7
9
ns
ns
ps
ps
ps
µs
ns
2
2
6
9
—
—
—
—
200
250
190
100
8a
8b
10
15
PCI_CLK[0:4] skew (pin-to-pin)
SDRAM_CLK[0:3] skew (pin-to-pin)
Internal PLL relock time
3
2, 4, 5
6
DLL lock range with DLL_EXTEND = 0 (disabled)
and normal tap delay; (default DLL mode)
See Figure 7
16
17
19
20
DLL lock range for other modes
Frequency of operation (OSC_IN)
OSC_IN rise and fall times
See Figure 8 through Figure 10
ns
MHz
ns
6
7
25
—
40
66
5
OSC_IN duty cycle measured at 1.4 V
60
%
14
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MOTOROLA
Electrical and Thermal Characteristics
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V
DD
Num
Characteristics and Conditions
OSC_IN frequency stability
Min
Max
Unit
Notes
21
—
100
ppm
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 through 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). Tclk is
the period of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length
(unloaded PC board runner) corresponds to approximately 1 ns of delay. For details about how Figure 7 through
Figure 10 may be used, refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory Clock Design
Guidelines for details about memory clock design on the MPC8245.
7. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and fall
times are not tested.
Figure 6 shows the PCI_SYNC_IN input clock timing diagram, and Figures 7 through 10 show the DLL
locking range loop delay versus frequency of operation.
1
5a
5b
2
3
CVIH
VM
VM
VM
PCI_SYNC_IN
CVIL
VM = Midpoint Voltage (1.4 V)
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Register settings that define each DLL mode are shown in Table 9.
Table 9. DLL Mode Definition
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
DLL Mode
Register at 0x72
Normal tap delay,
No DLL extend
0
0
0
Normal tap delay,
DLL extend
1
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Electrical and Thermal Characteristics
Table 9. DLL Mode Definition (continued)
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
Register at 0x72
DLL Mode
Max tap delay,
1
1
0
1
No DLL extend
Max tap delay,
DLL extend
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points. Refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory
Clock Design Guidelines, for details about memory design.
16
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MOTOROLA
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=0
and Normal Tap Delay
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17
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=1
and Normal Tap Delay
18
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=0
and Max Tap Delay
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19
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=1
and Max Tap Delay
4.3.2 Input AC Timing Specifications
Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2)
with LV = 3.3 V ± 0.3 V. See Figure 11 and Figure 12.
DD
20
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MOTOROLA
Electrical and Thermal Characteristics
Table 10. Input AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
10a PCI input signals valid to PCI_SYNC_IN (input setup)
10b Memory input signals valid to sys_logic_clk (input setup)
10b0 Tap 0, register offset <0x77>, bits 5:4 = 0b00
10b1 Tap 1, register offset <0x77>, bits 5:4 = 0b01
10b2 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
10b3 Tap 3, register offset <0x77>, bits 5:4 = 0b11
3.0
—
ns
1, 3
2.6
1.9
1.2
0.5
3.0
—
—
—
—
—
ns
2, 3, 6
10c
PIC miscellaneous debug input signals valid to sys_logic_clk
ns
2, 3
(input setup)
10d I2C input signals valid to sys_logic_clk (input setup)
3.0
—
—
ns
ns
2, 3
10e Mode select inputs valid to HRST_CPU/HRST_CTRL (input
setup)
9 × tCLK
2, 3–5
11
Tos—SDRAM_SYNC_IN to sys_logic_clk offset time
sys_logic_clk to memory signal inputs invalid (input hold)
0.4
1.0
ns
ns
7
11a
11a0 Tap 0, register offset <0x77>, bits 5:4 = 0b00
11a1 Tap 1, register offset <0x77>, bits 5:4 = 0b01
11a2 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
11a3 Tap 3, register offset <0x77>, bits 5:4 = 0b11
0
—
—
—
—
—
2, 3, 6
0.7
1.4
2.1
0
11b
HRST_CPU/HRST_CTRL to mode select inputs invalid (input
hold)
ns
2, 3, 5
MOTOROLA
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21
Electrical and Thermal Characteristics
Table 10. Input AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
11c
PCI_SYNC_IN to inputs invalid (input hold)
1.0
—
ns
1, 2, 3
Notes:
1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × GVDD_OVDD of the
signal in question for 3.3-V PCI signaling levels. See Figure 12.
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the
signal in question to the VM = 1.4 V of the rising edge of the memory bus clock. sys_logic_clk. sys_logic_clk is the
same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. Input timings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question
to the VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming
bits 5:4 of register offset <0x77> to select the desired input setup and hold times.
7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay
present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM
clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN must be shortened to accommodate this range relative to the SDRAM clock output trace lengths
to maintain phase-alignment of the memory clocks with respect to sys_logic_clk. It is recommended that the length
of SDRAM_SYNC_OUT to SDRAM_SYNC_IN be shortened by 0.7 ns. This is because that is the midpoint of the
range of Tos and allows the impact from the range of Tos to be reduced. Additional analyses taking into account trace
lengths and SDRAM loading will need to be performed to optimize timing. For more details on trace measurements
and accommodating for the Tos problem, refer to the Motorola application note AN2164, MPC8245/MPC8241
Memory Clock Design Guidelines.
22
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MOTOROLA
Electrical and Thermal Characteristics
VM
VM
PCI_SYNC_IN
VM
sys_logic_clk
VM
T
os
SDRAM_SYNC_IN
(after DLL locks)
VM
Shown in 2:1 Mode
10b-d
13b
11a
12b-d
14b
2.0 V
2.0 V
Memory
Inputs/Outputs
0.8 V
0.8 V
Output Timing
Input Timing
Notes:
VM = Midpoint voltage (1.4 V).
10b-d = Input signals valid timing.
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = sys_logic_clk to output valid timing.
13b = Output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
Tos = Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to be seen
before sys_logic_clk once the DLL locks.
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
PCI_SYNC_IN
GVDD_OVDD
2
GVDD_OVDD
2
GVDD_OVDD
2
10a
13a
14a
12a
11c
GVDD_OVDD
0.615
x
PCI
Inputs/Outputs
0.4 x
GVDD_OVDD
0.285
Input Timing
Output Timing
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
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Electrical and Thermal Characteristics
VM
HRST_CPU/HRST_CTRL
10e
11b
2.0 V
0.8 V
Mode Pins
VM = Midpoint Voltage (1.4 V)
Figure 13. Input Timing Diagram for Mode Select Signals
4.3.3 Output AC Timing Specification
Table 11 provides the processor bus AC timing specifications for the MPC8241 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V (see Figure 11). All output timings assume a purely
DD
resistive 50-Ω load (see Figure 14). Output timings are measured at the pin; time-of-flight delays must be
added for trace lengths, vias, and connectors in the system. These specifications are for the default driver
strengths that Table 4 indicates.
Table 11. Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
12a PCI_SYNC_IN to output valid, see Figure 15
12a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (default)
12a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10
—
—
—
—
—
6.0
6.5
7.0
7.5
4.5
ns
1, 3
12a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI
12a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00
12b sys_logic_clk to output valid (memory address, control, and data
ns
2
signals)
12c
sys_logic_clk to output valid (for all others)
—
—
—
7.0
5.0
6.0
ns
ns
ns
2
2
2
12d sys_logic_clk to output valid (for I2C)
12e sys_logic_clk to output valid (ROM/Flash/Port X)
13a Output hold (PCI), see Figure 15
13a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (default)
13a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10
13a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI
13a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00
13b Output hold (all others)
2.0
2.5
3.0
3.5
1.0
—
—
—
ns
1, 3, 4
—
—
—
ns
ns
2
14a PCI_SYNC_IN to output high impedance (for PCI)
14.0
1, 3
24
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Table 11. Output AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
14b sys_logic_clk to output high impedance (for all others)
Notes:
—
4.0
ns
2
1. All PCI signals are measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × GVDD_OVDD or
0.615 × GVDD_OVDD of the signal in question for 3.3 V PCI signaling levels. See Figure 12.
2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of
the memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the
same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP,
DEVSEL, PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.
4. To meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the
MPC8241 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also
affected). The initial value of the output hold delay is determined by the values on the MCP and CKE reset
configuration signals; the values on these two signals are inverted and subsequently stored as the initial settings of
PCI_HOLD_DEL = PMCR2[5, 4] (power management configuration register 2 <0x72>), respectively. Because MCP
and CKE have internal pull-up resistors, the default value of PCI_HOLD_DEL after reset is 0b00. Additional output
hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register.
See Figure 15 for PCI_HOLD_DEL effect on output valid and hold time.
Output Measurements are Made at the Device Pin
GVDD_OVDD/2 for
Z0 = 50 Ω
Output
PCI or Memory
RL = 50 Ω
Figure 14. AC Test Load for the MPC8241
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
OVDD/2
OVDD/2
PCI_SYNC_IN
12a2, 7.0 ns for 33 MHz PCI
PCI_HOLD_DEL = 10
13a2, 2.1 ns for 33 MHz PCI
PCI_HOLD_DEL = 10
PCI Inputs/Outputs
33 MHz PCI
12a0, 6.0 ns for 66 MHz PCI
PCI_HOLD_DEL = 00
13a0, 1 ns for 66 MHz PCI
PCI_HOLD_DEL = 00
PCI Inputs/Outputs
66 MHz PCI
As PCI_HOLD_DEL
Values Decrease
PCI Inputs
and Outputs
As PCI_HOLD_DEL
Values Increase
Output Valid
Output Hold
Note: Diagram not to scale.
Figure 15. PCI_HOLD_DEL Effect on Output Valid and Hold Time
26
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
2
4.3.4 I C AC Timing Specifications
2
Table 12 provides the I C input AC timing specifications for the MPC8241 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V.
DD
Table 12. I2C Input AC Timing Specifications
Num
Characteristic
Start condition hold time
Min
Max
Unit
Notes
1
2
4.0
—
—
CLKs
CLKs
1, 2
Clock low period
(time before the MPC8241 will drive SCL
8.0 + (16 × 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
1, 2, 4, 5
low as a transmitting slave after detecting 3({FDR[5],FDR[1]} == b’11) –
SCL low as driven by an external master) 2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
3
4
5
6
SCL/SDA rise time (from 0.5 to 2.4 V)
Data hold time
—
0
1
—
1
ms
ns
2
SCL/SDA fall time (from 2.4 to 0.5 V)
—
5.0
ms
Clock high period (time needed to either
receive a data bit or generate a START or
STOP)
—
CLKs
1, 2, 5
7
8
Data setup time
3.0
4.0
—
—
ns
3
Start condition setup time (for repeated
start condition only)
CLKs
1,2
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in this table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA signals
are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 17.
3. Timing is relative to the sampling clock (not SCL).
4. FDR[x] refers to the frequency divider register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)
determine the maximum I2C input frequency. See Table 13.
MOTOROLA
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27
Electrical and Thermal Characteristics
2
Table 13 provides the I C frequency divider register (I2CFDR) information for the MPC8241.
Table 13. MPC8241 Maximum I2C Input Frequency
Max I2C Input Frequency 1
FDR
Divider 2
(Dec)
Hex 2
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK SDRAM_CLK 4
@ 100 MHz
@ 133 MHz
20, 21
22, 23, 24, 25
0, 1
160, 192
224, 256, 320, 384
288, 320
1.13 MHz
733
1.72 MHz
1.11 MHz
819
3.44 MHz
2.22 MHz
1.63 MHz
1.29 MHz
4.58 MHz
2.95 MHz
2.18 MHz
1.72 MHz
540
2, 3, 26, 27, 28, 384, 448, 480, 512, 640,
428
649
29
768
4, 5
576, 640
302
234
458
354
917
709
1.22 MHz
943
6, 7, 2A, 2B, 2C,
2D
768, 896, 960, 1024,
1280, 1536
8, 9
1152, 1280
160
122
243
185
487
371
648
494
A, B, 2E,
2F, 30, 31
1536, 1792, 1920,
2048, 2560, 3072
C, D
2304, 2560
83
62
125
95
251
190
335
253
E, F, 32,
33, 34, 35
3072, 3584, 3840,
4096, 5120, 6144
10, 11
4608, 5120
42
31
64
48
128
96
170
128
12, 13, 36,
37, 38, 39
6144, 7168, 7680,
8192, 10240, 12288
14, 15
9216, 10240
21
16
32
24
64
48
85
64
16, 17, 3A,
3B, 3C, 3D
12288, 14336, 15360,
16384, 20480, 24576
18, 19
18432, 20480
10
8
16
12
32
24
43
32
1A, 1B,
3E, 3F
24576, 28672,
30720, 32768
1C, 1D
1E, 1F
36864, 40960
49152, 61440
5
4
8
6
16
12
21
16
Notes:
1. Values are in kHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values generate the same input frequency, but each Divider (Dec) value generates a unique
output frequency (see Table 14).
4. Available for the 266-MHz part only
28
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
Electrical and Thermal Characteristics
2
Table 14 provides the I C output AC timing specifications for the MPC8241 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V.
DD
Table 14. I2C Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) × (DFDR/16)/2N + (FDR[5]
== 1) × (DFDR/16)/2M
—
CLKs
1–3
2
3
Clock low period
DFDR/2
—
—
—
CLKs
ms
1–3
4
SCL/SDA rise time (from 0.5
to 2.4 V)
4
Data hold time
8.0 + (16 × 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1–3
5
6
7
SCL/SDA fall time (from 2.4 to 0.5 V)
Clock high time
—
DFDR/2
< 5
—
ns
5
CLKs
CLKs
1–3
1, 3
Data setup time (MPC8241 as a
master only)
(DFDR/2) – (output data hold time)
—
8
Start condition setup time (for
repeated start condition only)
DFDR + (output start condition hold time)
4.0
—
—
CLKs
CLKs
1–3
1, 2
9
Stop condition setup time
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The
qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times two plus one SDRAM_CLK clock. The resulting
delay value is added to the value in the table (where this note is referenced). See Figure 17.
3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the MPC8245 Integrated
Processor User’s Manual. FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable
number that would make the result of the divide (data hold time value) equal to a number less than 16. M is equal
to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9.
4. Because SCL and SDA are open-drain type outputs, which the MPC8241 can only drive low, the time required for
SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
5. Specified at a nominal 50 pF load
2
VM
VM
SCL
SDA
6
4
1
Figure 16. I2C Timing Diagram I
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
29
Electrical and Thermal Characteristics
3
5
VH
VL
VM
SCL
8
9
SDA
Figure 17. I2C Timing Diagram II
DFFSR Filter Clock
SDA
7
Input Data Valid
Note: DFFSR filter clock is the SDRAM_CLK clock times DFFSR value.
Figure 18. I2C Timing Diagram III
.
VM
SCL/SDArealtime
Delay
SCL/SDAqualified
VM
Note: The delay is the local memory clock times DFFSR times two plus one local memory clock.
Figure 19. I2C Timing Diagram IV (Qualified Signal)
30
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
4.3.5 PIC Serial Interrupt Mode AC Timing Specifications
Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC8241 at recommended
operating conditions (see Table 2) with GV _OV = 3.3 V ± 5% and LV = 3.3 V ± 0.3 V.
DD
DD
DD
Table 15. PIC Serial Interrupt Mode AC Timing Specifications
Num
Characteristic
S_CLK frequency
Min
Max
Unit
Notes
1
2
3
4
5
6
7
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
%
1
—
—
—
2
S_CLK duty cycle
40
60
S_CLK output valid time
Output hold time
—
6
ns
0
—
ns
S_FRAME, S_RST output valid time
S_INT input setup time to S_CLK
—
1 sys_logic_clk period + 6
ns
1 sys_logic_clk period + 2
—
0
ns
2
S_INT inputs invalid (hold time) to
S_CLK
—
ns
2
Notes:
1. See the MPC8245 Integrated Processor User’s Manual for a description of the PIC interrupt control register (ICR)
describing S_CLK frequency programming.
2. S_RST, S_FRAME, and S_INT shown in Figure 20 and Figure 21, depict timing relationships to sys_logic_clk and
S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the MPC8245
Integrated Processor User’s Manual for a complete description of the functional relationships between these
signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral
logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN
feedback loop is implemented and the DLL is locked. See the MPC8245 Integrated Processor User’s Manual for a
complete clocking description.
VM
VM
VM
sys_logic_clk
3
4
VM
S_CLK
VM
5
4
S_FRAME
S_RST
VM
VM
Figure 20. PIC Serial Interrupt Mode Output Timing Diagram
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MPC8241 Integrated Processor Hardware Specifications
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31
Electrical and Thermal Characteristics
VM
S_CLK
S_INT
7
6
Figure 21. PIC Serial Interrupt Mode Input Timing Diagram
4.3.6 IEEE 1149.1 (JTAG) AC Timing Specifications
Table 16 provides the JTAG AC timing specifications for the MPC8241 while in the JTAG operating mode
at recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V. Timings are independent of
DD
the system clock (PCI_SYNC_IN).
Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
Num
Characteristic
TCK frequency of operation
Min
Max
Unit
Notes
0
40
20
0
25
—
—
3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
TCK cycle time
2
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
3
4
TRST setup time to TCK falling edge
TRST assert time
10
10
5
—
—
—
—
30
30
—
—
15
15
1
5
6
7
Input data setup time
2
2
3
3
Input data hold time
15
0
8
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK to TDO data valid
9
0
10
5
11
15
0
12
13
TCK to TDO high impedance
0
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest (other than TDO) signal output timing with respect to TCK.
32
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
1
2
2
VM
VM
VM
TCK
3
3
VM = Midpoint Voltage
Figure 22. JTAG Clock Input Timing Diagram
TCK
4
TRST
5
Figure 23. JTAG TRST Timing Diagram
TCK
6
7
Data Inputs
Data Outputs
Data Outputs
Input Data Valid
8
9
Output Data Valid
Figure 24. JTAG Boundary Scan Timing Diagram
TCK
10
11
TDI, TMS
Input Data Valid
12
13
TDO
TDO
Output Data Valid
Figure 25. Test Access Port Timing Diagram
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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33
Package Description
5 Package Description
This section details package parameters, pin assignments, and dimensions.
5.1 Package Parameters for the MPC8241
The MPC8241 uses a 25 mm × 25 mm, cavity up, 357-pin plastic ball grid array (PBGA) package. The
package parameters are as follows.
Package outline
Interconnects
Pitch
25 mm × 25 mm
357
1.27 mm
Solder balls
ZP (PBGA)—62 Sn/36 Pb/2 Ag - available only in Rev B parts
ZQ (Thick subtrate PBGA)—62 Sn/36 Pb/2 Ag
VR (Lead free version of package)—95.5 Sn/4.0 Ag/0.5 Cu
0.75 mm
Solder ball diameter
Maximum module height 2.52 mm
Co-planarity specification 0.15 mm
Maximum force
6.0 lbs. total, uniformly distributed over package (8 grams/ball)
34
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
5.2 Pin Assignments and Package Dimensions
Figure 26 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZP package. Note
that this is available for Rev B parts only.
0.2
A
4X
D
C
0.20 C
0.25 C
0.35 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
E2
E
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER
BALL DIAMETER MEASURED PARALLEL TO
DATUM C.
MILLIMETERS
DIM MIN
---
A1 0.50
A2 0.95
A3 0.70
MAX
2.05
0.70
1.35
0.90
0.90
A
D2
B
TOP VIEW
b
D
D1
0.60
25.00 BSC
22.86 BSC
D2 22.40 22.60
D1
e
E
1.27 BSC
25.00 BSC
22.86 BSC
18X e
E1
E2 22.40 22.60
W
V
U
T
A2
A3
A1
R
P
N
M
L
A
K
J
E1
H
G
F
SIDE VIEW
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
2
4 6 8 10 12 14 16 18
357X
b
M
M
0.30
0.15
C A B
C
BOTTOM VIEW
Figure 26. MPC8241 Package Dimensions and Pinout Assignments
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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35
Package Description
Figure 27 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZQ and VR packages.
Figure 27. MPC8241 Package Dimensions and Pinout Assignments (ZQ and VR packages)
36
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
5.3 Pinout Listings
Table 17 provides the pinout listing for the MPC8241, 357 PBGA package.
Table 17. MPC8241 Pinout Listing
Power
Supply
Output
Driver Type
Signal Name
Package Pin Number
Pin Type
Notes
PCI Interface Signals
C/BE[3:0]
DEVSEL
FRAME
IRDY
V11 V7 W3 R3
I/O
I/O
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
1, 2
2, 3
2, 3
2, 3
3
U6
T8
U7
V6
I/O
I/O
LOCK
Input
I/O
AD[31:0]
U13 V13 U11 W14 V14 U12
W10 T10 V10 U9 V9 W9 W8
T9 W7 V8 V4 W4 V3 V2 T5
R6 V1 T2 U3 P3 T4 R1 T3 R4
U2 U1
DRV_PCI
1, 2
PAR
GNT[3:0]
GNT4/DA5
REQ[3:0]
REQ4/DA4
PERR
R7
I/O
Output
Output
Input
I/O
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_PCI
DRV_PCI
DRV_PCI
—
2
W15 U15 W17 V12
1, 2
T11
2, 4, 5
1, 6
V16 U14 T15 V15
W13
T7
—
5, 6
I/O
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
2, 3, 7
2, 3, 8
2, 3
SERR
U5
I/O
STOP
W5
W6
T12
U10
I/O
TRDY
I/O
2, 3
INTA
Output
Input
2, 8
IDSEL
Memory Interface Signals
MDL[0:31]
MDH[0:31]
DQM[0:7]
M19 M17 L16 L17 K18 J18
I/O
GVDD_OVDD
DRV_STD_MEM
DRV_STD_MEM
1, 9
K17 K16 J15 J17 H18 F16
H16 H15 G17 D19 B3 C4 C2
D3 G5 E1 H5 E2 F1 F2 G2 J5
H1 H4 J4 J1
M18 L18 L15 K19 K15 J19
J16 H17 G19 G18 G16 D18
F18 E18 G15 E15 C3 D4 E5
F5 D1 E4 D2 E3 F4 G3 G4
G1 H2 J3 J2 K5
I/O
GVDD_OVDD
1
A18 B18 A6 C7 D15 D14 A9
B8
Output
GVDD_OVDD DRV_MEM_CTRL
1
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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37
Package Description
Table 17. MPC8241 Pinout Listing (continued)
Power
Output
Driver Type
Signal Name
Package Pin Number
Pin Type
Notes
Supply
CS[0:7]
A17 B17 C16 C17 C9 C8 A10
B10
Output
GVDD_OVDD DRV_MEM_CTRL
1
FOE
RCS0
A7
I/O
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
10, 11
10, 11
C10
B9
Output
Output
I/O
RCS1
RCS2/TRIG_IN
RCS3/TRIG_OUT
SDMA[1:0]
SDMA[11:2]
P18
GVDD_OVDD
GVDD_OVDD
—
5, 12
N18
A15 B15
Output
I/O
DRV_STD_MEM
5
1, 10, 11
1
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
A11 B12 A12 C12 B13 C13
D12 A14 C14 B14
Output
DRDY
P1
Input
I/O
GVDD_OVDD
—
12, 13
5, 12
5, 12
5, 12
SDMA12/SRESET L3
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
SDMA13/TBEN
K3
K2
I/O
SDMA14/
I/O
CHKSTOP_IN
SDBA1
SDBA0
PAR[0:7]
C11
B11
Output
Output
I/O
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
E19 C19 D5 D6 E16 F17 B2
C1
GVDD_OVDD
DRV_STD_MEM
1
SDRAS
SDCAS
CKE
B19
D16
C6
Output
Output
Output
Output
Output
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
10
10
10, 11
WE
B16
A16
AS
10, 11
PIC Control Signals
IRQ0/S_INT
IRQ1/S_CLK
IRQ2/S_RST
IRQ3/S_FRAME
IRQ4/L_INT
P4
Input
I/O
GVDD_OVDD
—
R2
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
U19
P15
P2
I/O
I/O
I/O
38
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
Package Description
Table 17. MPC8241 Pinout Listing (continued)
Power
Output
Driver Type
Signal Name
Package Pin Number
Pin Type
Notes
Supply
I2C Control Signals
SDA
SCL
P17
R19
I/O
I/O
GVDD_OVDD
GVDD_OVDD
DRV_STD_MEM
DRV_STD_MEM
8, 12
8, 12
DUART Control Signals
SOUT1/PCI_CLK0 T16
Output
I/O
GVDD_OVDD
DRV_PCI_CLK
DRV_PCI_CLK
DRV_PCI_CLK
5, 14
5, 14
5, 14
SIN1/PCI_CLK1
U16
GVDD_OVDD
GVDD_OVDD
SOUT2/RTS1/
PCI_CLK2
W18
Output
SIN2/CTS1/
PCI_CLK3
V19
I/O
GVDD_OVDD
DRV_PCI_CLK
5, 14
Clock-Out Signals
PCI_CLK0/SOUT1 T16
Output
I/O
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_PCI_CLK
DRV_PCI_CLK
DRV_PCI_CLK
5, 14
5, 14, 24
5, 14
PCI_CLK1/SIN1
U16
PCI_CLK2/RTS1/
SOUT2
W18
Output
PCI_CLK3/CTS1/
SIN2
V19
I/O
GVDD_OVDD
DRV_PCI_CLK
5, 14, 24
5, 14
PCI_CLK4/DA3
PCI_SYNC_OUT
PCI_SYNC_IN
V17
Output
Output
Input
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_PCI_CLK
DRV_PCI_CLK
—
U17
V18
SDRAM_CLK[0:3]
D7 B7 C5 A5
Output
Output
Input
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
1, 22
SDRAM_SYNC_OUT B4
SDRAM_SYNC_IN A4
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
—
DRV_STD_MEM
—
CKO/DA1
OSC_IN
L1
Output
Input
5
R17
15
Miscellaneous Signals
HRST_CTRL
HRST_CPU
MCP
M2
L4
Input
Input
Output
Input
Input
I/O
GVDD_OVDD
—
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
—
K4
M1
L2
DRV_STD_MEM
10, 11, 16
NMI
—
—
SMI
12
5, 12
SRESET/SDMA12 L3
GVDD_OVDD DRV_MEM_CTRL
GVDD_OVDD DRV_MEM_CTRL
TBEN/SDMA13
QACK/DA0
K3
A3
I/O
5, 12
Output
GVDD_OVDD
DRV_STD_MEM
5, 11, 12
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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39
Package Description
Signal Name
Table 17. MPC8241 Pinout Listing (continued)
Power
Output
Driver Type
Package Pin Number
Pin Type
Notes
Supply
CHKSTOP_IN/
SDMA14
K2
I/O
GVDD_OVDD DRV_MEM_CTRL
5, 12
TRIG_IN/RCS2
TRIG_OUT/RCS3
MAA[0:2]
P18
I/O
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
—
5, 12
5, 12
N18
Output
Output
Output
Output
Output
DRV_STD_MEM
DRV_STD_MEM
DRV_STD_MEM
E17 D17 C18
K1
1, 10, 11
23
MIV
PMAA[0:1]
PMAA[2]
N19 N17
M15
DRV_STD_MEM 1, 2, 10, 11
DRV_STD_MEM
—
1, 2, 11
1, 5, 20
Test/Configuration Signals
PLL_CFG[0:4]/
DA[10:6]
N3 N2 N1 M4 M3
I/O
GVDD_OVDD
TEST0
RTC
TCK
P16
D13
T19
N15
T17
T18
R16
Input
Input
Input
Input
Output
Input
Input
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
—
13, 21
12
—
—
6, 13
6, 13
23
TDI
—
DRV_PCI
—
TDO
TMS
TRST
6, 13
6, 13
—
Power and Ground Signals
Ground
GNDRING/GND
F07 F08 F09 F10 F11 F12
F13 G07 G08 G09 G10 G11
G12 G13 H07 H08 H09 H10
H11 H12 H13 J07 J08 J09
J10 J11 J12 J13 K07 K08
K09 K10 K11 K12 K13 L07
L08 L09 L10 L11 L12 L13
M07 M08 M09 M10 M11 M12
M13 N07 N08 N09 N10 N11
N12 N13 P08 P09 P10 P11
P12 P13 R15
—
17
LVDD
R18 U18 T1 U4 T6 W11 T14 Reference
LVDD
—
—
voltage
3.3 V,
5.0 V
GVDD_OVDD
PWRRING
/
D09 D10 D11 E06 E07 E08
E09 E10 E11 E12 E13 E14
Power for GVDD_OVDD
memory
18
F06 F14 G06 G14 H06 H14 driversand
J06 J14 K06 K14 L06 L14
M06 M14 N06 N14 P06 P07
P14 R08 R09 R10 R11 R12
PCI/Stnd
3.3 V
40
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
Table 17. MPC8241 Pinout Listing (continued)
Power
Output
Driver Type
Signal Name
Package Pin Number
Pin Type
Notes
Supply
VDD
F03 H3 L5 N4 P5 V5 U8 W12 Power for
VDD
—
W16 R13 P19 L19 H19 F19
F15 C15 A13 A8 B5 A2
core 1.8 V
No Connect
AVDD
N5 W2 B1
M5
—
—
—
—
Power for
PLL (CPU
core logic)
1.8 V
AVDD
AVDD
2
R14
Power for
PLL
AVDD
2
—
(peripheral
logic)
1.8 V
Debug/Manufacturing Pins
DA0/QACK
DA1/CKO
A3
Output
Output
Output
Output
I/O
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
GVDD_OVDD
DRV_STD_MEM
DRV_STD_MEM
DRV_PCI
DRV_PCI_CLK
—
5, 11, 12
5
L1
DA2
R5
19
DA3/PCI_CLK4
DA4/REQ4
DA5/GNT4
V17
5
W13
5, 6
T11
Output
I/O
DRV_PCI
—
2, 4, 5
1, 5, 20
DA[10:6]/
N3 N2 N1 M4 M3
PLL_CFG[0:4]
DA[11]
T13
Output
Output
GVDD_OVDD
GVDD_OVDD
DRV_PCI
1, 19
19
DA[12:13]
M16 N16
DRV_STD_MEM
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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41
PLL Configuration
Signal Name
Table 17. MPC8241 Pinout Listing (continued)
Power
Output
Driver Type
Package Pin Number
Pin Type
Notes
Supply
DA[14:15]
B6 D8
Output
GVDD_OVDD DRV_MEM_CTRL
1, 19
Notes:
1. Multi-pin signals such as AD[31:0] or MDL[0:31] physical package pin numbers are listed in order corresponding to
the signal names. Ex: AD0 is on pin U1, AD1 is on pin U2,..., AD31 is on pin U13.
2. This pin is affected by a programmable PCI_HOLD_DEL parameter.
3. Motorola recommends placing a weak pull-up resistor (2–10 kΩ) ion this PCI control pin to LVDD
.
4. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only when the MPC8241 is in the
reset state.
5. This pin is a multiplexed signal and appears more than once in this table.
6. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not
guaranteed, but is sufficient to prevent unused inputs from floating.
7. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification (Rev. 2.2).
8. This pin is an open drain signal.
9. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only when the MPC8241 is in the
reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is
read into configuration bits during reset.
10.This pin has an internal pull-up resistor that is enabled only when the MPC8241 is in the reset state. The value of
the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits
during reset.
11.This pin is a reset configuration pin.
12.Motorola recommends placing a weak pull-up resistor (2–10 kΩ) on this pin to GVDD_OVDD
.
13.VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
14.External PCI clocking source or fanout buffer may be required for system if using the MPC8241 DUART
functionality because PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART
mode.
15.OSC_IN utilizes the 3.3-V PCI interface driver that is 5-V tolerant. See Table 2 for details.
16.This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open-drain.
17.All grounded pins are connected together. Connections should not be made to individual pins. The list represents
the balls that are connected to Ground.
18.GVDD_OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time including during power-on reset.
Note that GVDD_OVDD pins are all shorted together, PWRRING. The list represents the balls that are connected
to PWRRING. Connections should not be made to individual PWRRING pins.
19.Treat these pins as No Connects unless using debug address functionality.
20.PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of
HRST_CTRL and HRST_CPU negate in order to be latched.
21.Place a pull-up resistor of 120 Ω or less on the TEST0 pin.
22.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev. 1.1 (A). These signals
use DRV_MEM_CLK for chip Rev. 1.2B.
23.The driver capability of this pin is hardwired to 40 Ω and cannot be changed.
24.Motorola typically expects that customers using the serial port will have sufficient drivers available in the RS232
transceiver to drive the CTS pin actively as an input if they are using that mode. No pullups would be needed in
these circumstances.
6 PLL Configuration
The PLL_CFG[0:4] signals configure the internal PLLs of the MPC8241. For a specific PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
42
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
PLL Configuration
frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)
frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the
MPC8241 are shown in Table 18 and Table 19.
Table 18. PLL Configurations (166- and 200-MHz)
166 MHz-Part 2
200-MHz Part 2
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 3
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 3
(MHz)
PLL_
CFG
CPU
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
Ref 2
PCI-to-
Mem
(Mem VCO) (CPU VCO)
Mem-to-
CPU
[0:4] 1
Bus
Bus
Clock
Range
(MHz)
Clock
Range
(MHz)
0
2
3
4
6
00000
00010
000116
00100
001109
001116
Not available
34–37
25-265
344–445
507–663
75-78
34–44
50–66
50–88
Bypass
50–66
188-195
153–200
3 (2)
1 (4)
2.5 (2)
4.5 (2)
2 (4)
344–375
507–663
25–415
153–166
100–132
50–66
100–132 1 (Bypass)
50–82
100–164 25–448,10
100–176
2 (4)
2 (4)
Bypass
50–55
Bypass
Bypass
3 (2)
7
504–55 5
504–555
150–166
150–166
504–663
150–198 1 (Bypass)
Rev. B
7
00111
01000
Not available
504–663
50–66
Rev. D
8
50–55
76–82
150–198
152–200
198
1 (4)
2 (2)
2(2)
3 (2)
2 (2)
2.5(2)
2.5 (2)
3 (2)
2 (2)
2 (2)
3.5 (2)
4(2)
9
01001 384–415,11
01011
152–164 384–505,12 76–100
B
Not available
60–66
445
66
60–80
60–66
75–100
75–99
50–56
50
C
01100
01110
304–335
25–275
150–165
150–162
304–405
25–335
150–200
150–198
150–200
150–198
175–196
200
2 (4)
2 (4)
3 (2)
1.5 (2)
2 (4)
2(4)
E
50–54
10
12
14
16
17
19
1A
1B
1C
1D
10000 25–275,11
10010 504–555,11
10100
75–83
150–166 25–335,12
75–83
150–166
504–663
25–285
255
Not available
10110
10111
255
100
200
4(2)
2(2)
11001
11010
11011
11100
11101
335,13
66
165
3313–405
374–505
335,13
66–80
37–50
66
165–200
150–200
198
2(2)
2.5(2)
4 (2)
3(2)
374–415
37–41
150–166
1 (4)
2(2)
Not available
445,13
66
198
1.5(2)
1.5 (2)
Off
3(2)
445,13
66
166
4413–535
66–80
Not usable
165–200
2.5 (2)
Off
1E 1111014
Not usable
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
43
PLL Configuration
Table 18. PLL Configurations (166- and 200-MHz) (continued)
166 MHz-Part 2
200-MHz Part 2
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 3
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range 3
(MHz)
PLL_
CFG
CPU
Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
Ref 2
PCI-to-
Mem
(Mem VCO) (CPU VCO)
Mem-to-
CPU
[0:4] 1
Bus
Bus
Clock
Range
(MHz)
Clock
Range
(MHz)
1F
1111114
Not usable
Not usable
Off
Off
Notes:
1. PLL_CFG[0:4] settings not listed are reserved. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting
value. Note the impact of the relevant revisions for mode 7.
2. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
3. Limited by maximum PCI input frequency (66 MHz)
4. Limited by minimum CPU VCO frequency (300 MHz)
5. Limited by maximum CPU operating frequency.
6. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode.
7. Limited by minimum CPU operating frequency (100 MHz)
8. Limited due to maximum memory VCO frequency (352 MHz)
9. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the
OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the
processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This
mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply
in dual PLL bypass mode.
10.Limited by maximum CPU VCO frequency (704 MHz)
11.Limited by maximum system memory interface operating frequency (83 MHz @ 166 MHz CPU bus speed)
12.Limited by maximum system memory interface operating frequency (100 MHz @ 200 MHz CPU bus speed)
13.Limited by minimum memory VCO frequency (132 MHz)
14.In clock off mode, no clocking occurs inside the MPC8241, regardless of the PCI_SYNC_IN input.
Table 19. PLL Configurations (266-MHz Parts)
266-MHz Part 9
Multipliers
PLL_
PCI Clock Input
(PCI_SYNC_IN)
Range 1
Periph Logic/
Mem Bus
Clock Range
(MHz)
Ref 2
CPU Clock
Range
PCI-to-
Mem
(Mem VCO)
Mem-to-
CPU
(CPU VCO)
CFG[0:4] 10,11
(MHz)
(MHz)
0
1
2
3
4
6
00000
00001
25–355
25–295
75–105
75–88
188–263
225–264
225–266
100–133
100–176
3 (2)
3 (2)
2.5 (2)
3 (2)
00010
5015–595
5014–661
25–444
50–59
1 (4)
4.5 (2)
2 (4)
0001112
00100
50–66
1 (Bypass)
2 (4)
50–88
2 (4)
0011013
Bypass
Bypass
44
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
PLL Configuration
Multipliers
Table 19. PLL Configurations (266-MHz Parts) (continued)
266-MHz Part 9
PLL_
PCI Clock Input
(PCI_SYNC_IN)
Range 1
Periph Logic/
Mem Bus
Clock Range
(MHz)
Ref 2
CPU Clock
Range
PCI-to-
Mem
(Mem VCO)
Mem-to-
CPU
(CPU VCO)
CFG[0:4] 10,11
(MHz)
(MHz)
7 (Rev. B)
0011112
0011114
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
111108
11110
506–661
50–66
150–198
Not Available
150–198
152–264
225–261
204–264
150–220
238–263
150–264
263
1 (Bypass)
3 (2)
7 (Rev. D)
8
506–661
386–661
25–295
453–595
306–444
453–505
25–445
255
50–66
76–132
50–58
1 (4)
2 (2)
3 (2)
2 (2)
9
A
2 (4)
4.5 (2)
3 (2)
B
68–88
1.5 (2)
2 (4)
C
60–88
2.5 (2)
3.5 (2)
3 (2)
D
68–75
1.5 (2)
2 (4)
E
50–88
F
75
3 (2)
3.5 (2)
2 (2)
10
25–445
25–265
506–661
75–132
100–106
75–99
150–264
250–266
150–198
3 (2)
11
4 (2)
2.5 (2)
2 (2)
12
1.5 (2)
4 (2)
13
Not available
50–76
3 (2)
14
25–385
175–266
2 (4)
3.5 (2)
4 (2)
15
Not available
50–66
2.5 (2)
2 (4)
16
25–335
25–335
200–264
200–264
204–264
165–265
200–264
204–264
198–264
165–248
4 (2)
17
100–132
68–88
4 (2)
2 (2)
18
273–355
333–535
5018–661
343–445
443–595
443–661
2.5 (2)
2 (2)
3 (2)
19
1A
66–106
50–66
2.5 (2)
4 (2)
1 (4)
1B
68–88
2 (2)
3 (2)
1C
66–88
1.5 (2)
1.5 (2)
Off
3 (2)
1D
66–99
2.5 (2)
Off
1E (Rev. B)
1E (Rev. D)
Not usable
66-76
333-385
231-266
2(2)
3.5(2)
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
45
PLL Configuration
Table 19. PLL Configurations (266-MHz Parts) (continued)
266-MHz Part 9
Multipliers
PLL_
PCI Clock Input
(PCI_SYNC_IN)
Range 1
Periph Logic/
Mem Bus
Clock Range
(MHz)
Ref 2
CPU Clock
Range
PCI-to-
Mem
(Mem VCO)
Mem-to-
CPU
(CPU VCO)
CFG[0:4] 10,11
(MHz)
(MHz)
1F
111118
Not usable
Off
Off
Notes:
1. Limited by maximum PCI input frequency (66 MHz)
2. Note the impact of the relevant revisions for modes 7 and 1E
3. Limited by minimum memory VCO frequency (132 MHz)
4. Limited due to maximum memory VCO frequency (352 MHz)
5. Limited by maximum CPU operating frequency
6. Limited by minimum CPU VCO frequency (300 MHz)
7. Limited by maximum CPU VCO frequency (704 MHz)
8. In clock off mode, no clocking occurs inside the MPC8241, regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10.PLL_CFG[0:4] settings that are not listed are reserved.
11.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
12.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode.
13.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the
OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation and the
processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This
mode is intended for hardware modeling support. The AC timing specifications given in this document do not apply
in dual PLL bypass mode.
14.Limited by minimum CPU operating frequency (100 MHz)
15.Limited by minimum memory bus frequency (50 MHz)
46
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8241.
7.1 PLL Power Supply Filtering
The AV and AV 2 power signals on the MPC8241 provide power to the peripheral logic/memory bus
DD
DD
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AV and AV 2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant
DD
DD
frequency range of the PLLs. Motorola recommends two separate circuits that are similar to the one shown
in Figure 28 using surface mount capacitors with minimum effective series inductance (ESL) for AV and
DD
AV 2 power signal pins. In High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993)
DD
Dr. Howard Johnson recommends using multiple small capacitors of equal value instead of multiple values.
Place the circuits as close as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routing directly as possible from the capacitors to the input signal pins with minimal
inductance of vias is important.
10 Ω
VDD
AVDD or AVDD2
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 28. PLL Power Supply Filter Circuit
7.2 Decoupling Recommendations
Dynamic power management, large address and data buses, and high operating frequencies enable the
MPC8241 to generate transient power surges and high frequency noise in its power supply, especially while
driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Motorola
recommends that system designers place at least one decoupling capacitor at each V , GV _OV , and
DD
DD
DD
LV pin of the MPC8241, and that these decoupling capacitors receive their power from dedicated power
DD
planes in the PCB to utilize short traces to minimize inductance. These capacitors should have a value of
0.1 µF. To minimize lead inductance, use only ceramic SMT (surface mount technology) capacitors,
preferably 0508 or 0603, on which connections are made along the length of the part.
In addition, distribute several bulk storage capacitors around the PCB to feed the V , GV _OV , and
DD
DD
DD
LV planes and enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
DD
a low ESR (equivalent series resistance) rating to ensure the necessary quick response time, and should be
connected to the power and ground planes through two vias to minimize inductance. Motorola recommends
using bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
7.3 Connection Recommendations
To ensure reliable operation, Motorola recommends connecting unused inputs to an appropriate signal level.
Unused active-low inputs should be tied to OV . Unused active-high inputs should be connected to GND.
DD
All no connect (NC) signals must remain unconnected.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
47
System Design Information
Power and ground connections must be made to all external V , GV _OV , LV , and GND pins of
DD
DD
DD
DD
the MPC8241.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to
the PCI_SYNC_IN input of the MPC8241.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8241. The trace length may be used to skew or adjust
the timing window as needed. See Motorola application notes AN1849/D, the Tundra Tsi107™ Design
Guide, and AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information
about this topic. Note the SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).
7.4 Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress, and thus do not
require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) are disabled, and their outputs drive logic zeros when they would otherwise be driven. For
this mode, these pins do not require pull-up resistors and should be left unconnected by the system to
minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120 Ω or less connected to GV _OV
.
DD
DD
Motorola recommends that RTC should have weak pull-up resistors (2–10 kΩ) connected to GV _OV
DD
DD
and that the following signals should be pulled up to GV _OV with weak pull-up resistors (2–10 kΩ):
DD
DD
SDA, SCL, SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2,
QACK/DA0, and DRDY.
The following PCI control signals should be pulled up to LV (the clamping voltage) with weak pull-up
DD
resistors (2–10 kΩ): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The resistor
values may need to have stronger adjustment to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors that are enabled only while the device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See
Table 17 for more information.
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND by means of 1-kΩ pull-down resistors to ensure that a logic
zero level is read into the configuration bits during reset if the default logic-one level is not desired.
Any other unused active low input pins should be tied to a logic-one level by means of weak pull-up resistors
(2–10 kΩ) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND by means of weak pull-down resistors (2–10 kΩ).
48
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
7.5 PCI Reference Voltage—LVDD
The MPC8241 PCI reference voltage (LV ) pins should be connected to 3.3 ± 0.3 V power supply if
DD
interfacing the MPC8241 into a 3.3-V PCI bus system. Similarly, the LV pins should be connected to
DD
5.0 V ± 5% power supply if interfacing the MPC8241 into a 5-V PCI bus system. For either reference
voltage, the MPC8241 always performs 3.3-V signaling as described in the PCI Local Bus Specification
manual (Rev. 2.2). The MPC8241 tolerates 5-V signals when interfaced into a 5-V PCI bus system. (See
Errata No. 18 in the MPC8245/MPC8241 Integrated Processor Chip Errata).
7.6 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to assert HRESET or TRST independently to control the processor
completely. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, the COP reset signals must be merged into these signals with
logic.
The arrangement shown in Figure 29 allows the COP to assert HRESET or TRST independently while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
to ensure that the JTAG scan chain is initialized during power-on. The COP header shown in Figure 29 adds
many benefits—breakpoints, watchpoints, register and memory examination/modification, and other
standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated
footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a 'Berg header'). The connector typically has
pin 14 removed as a connector key.
Numbering for the COP header shown in Figure 29 is not standardized; consequently, many different pin
numbers have been observed from emulator vendors. Some are numbered top-to-bottom followed by
left-to-right, while others use left-to-right followed by top-to-bottom. Others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 29 is common to all known emulators.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
49
System Design Information
MPC8245
SRESET 5
HRST_CPU
SRESET 5
HRESET 7
From Target
Board Sources
(if any)
HRST_CTRL
10 kΩ
10 kΩ
10 kΩ
HRESET
13
11
OVDD
OVDD
OVDD
SRESET 5
10 kΩ
0 Ω 8
OVDD
TRST 7
TRST
4
1
3
2
4
1 kΩ
VDD_SENSE
6
5 2
OVDD
OVDD
10 kΩ
5
7
6
8
10 kΩ
15 3
OVDD
10 kΩ
Key
9
10
12
14 4
OVDD
CHKSTOP_IN 6
TMS
CHKSTOP_IN 6
TMS
11
8
KEY
13
15
9
No pin
TDO
TDI
16
1
TDO
3
TDI
COP Connector
Physical Pin Out
TCK
7
TCK
QACK 1
2
NC
NC
NC
10
12
16
Notes:
1. QACK is an output on the MPC8245 and is not required at the COP header for emulation.
2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8245.
Connect pin 5 of the COP header to OVDD with a 1- kΩ pull-up resistor.
3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8245.
Connect pin 15 of the COP header to OVDD with a 10-kΩ pull-up resistor.
4. Pin 14 is not physically present on the COP header.
5. SRESET functions as output SDMA12 in extended ROM mode.
6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
7. The COP port and target board should be able to independently assert HRESET and TRST to
the processor in order to fully control the processor as shown above.
.8. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the C
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
Figure 29. COP Connector Diagram
50
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
7.7 Thermal Management Information
This section provides thermal management information for the plastic ball grid array (PBGA) package for
air-cooled applications. Depending on the application environment and the operating frequency, a heat sink
may be required to maintain junction temperature within specifications. Proper thermal control design is
primarily dependent on the system-level design: heat sink, airflow, and thermal interface material. To reduce
the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive,
spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly (see
Figure 30).
PBGA Package
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface
Material
Wire
Die
Printed-Circuit Board
Option
Figure 30. Package Exploded Cross-Sectional View with Several Heat Sink Options
Figure 31 depicts the die junction-to-ambient thermal resistance for four typical cases:
•
•
•
•
A heat sink is not attached to the PBGA package and a high board level thermal loading from
adjacent components exists (label used—1s).
A heat sink is not attached to the PBGA package and a low board level thermal loading from
adjacent components exists (label used—2s2p).
A large heat sink (cross cut extrusion, 38 × 38 × 16.5 mm) is attached to the PBGA package and a
high board level thermal loading from adjacent components exists (label used—1s/sink).
A large heat sink (cross cut extrusion, 38 × 38 × 16.5 mm) is attached to the PBGA package and a
low board level thermal loading from adjacent components exists (label used—2s2p/sink).
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
51
System Design Information
50.0
40.0
30.0
20.0
10.0
1s
2s2p
1s/sink
2s2p/sink
0.0
0
0.5
1
1.5
2
2.5
Airflow Velocity (m/s)
Figure 31. Die Junction-to-Ambient Resistance
The board designer can choose among several types of heat sinks to place on the MPC8241. Several
commercially available heat sinks for the MPC8241 are provided by the following vendors:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
408-749-7601
Alpha Novatech
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
603-635-5102
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, and Wakefield Engineering
offer different heat sink-to-ambient thermal resistances, and may or may not need airflow.
52
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
7.7.1 Internal Package Conduction Resistance
For the PBGA, die-up, packaging technology, shown in Figure 30, the intrinsic conduction thermal
resistance paths are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-ball thermal resistance
Figure 32 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 32. PBGA Package with Heat Sink Mounted to a Printed-Circuit Board
For this die-up, wire-bond PBGA package, heat generated on the active side of the chip is conducted mainly
through the mold cap, the heat sink attach material (or thermal interface material), and finally through the
heat sink where forced-air convection removes it.
7.7.2 Adhesives and Thermal Interface Materials
A thermal interface material should be used between the top of the mold cap and the bottom of the heat sink
to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring
clip mechanism, Figure 33 shows the thermal performance of three thin-sheet thermal-interface materials
(silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact
pressure. As shown, the performance of these thermal interface materials improves with increasing contact
pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare
joint results in a thermal resistance approximately seven times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 30). Therefore, the synthetic grease offers the best thermal performance, considering the low
interface pressure. Of course, the selection of any thermal interface material depends on many factors:
thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and
so on.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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53
System Design Information
Silicone Sheet (0.006 in.)
Bare Joint
2
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 33. Thermal Performance of Select Thermal Interface Material
40
50
60
70
80
The board designer can choose among several types of thermal interface. Heat sink adhesive materials
should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment
shock/vibration requirements. Several commercially-available thermal interfaces and adhesive materials are
provided by the following vendors:
The Bergquist Company
18930 West 78 St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
781-935-4850
800-248-2481
th
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
888-642-7674
Phoenix, AZ 85044
Internet: www.microsi.com
54
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
888-246-9050
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
7.7.3 Heat Sink Usage
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
T = T + (R × P )
J
A
θJA
D
where:
T = ambient temperature for the package (°C)
A
R
= junction-to-ambient thermal resistance (°C/W)
θJA
P = power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, two values are in common usage: the value determined
on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA,
these values can be different by a factor of two. Which value is closer to the application depends on the
power dissipated by other components on the board. The value obtained on a single-layer board is
appropriate for the tightly packed printed-circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
R
R
R
= junction-to-ambient thermal resistance (°C/W)
= junction-to-case thermal resistance (°C/W)
= case-to-ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For instance, the user can change the size of the heat
θCA
sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit
board, or the thermal dissipation on the printed-circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
thermal characterization parameter (ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (ψ × P )
J
T
JT
D
where:
T = thermocouple temperature atop the package (°C)
T
ψ
D
= thermal characterization parameter (°C/W)
JT
P = power dissipation in package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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55
System Design Information
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance that is caused by removing part of the thermal interface to the heat sink. Considering
the experimental difficulties with this technique, many engineers measure the heat sink temperature and
then back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
In many cases, it is appropriate to simulate the system environment using a computational fluid dynamics
thermal simulation tool. In such a tool, the simplest thermal model of a package that has demonstrated
reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a
junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink is used or
where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal
resistance describes the thermal performance when most of the heat is conducted to the printed-circuit
board.
7.8 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
56
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
Document Revision History
8 Document Revision History
Table 20 provides a revision history for this hardware specification.
C
Table 20. Revision History Table
Revision
Date
Substantive Change(s)
0
—
—
Initial release.
Updated Features list in Section 1.2.
0.1
Corrected pin assignments in Table 16 for DA[15] and DQM[3] signals.
Added vendor (Cool Innovations, Inc.) to list of heat sink vendors.
0.2
—
Table 16—Corrected pin number for PLL_CFG0/DA10 to N3. The pin was already correctly
listed for DA10/PLL_CFG0. Updated note 1 to reflect pin assignments for the MPC8241.
Updated footnotes throughout document.
Section 1.4.3.3—Updated note 4 to correct bit values of PCI_HOLD_DEL in PMCR2.
Section 1.6—Updated notes in Table 17. Included memory VCO minimum and maximum
numbers.
Section 1.7.8—Updated description of bits PCI_HOLD_DEL in PMCR2.
Section 1.7.10.3—Replaced thermal characterization parameter (YJT) with correct thermal
characterization parameter (ψ ). Changed ψ symbol to ψ .
JT JT
π
0.3
—
—
Corrected solder ball information in Section 1.5.1 to 62 Sn/36 Pb/2 Ag.
Section 1.4.3.1—Corrected DLL_EXTEND labeling in Figures 5 through 8. Removed note
for pin TRIG_OUT/RCS3 in Table 16, as well as from the list of pins needing to be pulled up
to IVDD in Section 1.7.6.
Corrected order information labeling in Section 1.9 to MPC8241XZPXXXX. Also corrected
label description of ZU = PBGA to ZP = PBGA.
1
Updated document template.
Section 1.4.1.5—Updated driver type names in Table 4 so that they are consistent with the
driver types referred to in the MPC8245 Integrated Processor User’s Manual. Added notes
5 and 6 to Table 4.
Section 1.4.3.1—Added reference to AN2164 in note 7. Labeled N value in Figures 5
through 8.
Section 1.4.3.2—Updated Figure 9 to show Tos.
Table 9—Changed default for 0x77 bits 5:4 to 0b10.
Section 1.4.3.3—Added item 12e to Table 10 for SDRAM_SYNC_IN to Output Valid Timing.
Updated Figure 13 to state GVDD_OVDD instead of OVDD
.
Section 1.5.3—Updated driver type names to match those used in Table 4. Updated notes
for the following signals: DRDY, SDRAM_CLK[0:3], MIV, RTC, TDO, and DA[11].
Section 1.6—Updated PLL table and notes.
Removed old Section 1.7.2 on voltage sequencing requirements. Added cautions regarding
voltage sequencing to the end of Table 2 in Section 1.4.1.2.
Section 1.7.3—Changed sentence recommendation regarding decoupling capacitors.
Section 1.7.5—Added reference to AN2164.
Section 1.7.6—Added sentence regarding the PLL_CFG signals.
Removed old Section 1.7.8 since the MPC8241 cannot be used as a drop in replacement for
the MPC8240 because of pin compatibility issues.
Section 1.7.8—Updated TRST information in this section and Figure 26.
Section 1.7.9—Updated list for heat sink and thermal interface vendors.
Section 1.9—Changed format of ordering information section. Added tables to reflect part
number specifications also available.
Added Sections 1.9.2 and 1.9.3.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
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57
Document Revision History
Table 20. Revision History Table (continued)
Substantive Change(s)
Revision
Date
2
—
Section 1.4.1.2—Updated note 1 to include 266-MHz part. Added a line to cautions 2 and 3
in the notes section of Table 2. Added Figures 4 and 5 to show the overshoot and undershoot
requirements for the PCI interface.
Section 1.4.1.3—Table 3: Updated minimum value for input high voltage, and maximum
value for capacitance.
Section 1.4.3.2—Appended Figures 9 and 10.
Section 1.4.3.4—Added a column to Table 13 to include 133-MHz memory bus speed for
266-MHz part.
Section 1.5.2—Changed Figure 24 to accommodate new package offerings.
Section 1.6—Added Table 19 for PLL of the 266-MHz part.
Section 1.7.7—Corrected note numbering in COP connector diagram.
Section 1.9.1—Updated package description in part marking nomenclature.
3
—
Section 1.4.1.2—Changed recommended value in Table 2 for I/O buffer supply to 3.3 ± 0.3
V. Changed wording referencing Figure 4 to refer to the MPC8241.
Section 1.4.2—Table 6: Updated values for thermal characterization data as per the new
packaging and 266-MHz part. Added note 7 for the difference between the 166-/200-MHz
and the 266-MHz packaging.
Section 1.4.3—Corrected the voltage listing for the 266-MHz part to 1.8 ± 0.1 V in Table 7.
Section 1.5—Changed package parameters and illustration based on new packaging.
Section 1.6—Table 18: Modified PLL configuration for 166- and 200-MHz parts for mode 7
to specify that this mode is not available for Rev. D of the part. Added sentence to note 1
referencing update for mode 7. Table 19: Made several range updates for various modes to
accommodate VCO limits. Added mode 7 and 1E updates for Rev. D. Updated VCO limits
listed in notes 4, 6, and 7.
4
—
Section 1.4.1.2—Table 2: Changed note 1. Figure 2: Updated note 2 and removed ‘voltage
regulator delay’ label since Section 1.7.2 is being deleted this revision. Also, updated Table
5, note 1 to reflect deletion of Section 1.7.2.
Section 1.4.1.3—Table 3: Updated the maximum input capacitance from 15 to 16 pF based
on characterization data.
Section 1.4.3.1—Updated PCI_SYNC_IN jitter specifications to 200 ps.
Section 1.4.3.3—Table 11, item 12b: added the word ‘address’ to help clarify which signals
the spec applies to. Figure 15: edited timing for items 12a0 and 12a2 to correspond with
Table 11.
Section 1.5.2—Changed some dimension values for the side view of package.
Section 1.5.3—Updated notes for the QACK/DA0 signal because this signal has been found
to have no internal pull resistor.
Section 1.6—Updated note numbering list for Table 19. Removed mode 5 from PLL tables
since that mode is no longer supported.
Section 1.7.2 —This section was removed as it was not necessary since the power
information is covered in Section 1.4.1.5.
Section 1.7.4—Added the words ‘the clamping voltage’ to describe LVDD in the sixth
paragraph. Changed the QACK/DA0 signal from the list of signals having an internal pull-up
resistor to the list of signals needing a weak pull-up resistor to OVDD
.
Section 1.9.1—Table 21: Added processor version register value column.
5
—
Section 5.1— Updated package information to include all package offerings.
Section 5.2 — Included package case outline for ZP (Rev. B) packaging parts.
Section 9 — Updated Part markings for the offerings of the MPC8241.
All sections — Nontechnical reformatting
58
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Ordering Information
Table 20. Revision History Table (continued)
Substantive Change(s)
Revision
Date
6
—
Section 4.1.2 — Figure 2: Added note 6 and related label for latching of the PLL_CFG
signals.
Section 4.1.3 — Updated specifications for the input high and input low voltages of
PCI_SYNC_IN.
Section 4.3.1 — Table 8: Corrected typo for first number 1a to 1; Updated characteristics for
the DLL lock range for the default and remaining three DLL locking modes; Reworded note
description for note 6. Replaced contents of Table 9 with bit descriptions for the four DLL
locking modes. In Figures 7 through 10, updated the DLL locking mode graphs.
Section 4.3.2 — Table 10: Changed the name of references for timing parameters from
SDRAM_SYNC_IN to sys_logic_clk to be consistent with Figure 11. Followed the same
change for note 2.
Section 4.3.3— Table 11: Changed the name of references for timing parameters from
SDRAM_SYNC_IN to sys_logic_clk to be consistent with Figure 11. Followed the same
change for note 2.
Section 5.3 — Table 17: Removed extra listing of DRDY in test/configuration signal list and
updated relevant notes for signal in memory Interface signal listing. Updated note #20.
Added note 24 for the signals of the UART interface.
Section 7.6 — Added relevant notes to this section and updated Figure 29.
6.1
7
—
Section 4.3.1 — Table 9: Corrected last row to state the correct description for the bit set-
ting: Max tap delay, DLL extend. Figure 8: Corrected the label name for the DLL graph to
state “DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=1 and
Normal Tap Delay”
05/11/2004
Section 4.1.4 —Table 4: Changed the default for drive strength of DRV_STD_MEM.
Section 4.3.1 —Table 8: Changed the wording for item 15’s description.
Section 4.3.4 —Table 10: Changed Tos range and wording in note 7; Figure 11: changed
wording for SDRAM_SYNC_IN description relative to TOS
.
9 Ordering Information
Ordering information for the parts that this document fully covers is provided in Section 9.1, “Part Numbers
Fully Addressed by This Document.” Section 9.2, “Part Numbers Not Fully Addressed by This Document,”
lists the part numbers which do not fully conform to the specifications of this document. These special part
numbers require an additional document called a 'part number specification'.
9.1 Part Numbers Fully Addressed by This Document
Table 21 provides the Motorola part numbering nomenclature for the MPC8241. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes
an application modifier that may specify special application conditions. Each part number also contains a
revision code that refers to the die mask revision number. Read the Revision ID register at address offset
0x08 to determine the revision level.
MOTOROLA
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
59
Ordering Information
Table 21. Part Numbering Nomenclature
XPC nnnn
xx
nnn
x
L
Processor
Version
Register
Value
Processor
Frequency 2
(MHz)
Product
Code
Part
Identifier
Revision
Level
Process Descriptor
Package 1, 3
ZP = PBGA
166
200
B:1.2
Rev. ID:0x12
MPC
8241
L = Standard Spec.
1.8 V ± 100 mV
0° to 105°C
0x80811014
ZQ = thick substrate and
thick mold cap PBGA
VR = Lead free version of
package
166
200
266
D:1.4
Rev. ID:0x14
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support
other maximum core frequencies.
3. ZP packaging is only available for Rev. B (1.2) devices. Note that the 266-MHz part is only offered as a Rev. D part.
9.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate part number specifications that supplement and supersede this document (see
Table 22).
Table 22. Part Numbers Addressed by MPC8241TXXPNS Series
XPC nnnn
xx
nnn
x
L
Processor
Version
Register
Value
Processor
Frequency 2
(MHz)
Product
Code
Part
Identifier
Revision
Level
Process Descriptor
Package 1, 3
ZP =PBGA
166
200
B:1.2
Rev. ID:0x12
T = Extended
Temperature Spec.
1.8 V ± 100 mV
-40° to 105°C
0x80811014
ZQ = thick substrate and
thick mold cap PBGA
VR = Lead free version of
package
166
200
266
MPC
8241
D:1.4
Rev. ID:0x14
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support
other maximum core frequencies.
3. ZP packaging is only available for Rev. B (1.2) devices. Note that the 266-MHz part is only offered as a Rev. D part.
60
MPC8241 Integrated Processor Hardware Specifications
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MOTOROLA
Ordering Information
9.2.1 Part Marking
Figure 34 shows how parts are marked.
MPC8241L
xx266x
MMMMMM
ATWLYYWWA
8241
PBGA
Notes:
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 34. Part Marking for PBGA Device
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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Ordering Information
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62
MPC8241 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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Ordering Information
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(800) 521-6274
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Tokyo 106-8573 Japan
Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document.
81-3-3440-3569
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
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limitation consequential or incidental damages. “Typical” parameters which may be provided in
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© Motorola, Inc. 2004
MPC8241EC
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