MPC8245TZU266D [MOTOROLA]
32-BIT, 266MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352;
| 型号： | MPC8245TZU266D |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 266MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件： | 总64页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MPC8245EC
Rev. 5.1, 2/2004
MPC8245
Integrated Processor
Hardware Specifications
The MPC8245 combines a PowerPC™ MPC603e core with a PCI bridge. The PCI support on
the MPC8245 allows system designers to rapidly design systems using peripherals already
designed for PCI and the other standard interfaces. The MPC8245 also integrates a
high-performance memory controller that supports various types of ROM and SDRAM. The
MPC8245 is the second of a family of products that provide system-level support for industry
standard interfaces with a MPC603e processor core.
This hardware specification describes pertinent electrical and physical characteristics of the
MPC8245. For functional characteristics of the processor, refer to the MPC8245 Integrated
Processor User’s Manual (MPC8245UM).
This hardware specification contains the following topics:
Topic
Page
1
Section 1, “Overview”
Section 2, “Features”
3
Section 3, “General Parameters”
Section 4, “Electrical and Thermal Characteristics”
Section 5, “Package Description”
Section 6, “PLL Configurations”
Section 7, “System Design Information”
Section 8, “Document Revision History”
Section 9, “Ordering Information”
5
5
32
40
44
57
60
To locate any published errata or updates for this document, refer to the website at
http://www.motorola.com/semiconductors
1 Overview
The MPC8245 integrated processor is comprised of a peripheral logic block and a 32-bit
superscalar MPC603e core, as shown in Figure 1.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
MPC8245
Processor Core Block
(64-Bit) Two-Instruction Fetch
Additional Features:
• Prog I/O with Watchpoint
• JTAG/COP Interface
• Power Management
Processor
PLL
Branch
Processing
Unit
Instruction Unit
(BPU)
(64-Bit) Two-Instruction Dispatch
System
Register
Unit
Floating-
Integer
Unit
(IU)
Load/Store
Point
Unit
Unit
(LSU)
(FPU)
(SRU)
64-Bit
Data
MMU
Instruction
MMU
16-Kbyte
Data
Cache
16-Kbyte
Instruction
Cache
Peripheral Logic Bus
Peripheral Logic Block
Data Bus
Data (64-Bit)
Address
(32-Bit)
Data Path
(32- or 64-Bit)
with 8-Bit Parity
or ECC
ECC Controller
Message
Unit
(with I2O)
Central
Control
Unit
Memory
Controller
Memory/ROM/
PortX Control/Address
DMA
Controller
Performance
Monitor
SDRAM_SYNC_IN
SDRAM Clocks
I2C
Controller
I2C
DLL
Peripheral Logic
PLL
PCI_SYNC_IN
PIC
5 IRQs/
16 Serial
Interrupts
Interrupt
Controller/
Timers
Configuration
Registers
PCI Bus
Interface Unit
DUART
Address
Translator
PCI
Arbiter
Watchpoint
Facility
Fanout
Buffers
PCI Bus
Clocks
OSC_IN
32-Bit
Five
PCI Interface Request/Grant
Pairs
Figure 1. MPC8245 Block Diagram
2
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),
2
memory controller, DMA controller, PIC interrupt controller, a message unit (and I O interface), and an I C
2
controller. The processor core is a full-featured, high-performance processor with floating-point support,
memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power management
features. The integration reduces the overall packaging requirements and the number of discrete devices
required for an embedded system.
The MPC8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The processor core is clocked from a separate PLL that is referenced to the peripheral
logic PLL. This allows the microprocessor and the peripheral logic block to operate at different frequencies
while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on
memory data bus width) and a 32-bit address bus along with control signals that enable the interface
between the processor and peripheral logic to be optimized for performance. PCI accesses to the MPC8245
memory space are passed to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety of embedded
applications. The MPC8245 can be used as either a PCI host or PCI agent controller.
2 Features
Major features of the MPC8245 are as follows:
•
Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management—Supports 60x nap, doze, and sleep modes
Peripheral logic
•
— Peripheral logic bus
– Supports various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Supports full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Supports up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– Supports one to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/PortX space
– Base ROM space supports 8-bit data path or same size as the SDRAM data path (32- or
64-bit)
– Extended ROM space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data
path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Support for dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Support for PCI locked accesses to memory
– Support for accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Some internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Supports direct mode or chaining mode (automatic linking of DMA transfers)
– Supports scatter gathering—Read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I O message interface
2
2
— I C controller with full master/slave support that accepts broadcast messages
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers with cascade
— Two (dual) universal asynchronous receiver/transmitters (UARTs)
4
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
General Parameters
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
System-level performance monitor facility
Debug features
•
•
— Memory attribute and PCI attribute signals
— Debug address signals
— MIV signal—Marks valid address and data bus cycles on the memory bus
— Programmable input and output signals with watchpoint capability
— Error injection/capture on data path
— IEEE 1149.1 (JTAG)/test interface
3 General Parameters
The following list provides a summary of the general parameters of the MPC8245:
Technology
Die size
0.25-µm CMOS, five-layer metal
2
49.2 mm
Transistor count
Logic design
Packages
4.5 million
Fully-static
Surface-mount 352 tape ball grid array (TBGA)
Core power supply
1.8 V ± 100 mV DC (only for 266- and 300-MHz parts)
2.0 V ± 100 mV DC (for 266-, 300-, 333-, and 350-MHz parts)
(nominal, see Table 2 for details and recommended operating conditions)
I/O power supply
3.0- to 3.6-V DC
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8245.
4.1 DC Electrical Characteristics
This section covers ratings, conditions, and other DC electrical characteristics.
4.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings
Characteristic 1
Symbol
Range
Unit
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs
VDD
GVDD
–0.3 to 2.1
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.1
V
V
V
V
OVDD
AVDD/AVDD
2
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
Electrical and Thermal Characteristics
Table 1. Absolute Maximum Ratings (continued)
Characteristic 1
Symbol
Range
Unit
Supply voltage—PCI reference
LVDD
Vin
–0.3 to 5.4
–0.3 to 3.6
0 to 105
V
V
Input voltage 2
Operational die-junction temperature range
Storage temperature range
Notes:
Tj
°C
°C
Tstg
–55 to 150
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stress beyond those listed may affect device reliability
or cause permanent damage to the device.
2. PCI inputs with LVDD = 5 V ± 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5 V DC.
6
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8245.
Table 2. Recommended Operating Conditions1
Recommended
Value
Characteristic
Symbol
Unit
Notes
Supply voltage
VDD
1.7 to 2.1 V
1.9 to 2.2 V
3.3 ± 0.3
V
V
V
V
V
V
V
V
V
V
V
V
°C
4, 7
5, 7
I/O buffer supply for PCI and standard
Supply voltages for memory bus drivers
CPU PLL supply voltage
OVDD
GVDD
AVDD
7
3.3 ± 10%
9
1.8 ± 100 mV
2.0 ± 100 mV
1.8 ± 100 mV
2.0 ± 100 mV
5.0 ± 5%
5, 7, 12
7, 12
4, 7, 12
5, 7, 12
2, 10, 11
3, 10, 11
2, 3
PLL supply voltage—peripheral logic
PCI reference
AVDD2
LVDD
3.3 ± 0.3
Input voltage
PCI inputs
Vin
0 to 3.6 or 5.75
0 to 3.6
All other inputs
6
Die-junction temperature
Tj
0 to 105
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 5.0-V DC power supply.
3. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3-V DC power supply.
4. Note that the voltage range of 1.7–2.1 volts applies to parts marked as having a maximum CPU speed of 266 and
300 MHz. See Table 7.
5.) The voltage range of the 1.9–2.2 volts applies to parts marked as having a maximum CPU speed of 333 and 350
MHz. See Table 7.
Cautions:
6. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at all times,
including during power-on reset. Input voltage (Vin) must not be greater than GVDD/OVDD by more than 0.6 V at all
times, including during power-on reset.
7. OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time, including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
8. VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6 V at any time, including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
9. GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time, including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
10.LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on reset. This limit
may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
11.LVDD must not exceed OVDD by more than 3.0 V at any time, including during power-on reset. This limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
12.This voltage is the input to the filter discussed in Section 7.1, “PLL Power Supply Filtering”, and not necessarily the
voltage at the AVDD pin, which may be reduced from VDD by the filter.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
7
Electrical and Thermal Characteristics
Figure 2 shows supply voltage sequencing and separation cautions.
LVDD @ 5 V
5 V
11 10
See Note 1
3.3 V
2.0 V
11
OVDD/GVDD/(LVDD @ 3.3 V - - - -)
10
7, 9
8
VDD/AVDD/AVDD
2
100 µs
PLL
VDD Stable
Relock
Time 3
0
6
Time
HRST_CPU,
PLL
HRST_CTRL
Asserted 255
External Memory
Power Supply Ramp Up 2
Reset
Clock Cycles 3
Configuration Pins
Nine External Memory
Clock Cycles Setup Time 4
HRST_CPU,
HRST_CTRL
VM = 1.4 V
Maximum Rise Time Must Be Less Than
One External Memory Clock Cycle 5
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.
2. See Cautions section of Table 2 for additional information on this topic.
3. Refer to Table 8 for additional information on PLL relock and reset signal assertion timing
requirements.
4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements.
5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one
SDRAM_SYNC_IN clock cycle for the device to be in the nonreset state.
6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the
negation of HRST_CTRL and HRST_CPU negate in order to be latched.
Figure 2. Supply Voltage Sequencing and Separation Cautions
8
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 shows the undershoot and overshoot voltage of the memory interface of the MPC8245.
4 V
GVDD + 5%
GVDD
VIH
GND
GND – 0.3 V
VIL
GND – 1.0 V
Not to Exceed 10%
of tSDRAM_CLK
Figure 3. Overshoot/Undershoot Voltage
Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI interface of the MPC8245 for
the 3.3- and 5-V signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 4. Maximum AC Waveforms for 3.3-V Signaling
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
9
Electrical and Thermal Characteristics
11 ns
(Min)
+11 V
0 V
Overvoltage
Waveform
11 V p-to-p
(Min)
4 ns
(Max)
4 ns
(Max)
62.5 ns
+5.25 V
Undervoltage
Waveform
10.75 V p-to-p
(Min)
–5.5 V
Figure 5. Maximum AC Waveforms for 5-V Signaling
4.1.3 DC Electrical Characteristics
Table 3 provides the DC electrical characteristics for the MPC8245 at recommended operating conditions.
Table 3. DC Electrical Specifications
At recommended operating conditions (see Table 2)
Characteristic
Condition 3
Symbol
Min
Max
Unit
Notes
Input high voltage
PCI only, except
PCI_SYNC_IN
VIH
0.65 × OVDD
LVDD
V
1
Input low voltage
Input high voltage
PCI only, except
PCI_SYNC_IN
VIL
VIH
—
0.3 × OVDD
V
V
All other pins, including
PCI_SYNC_IN
2.0
3.3
(GVDD = 3.3 V)
Input low voltage
All inputs, including
PCI_SYNC_IN
VIL
GND
—
0.8
±70
±10
—
V
µA
µA
V
Input leakage current for
pins using DRV_PCI driver @ LVDD = 4.75 V
0.5 V ≤ Vin ≤ 2.7 V
IL
4
4
2
2
Input leakage current for
all others
LVDD = 3.6 V
GVDD ≤ 3.465 V
IL
—
Output high voltage
IOH = driver-dependent
(GVDD = 3.3 V)
VOH
2.4
—
Output low voltage
IOL = driver-dependent
(GVDD = 3.3 V)
VOL
0.4
V
10
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Table 3. DC Electrical Specifications (continued)
At recommended operating conditions (see Table 2)
Characteristic
Condition 3
Symbol
Min
Max
Unit
Notes
Capacitance
Notes:
1. See Table 17 for pins with internal pull-up resistors.
Vin = 0 V, f = 1 MHz
Cin
—
16.0
pF
2. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with
that pin as listed in Table 17.
3. These specifications are for the default driver strengths indicated in Table 4.
4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is
measured for nominal OVDD/LVDD, and VDD or both OVDD/LVDD and VDD must vary in the same direction.
4.1.4 Output Driver Characteristics
Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values
are preliminary estimates from an IBIS model and are not tested.
Table 4. Drive Capability of MPC8245 Output Pins 5
Programmable
Supply
Driver Type
Output Impedance
IOH
IOL
Unit
Notes
Voltage
(Ω)
DRV_STD_MEM
20
40 (default)
20
OVDD = 3.3 V
36.6
18.6
12.0
6.1
18.0
9.2
mA
mA
mA
mA
mA
mA
mA
2, 4, 6
2, 4, 6
1, 3
DRV_PCI
12.4
6.3
40 (default)
6 (default)
20
1, 3
DRV_MEM_CTRL
DRV_PCI_CLK
DRV_MEM_CLK
Notes:
GVDD = 3.3 V
89.0
36.6
18.6
42.3
18.0
9.2
2, 4
2, 4
40
2, 4
1. For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolating
between the 0.3- and 0.4-V table entries’ current values that correspond to the PCI VOH = 2.97 = 0.9 × OVDD (OVDD
= 3.3 V) where table entry voltage = OVDD – PCI VOH
.
2. For all others with GVDD or OVDD = 3.3 V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the
0.9-V table entry that corresponds to the VOH = 2.4 V where table entry voltage = GVDD/OVDD – VOH
.
3. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V = PCI VOL = 0 × OVDD
(OVDD = 3.3 V) by interpolating between the 0.3- and 0.4-V table entries.
4. For all others with GVDD or OVDD = 3.3 V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the
0.4-V table entry.
5. See driver bit details for output driver control register (0x73) in the MPC8245 Integrated Processor User’s Manual.
6. See Chip Errata No. 19 in the MPC8245/MPC8241 RISC Microprocessor Chip Errata.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
11
Electrical and Thermal Characteristics
4.1.5 Power Characteristics
Table 5 provides power consumption data for the MPC8245.
Table 5. Power Consumption
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Mode
Unit Notes
66/66/266 66/133/266 66/66/300 66/100/300 33/83/333 66/133/333 66/100/350
Typical
Max—FP
Max—INT
Doze
1.7
(1.5)
2.0
(1.8)
1.8
(1.7)
2.0
(1.8)
2.0
2.6
2.2
1.4
0.5
0.3
2.3
2.8
2.4
1.6
0.7
0.4
2.2
2.8
2.4
1.5
0.6
0.3
W
W
W
W
W
W
1, 5
1, 2
2.2
(1.9)
2.4
(2.1)
2.3
(2.0)
2.5
(2.2)
1.8
(1.6)
2.1
(1.8)
2.0
(1.8)
2.1
(1.8)
1, 3
1.1
(1.0)
1.4
(1.3)
1.2
(1.1)
1.4
(1.3)
1, 4, 6
1, 4, 6
1, 4, 6
Nap
0.4
(0.4)
0.7
(0.7)
0.4
(0.4)
0.6
(0.6)
Sleep
0.2
0.4
0.2
0.3
(0.2)
(0.4)
(0.4)
(0.3)
I/O Power Supplies 10
Mode
Min
Max
Unit Notes
Typ—OVDD
Typ—GVDD
Notes:
134 (121)
324 (292)
334 (301)
mW
mW
7, 8
7, 9
800 (720)
1. The values include VDD, AVDD, and AVDD2 but do not include I/O supply power. Information on OVDD and GVDD
supply power is captured in the I/O power supplies section of this table. Values shown in parenthesis ( ) indicate
power consumption at VDD/AVDD/AVDD2 = 1.8 V.
2. Maximum—FP power is measured at VDD = 2.1 V with dynamic power management enabled while running an
entirely cache-resident, looping, floating-point multiplication instruction.
3. Maximum—INT power is measured at VDD = 2.1 V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at VDD = 2.1 V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at VDD = AVDD = 2.0 V, OVDD = 3.3 V where a nominal FP value, a nominal INT value,
and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries
to local memory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the MPC8245 performing cache resident integer operations
at the slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8. The typical maximum OVDD value resulted from the MPC8245 operating at the fastest frequency combination of
66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros
to PCI memory.
9. The typical maximum GVDD value resulted from the MPC8245 operating at the fastest frequency combination of
66:100:350 (PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros
on 64-bit boundaries to local memory.
10.Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW. Guaranteed by design and not tested.
12
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
4.2 Thermal Characteristics
Table 6 provides the package thermal characteristics for the MPC8245. For further information, see
Section 7.8, “Thermal Management Information.”
Table 6. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection
(Single-layer board—1s)
R
16.1
°C/W
1, 2
JA
θ
Junction-to-ambient natural convection
(Four-layer board—2s2p)
R
12.0
11.6
9.0
°C/W
°C/W
°C/W
1, 3
1, 3
1, 3
JMA
JMA
JMA
θ
θ
θ
Junction-to-ambient (@200 ft/min)
(Single-layer board—1s)
R
R
Junction-to-ambient (@200 ft/min)
(Four layer board—2s2p)
Junction-to-board
R
4.8
1.8
1.0
°C/W
°C/W
°C/W
4
5
6
JB
JC
θ
Junction-to-case
R
θ
Junction-to-package top (natural convection)
ΨJT
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate used for case temperature.
6. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
4.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC8245. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Table 7 and tested for conformance to the AC
specifications for that frequency. The processor core frequency is determined by the bus (PCI_SYNC_IN)
clock frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency. See Section 9, “Ordering Information,” for more details on ordering parts.
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Electrical and Thermal Characteristics
Table 7 provides the operating frequency information for the MPC8245 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V.
DD
Table 7. Operating Frequency 1
266 MHz 300 MHz 333 MHz
VDD/AVDD/AVDD2 = 1.7–2.1 V VDD/AVDD/AVDD2 = 1.9–2.2 V
350 MHz
Characteristic 2, 3
Unit
Processor frequency
(CPU)
100–266
50–133
100–300
50–100 4
100–333
50–133
100–350
50–100 4
MHz
Memory bus frequency
PCI input frequency
Notes:
MHz
MHz
25–66
1. See part number specification document MPC8245RZUPNS for additional part offering information.
2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting
peripheral logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configurations,”
for valid PLL_CFG[0:4] settings and PCI_SYNC_IN frequencies.
3. See Table 18 and Table 19 for more details on VCO limitations for memory and CPU VCO frequencies of various
PLL configurations.
4. There are no available PLL_CFG[0:4] settings that support 133-MHz memory interface operation at 300-MHz and
350-MHz CPU operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running
these parts at slower processor speeds may produce ratios that will run above 100 MHz. See Table 18 for the PLL
settings.
4.3.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in
Section 4.3.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths
indicated in Table 4.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V
DD
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1
Frequency of operation (PCI_SYNC_IN)
25
—
40
6
66
2.0
60
MHz
ns
%
2, 3 PCI_SYNC_IN rise and fall times
1
4
PCI_SYNC_IN duty cycle measured at 1.4 V
PCI_SYNC_IN pulse width high measured at 1.4 V
PCI_SYNC_IN pulse width low measured at 1.4 V
PCI_SYNC_IN jitter
5a
5b
7
9
ns
ns
ps
ps
ps
µs
ns
2
2
6
9
—
—
—
—
200
250
190
100
8a
8b
10
15
PCI_CLK[0:4] skew (pin-to-pin)
SDRAM_CLK[0:3] skew (pin-to-pin)
Internal PLL relock time
3
2, 4, 5
6
DLL lock range with DLL_EXTEND = 0
(disabled) and normal tap delay default
See Figure 7
14
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Electrical and Thermal Characteristics
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V
DD
Num
Characteristics and Conditions
DLL lock range for other modes
Min
Max
Unit
Notes
16
17
See Figure 8 through Figure 10
ns
MHz
ns
6
Frequency of operation (OSC_IN)
OSC_IN rise and fall times
25
—
40
—
66
5
19
7
20
OSC_IN duty cycle measured at 1.4 V
OSC_IN frequency stability
60
100
%
21
ppm
Notes:
1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin-to-pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). Tclk is
the period of one SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propagation delay of the DLL synchronization
feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length
(unloaded PC board runner) corresponds to approximately 1 ns of delay. For details about how Figure 7 through
Figure 10 may be used refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory Clock Design
Guidelines, for details about memory clock design on the MPC8245.
7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall
times are not tested.
Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in
Table 8.
1
5a
5b
2
3
VM
VM
VM
PCI_SYNC_IN
VM = Midpoint Voltage (1.4 V)
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation. These
graphs define the areas of DLL locking for various modes. The gray areas show where the DLL will lock.
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Electrical and Thermal Characteristics
Register settings that define each DLL mode are shown in Table 9.
Table 9. DLL Mode Definition
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
DLL Mode
Register at 0x72
Normal tap delay,
No DLL extend
0
0
1
1
0
Normal tap delay,
DLL extend
1
0
1
Max tap delay,
No DLL extend
Max tap delay,
DLL extend
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points. Refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory
Clock Design Guidelines, for details on memory design.
16
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MOTOROLA
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=0
and Normal Tap Delay
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Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=1
and Normal Tap Delay
18
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MOTOROLA
Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=0
and Max Tap Delay
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Electrical and Thermal Characteristics
30
27.5
25
22.5
20
17.5
15
12.5
10
7.5
0
1
2
3
4
5
Tloop Propagation Delay Time (ns)
Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend=1
and Max Tap Delay
4.3.2 Input AC Timing Specifications
Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2)
with LV = 3.3 V ± 0.3 V.
DD
Table 10. Input AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
10a PCI input signals valid to PCI_SYNC_IN (input setup)
3.0
—
ns
1, 3
10b Memory input signals valid to sys_logic_clk (input setup)
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Table 10. Input AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
10b0 Tap 0, register offset <0x77>, bits 5–4 = 0b00
10b1 Tap 1, register offset <0x77>, bits 5–4 = 0b01
10b2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)
10b3 Tap 3, register offset <0x77>, bits 5–4 = 0b11
2.6
1.9
1.2
0.5
3.0
—
—
—
—
—
ns
2, 3, 6
10c
PIC, misc. debug input signals valid to sys_logic_clk
ns
2, 3
(input setup)
10d I2C input signals valid to sys_logic_clk (input setup)
3.0
—
—
ns
ns
2, 3
10e Mode select inputs valid to HRST_CPU/HRST_CTRL (input
setup)
9 × tCLK
2, 3–5
11
Tos—SDRAM_SYNC_IN to sys_logic_clk offset time
sys_logic_clk to memory signal inputs invalid (input hold)
0.65
1.0
ns
ns
7
11a
11a0 Tap 0, register offset <0x77>, bits 5–4 = 0b00
11a1 Tap 1, register offset <0x77>, bits 5–4 = 0b01
11a2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)
11a3 Tap 3, register offset <0x77>, bits 5–4 = 0b11
0
—
—
—
—
—
2, 3, 6
0.7
1.4
2.1
0
11b
HRST_CPU/HRST_CTRL to mode select inputs invalid (input
hold)
ns
ns
2, 3, 5
1, 2, 3
11c
PCI_SYNC_IN to Inputs invalid (input hold)
1.0
—
Notes:
1. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in
question for 3.3-V PCI signaling levels. See Figure 12.
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the
signal in question to the VM = 1.4 V of the rising edge of the memory bus clock, sys_logic_clk. sys_logic_clk is the
same as PCI_SYNC_IN in 1:1 mode but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. Input timings are measured at the pin.
4. tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question
to the VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming
bits 5–4 of register offset <0x77> to select the desired input setup and hold times.
7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay
present on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM
clocks become offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN must be shortened by this amount relative to the SDRAM clock output trace lengths to maintain
phase-alignment of the memory clocks with respect to sys_logic_clk. Note that the DLL locking range graphs of
Figure 7 through Figure 10 compensate for Tos, and there is no additional requirement to shorten Tloop by the
duration of Tos. Refer to the Motorola application note AN2164, MPC8245/MPC8241 Memory Clock Design
Guidelines, for more details on accommodating for the problem of Tos and trace measurements in general.
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Electrical and Thermal Characteristics
Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and
PCI_SYNC_IN, respectively.
VM
PCI_SYNC_IN
VM
VM
sys_logic_clk
VM
T
os
SDRAM_SYNC_IN
(after DLL locks
VM
if no compensation
for Tos is made)
Shown in 2:1 Mode
10b-d
13b
14b
11a
12b-d
2.0 V
2.0 V
Memory
Inputs/Outputs
0.8 V
0.8 V
Output Timing
Input Timing
Notes:
VM = Midpoint voltage (1.4 V).
10b-d = Input signals valid timing.
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = SDRAM_SYNC_IN to output valid timing.
13b = Output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
Tos = Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to be seen
before sys_logic_clk once the DLL locks if no other accommodation is made for the delay.
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
OVDD ÷ 2
OVDD ÷ 2
OVDD ÷ 2
PCI_SYNC_IN
10a
13a
14a
12a
11c
0.615 × OVDD
0.285 × OVDD
PCI
Inputs/Outputs
0.4 × OVDD
Input Timing
Output Timing
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
22
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Electrical and Thermal Characteristics
Figure 13 shows the input timing diagram for mode select signals.
VM
HRST_CPU/HRST_CTRL
10e
11b
2.0 V
0.8 V
Mode Pins
VM = Midpoint Voltage (1.4 V)
Figure 13. Input Timing Diagram for Mode Select Signals
4.3.3 Output AC Timing Specification
Table 11 provides the processor bus AC timing specifications for the MPC8245 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V. See Figure 11 for the input/output timing diagram
DD
referenced to sys_logic_clk. All output timings assume a purely resistive 50-Ω load (see Figure 14 for the AC
test load for the MPC8245). Output timings are measured at the pin; time-of-flight delays must be added for
trace lengths, vias, and connectors in the system. These specifications are for the default driver strengths
indicated in Table 4.
Table 11. Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
12a PCI_SYNC_IN to output valid, see Figure 15
12a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66 MHz PCI (default)
12a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10
—
—
—
—
—
6.0
6.5
7.0
7.5
4.5
ns
1, 3
12a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33 MHz PCI
12a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CKE] = 00
12b sys_logic_clk to output valid (memory control, address, and data
ns
2
signals)
12c
sys_logic_clk to output valid (for all others)
—
—
—
7.0
5.0
6.0
ns
ns
ns
2
2
2
12d sys_logic_clk to output valid (for I2C)
12e sys_logic_clk to output valid (ROM/Flash/PortX)
13a Output hold (PCI), see Figure 15
13a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66-MHz PCI (default)
13a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10
13a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33-MHz PCI
13a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CKE] = 00
13b Output hold (all others)
2.0
2.5
3.0
3.5
1.0
—
—
—
ns
1, 3, 4
—
—
—
ns
ns
2
14a PCI_SYNC_IN to output high impedance (for PCI)
14.0
1, 3
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Electrical and Thermal Characteristics
Table 11. Output AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
14b sys_logic_clk to output high impedance (for all others)
Notes:
—
4.0
ns
2
1. All PCI signals are measured from GVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD
of the signal in question for 3.3 V PCI signaling levels. See Figure 12.
2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of
the memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the
same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising
edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 11.
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP,
DEVSEL, PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.
4. In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI
systems, the MPC8245 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid
timing is also affected). The initial value of the output hold delay is determined by the values on the MCP and CKE
reset configuration signals; the values on these two signals are inverted and stored as the initial settings of
PCI_HOLD_DEL = PMCR2[5:4] (power management configuration register 2 <0x72>), respectively. Since MCP
and CKE have internal pull-up resistors, the default value of PCI_HOLD_DEL after reset is 0b00. Further output
hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register.
Figure 15 shows the PCI_HOLD_DEL effect on output valid and hold time.
Output Measurements are Made at the Device Pin
OVDD/2 for PCI
Z0 = 50 Ω
Output
GVDD/2 for Memory
RL = 50 Ω
Figure 14. AC Test Load for the MPC8245
24
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
Electrical and Thermal Characteristics
OVDD/2
OVDD/2
PCI_SYNC_IN
12a2, 7.0 ns for 33 MHz PCI
PCI_HOLD_DEL = 10
13a2, 2.1 ns for 33-MHz PCI
PCI_HOLD_DEL = 10
PCI Inputs/Outputs
33 MHz PCI
12a0, 6.0 ns for 66 MHz PCI
PCI_HOLD_DEL = 00
13a0, 1 ns for 66-MHz PCI
PCI_HOLD_DEL = 00
PCI Inputs/Outputs
66 MHz PCI
As PCI_HOLD_DEL
Values Decrease
PCI Inputs
and Outputs
As PCI_HOLD_DEL
Values Increase
Output Valid
Output Hold
Note: Diagram not to scale.
Figure 15. PCI_HOLD_DEL Effect on Output Valid and Hold Time
2
4.3.4 I C AC Timing Specifications
2
Table 12 provides the I C input AC timing specifications for the MPC8245 at recommended operating
conditions (see Table 2) with LV = 3.3 V ± 0.3 V.
DD
Table 12. I2C Input AC Timing Specifications
Num
Characteristic
Start condition hold time
Min
Max
Unit
Notes
1
2
4.0
—
—
CLKs
1, 2
Clock low period
8.0 + (16 × 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
CLKs 1, 2, 4, 5
(time before the MPC8245 will drive SCL
low as a transmitting slave after detecting
SCL low as driven by an external master)
3
4
SCL/SDA rise time (from 0.5 V to 2.4 V)
Data hold time
—
0
1
ms
ns
—
2
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Electrical and Thermal Characteristics
Table 12. I2C Input AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
5
6
SCL/SDA fall time (from 2.4 V to 0.5 V)
—
1
ms
Clock high period
5.0
—
CLKs
1, 2, 5
(time needed to either receive a data bit or
generate a START or STOP)
7
8
Data setup time
3.0
4.0
—
—
ns
3
Start condition setup time (for repeated
start condition only)
CLKs
1,2
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The
qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 17 for the I2C timing diagram II.
3. Timing is relative to the sampling clock (not SCL).
4. FDR[x] refers to the frequency divider register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)
determine the maximum I2C input frequency. See Table 13 for more information.
2
Table 13 provides the I C frequency divider register (I2CFDR) information for the MPC8245.
Table 13. MPC8245 Maximum I2C Input Frequency
Max I2C Input Frequency 1
FDR
Divider 2
(Dec)
Hex 2
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK
@ 100 MHz
SDRAM_CLK
@ 133 MHz
20, 21
22, 23, 24, 25
0, 1
160, 192
224, 256, 320, 384
288, 320
1.13 MHz
733
1.72 MHz
1.11 MHz
819
3.44 MHz
2.22 MHz
1.63 MHz
1.29 MHz
4.58 MHz
2.95 MHz
2.18 MHz
1.72 MHz
540
2, 3, 26, 27, 28, 384, 448, 480, 512, 640,
428
649
29
768
4, 5
576, 640
302
234
458
354
917
709
1.22 MHz
943
6, 7, 2A, 2B, 2C,
2D
768, 896, 960, 1024,
1280, 1536
8, 9
1152, 1280
160
122
243
185
487
371
648
494
A, B, 2E,
2F, 30, 31
1536, 1792, 1920,
2048, 2560, 3072
C, D
2304, 2560
83
62
125
95
251
190
335
253
E, F, 32,
33, 34, 35
3072, 3584, 3840,
4096, 5120, 6144
10, 11
4608, 5120
42
64
128
170
26
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
Electrical and Thermal Characteristics
Table 13. MPC8245 Maximum I2C Input Frequency (continued)
Max I2C Input Frequency 1
FDR
Divider 2
(Dec)
Hex 2
SDRAM_CLK
@ 33 MHz
SDRAM_CLK
@ 50 MHz
SDRAM_CLK
@ 100 MHz
SDRAM_CLK
@ 133 MHz
12, 13, 36,
37, 38, 39
6144, 7168, 7680,
8192, 10240, 12288
31
48
96
128
14, 15
9216, 10240
21
16
32
24
64
48
85
64
16, 17, 3A,
3B, 3C, 3D
12288, 14336, 15360,
16384, 20480, 24576
18, 19
18432, 20480
10
8
16
12
32
24
43
32
1A, 1B,
3E, 3F
24576, 28672,
30720, 32768
1C, 1D
1E, 1F
36864, 40960
49152, 61440
5
4
8
6
16
12
21
16
Notes:
1. Values are in KHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple divider (Dec) values generate the same input frequency, but each divider (Dec) value generates a unique
output frequency as shown in Table 14.
2
Table 14 provides the I C output AC timing specifications for the MPC8245 at recommended operating
2
conditions (see Table 2) with LV = 3.3 V ± 0.3 V. Figure 16 through 19 show the I C timing diagrams.
DD
Table 14. I2C Output AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) × (DFDR/16)/2N +
(FDR[5] == 1) × (DFDR/16)/2M
—
CLKs
1, 2, 3
2
3
Clock low period
DFDR/2
—
—
—
CLKs
ms
1, 2, 3
4
SCL/SDA rise time
(from 0.5 V to 2.4 V)
4
Data hold time
8.0 + (16 × 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1, 2, 3
5
SCL/SDA fall time
—
< 5
ns
5
(from 2.4 V to 0.5 V)
6
7
Clock high time
DFDR/2
—
—
CLKs
CLKs
1, 2, 3
1, 3
Data setup time
(DFDR/2) – (output data hold time)
(MPC8245 as a master only)
8
Start condition setup time
DFDR + (output start condition hold time)
—
CLKs
1, 2, 3
(for repeated start condition only)
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
27
Electrical and Thermal Characteristics
Table 14. I2C Output AC Timing Specifications (continued)
Num
Characteristic
Min
Max
Unit
Notes
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The
qualified SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 17.
3. DFDR is the decimal divider number indexed by the value of FDR[5:0]. Refer to Table 10-5 in the MPC8245
Integrated Processor User’s Manual. FDR[x] refers to bit x of the frequency divider register I2CFDR. N is equal to
a variable number that would make the result of the divide (data hold time value) equal to a number less than 16.
M is equal to a variable number that would make the result of the divide (data hold time value) equal to a number
less than 9.
4. Since SCL and SDA are open-drain type outputs, which the MPC8245 can only drive low, the time required for SCL
or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
5. Specified at a nominal 50-pF load.
2
VM
VM
SCL
SDA
6
4
1
Figure 16. I2C Timing Diagram I
3
5
VH
VM
SCL
SDA
VL
8
9
Figure 17. I2C Timing Diagram II
DFFSR Filter Clock
SDA
7
Input Data Valid
Note: DFFSR filter clock is the SDRAM_CLK clock times DFFSR value.
Figure 18. I2C Timing Diagram III
28
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
VM
SCL/SDArealtime
Delay
SCL/SDAqualified
VM
Note: The delay is the local memory clock times DFFSR times two plus one local memory clock.
Figure 19. I2C Timing Diagram IV (Qualified Signal)
4.3.5 PIC Serial Interrupt Mode AC Timing Specifications
Table 15 provides the PIC serial interrupt mode AC timing specifications for the MPC8245 at recommended
operating conditions (see Table 2) with GV = 3.3 V ± 5% and LV = 3.3 V ± 0.3 V.
DD
DD
Table 15. PIC Serial Interrupt Mode AC Timing Specifications
Num
Characteristic
S_CLK frequency
Min
Max
Unit
Notes
1
2
3
4
5
6
7
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
%
1
—
—
—
2
S_CLK duty cycle
40
60
S_CLK output valid time
Output hold time
—
6
ns
0
—
ns
S_FRAME, S_RST output valid time
S_INT input setup time to S_CLK
—
1 sys_logic_clk period + 6
ns
1 sys_logic_clk period + 2
—
0
ns
2
S_INT inputs invalid (hold time) to
S_CLK
—
ns
2
Notes:
1. See the MPC8245 Integrated Processor User’s Manual for a description of the PIC interrupt control register (ICR)
describing S_CLK frequency programming.
2. S_RST, S_FRAME and S_INT shown in Figure 20 and Figure 21, depict timing relationships to sys_logic_clk and
S_CLK and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the MPC8245
Integrated Processor User’s Manual for a complete description of the functional relationships between these
signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral
logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN
feedback loop is implemented and the DLL is locked. See the MPC8245 Integrated Processor User’s Manual for a
complete clocking description.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
29
Electrical and Thermal Characteristics
VM
VM
VM
sys_logic_clk
3
4
VM
S_CLK
VM
5
4
S_FRAME
S_RST
VM
VM
Figure 20. PIC Serial Interrupt Mode Output Timing Diagram
VM
S_CLK
S_INT
7
6
Figure 21. PIC Serial Interrupt Mode Input Timing Diagram
4.3.6 IEEE 1149.1 (JTAG) AC Timing Specifications
Table 16 provides the JTAG AC timing specifications for the MPC8245 while in the JTAG operating mode
at recommended operating conditions (see Table 2) with LV = 3.3 V ± 0.3 V. Timings are independent of
DD
the system clock (PCI_SYNC_IN).
Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
Num
Characteristic
TCK frequency of operation
Min
Max
Unit
Notes
0
40
20
0
25
—
—
3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
TCK cycle time
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
3
4
TRST setup time to TCK falling edge
TRST assert time
10
10
5
—
—
—
—
30
30
—
—
1
5
6
Input data setup time
2
2
3
3
7
Input data hold time
15
0
8
TCK to output data valid
TCK to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
9
0
10
11
5
15
30
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) (continued)
Num
Characteristic
Min
Max
Unit
Notes
12
13
TCK to TDO data valid
TCK to TDO high impedance
0
0
15
15
ns
ns
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest (other than TDO) signal output timing with respect to TCK.
Figure 22 through 25 show the different timing diagrams.
1
2
2
VM
VM
VM
TCK
3
3
VM = Midpoint Voltage
Figure 22. JTAG Clock Input Timing Diagram
TCK
4
TRST
5
Figure 23. JTAG TRST Timing Diagram
TCK
6
7
Data Inputs
Data Outputs
Data Outputs
Input Data Valid
8
9
Output Data Valid
Figure 24. JTAG Boundary Scan Timing Diagram
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
31
Package Description
TCK
10
11
TDI, TMS
Input Data Valid
12
13
TDO
TDO
Output Data Valid
Figure 25. Test Access Port Timing Diagram
5 Package Description
This section details package parameters, pin assignments, and dimensions.
5.1 Package Parameters for the MPC8245
The MPC8245 uses a 35 mm × 35 mm, cavity-up, 352-pin tape ball grid array (TBGA) package. The
package parameters are as follows.
Package Outline
Interconnects
Pitch
35 mm × 35 mm
352
1.27 mm
Solder Balls
ZU (TBGA package)—62 Sn/36 Pb/2 Ag
VV (Lead free version of package)—95.5 Sn/4.0 Ag/0.5 Cu
Solder Ball Diameter
Maximum Module Height
Co-Planarity Specification
Maximum Force
0.75 mm
1.65 mm
0.15 mm
6.0 lbs. total, uniformly distributed over package (8 grams/ball)
32
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
5.2 Pin Assignments and Package Dimensions
Figure 26 shows the top surface, side profile, and pinout of the MPC8245, 352 TBGA package.
– F –
B
CORNER
– E –
– T –
0.150 T
A
MIN
34.8
34.8
1.45
.60
MAX
35.2
35.2
1.65
.90
A
B
C
D
G
H
K
L
Top View
1.27 BASIC
.85 .95
31.75 BASIC
.50 .70
26 24 22 20 18 16 14 12 10 8
25 23 21 19 17 15 13 11
6
4
2
9
7
5
3
1
A
C
E
G
J
B
D
F
H
K
M
P
T
L
N
R
U
W
K
V
Y
AA
C
AB
AC
AD
AE
AF
H
L
Bottom View
G
352X ∅ D
K
Notes:
1. Drawing not to scale.
2. All measurements are in millimeters (mm).
Figure 26. MPC8245 Package Dimensions and Pinout Assignments
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
33
Package Description
5.3 Pinout Listings
Table 17 provides the pinout listing for the MPC8245, 352 TBGA package.
Table 17. MPC8245 Pinout Listing
Power
Supply
Output
Driver Type
Name
Pin Numbers
Type
Notes
PCI Interface Signals
C/BE[3:0]
P25 K23 F23 A25
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
—
6, 15
8, 15
8, 15
8, 15
8
DEVSEL
FRAME
IRDY
H26
J24
K25
J26
I/O
I/O
LOCK
Input
I/O
AD[31:0]
V25 U25 U26 U24 U23
T25 T26 R25 R26 N26
N25 N23 M26 M25 L25
L26 F24 E26 E25 E23
D26 D25 C26 A26 B26
A24 B24 D19 B23 B22
D22 C22
DRV_PCI
6, 15
PAR
G25
I/O
Output
Output
Input
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
DRV_PCI
DRV_PCI
DRV_PCI
—
15
GNT[3:0]
GNT4/DA5
REQ[3:0]
REQ4/DA4
PERR
W25 W24 W23 V26
6, 15
W26
7, 15, 14
6, 12
Y25 AA26 AA25 AB26
Y26
G26
F26
—
12, 14
8, 15, 18
8, 15, 16
8, 15
I/O
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
DRV_PCI
SERR
I/O
STOP
H25
K26
AC26
I/O
TRDY
I/O
8, 15
INTA
Output
10, 15,
16
IDSEL
P26
Input
OVDD
—
Memory Interface Signals
MDL[0:31]
AD17 AE17 AE15 AF15 I/O GVDD
DRV_STD_MEM
5, 6
AC14 AE13 AF13 AF12
AF11 AF10 AF9 AD8 AF8
AF7 AF6 AE5 B1 A1 A3
A4 A5 A6 A7 D7 A8 B8
A10 D10 A12 B11 B12
A14
34
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
Table 17. MPC8245 Pinout Listing (continued)
Power
Output
Driver Type
Name
MDH[0:31]
Pin Numbers
Type
Notes
Supply
AC17 AF16 AE16 AE14
AF14 AC13 AE12 AE11
AE10 AE9 AE8 AC7 AE7
AE6 AF5 AC5 E4 A2 B3
D4 B4 B5 D6 C6 B7 C9
A9 B10 A11 A13 B13 A15
I/O
GVDD
DRV_STD_MEM
6
DQM[0:7]
CS[0:7]
AB1 AB2 K3 K2 AC1 AC2
K1 J1
Output
Output
GVDD
GVDD
DRV_MEM_CTRL
DRV_MEM_CTRL
6
6
Y4 AA3 AA4 AC4 M2 L2
M1 L1
FOE
H1
I/O
GVDD
GVDD
GVDD
OVDD
GVDD
GVDD
GVDD
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
6 ohms
3, 4
3, 4
RCS0
N4
Output
Output
I/O
RCS1
N2
RCS2/TRIG_IN
RCS3/TRIG_OUT
SDMA[1:0]
SDMA[11:2]
AF20
AC18
W1 W2
10, 14
14
Output
I/O
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
3, 4, 6
6
N1 R1 R2 T1 T2 U4 U2
U1 V1 V3
Output
DRDY
B20
B16
B14
D14
Input
I/O
OVDD
GVDD
GVDD
GVDD
—
9, 10
10, 14
10, 14
10, 14
SDMA12/SRESET
SDMA13/TBEN
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
I/O
SDMA14/
I/O
CHKSTOP_IN
SDBA1
SDBA0
PAR[0:7]
P1
P2
Output
Output
I/O
GVDD
GVDD
GVDD
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_STD_MEM
AF3 AE3 G4 E2 AE4 AF4
D2 C2
6
SDRAS
SDCAS
CKE
AD1
AD2
H2
Output
Output
Output
Output
Output
GVDD
GVDD
GVDD
GVDD
GVDD
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_MEM_CTRL
3
3
3, 4
WE
AA1
Y1
AS
3, 4
PIC Control Signals
IRQ0/S_INT
IRQ1/S_CLK
IRQ2/S_RST
C19
Input
I/O
OVDD
OVDD
OVDD
—
B21
DRV_PCI
DRV_PCI
AC22
I/O
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
35
Package Description
Table 17. MPC8245 Pinout Listing (continued)
Power
Output
Driver Type
Name
Pin Numbers
Type
Notes
Supply
IRQ3/S_FRAME
IRQ4/L_INT
AE24
I/O
I/O
OVDD
OVDD
DRV_PCI
DRV_PCI
A23
I2C Control Signals
SDA
SCL
AE20
AF21
I/O
I/O
OVDD
OVDD
DRV_STD_MEM
DRV_STD_MEM
10, 16
10, 16
DUART Control Signals
SOUT1/PCI_CLK0
SIN1/PCI_CLK1
AC25
AB25
Output
I/O
GVDD
GVDD
DRV_PCI_CLK
DRV_PCI_CLK
13, 14
13, 14,
26
SOUT2/RTS1/
PCI_CLK2
AE26
AF25
Output
I/O
GVDD
GVDD
DRV_PCI_CLK
DRV_PCI_CLK
13, 14
SIN2/CTS1/
PCI_CLK3
13, 14,
26
Clock-Out Signals
PCI_CLK0/SOUT1
PCI_CLK1/SIN1
AC25
AB25
Output
I/O
GVDD
GVDD
DRV_PCI_CLK
DRV_PCI_CLK
13, 14
13, 14,
26
PCI_CLK2/RTS1/
SOUT2
AE26
AF25
Output
I/O
GVDD
GVDD
DRV_PCI_CLK
DRV_PCI_CLK
13, 14
PCI_CLK3/CTS1/
SIN2
13, 14,
26
PCI_CLK4/DA3
PCI_SYNC_OUT
PCI_SYNC_IN
AF26
AD25
AB23
Output
Output
Input
GVDD
GVDD
GVDD
GVDD
DRV_PCI_CLK
DRV_PCI_CLK
—
13, 14
SDRAM_CLK [0:3]
D1 G1 G2 E1
Output
DRV_MEM_CTRL
or
DRV_MEM_CLK
6, 21
21
SDRAM_SYNC_OUT C1
Output
GVDD
DRV_MEM_CTRL
or
DRV_MEM_CLK
SDRAM_SYNC_IN
CKO/DA1
H3
Input
Output
Input
GVDD
OVDD
OVDD
—
DRV_STD_MEM
—
B15
AD21
14
19
OSC_IN
Miscellaneous Signals
HRST_CTRL
HRST_CPU
A20
A19
Input
Input
OVDD
OVDD
—
—
36
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
Table 17. MPC8245 Pinout Listing (continued)
Power
Output
Driver Type
Name
Pin Numbers
Type
Notes
Supply
MCP
NMI
SMI
A17
D16
A18
B16
B14
F2
Output
Input
Input
I/O
OVDD
OVDD
OVDD
GVDD
GVDD
OVDD
GVDD
DRV_STD_MEM
—
3, 4, 17
—
10
SRESET/SDMA12
TBEN/SDMA13
QACK/DA0
DRV_MEM_CTRL
DRV_MEM_CTRL
DRV_STD_MEM
DRV_MEM_CTRL
10, 14
10, 14
4, 14, 25
10, 14
I/O
Output
I/O
CHKSTOP_IN/
SDMA14
D14
TRIG_IN/RCS2
TRIG_OUT/RCS3
MAA[0:2]
AF20
AC18
I/O
OVDD
GVDD
GVDD
OVDD
OVDD
—
10, 14
14
Output
Output
Output
Output
DRV_MEM_CTRL
DRV_STD_MEM
—
AF2 AF1 AE1
A16
3, 4, 6
24
MIV
PMAA[0:1]
AD18 AF18
DRV_STD_MEM
3, 4, 6,
15
PMAA[2]
AE19
Output
OVDD
DRV_STD_MEM
DRV_STD_MEM
4, 6, 15
Test/Configuration Signals
PLL_CFG[0:4]/
DA[10:6]
A22 B19 A21 B18 B17
I/O
OVDD
6, 14, 20
TEST0
RTC
TCK
AD22
Y2
Input
Input
Input
Input
Output
Input
Input
OVDD
GVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
1, 9
11
AF22
AF23
AC21
AE22
AE23
9, 12
9, 12
24
TDI
TDO
TMS
TRST
9, 12
9, 12
Power and Ground Signals
GND
AA2 AA23 AC12 AC15 Ground
—
—
AC24 AC3 AC6 AC9
AD11 AD14 AD16 AD19
AD23 AD4 AE18 AE2
AE21 AE25 B2 B25 B6
B9 C11 C13 C16 C23 C4
C8 D12 D15 D18 D21
D24 D3 F25 F4 H24 J25
J4 L24 L3 M23 M4 N24
P3 R23 R4 T24 T3 V2
V23 W3
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
37
Package Description
Table 17. MPC8245 Pinout Listing (continued)
Power
Output
Driver Type
Name
Pin Numbers
Type
Notes
Supply
LVDD
AC20 AC23 D20 D23
G23 P23 Y23
Reference
voltage
3.3 V, 5.0 V
LVDD
—
—
GVDD
AB3 AB4 AC10 AC11
AC8 AD10 AD13 AD15
AD3 AD5 AD7 C10 C12
C3 C5 C7 D13 D5 D9 E3
G3 H4 K4 L4 N3 P4 R3
U3 V4 Y3
Power for
memory drivers
3.3 V
GVDD
OVDD
AB24 AD20 AD24 C14
C20 C24 E24 G24 J23
K24 M24 P24 T23 Y24
PCI/Stnd 3.3 V
OVDD
—
—
VDD
AA24 AC16 AC19 AD12
AD6 AD9 C15 C18 C21
D11 D8 F3 H23 J3 L23
M3 R24 T4 V24 W4
Power for core
1.8/2.0 V
VDD
22
No Connect
AVDD
D17
C17
—
—
—
—
23
22
Power for PLL
(CPU core logic)
1.8/2.0 V
AVDD
AVDD2
AF24
Power for PLL
(peripheral
logic)
AVDD
2
—
22
1.8/2.0 V
Debug/Manufacturing Pins
DA0/QACK
DA1/CKO
DA2
F2
Output
Output
Output
Output
I/O
OVDD
OVDD
DRV_STD_MEM
DRV_STD_MEM
DRV_PCI
4, 10, 25
14
B15
C25
OVDD
GVDD
OVDD
OVDD
OVDD
2
DA3/PCI_CLK4
DA4/REQ4
DA5/GNT4
AF26
DRV_PCI_CLK
—
14
Y26
12, 14
7, 15, 14
6, 14, 20
W26
Output
I/O
DRV_PCI
DA[10:6]/
A22 B19 A21 B18 B17
DRV_STD_MEM
PLL_CFG[0:4]
DA[11]
AD26
Output
Output
OVDD
OVDD
DRV_PCI
2
DA[12:13]
AF17 AF19
DRV_STD_MEM
2, 6
38
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Package Description
Table 17. MPC8245 Pinout Listing (continued)
Power
Output
Driver Type
Name
Pin Numbers
Type
Notes
Supply
DA[14:15]
Notes:
1. Place a pull-up resistor of 120 Ω or less on the TEST0 pin.
2. Treat these pins as no connects (NC) unless using debug address functionality.
F1 J2
Output
GVDD
DRV_MEM_CTRL
2, 6
3. This pin has an internal pull-up resistor that is enabled only when the MPC8245 is in the reset state. The value of
the internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits
during reset if the signal is left unterminated.
4. This pin is a reset configuration pin.
5. DL[0] is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8245 is in
the reset state. The value of the internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is
read into configuration bits during reset.
6. Multi-pin signals such as AD[31:0] and MDL[0:31] have their physical package pin numbers listed in order
corresponding to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22,..., AD31 is on pin V25.
7. GNT4 is a reset configuration pin and has an internal pull-up resistor that is enabled only when the MPC8245 is in
the reset state.
8. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this PCI control pin to LVDD
.
9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 3.
10.Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD
11.Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to GVDD
.
.
12.This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not
guaranteed but is sufficient to prevent unused inputs from floating.
13.External PCI clocking source or fan-out buffer may be required for system if using the MPC8245 DUART
functionality since PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.
14.This pin is a multiplexed signal and appears more than once in this table.
15.This pin is affected by programmable PCI_HOLD_DEL parameter.
16.This pin is an open-drain signal.
17.This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open-drain.
18.This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.
19.OSC_IN utilizes the 3.3-V PCI interface driver which is 5-V tolerant, see Table 2 for details.
20.PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of
HRST_CTRL and HRST_CPU negate in order to be latched.
21.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals
use DRV_MEM_CLK for chip Rev 1.2 (B).
22.The 266- and 300-MHz part offerings can be run at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Note that
source voltage should be 2.0 ± 100 mV for 333- and 350-MHz parts.
23.This pin was formally LAVDD on the MPC8240. It is a NC on the MPC8245. This should not pose a problem when
replacing an MPC8240 with an MPC8245.
24.The driver capability of this pin is hardwired to 40 Ω and cannot be changed.
25.Motorola recommends that a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD so that a 1 may be
detected at reset if an external memory clock is not being used and PLL[0:4] does not select a half-clock frequency
ratio.
26.Motorola typically expects that customers using the serial port will have sufficient drivers available in the RS232
transceiver to drive the CTS pin actively as an input if they are using that mode. No pullups would be needed in this
circumstance.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
39
PLL Configurations
6 PLL Configurations
The internal PLLs of the MPC8245 are configured by the PLL_CFG[0:4] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory
bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e
CPU PLL (VCO) frequency of operation for memory-to-CPU frequency multiplying. The PLL
configurations for the MPC8245 are shown in Table 18 and Table 19.
Table 18. PLL Configurations (266- and 300-MHz Parts)
266-MHz Part 9
300-MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCIClock
Input
(PCI_
Ref.
No.
PLL_CFG
[0:4] 10,13
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Mem
(Mem
VCO)
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
0
1
2
3
4
6
0000012
0000112
0001011
0001111,14
0010012
0011015
0011114
25–355
25–295
75–105 188–263 25–405
75–88 225–264 25–335
50–59 225–266 5018–661
50–66 100–133 5017–661
50–92 100–184 25–464
Bypass
75–120 188–300
75–99 225–297
50–66 225–297
3 (2)
3 (2)
1 (4)
2.5 (2)
3 (2)
5018–595
5017–661
25–464
4.5 (2)
2 (4)
50–66 100–133 1 (Bypass)
50–92 100–184
Bypass
2 (4)
2 (4)
Bypass
7
606–661
60–66 180–198 606–661
60–66 180–198 1 (Bypass)
3 (2)
Rev B
7
0011114
Not available
Rev D
8
9
0100012
0100112
0101012
0101112
0110012
0110112
0111012
0111112
1000012
1000112
1001012
1001112
1010012
1010112
606–661
456–661
25–295
453–595
366–464
453–505
306–445
255
60–66 180–198 606–661
90–132 180–264 456–661
50–58 225–261 25–335
68–88 204–264 453–661
72–92 180–230 366–464
68–75 238–263 453–575
60–88 180–264 306–464
60–66 180–198
90–132 180–264
50–66 225–297
68–99 204–297
72–92 180–230
68–85 238–298
60–92 180–276
75–85 263–298
90–132 180–264
1 (4)
2 (2)
3 (2)
2 (2)
A
2 (4)
4.5 (2)
3 (2)
B
1.5 (2)
2 (4)
C
2.5 (2)
3.5 (2)
3 (2)
D
1.5 (2)
2 (4)
E
F
75
263
25–285
3 (2)
3.5 (2)
2 (2)
10
11
12
13
14
15
306–442,5 90–132 180–264 306–442
3 (2)
25–265
100–106 250–266 25–292 100–116 250–290
90–99 180–198 606–661
90–99 180–198
100 300
4 (2)
2.5 (2)
2 (2)
606–661
1.5 (2)
4 (2)
Not available
252
3 (2)
266–385
52–76 182–266 266–425
52–84 182–294
68–75 272–300
2 (4)
3.5 (2)
4 (2)
Not available
273–305
2.5 (2)
40
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
PLL Configurations
Table 18. PLL Configurations (266- and 300-MHz Parts) (continued)
266-MHz Part 9
300-MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCIClock
Input
(PCI_
Ref.
No.
PLL_CFG
[0:4] 10,13
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Mem
(Mem
VCO)
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
16
17
18
19
1A
1B
1C
1D
1011012
1011112
1100012
1100112
1101012
1101112
1110012
1110112
111108
25–335
25–335
50–66 200–264 25–375
100–132 200–264 25–332 100–132 200–264
50–74 200–296
2 (4)
4 (2)
4 (2)
2 (2)
3 (2)
2.5 (2)
4 (2)
3 (2)
3 (2)
2.5 (2)
Off
273–355
366–535
5018–661
343–445
443–595
486–661
68–88 204–264 273–405
72–106 180–265 366–592
50–66 200–264 5018–661
68–88 204–264 343–505
66–88 198–264 443–661
72–99 180–248 486–661
Not usable
68–100 204–300
72–118 180–295
50–66 200–264
68–100 204–300
66–99 198–297
72–99 180–248
Not usable
2.5 (2)
2 (2)
1 (4)
2 (2)
1.5 (2)
1.5 (2)
Off
1E
Rev B
1E
11110
333–385
66–76 231–266 333–425
66–84 231–294
2(2)
3.5(2)
Rev D
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
41
PLL Configurations
Table 18. PLL Configurations (266- and 300-MHz Parts) (continued)
266-MHz Part 9
300-MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCIClock
Input
(PCI_
Ref.
No.
PLL_CFG
[0:4] 10,13
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Mem
(Mem
VCO)
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
1F
111118
Not usable
Not usable
Off
Off
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2 Limited by maximum system memory interface operating frequency (100 MHz @ 300-MHz CPU).
3. Limited by minimum memory VCO frequency (133 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency.
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (800 MHz).
8. In clock-off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10.PLL_CFG[0:4] settings not listed are reserved.
11.Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not backward-compatible.
12.PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from or does not exist on the MPC8240 and may
not be fully backward-compatible.
13.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode.
15.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the
OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor
PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is
intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual
PLL bypass mode.
16.Limited by maximum system memory interface operating frequency (133 MHz @ 266-MHz CPU).
17.Limited by minimum CPU operating frequency (100 MHz).
18.Limited by minimum memory bus frequency (50 MHz).
Table 19. PLL Configurations (333- and 350-MHz Parts)
333 MHz Part 9
350 MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCI Clock
Input
(PCI_
PLL_
CFG
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Ref
Mem
(Mem
VCO)
[0:4] 10,13
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
0
0000012
25–4416
75–132 188–330 25–4416
75–132 188–330
3 (2)
2.5 (2)
42
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
PLL Configurations
Table 19. PLL Configurations (333- and 350-MHz Parts) (continued)
333 MHz Part 9
350 MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCI Clock
Input
(PCI_
PLL_
CFG
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Ref
Mem
(Mem
VCO)
[0:4] 10,13
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
1
2
3
4
6
0000112
0001011
25–375
75–111 225–333
25–385
75–114 225–342
50–66 225–297
3 (2)
1 (4)
3 (2)
4.5 (2)
2 (4)
5018–661
50–66 225–297 5018–661
50–66 100–133 5017–661
0001111,14 5017–661
50–66 100–133 1 (Bypass)
0010012
0011015
0011114
25–464
50–92 100–184
Bypass
25–464
50–92 100–184
Bypass
2 (4)
Bypass
2 (4)
7
606–661
60–66 180–198 606–661
60–66 180–198 1 (Bypass)
3 (2)
Rev B
7
0011114
Not available
25
100
350
4(2)
3.5(2)
Rev D
8
9
0100012
0100112
0101012
0101112
0110012
0110112
0111012
0111112
1000012
1000112
1001012
1001112
1010012
1010112
1011012
1011112
1100012
1100112
1101012
1101112
1110012
606–661
456–661
25–375
60–66 180–198 606–661
90–132 180–264 456–661
60–66 180–198
90–132 180–264
50–76 225–342
68–99 204–297
72–92 180–230
68–99 238–347
60–92 180–276
75–99 263–347
90–132 180–264
100–132 250–330
90–99 180–198
100–116 300–348
52–94 182–329
68–85 272–340
50–86 200–344
100–132 200–264
68–115 204–345
72–132 180–330
50–66 200–264
68–116 204–348
66–99 198–297
1 (4)
2 (2)
3 (2)
2 (2)
A
50–74 225–333
25–385
2 (4)
4.5 (2)
3 (2)
B
453–661
366–464
453–635
306–464
25–315
68–99 204–297 453–661
72–92 180–230 366–464
68–95 238–333 453–661
60–92 180–276 306–464
1.5 (2)
2 (4)
C
2.5 (2)
3.5 (2)
3 (2)
D
1.5 (2)
2 (4)
E
F
75–93 263–326
90–132 180–264 306–442
100–132 250–330
25–332
90–99 180–198 606–661
100–108 300–324
25–295
25–335
3 (2)
3.5 (2)
2 (2)
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
306–442
25–332
3 (2)
4 (2)
2.5 (2)
2 (2)
606–661
25–275
1.5 (2)
4 (2)
3 (2)
266–474
273–335
25–415
52–94 182–329 266–474
68–83 272–332 273–345
2 (4)
3.5 (2)
4 (2)
2.5 (2)
2 (4)
50–82 200–328
100–132 200–264
25–435
25–332
4 (2)
25–332
4 (2)
2 (2)
273–445
366–661
5018–661
343–555
443–661
68–110 204–330 273–465
72–132 180–330 366–661
50–66 200–264 5018–661
68–110 204–330 343–585
66–99 198–297 443–661
2.5 (2)
2 (2)
3 (2)
2.5 (2)
4 (2)
1 (4)
2 (2)
3 (2)
1.5 (2)
3 (2)
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
43
System Design Information
Table 19. PLL Configurations (333- and 350-MHz Parts) (continued)
333 MHz Part 9
350 MHz Part 9
Multipliers
Periph
Logic/
Mem
Periph
Logic/
Mem
PCI Clock
Input
(PCI_
SYNC_IN)
Range 1
(MHz)
PCI Clock
Input
(PCI_
PLL_
CFG
CPU
Clock
CPU
Clock
Range
(MHz)
PCI-to-
Mem-to-
CPU
(CPU
Ref
Mem
(Mem
VCO)
[0:4] 10,13
Bus
Bus
Range SYNC_IN)
Clock
Range
(MHz)
Clock
Range
(MHz)
(MHz)
Range 1
(MHz)
VCO)
1D
1110112
111108
486–661
72–99 180–248 486–661
Not usable
72–99 180–248
Not usable
1.5 (2)
Off
2.5(2)
Off
1E
Rev B
1E
Rev D
11110
333–475
66–94 231–329 333–505
66–100 231–350
Not usable
2(2)
Off
3.5(2)
Off
1F
111118
Not usable
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum system memory interface operating frequency (100 MHz @ 350-MHz CPU).
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency.
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (800 MHz).
8. In clock-off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10.PLL_CFG[0:4] settings not listed are reserved.
11.Multiplier ratios for this PLL_CFG[0:4] setting are different from or do not exist on the MPC8240 and are not
backward-compatible.
12.PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backward-compatible.
13.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL
is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware
modeling support. The AC timing specifications given in this document do not apply in PLL bypass mode.
15.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the
OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor
PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is
intended for hardware modeling support. The AC timing specifications given in this document do not apply in dual
PLL bypass mode.
16.Limited by maximum system memory interface operating frequency (133 MHz @ 333-MHz CPU).
17.Limited by minimum CPU operating frequency (100 MHz).
18.Limited by minimum memory bus frequency (50 MHz).
7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8245.
44
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
System Design Information
7.1 PLL Power Supply Filtering
The AVDD and AVDD2 power signals on the MPC8245 provide power to the peripheral logic/memory bus
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AV
and AV 2 input signals should be filtered of any noise in the 500-KHz to 10-MHz resonant
DD
DD
frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 27 using surface
mount capacitors with minimum effective series inductance (ESL) is recommended for AV and AV
2
DD
DD
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital
Design: A Handbook of Black Magic (Prentice Hall, 1993), using multiple small capacitors of equal value
is recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize noise
coupled from nearby circuits. Routing directly as possible from the capacitors to the input signal pins with
minimal inductance of vias is important.
10 Ω
VDD
AVDD or AVDD2
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 27. PLL Power Supply Filter Circuit
7.2 Decoupling Recommendations
Due to its dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC8245 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC8245 system, and the MPC8245 itself requires a clean, tightly regulated source of
power. Therefore, the system designer should place at least one decoupling capacitor at each V , OV
,
DD
DD
GV , and LV
pin of the MPC8245. These decoupling capacitors should receive their power from
DD
DD
dedicated power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should
have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the
length of the part.
In addition, several bulk storage capacitors should be distributed around the PCB, feeding the V , OV
,
DD
DD
GV , and LV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
DD
DD
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary.
They should also be connected to the power and ground planes through two vias to minimize inductance.
Suggested bulk capacitors: 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
7.3 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active-low inputs should be tied to OV . Unused active-high inputs should be connected to
DD
GND. All NC signals must remain unconnected.
Power and ground connections must be made to all external V , OV , GV , LV , and GND pins of
DD
DD
DD
DD
the MPC8245.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
45
System Design Information
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and returned to the
PCI_SYNC_IN input of the MPC8245.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8245. The trace length may be used to skew or adjust
the timing window as needed. See the Motorola application notes AN1849, the Tundra Tsi107™ Design
Guide, and AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more information on this
topic. Note that there is an SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (refer to Table 10 for
the input AC timing specifications).
7.4 Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (MDL[0:31]
and PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally
be driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the
system to minimize possible output switching.
The TEST0 pin requires a pull-up resistor of 120 Ω or less connected to OV
.
DD
RTC should have weak pull-up resistors (2–10 kΩ) connected to GV
.
DD
The following signals should be pulled up to OV with weak pull-up resistors (2–10 kΩ): SDA, SCL,
DD
SMI, SRESET/SDMA12, TBEN/SDMA13, CHKSTOP_IN/SDMA14, TRIG_IN/RCS2, INTA,
QACK/DA0 and DRDY. Note that QACK/DA0 should be left without a pull-up resistor only if an external
clock is used because this signal enables internal clock flipping logic when it is low on reset, which is
necessary when the PLL[0:4] signals select a half-clock frequency ratio and an external PLL is used to drive
the SDRAM device.
It is recommended that the following PCI control signals be pulled up to LV (the clamping voltage) with
DD
weak pull-up resistors (2–10 kΩ): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, and TRDY. The
resistor values may need to be adjusted stronger to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[3:0], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors enabled only while device is in the reset state:
GNT4/DA5, MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], and PMAA[0:2]. See
Table 17 for more information on the MPC8245 pins.
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These
pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few clocks
after the negation of HRST_CPU and HRST_CTRL.
Reset configuration pins should be tied to GND via 1-kΩ pull-down resistors to ensure a logic 0 level is read
into the configuration bits during reset if the default logic 1 level is not desired.
Any other unused active low input pins should be tied to a logic-one level through weak pull-up resistors
(2–10 kΩ) to the appropriate power supply listed in Table 17. Unused active high input pins should be tied
to GND through weak pull-down resistors (2–10 kΩ).
46
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
7.5 PCI Reference Voltage—LVDD
The MPC8245 PCI reference voltage (LV ) pins should be connected to a 3.3 ± 0.3 V power supply if
DD
interfacing the MPC8245 into a 3.3-V PCI bus system. Similarly, the LV pins should be connected to a
DD
5.0 V ± 5% power supply if interfacing the MPC8245 into a 5-V PCI bus system. For either reference
voltage, the MPC8245 always performs 3.3-V signaling as described in the PCI Local Bus Specification
(Rev. 2.2). The MPC8245 tolerates 5-V signals when interfaced into a 5-V PCI bus system.
7.6 MPC8245 Compatibility with MPC8240
The MPC8245 AC timing specifications are backward-compatible with those of the MPC8240, except for
the requirements of item 11 in Table 10. Timing adjustments are needed as specified for T
os
(SDRAM_SYNC_IN to sys_logic_clk offset) time requirements.
The MPC8245 does not support the SDRAM flow-through memory interface.
The nominal core V power supply changes from 2.5 V on the MPC8240 to 1.8/2.0 V on the MPC8245.
DD
See Table 2 for details.
For example, the MPC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different ‘PCI-to-Mem’ and
‘Mem-to-CPU’ multiplier ratio than the same setting on the MPC8240, and thus, is not
backward-compatible. See Table 18 for details.
Most of the MPC8240 PLL_CFG[0:4] settings are subsets of the PCI_SYNC_IN input frequency range
accepted by the MPC8245. However, the parts will not be fully backward-compatible since the ranges of
the two parts do not always match. Note that modes 0x8 and 0x18 of the MPC8245 are not compatible with
settings 0x8 and 0x18 on the MPC8240. See Table 18 and Table 19 for details.
There are two additional reset configuration signals on the MPC8245 that are not used as reset configuration
signals on the MPC8240: SDMA0 and SDMA1.
The SDMA0 reset configuration pin selects between the MPC8245 DUART and the MPC8240 backward
compatible mode PCI_CLK[0:4] functionality on these multiplexed signals. The default state (logic 1) of
SDMA0 selects the MPC8240 backward compatible mode of PCI_CLK[0:4] functionality while a logic 0
state on the SDMA0 signal selects DUART functionality. If using the DUART mode, note that four of the
five PCI clocks, PCI_CLK[0:3], are not available.
The SDMA1 reset configuration pin selects between MPC8245 extended ROM functionality and MPC8240
backward-compatible functionality on the multiplexed signals: TBEN, CHKSTOP_IN, SRESET,
TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240
backward-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended ROM
functionality. If using the extended ROM mode, note that the TBEN, CHKSTOP_IN, SRESET, TRIG_IN,
and TRIG_OUT functionalities are not available.
The driver names and capability of the pins for the MPC8245 and that of the MPC8240 vary slightly. Refer
to the drive capability table (for the ODCR register at 0x73) in the MPC8240 Integrated Processor
Hardware Specifications and Table 4 for more details.
The programmable PCI output valid and output hold feature controlled by bits in the power management
configuration register 2 (PMCR2) <0x72> has changed slightly in the MPC8245. For the MPC8240, three
bits, PMCR2[6:4] = PCI_HOLD_DEL, are used to select 1 of 8 possible PCI output timing configurations.
PMCR2[6:5] are software-controllable but are initially set by the reset configuration state of the MCP and
CKE signals, respectively; PMCR2[4] can be changed by software. The default configuration for
PMCR2[6:4] = 0b110 since the MCP and CKE signals have internal pull-up resistors, but this default
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
47
System Design Information
configuration does not select 33- or 66-MHz PCI operation output timing parameters for the MPC8240; this
choice is made by software. For the MPC8245, only two bits in the power management configuration
register 2 (PMCR2), PMCR2[5:4] = PCI_HOLD_DEL, control the variable PCI output timing.
PMCR2[5:4] are software controllable but are initially set by the inverted reset configuration state of the
MCP and CKE signals, respectively. The default configuration for PMCR2[5:4] = 0b00 since the MCP and
CKE signals have internal pull-up resistors and the values from these signals are inverted; this default
configuration selects 66-MHz PCI operation output timing parameters. There are four programmable PCI
output timing configurations on the MPC8245, see Table 11 for details.
Voltage sequencing requirements for the MPC8245 are similar to those for the MPC8240; however, two
changes applicable to the MPC8245. First, there is an additional requirement for the MPC8245 that the
non-PCI input voltages (V ) must not be greater than GV
or OV by more than 0.6 V at all times,
in
DD
DD
including during power-on reset (see Caution 5 in Table 2). Second, for the MPC8245, LV
must not
DD
exceed OV by more than 3.0 V at any time, including during power-on reset (see Caution 10 in Table 2);
DD
the allowable separation between LV and OV is 3.6 V for the MPC8240.
DD
DD
There is no LAV input voltage supply signal on the MPC8245 since the SDRAM clock delay-locked loop
DD
(DLL) has power supplied internally. Signal D17 should be treated as a NC for the MPC8245. Application
note document AN2128 highlights the differences between the MPC8240 and the MPC8245.
7.7 JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more
reliable power-on reset performance can be obtained if the TRST signal is asserted during power-on reset.
Because the JTAG interface is also used for accessing the common on-chip processor (COP) function,
simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status monitoring
signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control
the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers,
power supply failures, or push-button switches, the COP reset signals must be merged into these signals with
logic.
The arrangement shown in Figure 28 allows the COP port to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset
signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While
Motorola recommends that the COP header be designed into the system as shown in Figure 28, if this is not
possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need
to be wired onto the system in debug situations.
The arrangement shown in Figure 28 allows the COP to independently assert HRESET or TRST while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
ensuring that the JTAG scan chain is initialized during power-on. The COP header shown in Figure 28 adds
many benefits—breakpoints, watchpoints, register and memory examination/modification, and other
standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated
footprint for a header to be added when needed.
48
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
The COP interface has a standard header for connection to the target system based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has
pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 28; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom and still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 28 is common to all known emulators.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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System Design Information
MPC8245
SRESET 5
HRST_CPU
SRESET 5
HRESET 7
From Target
Board Sources
(if any)
HRST_CTRL
10 kΩ
10 kΩ
10 kΩ
HRESET
13
11
OVDD
OVDD
OVDD
SRESET 5
10 kΩ
0 Ω 8
OVDD
TRST 7
TRST
4
1
3
2
4
1 kΩ
VDD_SENSE
6
5 2
OVDD
OVDD
10 kΩ
5
7
6
8
10 kΩ
15 3
OVDD
10 kΩ
Key
9
10
12
14 4
OVDD
CHKSTOP_IN 6
TMS
CHKSTOP_IN 6
TMS
11
8
KEY
13
15
9
No pin
TDO
TDI
16
1
TDO
3
TDI
COP Connector
Physical Pin Out
TCK
7
TCK
QACK 1
2
NC
NC
NC
10
12
16
Notes:
1. QACK is an output on the MPC8245 and is not required at the COP header for emulation.
2. RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8245.
Connect pin 5 of the COP header to OVDD with a 1- kΩ pull-up resistor.
3. CKSTP_OUT normally found on pin 15 of the COP header is not implemented on the MPC8245.
Connect pin 15 of the COP header to OVDD with a 10-kΩ pull-up resistor.
4. Pin 14 is not physically present on the COP header.
5. SRESET functions as output SDMA12 in extended ROM mode.
6. CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
7. The COP port and target board should be able to independently assert HRESET and TRST to
the processor in order to fully control the processor as shown above.
.8. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the C
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
Figure 28. COP Connector Diagram
50
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
7.8 Thermal Management Information
This section provides thermal management information for the tape ball grid array (TBGA) package for
air-cooled applications. Depending on the application environment and the operating frequency, heat sinks
may be required to maintain junction temperature within specifications. Proper thermal control design is
primarily dependent upon the system-level design: the heat sink, airflow, and thermal interface material. To
reduce the die-junction temperature, heat sinks may be attached to the package by several methods:
adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly.
Figure 29 displays a package-exploded cross-sectional view of a TBGA package with several heat sink
options.
TBGA Package
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface
Material
Die
Printed-Circuit Board
Option
Figure 29. Package-Exploded Cross-Sectional View with Several Heat Sink Options
Figure 30 depicts the die junction-to-ambient thermal resistance for four typical cases:
•
•
•
•
A heat sink is not attached to the TBGA package, and there exists high board-level thermal loading
from adjacent components.
A heat sink is not attached to the TBGA package, and there exists low board-level thermal loading
from adjacent components.
A heat sink (for example, ChipCoolers) is attached to the TBGA package, and there exists high
board-level thermal loading from adjacent components.
A heat sink (for example, ChipCoolers) is attached to the TBGA package, and there exists low
board-level thermal loading from adjacent components.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
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51
System Design Information
18
16
14
12
10
8
No heat sink and high thermal board-level loading of
adjacent components
No heat sink and low thermal board-level loading of
adjacent components
Attached heat sink and high thermal board-level loading of
adjacent components
Attached heat sink and low thermal board-level loading of
adjacent components
6
4
2
0
0.5
1
1.5
2
2.5
Airflow Velocity (m/s)
Figure 30. Die Junction-to-Ambient Resistance
The board designer can choose between several types of heat sinks to place on the MPC8245. Several
commercially-available heat sinks for the MPC8245 are provided by the following vendors:
Aavid Thermalloy
603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
Alpha Novatech
408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Tyco Electronics
800-522-6752
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
52
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
System Design Information
603-635-5102
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, and Wakefield Engineering
offer different heat sink-to-ambient thermal resistances and may or may not need airflow.
7.8.1 Internal Package Conduction Resistance
The intrinsic conduction thermal resistance paths for the TBGA cavity-down packaging technology shown
in Figure 31 are as follows:
•
•
Die junction-to-case thermal resistance
Die junction-to-ball thermal resistance
Figure 31 depicts the primary heat transfer path for a package with an attached heat sink mounted on a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 31. TBGA Package with Heat Sink Mounted to a Printed-Circuit Board
In a TBGA package the active side of the die faces the printed-circuit board. Most of the heat travels through
the die, across the die attach layer, and into the copper spreader. Some of the heat is removed from the top
surface of the spreader through convection and radiation. Another portion of the heat enters the
printed-circuit board through the solder balls. The heat is then removed off the exposed surfaces of the board
through convection and radiation. If a heat sink is used, a larger percentage of heat leaves through the top
side of the spreader.
7.8.2 Adhesives and Thermal Interface Materials
A thermal interface material is recommended between the top of the package and the bottom of the heat sink
to minimize thermal contact resistance. For those applications where the heat sink is attached by a spring
clip mechanism, Figure 32 shows the thermal performance of three thin-sheet thermal-interface materials
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
53
System Design Information
(silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact
pressure. As shown, the performance of these thermal interface materials improves with increasing contact
pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare
joint results in a thermal resistance approximately seven times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 32). Therefore, synthetic grease offers the best thermal performance, considering the low interface
pressure. Of course, the selection of any thermal interface material depends on many factors: thermal
performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on.
Silicone Sheet (0.006 in.)
Bare Joint
2
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 32. Thermal Performance of Select Thermal Interface Material
40
50
60
70
80
The board designer can choose between several types of thermal interfaces. Heat sink adhesive materials
should be selected based on high conductivity and yet adequate mechanical strength to meet equipment
shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive
materials provided by the following vendors:
Chomerics, Inc.
781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
800-248-2481
Midland, MI 48686-0997
Internet: www.dow.com
54
MPC8245 Integrated Processor Hardware Specifications
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MOTOROLA
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888-642-7674
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
The Bergquist Company
18930 West 78 St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
888-246-9050
th
Thermagon Inc.
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
7.8.3 Heat Sink Usage
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
T = T + (R × P )
J
A
θJA
D
where
T = ambient temperature for the package (°C)
A
R
= junction-to-ambient thermal resistance (°C/W)
θJA
P = power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, two values are in common usage: the value determined
on a single-layer board and the value obtained on a board with two planes. Which value is closer to the
application depends on the power dissipated by other components on the board. The value obtained on a
single-layer board is appropriate for the tightly packed printed-circuit board. The value obtained on the
board with the internal planes is usually appropriate if the board has low power dissipation and the
components are well separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where
R
R
R
= junction-to-ambient thermal resistance (°C/W)
= junction-to-case thermal resistance (°C/W)
= case-to-ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device-related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case-to-ambient thermal resistance, R
. For instance, the user can change the size of the heat
θCA
sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit
board, or the thermal dissipation on the printed-circuit board surrounding the device.
To determine the junction temperature of the device in the application without a heat sink, the thermal
characterization parameter (Ψ ) can be used to determine the junction temperature with a measurement of
JT
the temperature at the top center of the package case using the following equation:
T = T + (Ψ × P )
J
T
JT
D
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
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System Design Information
where:
T = thermocouple temperature atop the package (°C)
T
Ψ
= thermal characterization parameter (°C/W)
JT
P = power dissipation in package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the interface.
From this case temperature, the junction temperature is determined from the junction-to-case thermal
resistance.
In many cases, it is appropriate to simulate the system environment using a computational fluid dynamics
thermal simulation tool. In such a tool, the simplest thermal model of a package that has demonstrated
reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a
junction-to-case thermal resistance. The junction-to-case covers the situation where a heat sink will be used
or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board
thermal resistance describes the thermal performance when most of the heat is conducted to the
printed-circuit board.
7.9 References
Semiconductor Equipment and Materials International
805 East Middlefield Rd.
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
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Document Revision History
8 Document Revision History
Table 20 provides a revision history for this hardware specification.
Table 20. Revision History Table
Revision
Substantive Change(s)
Number
0.0
0.1
Initial release.
Made VDD/AVDD/AVDD2 = 1.8 V ± 100 mV information for 133-MHz memory interface operation to
Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2.
Pin D17, formerly LAVDD (supply voltage for DLL), is a NC on the MPC8245 since the DLL voltage is
supplied internally. Eliminated all references to LAVDD; updated Section 1.7.1.
Previous Note 4 of Table 2 did not apply to the MPC8245 (MPC8240 document legacy). New Note 4
added in reference to maximum CPU speed at reduced VDD voltage.
Updated the Programmable Output Impedance of DEV_MEM_ADDR in Table 4 to 6 Ω to reflect
characterization data.
Updated Table 5 to reflect reduced power consumption when operating VDD/AVDD/AVDD2 = 1.8 V ± 100
mV. Changed Notes 2, 3, and 4 to reflect VDD at 1.9 V. Changed Note 5 to represent VDD = AVDD = 1.8 V.
Updated Table 7 to reflect VDD/AVDD/AVDD2 voltage level operating frequency dependencies; changed
250 MHz device column to 266 MHz; modified Note 1 eliminating VCO references; added Note 2.
Changed 250 MHz processor frequency offering to 266 MHz.
Changed Spec 12b for memory output valid time in Table 11 from 5.5 ns to 4.5 ns; this is a key
specification change to enable 133-MHz memory interface designs.
Updated Pinout Table 16 with the following changes:
• Pin types for RCS0, RCS3/TRIG_OUT and DA[11:15] were erroneously listed as I/O, changed Pin
Types to Output.
• Pin types for REQ4/DA4, RCS2/TRIG_IN, and PLL_CFG[0:4]/DA[10:6] were erroneously listed as
Input, changed Pin Types to I/O.
• Changed Pin D17 from LAVDD to No Connect; deleted Note 21 and references.
• Notes 3, 5, and 7 contained references to the MPC8240 (MPC8240 document legacy); changed these
references to MPC8245.
• Previous Notes 13 and 14 did not apply to the MPC8245 (MPC8240 document legacy), these notes
were deleted; moved Note 19 to become new Note 13; moved Note 20 to become new Note 14;
updated associated references.
• Added Note 3 to SDMA[1:0] signals about internal pull-up resistors during reset state.
• Reversed vector ordering for the PCI Interface Signals: C/BE[0:3] changed to C/BE[3:0], AD[0:31]
changed to AD[31:0], GNT[0:3] changed to GNT[3:0], and REQ[0:3] changed to REQ[3:0]. The
package pin number orderings were also reversed meaning that pin functionality did NOT change. For
example, AD0 is still on signal C22, AD1 is still on signal D22,..., AD31 is still on signal V25. This
change was made to make the vectored PCI signals in this hardware specification consistent with the
PCI Local Bus Specification and the MPC8245 Integrated Processor User’s Manual vector ordering.
• Changed TEST1/DRDY signal on pin B20 to DRDY.
• Changed TEST2 signal on pin Y2 to RTC for performance monitor use.
Updated PLL Table 17 with the following changes for 133-MHz memory interface operation:
• Added Ref. 9 (01001) and Ref. 17 (10111) details; removed these settings from Note 10 (reserved
settings list).
• Enhanced range of Ref. 10 (10000).
• Updated Note 13, changed bits 16–20 erroneous information to correct bits 23–19.
• Added Notes 16 and 17.
Added information to Section 1.7.8 in reference to CHKSTOP_IN and SRESET being unavailable in
extended ROM mode.
MOTOROLA
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Document Revision History
Table 20. Revision History Table (continued)
Substantive Change(s)
Revision
Number
0.2
Changed core supply voltage to 2.0 ± 100 mV in Section 1.3. (Supply voltage of 1.8 ± 100 mV is no longer
recommended.)
Changed rows 2, 5, and 6 of Table 2 to 2.0 ± 100 mV in the “Recommended Value” column.
Changed the power consumption numbers in Table 5 to reflect the power values for VDD = 2.0 V. (Notes
2, 3, 4, and 5 of the table were also updated to reflect the new value of VDD.)
Updated Table 9 for VDD/AVDD/AVDD2 to 2.0 ± 100 mV.
Table 8: VDD/AVDD/AVDD2 was changed to 2.0 V for both CPU frequency offerings. Note 2 was updated
by removing the “at reduced voltage...” statement.
Table 10: Update maximum time of the rows 12a0 through 12a3.
Table 16: Fixed overbars for the active-low signals. Changed pin type information for VDD, AVDD, and
AVDD2 to 2.0 V.
Changed Note 16 of Table 17 to a value of 2.0 V for VDD/AVDD/AVDD2.
Removed second sentence of the second paragraph in Section 1.7.2 because it referenced information
about a 1.8-V design.
Removed reference to 1.8 V in third sentence of Section 1.7.7.
0.3
Section 1.4.1.5—Changed Max-FP value for 33/133/266 of Table 5 from 2.3 to 2.1 watts to represent
characterization data. Changed Note 4 to say VDD = 2.1 for power measurements (for 2-V part). Changed
numbers for maximum I/O power supplies for OVDD and GVDD to represent characterization data.
Section 1.4.3.1—Added four graphs (Figures 5–8) and description for DLL Locking Range vs. Frequency
of Operation to replace Figure 5 of Rev 0.2 document.
Section 1.4.3.2—Added row (item 11: Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN timing) to Table 9 to
include offset change requirement.
Section 1.5.3—Changed Note 4 of PLL_CFG pins in Table 16 to Note 20.
Section 1.7.2—Added diode (MUR420) to Figure 27, Voltage Sequencing Circuit, to compensate for
voltage extremes in design.
Section 1.7.5—Added sentence with regards to SDRAM_SYNC_IN to PCI_SYNC_IN timing requirement
(Tsu) as a connection recommendation.
Section 1.7.8—Mention of Tsu offset timing and driver capability differences between the MPC8240 and
the MPC8245.
0.4
Section 1.2—Changed Features list (format) to match with the features list of the MPC8245 Integrated
Processor User’s Manual.
Section 1.4.1.2—Updated Table 2 to include 1.8 ± 100mV numbers.
Section 1.4.3—Changed Table 7 to include new part offerings of 333 and 350 MHz. Added rows to include
VCO frequency ranges for all parts for both memory VCO and CPU VCO.
Section 1.4.1.5—Updated power consumption table to include 1.8 V (VDD) and higher frequency
numbers.
Section 1.4.3—Updated Table 7 to include higher frequency offerings and CPU VCO frequency range.
Section 1.4.3.1—Changed lettering to caps for DLL_EXTEND and DLL_MAX_DELAY in graph
description section.
Section 1.4.3.2—Changed name of item 11 from Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN Time to
Tos—SDRAM_SYNC_IN to sys_logic_clk Offset Time. Changed name to Tos in Note 7 as well.
Section 1.6—Updated notes in Table 17. Included minimum and maximum VCO numbers for memory
VCO. Changed Note 13 for location of PLL_CFG[0:4] to correct bits location. Bits 7–4 of register offset
<0xE2>. Added Table 18 to cover PLL configuration of higher frequency part offerings.
Section: 1.7—Changed frequency ranges for reference numbers 0, 9, 10, and 17, for the 300-MHz part
to include the higher memory bus frequencies when operating at lower CPU bus frequencies. Added
Table 18 to include PLL configurations for the 333 MHz and the 350 MHz CPU part offerings. Added VCO
multipliers in Tables 17 and 18.
Section 1.7.8—Changed Tsu—SDRAM_SYNC_IN to PCI_SYNC_IN Time to Tos—SDRAM_
SYNC_IN to sys_logic_clk Offset Time.”
Section 1.7.10—Added vendor (Cool Innovations, Inc.) to list of heat sink vendors.
58
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Document Revision History
Table 20. Revision History Table (continued)
Substantive Change(s)
Revision
Number
0.5
1
Corrected labels for Figures 5 through 8.
Updated document template.
Section 1.4.1.4—Changed the driver type names in Table 6 to match with the names used in the
MPC8245 User’s Manual.
Section 1.5.3—Updated driver type names for signals in Table 16 to match with names used in the
MPC8245 Integrated Processor User’s Manual.
Section 1.4.1.2—Updated Table 7 to refer to new PLL Tables for VCO limits.
Section 1.4.3.3—Added item 12e to Table 10 for SDRAM_SYNC_IN to Output Valid timing.
Section 1.5.1—Updated solder balls information to 62Sn/36PB/2Ag.
Section 1.6—Updated PLL Tables 17 and 18 and appropriate notes to reflect changes of VCO ranges for
memory and CPU frequencies.
Section 1.7—Updated voltage sequencing requirements in Table 2 and removed Section 1.7.2.
Section 1.7.8—Updated TRST information and Figure 26.
New Section 1.7.2—Updated the range of I/O power consumption numbers for OVDD and GVDD to correct
values as in Table 5. Updated fastest frequency combination to 66:100:350 MHz.
Section 1.7.9—Updated list for heat sink and thermal interface vendors.
Section 1.9—Changed format of Ordering Information section. Added tables to reflect part number
specifications also available.
Added Sections 1.9.2 and 1.9.3.
2
Globally changed EPIC to PIC.
Section 1.4.1.4—Note 5: Changed register reference from 0x72 to 0x73.
Section 1.4.1.5—Table 5: Updated power dissipation numbers based on latest characterization data.
Section 1.4.2—Table 6: Updated table to show more thermal specifications.
Section 1.4.3—Table 7: Updated minimum memory bus value to 50 MHz.
Section 1.4.3.1—Changed equations for DLL locking range based on characterization data. Added
updates and reference to AN2164 for note 6. Added table defining Tdp parameters. Labeled N value in
Figures 5 through 8.
Section 1.4.3.2—Table 10: Changed bit definitions for tap points. Updated note on Tos and added
reference to AN2164 for note 7. Updated Figure 9 to show significance of Tos.
Section 1.4.3.4—Added column for SDRAM_CLK @ 133 MHz
Sections 1.5.1 and 1.5.2—Corrected packaging information to state TBGA packaging.
Section 1.5.3—Corrected some signals in Table 16 which were missing overbars in the Rev 1.0 release
of the document.
Section 1.6—Updated Note 10 of Tables 18 and 19.
Section 1.7.3—Changed sentence recommendation regarding decoupling capacitors.
Section 1.9—Updated format of tables in Ordering Information section.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
59
Ordering Information
Table 20. Revision History Table (continued)
Substantive Change(s)
Revision
Number
3
Section 1.4.1.2—Figure 2: Updated Note 2 and removed ‘voltage regulator delay’ label since Section
1.7.2 is being deleted this revision. Added Figures 4 and 5 to show voltage overshoot and undershoot of
the PCI interface on the MPC8245.
Section 1.4.1.3—Table 3: Updated the maximum input capacitance from 7 to 16 pF based on
characterization data.
Section 1.4.3.1—Updated PCI_SYNC_IN jitter specifications to 200 ps.
Section 1.4.3.3—Table 11, item 12b: added the word ‘address’ to help clarify which signals the spec
applies to. Figure 15: edited timing for items 12a0 and 12a2 to correspond with Table 11.
Section 1.5.3—Updated notes for the QACK/DA0 signal because this signal has been found to have no
internal pull resistor.
Section 1.6—Corrected note numbers for reference numbers 3,10,1B, and 1C of the PLL tables. Updated
PLL specifications for modes 7 and 1E.
Section 1.7.2—Removed this section since the information already exists in Section 1.4.1.5.
Section 1.7.4—Added the words ‘the clamping voltage’ to describe LVDD in the sixth paragraph. Changed
the QACK/DA0 signal from the list of signals having an internal pull-up resistor to the list of signals
needing a weak pull-up resistor to OVDD
.
Section 1.9.1—Tables 21 thru 23: Added processor version register value.
4
5
Section 1.4.1.2—Updated notes for GVDD, AVDD, AVDD2.
Section 1.5.1—Updated solder ball information to include lead free (V V) balls.
Section 1.5.3—Updated Note 25 for QACK/DA0 signal. Added a sentence to Note 3.
Section 1.6 —Incorporated Note 19 into Note 12 and modified Tables 18 and 19 accordingly.
Section 1.9—Updated part marking nomenclature where appropriate to include the lead free offering.
Replaced reference to PNS document MPC8245RZUPNS with MPC8245ARZUPNS.
Section 4.1.2 — Added note 6 and related label for latching of the PLL_CFG signals.
Section 4.1.3 — Updated specifications for the input high and input low voltages of PCI_SYNC_IN.
Section 4.3 — Table 7, updated specifications for the voltage range of VDD for specific CPU frequencies.
Section 4.3.1 — Table 8: Corrected typo for first number 1a to 1; Updated characteristics for the DLL lock
range for the default and remaining three DLL locking modes; Reworded note description for note 6.
Replaced contents of Table 9 with bit descriptions for the four DLL locking modes. In Figures 7 through
10, updated the DLL locking mode graphs.
Section 4.3.2 — Table 10: Changed the name of references for timing parameters from
SDRAM_SYNC_IN to sys_logic_clk to be consistent with Figure 11. Followed the same change for note 2.
Section 4.3.3— Table 11: Changed the name of references for timing parameters from
SDRAM_SYNC_IN to sys_logic_clk to be consistent with Figure 11. Followed the same change for note 2.
Section 5.3 — Table 17: Removed extra listing of DRDY in Test/Configuration signal list and updated
relevant notes for signal in Memory Interface signal listing. Updated note #20. Added note 26 for the
signals of the UART interface.
Section 7.6 — Added reference to AN2128 application note that highlights the differences between the
MPC8240 and the MPC8245.
Section 7.7 — Added relevant notes to this section and updated Figure 29.
5.1
Section 4.3.1 — Table 9: Corrected last row to state the correct description for the bit setting. Max tap
delay, DLL extend. Figure 8: Corrected the label name for the DLL graph to state “DLL Locking Range
Loop Delay vs. Frequency of Operation for DLL_Extend=1 and Normal Tap Delay”
9 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 9.1,
“Part Numbers Fully Addressed by This Document.” Section 9.2, “Part Numbers Not Fully Addressed by
This Document,” lists the part numbers that do not fully conform to the specifications of this document.
These special part numbers require an additional document called a part number specification.
60
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Ordering Information
9.1 Part Numbers Fully Addressed by This Document
Table 21 provides the Motorola part numbering nomenclature for the MPC8245. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact a local
Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes an
application modifier that may specify special application conditions. Each part number also contains a
revision code that refers to the die mask revision number. The revision level can be determined by reading
the Revision ID register at address offset 0x08.
Table 21. Part Numbering Nomenclature
MPC nnnn
xx
nnn
x
L
Processor
Version Register
Value
Product
Code
Part
Identifier
Processor
Process Descriptor
Package 1
Revision Level
Frequency 2
MPC
8245
L:1.8/2.0 V ± 100 mV
ZU = TBGA
V V= Lead
free TBGA
266
300
0° to 105°C
D:1.4 Rev ID:0x14
0x80811014
L:2.0 V ± 100 mV
ZU = TBGA
V V= Lead
free TBGA
333
350
0° to 105°C
Notes:
1. See Section 5, “Package Description,” for more information on available package types. Note that the V V
package option is only available in part revision D.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in
this specification support all core frequencies. Additionally, parts addressed by part number specifications may
support other maximum core frequencies.
9.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are
described in separate part number specifications that supplement and supersede this document. Table 22
shows the part numbers addressed by the MPC8245TXXnnnx series. The revision level can be determined
by reading the Revision ID register at address offset 0x08.
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
61
Ordering Information
Table 22. Part Numbers Addressed by MPC8245TXXnnnx Series
Part Number Specification Markings
(Document Order No. MPC8245TXXPNS)
MPC
nnnn
xx
nnn
x
X
Processor
Revision Level Version Register
Value
Product
Code
Part
Identifier
Processor
Process Descriptor Package 1
Frequency 2
MPC
8245
T :2.0 V ± 100 mV
ZU = TBGA
V V3= Lead
free TBGA
266
300
333
350
B:1.2 Rev ID:0x12
D:1.4 Rev ID:0x14
0x80811014
–40° to 105°C
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in
this specification support all core frequencies. Additionally, parts addressed by part number specifications may
support other maximum core frequencies.
3. Note that the V V package option is only available in part revision D.
Table 23 shows the part numbers addressed by the MPC8245ARZUnnnx series.
Table 23. Part Numbers Addressed by MPC8245ARZUnnnx Series
Part Number Specification Markings
(Document Order No. MPC8245ARZUPNS)
MPC nnnn
X
xx
nnn
x
X
Processor
Version
Register
Value
Product
Code
Part
Process 3
Process
Descriptor
Processor
Package 1
Revision Level
Identifier Identifier
Frequency 2
R:2.1 V ± 100 mV ZU = TBGA
400
D:1.4 Rev ID:0x14 0x80811014
D:1.4 Rev ID:0x14 0x80811014
-
0° to 85°C
MPC
MPC
8245
8245
A
R:2.1 V ± 100 mV ZU = TBGA
400
466
0° to 85°C
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in
this specification support all core frequencies. Additionally, parts addressed by part number specifications may
support other maximum core frequencies.
3. Process identifier “A” represents parts that are manufactured under a 29-angstrom process verses the original
35-angstrom process.
62
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Ordering Information
Parts are marked as the example shown in Figure 33.
MPC8245L
XX350C
MMMMMM
ATWLYYWWA
8245
TBGA
Notes:
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
Figure 33. Part Marking for TBGA Device
MOTOROLA
MPC8245 Integrated Processor Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
63
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(800) 521-6274
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3-20-1, Minami-Azabu Minato-ku
Tokyo 106-8573 Japan
Information in this document is provided solely to enable system and software implementers to use
Motorola products. There are no express or implied copyright licenses granted hereunder to design
or fabricate any integrated circuits or integrated circuits based on the information in this document.
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© Motorola, Inc. 2004
MPC8245EC
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