MPC8247ZQTIE_技术文档

Advance Information

MPC8272EC

Rev. 0.1 9/2003

MPC8272 Family

Hardware Speciﬁcations

This hardware speciﬁcation contains detailed information on power considerations, DC/AC

electrical characteristics, and AC timing speciﬁcations for the MPC8272 family of

devices—the MPC8272, the MPC8248, the MPC8271, and the MPC8247. The CPU on these

TM

devices is a 32-bit PowerPC

core that incorporates memory management units (MMUs)

and instruction and data caches and that implements the PowerPC instruction set. These

devices are .13µm (HiP7) members of the PowerQUICC II™ family of integrated

communications processors. They include a modiﬁed communications processor module

(CPM) and an integrated security engine (SEC) for encryption (the MPC8272 and the

MPC8248 only).

All four devices are collectively referred to throughout this hardware speciﬁcation as ‘the

MPC8272’ unless otherwise noted. The following topics are addressed:

Topic

Page

2

Section 1, “Features”

Section 2, “Electrical and Thermal Characteristics”

Section 2.1, “DC Electrical Characteristics”

Section 2.2, “Thermal Characteristics”

Section 2.3, “AC Electrical Characteristics”

Section 3, “Clock Conﬁguration Modes”

Section 4, “Pinout”

6

10

11

18

34

45

48

Section 5, “Package”

Section 6, “Ordering Information”

Section 7, “Document Revision History”

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Features

Figure 1 shows the superset block diagram.

16 Kbytes

I-Cache

1

Security (SEC)

I-MMU

System Interface Unit

(SIU)

60x Bus

G2_LE Core

16 Kbytes

D-Cache

Bus Interface Unit

PCI Bus

32 bits, up to 66 MHz

60x-to-PCI

Bridge

D-MMU

Memory Controller

Communication Processor Module (CPM)

Clock Counter

16 KB

Data

RAM

4 KB

Instruction

RAM

Timers

Serial

DMA

Interrupt

Controller

System Functions

Parallel I/O

32-bit RISC Microcontroller

and Program ROM

Virtual

IDMAs

Baud Rate

Generators

I²C

USB 2.0

FCC1

FCC2

SCC1

SCC3

SCC4

SMC1

SMC2

SPI

Time Slot Assigner

Serial interface

Serial Interface

Non-Multiplexed

I/O

2 MII/RMII

Ports

1 8-bit Utopia

2 TDM Ports

2

Port

Note

1

MPC8272/8248 only

MPC8272/8271 only

2

Figure 1. Block Diagram

1

Features

The major features of the MPC8272 are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the MPC603e microprocessor

— System core microprocessor supporting frequencies of 266-400 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— Supports bus snooping for cache coherency

— Floating-point unit (FPU) supports ﬂoating-point arithmetic

— Support for cache locking

2

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Features

•

Low-power consumption

Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

Separate PLLs for G2_LE core and for the communications processor module (CPM)

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1,

7:1, and 8:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, and 6:1 ratios

64-bit data and 32-bit address 60x bus

•

— Bus supports multiple master designs—up to two external masters

— Supports single transfers and burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

•

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

•

Eight bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other

user-deﬁnable peripherals

— Byte write enables

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x)

— Dedicated interface logic for SDRAM

Disable CPU mode

•

Integrated security engine (SEC) (MPC8272 and MPC8248 only)

— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms

in hardware

•

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for ﬂexible support

for communications peripherals

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Features

— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port

RAM size is 16 Kbyte plus 4Kbyte dedicated instruction RAM.)

•

Universal serial bus (USB) controller

— Supports USB 2.0 full/low rate compatible

— USB host mode

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stufﬁng

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and

data rate conﬁguration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

— Supports USB slave mode

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stufﬁng

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Two fast communication controllers (FCCs) supporting the following protocols:

– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII)

– Transparent

– HDLC—up to T3 rates (clear channel)

– One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155

Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0

CBR, VBR, UBR, ABR trafﬁc types, up to 64-K external connections

— Three serial communications controllers (SCCs) identical to those on the MPC860 supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BiSync) communications

– Transparent

– QUICC multichannel controller (QMC) up to 64 channels

• Independent transmit and receive routing, frame synchronization.

4

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Features

• Serial-multiplexed (full-duplex) input/output 2048-, 1544-, and 1536-Kbps PCM

highways

• Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN

basic rate, ISDN primary rate, and user deﬁned.

• Subchanneling on each time slot.

• Independent transmit and receive routing, frame synchronization and clocking

• Concatenation of any not necessarily consecutive time slots to channels independently

for Rx/Tx

• Supports H1,H11, and H12 channels

• Allows dynamic allocation of channels

– SCC3 in NMSI mode is not usable when USB is enabled.

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provides management for BRI devices as general-circuit interface (GCI) controllers in

time-division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

2

— One I C controller (identical to the MPC860 I C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to two TDM interfaces

– Supports one group of two TDM channels

– 1024 bytes of SI RAM

— Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,

SCC, SMC, and USB serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

PCI bridge

•

— PCI Speciﬁcation revision 2.2-compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI to 60x memory and 60x memory to PCI streaming

— PCI host bridge or peripheral capabilities

— Includes four DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes the conﬁguration registers required by the PCI standard (which are automatically

loaded from the EPROM to conﬁgure the MPC8272) and message and doorbell registers

— Supports the I O standard

2

— Hot-Swap friendly (supports the Hot Swap Speciﬁcation as deﬁned by PICMG 2.1 R1.0August

3, 1998)

— Support for 66-MHz, 3.3-V speciﬁcation

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Electrical and Thermal Characteristics

— 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port

2

Electrical and Thermal Characteristics

This section provides AC and DC electrical speciﬁcations and thermal characteristics for the MPC8272.

2.1

DC Electrical Characteristics

Table 1 shows the maximum electrical ratings.

1

Table 1. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

2

Core supply voltage

VDD

VCCSYN

VDDH

VIN

–0.3 – 2.25

–0.3 – 4.0

V

2

PLL supply voltage

3

I/O supply voltage

V

4

Input voltage

GND(–0.3) – 3.6

120

V

Junction temperature

T

˚C

j

Storage temperature range

T

(–55) – (+150)

STG

1

Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

2

3

Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.

Caution:VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec.VDDH should

not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

4

Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

Table 2 lists recommended operational voltage conditions.

1

Table 2. Recommended Operating Conditions

Rating

Symbol

Value

Unit

Core supply voltage

PLL supply voltage

I/O supply voltage

Input voltage

VDD

VCCSYN

VDDH

VIN

1.425 – 1.575

V

3.135 – 3.465

V

GND (-0.3) – 3.465

V

2

Junction temperature (maximum)

Ambient temperature

T

105

˚C

j

2

T

0–70

A

1

2

Caution:These are the recommended and tested operating conditions. Proper operation outside of these conditions

is not guaranteed.

Note that for extended temperature parts the range is (-40) – 105 .

T

j

A

NOTE: Core, PLL, and I/O Supply Voltages

VDDH, VCCSYN, and VDD must track each other and vary in the same

direction—either in the positive direction (+0.165 VDDH and

+0.075 VDD) or in the negative direction (–0.165 VDDH and

–0.075 VDD).

6

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Electrical and Thermal Characteristics

This device contains circuitry protecting against damage due to high static voltage or electrical ﬁelds;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (either GND or V ).

CC

Figure 2 shows the undershoot and overshoot voltage of the 60x bus memory interface of the MPC8272.

Note that in PCI mode the I/O interface is different.

4 V

GV + 5%

DD

V

GV

IH

DD

GND

GND – 0.3 V

IL

GND – 1.0 V

Not to exceed 10%

of t

SDRAM_CLK

Figure 2. Overshoot/Undershoot Voltage

Table 3 shows DC electrical characteristics.

1

Table 3. DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

2

Input high voltage, all inputs except CLKIN

Input low voltage

V

2.0

GND

2.4

GND

—

3.465

0.8

3.465

0.4

10

V

IH

V

IL

CLKIN input high voltage

V

IHC

CLKIN input low voltage

V

I

V

ILC

IN

3

Input leakage current, V = VDDH

µA

V

IN

3

Hi-Z (off state) leakage current, V = VDDH

I

—

10

IN

OZ

Signal low input current, V = 0.8 V

I

—

1

IL

L

Signal high input current, V = 2.0 V

I

—

1

IH

H

Output high voltage, I = –2 mA

V

2.4

—

OH

except UTOPIA mode, and open drain pins

4

In UTOPIA mode (UTOPIA pins only): I = -8.0mA

OH

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

4

In UTOPIA mode (UTOPIA pins only): I = 8.0mA

V

—

0.5

V

OL

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

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7

Electrical and Thermal Characteristics

Table 3. DC Electrical Characteristics (continued)

1

Characteristic

Symbol

Min

Max

Unit

I

= 6.0mA

V

—

0.4

V

OL

BR

BG/IRQ6

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG/IRQ7

DBB/IRQ3

D[0-63]

IRQ3/CKSTP_OUT/EXT_BR3

IRQ4/CORE_SRESET/EXT_BG3

IRQ5/TBEN/EXT_DBG3/CINT

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

BADDR31/IRQ5/CINT

CPU_BR/INT_OUT

IRQ0/NMI_OUT

PORESET/PCI_RST

HRESET

SRESET

RSTCONF

8

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MOTOROLA

Electrical and Thermal Characteristics

1

Table 3. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

I

= 5.3mA

V

—

0.4

V

OL

CS[0-5]

CS6/BCTL1/SMI

CS7/TLBSYNC

BADDR27/ IRQ1

BADDR28/ IRQ2

ALE/ IRQ4

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4

PSDAMUX/PGPL5

PCI_HOST

PCI_ARB_EN

DLL_ENABLE

MODCK1/RSRV/TC(0)/BNKSEL(0)

MODCK2/CSE0/TC(1)/BNKSEL(1)

MODCK3/CSE1/TC(2)/BNKSEL(2)

I

= 3.2mA

OL

PAR

FRAME/SMI

TRDY

IRDY

STOP

DEVSEL

IDSEL

PERR

SERR

REQ0

REQ1

GNT0

GNT1

GNT2

RST

INTA

REQ2

DLLOUT

AD(0-31)

C/BE(0-3)

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

TDO

1

The default conﬁguration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input.To prevent

excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to conﬁgure them as outputs.

2

3

4

Minimum V for TRST and PORESET is 2.2 mA.

IH

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

MPC8272 and MPC8271 only.

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Electrical and Thermal Characteristics

2.2

Thermal Characteristics

Table 4 describes thermal characteristics.

Table 4. Thermal Characteristics

Characteristic

Junction-to-ambient—

Symbol

Value

Unit

Air Flow

27

21

19

16

11

8

Natural convection

1

θ

JA

single-layer board

°C/W

1 m/s

Junction-to-ambient—

four-layer board

Natural convection

θ

°C/W

JA

1 m/s

—

2

Junction-to-board

θ

°C/W

JB

JC

3

Junction-to-case

—

1

2

Assumes no thermal vias

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

3

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

2.2.1

Layout Practices

Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground pin

CC

should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct

groups of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF

CC

bypass capacitors located as close as possible to the four sides of the package. The capacitor leads and

associated printed circuit traces connecting to chip V and ground should be kept to less than half an inch

CC

per capacitor lead. A four-layer board employing two inner layers as V_CCand GND planes is recommended.

All output pins on the MPC8272 have fast rise and fall times. Printed circuit (PC) trace interconnection

length should be minimized in order to minimize overdamped conditions and reﬂections caused by these

fast output switching times. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be inputs

CC

during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

Table 5 provides preliminary, estimated power dissipation for various conﬁgurations. Note that suitable

thermal management is required to ensure the junction temperature does not exceed the maximum speciﬁed

value. Also note that the I/O power should be included when determining whether to use a heat sink.

10

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Electrical and Thermal Characteristics

1

Table 5. Estimated Power Dissipation for Various Conﬁgurations

2, 3

P

(W)

INT

CPM

Multiplication

Factor

CPU

Multiplication

Factor

Bus

(MHz)

CPM

(MHz)

CPU

(MHz)

Vddl 1.5 Volts

Nominal

Maximum

66.67

100

3

2

200

4

3

4

266

300

400

0.75

0.85

1

0.8

0.9

100

1.05

1

2

3

Test temperature = 105˚ C)

= I x V Watts

P

INT

DD

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)

83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)

100 MHz = 0.5 W (nominal), 0.6 W (maximum)

2.3

AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and

inputs for 66.67-/83.33-/100-MHz MPC8272 devices. Note that AC timings are based on a 50-pf load.

Typical output buffer impedances are shown in Table 6.

1

Table 6. Output Buffer Impedances

Output Buffers

Typical Impedance (Ω)

60x bus

45

25

Memory controller

Parallel I/O

PCI

1

These are typical values at 65˚ C. Impedance may vary by ±25% with process and temperature.

2.3.1

CPM AC Characteristics

Table 7 lists CPM output characteristics.

1

Table 7. AC Characteristics for CPM Outputs

Spec Number

Characteristic

Value (ns)

Maximum Delay Minimum Delay

Max

Min

66

83

100

66

83

100

MHz MHz MHz MHz MHz MHz

sp36a

sp36b

sp38a

sp37a

sp37b

sp39a

FCC outputs—internal clock (NMSI)

FCC outputs—external clock (NMSI)

6

5.5

12

16

5.5

12

16

1

2

1

2

1

2

14

19

SCC/SMC/SPI/I2C outputs—internal clock

(NMSI)

0.5

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Electrical and Thermal Characteristics

Table 7. AC Characteristics for CPM Outputs (continued)

1

Spec Number

Characteristic

Value (ns)

Maximum Delay Minimum Delay

Max

Min

66

83

100

66

83

100

MHz MHz MHz MHz MHz MHz

sp38b

sp39b

SCC/SMC/SPI/I2C outputs—external clock

(NMSI)

19

16

2

sp40

sp42

sp41

sp43

TDM outputs/SI

TIMER/IDMA outputs

PIO outputs

14

12

11

12

11

5

1

3

0.5

sp42a

sp43a

0.5

1

Output speciﬁcations are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

Table 8 lists CPM input characteristics.

1

Table 8. AC Characteristics for CPM Inputs

Spec Number

Characteristic

Value (ns)

Setup

Hold

Setup

83

Hold

83

66

100

66

100

MHz MHz MHz MHz MHz MHz

sp16a

sp16b

sp18a

sp17a

sp17b

sp19a

FCC inputs—internal clock (NMSI)

FCC inputs—external clock (NMSI)

10

3

8

0

2

0

2

0

2

0

2.5

16

2.5

16

SCC/SMC/SPI/I2C inputs—internal clock

(NMSI)

20

sp18b

sp19b

SCC/SMC/SPI/I2C inputs—external clock

(NMSI)

5

4

2

sp20

sp22

sp21

sp23

TDM inputs/SI

7

5

8

5

8

4

3

PIO/TIMER/IDMA inputs

10

0.5

1

Input speciﬁcations are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

NOTE

Although the speciﬁcations generally reference the rising edge of the

clock, the following AC timing diagrams also apply when the falling edge

is the active edge.

12

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Electrical and Thermal Characteristics

Figure 3 shows the FCC internal clock.

BRG_OUT

sp17a

sp16a

FCC input signals

sp36a/sp37a

FCC output signals

Note: When GFMR[TCI] = 0

sp36a/sp37a

FCC output signals

Note: When GFMR.[TCI] = 1

Figure 3. FCC Internal Clock Diagram

Figure 4 shows the FCC external clock.

Serial ClKin

sp17b

sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 1

Figure 4. FCC External Clock Diagram

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13

Electrical and Thermal Characteristics

2

Figure 5 shows the SCC/SMC/SPI/I C external clock.

Serial CLKin

sp19b

sp18b

SCC/SMC/SPI/I2C input signals

(See note)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 5. SCC/SMC/SPI/I C External Clock Diagram

2

Figure 6 shows the SCC/SMC/SPI/I C internal clock.

BRG_OUT

sp19a

sp18a

SCC/SMC/SPI/I2C input signals

(See note)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram

14

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical and Thermal Characteristics

Figure 7 shows TDM input and output signals.

Serial CLKin

sp20

sp21

TDM input signals

TDM output signals

sp40/sp41

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

Figure 8 shows PIO and timer signals.

Sys clk

sp23

sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23

sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43

sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO and Timer Signal Diagram

15

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical and Thermal Characteristics

2.3.2

SIU AC Characteristics

Table 9 lists SIU input characteristics.

NOTE: PCI AC Timing

The MPC8272 meets the timing requirements of PCI Speciﬁcation

Revision 2.2. Refer to Section 3, “Clock Conﬁguration Modes” and “Note:

Tval (Output Hold)” to determine if a speciﬁc clock conﬁguration is

compliant.

1

Table 9. AC Characteristics for SIU Inputs

Spec Number

Characteristic

Value (ns)

Setup

Hold

Setup

Hold

66

83

100

66

83

100

MHz

sp11

sp11a

sp12

sp13

sp15

sp10

AACK/TA/TS/DBG/BG/BR

ARTRY/ TEA

6

5

4

3.5

4

0.5

Data bus in normal mode

Data bus in pipeline mode

All other pins

3.5

2.5

3.5

1

Input speciﬁcations are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

Table 10 lists SIU output characteristics.

1

Table 10. AC Characteristics for SIU Outputs

Spec Number

Characteristic

Value (ns)

Max

Min

Maximum Delay

Minimum Delay

66

83

100

66

83

100

MHz

sp31

sp32

sp30

PSDVAL/TEA/TA

7

8

6

5.5

1

ADD/ADD_atr./BADDR/CI/GBL/W

T

6.5

2

sp33

sp34

sp35

sp30

Data bus

6.5

6

6.5

5.5

0.5

1

0.5

1

0.5

1

Memory controller signals/ALE

All other signals

6

1

2

Output speciﬁcations are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing.

16

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical and Thermal Characteristics

Figure 9 shows the interaction of several bus signals.

CLKin

sp10

sp11

sp11a

sp12

AACK/TA/TS/

DBG/BG/BR input signals

ARTRY/TEA input signals

DATA bus normal mode

input signal

sp10

sp15

All other input signals

sp30

sp31

PSDVAL/TEA/TA output signals

sp32

sp30

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp33

DATA bus output signals

sp35

All other output signals

(except AP)

sp10

sp13

DATA bus pipeline mode

input signal

Figure 9. Bus Signals

Figure 10 shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 10. MEMC Mode Diagram

17

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Electrical and Thermal Characteristics

NOTE

Generally, all MPC8272 bus and system output signals are driven from the

rising edge of the input clock (CLKin). Memory controller signals,

however, trigger on four points within a CLKin cycle. Each cycle is

divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the

rising edge, and T3 at the falling edge, of CLKin. However, the spacing of

T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.

Table 11. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

PLL Clock Ratio

T2

T3

T4

1:2, 1:3, 1:4, 1:5, 1:6

1/4 CLKin

1/2 CLKin

3/4 CLKin

1:2.5

1:3.5

3/10 CLKin

4/14 CLKin

1/2 CLKin

8/10 CLKin

11/14 CLKin

Figure 11 is a representation of the information in Table 11.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

T1

T2

T3

T4

for 1:2.5

T2

T4

for 1:3.5

T2

T4

Figure 11. Internal Tick Spacing for Memory Controller Signals

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC speciﬁcations are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

18

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Clock Configuration Modes

3

Clock Conﬁguration Modes

The clocking mode is set according to two input pins—PCI_CFG[0] and PCI_MODCK—as shown in

Table 12.

Table 12. MPC8272 Clocking Modes

Pins

PCI Clock Frequency

Clocking Mode

Reference

Range (MHZ)

1

PCI_CFG[0]

PCI_MODCK

0

1

0

1

0

1

PCI host

50–66

25–50

50–66

25–50

Table 13

Table 14

Table 15

Table 16

PCI agent

1

Determines PCI clock frequency range

Within each mode, the conﬁguration of bus, core, PCI, and CPM frequencies is determined by seven bits

during the power-on reset—three hardware conﬁguration pins (MODCK[1–3]) and four bits from hardware

conﬁguration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected

clock operation mode as described in the following sections.

NOTE

Clock conﬁgurations change only after POR is asserted.

NOTE:Tval (Output Hold)

The minimum Tval = 2 when PCI_MODCK = 1, and the minimum

Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock

conﬁgurations that ﬁt this condition to achieve PCI-compliant AC timing.

3.1

PCI Host Mode

Table 13 and Table 14 show conﬁgurations for PCI host mode. The frequency values listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

conﬁguration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input

clock is the bus clock.

1, 2

Table 13. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=0)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

50.0 66.7

60.0 80.0

71.4 80.0

2

100.0 133.3

150.0 200.0

178.6 200.0

2.5

3

125.0 166.7

150.0 200.0

180.0 240.0

250.0 280.0

2

3

50.0 66.7

59.5 66.7

2

2.5

3

3.5

19

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 13. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=0)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0000_100

0000_101

0000_110

0000_111

62.5 80.0

50.0 66.7

2.5

3

156.3 200.0

150.0 200.0

4

3

250.0 320.0

150.0 200.0

3

52.1 66.7

50.0 66.7

PCI host mode (PCI_MODCK=1) only (refer to Table 14)

62.5 66.7

3

187.5 200.0

4

250.0 266.6

3

62.5 66.7

Full Conﬁguration Modes

0001_000

0001_001

0001_010

0001_011

50.0 66.7

3

150.0 200.0

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

3

50.0 66.7

0010_000

0010_001

0010_010

0010_011

50.0 66.7

4

200.0 266.6

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

4

50.0 66.7

0010_100

0010_101

0010_110

75.0 100.0

4

300.0 400.0

5

5.5

6

375.0 500.0

412.5 549.9

450.0 599.9

6

50.0 66.7

0011_000

0011_001

0011_010

0011_011

50.0 66.7

5

250.0 333.3

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

5

50.0 66.7

0100_000

0100_001

0100_010

0100_011

Reserved

50.0 66.7

6

300.0 400.0

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

6

50.0 66.7

0101_000

0101_001

50.0 66.7

2

100.0 133.3

2.5

3

125.0 166.7

150.0 200.0

2

50.0 66.7

20

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 13. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=0)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0101_010

0101_011

0101_100

PCI host mode (PCI_MODCK=1) only (refer to Table 14)

62.5 66.7

55.6 66.7

2

125.0 133.3

111.1 133.3

4

250.0 266.6

250.0 300.0

2

62.5 66.7

55.6 66.7

4.5

0101_101

0101_110

0101_111

83.3 111.1

3

250.0 333.3

3.5

4

291.7 388.9

333.3 444.4

375.0 500.0

5

50.0 66.7

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 80.0

71.4 80.0

62.5 80.0

60.0 80.0

2.5

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

2.5

3

150.0 200.0

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

300.0 400.0

360.0 480.0

3

50.0 66.7

59.5 66.7

52.1 66.7

50.0 66.7

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

3

50.0 66.7

3

150.0 200.0

3

50.0 66.7

PCI host mode (PCI_MODCK=1) only (refer to Table 14)

62.5 66.7

55.6 66.7

3

187.5 200.0

166.7 200.0

4

250.0 266.6

250.0 300.0

3

62.5 66.7

55.6 66.7

4.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 88.9

71.4 88.9

66.7 88.9

3

200.0 266.6

214.3 266.6

200.0 266.6

3

3.5

4

200.0 266.6

250.0 311.1

266.7 355.5

300.0 400.0

400.0 533.3

433.3 577.7

4

50.0 66.7

53.6 66.7

50.0 66.7

4.5

6

6.5

1001_000

57.1 76.2

3.5

200.0 266.6

2.5

142.9 190.5

4

50.0 66.7

21

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 13. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=0)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1001_001

1001_010

1001_011

1001_100

57.1 76.2

71.4 76.2

62.5 76.2

57.1 76.2

3.5

200.0 266.6

250.0 266.6

218.8 266.6

200.0 266.6

3

171.4 228.5

250.0 266.6

250.0 304.7

257.1 342.8

4

50.0 66.7

62.5 66.7

54.7 66.7

50.0 66.7

3.5

4

4.5

1001_101

1001_110

1001_111

85.7 114.3

3.5

300.0 400.0

5

5.5

6

428.6 571.4

471.4 628.5

514.3 685.6

6

50.0 66.7

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 100.0

2

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

300.0 400.0

3

50.0 66.7

3.5

4

1010_101

1010_110

1010_111

100.0 133.3

2

200.0 266.6

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

4

50.0 66.7

3.5

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 106.7

2.5

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

360.0 480.0

4

50.0 66.7

3.5

4

4.5

1101_000

1101_001

1101_010

1101_011

1101_100

100.0 133.3

2.5

250.0 333.3

3

3.5

4

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

5

50.0 66.7

4.5

5

22

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 13. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=0)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1101_101

1101_110

125.0 166.7

2

250.0 333.3

3

4

375.0 500.0

500.0 666.6

5

50.0 66.7

1110_000

1110_001

1110_010

1110_011

1110_100

100.0 133.3

3

300.0 400.0

3.5

4

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

6

50.0 66.7

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency

guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock

mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as

shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.

The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so

that the resulting conﬁguration does not exceed the frequency rating of the user’s device.

2

3

PCI_MODCK determines the PCI clock frequency range. Refer to Table 14 for lower range conﬁgurations.

MODCK_H = hard reset conﬁguration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).

MODCK[1-3] = three hardware conﬁguration pins.

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

1, 2

Table 14. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=1)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

50.0 100.0

60.0 120.0

71.4 120.0

2

100.0 200.0

150.0 300.0

178.6 300.0

2.5

3

125.0 250.0

150.0 300.0

180.0 360.0

250.0 420.0

4

6

25.0 50.0

29.8 50.0

2

2.5

3

3.5

23

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 14. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=1)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0000_100

0000_101

0000_110

0000_111

62.5 120.0

50.0 100.0

71.4 100.0

62.5 100.0

2.5

3

156.3 300.0

150.0 300.0

214.3 300.0

187.5 300.0

4

3

250.0 480.0

150.0 300.0

250.0 350.0

250.0 400.0

6

26.0 50.0

25.0 50.0

35.7 50.0

31.3 50.0

3

3.5

4

3

Full Conﬁguration Modes

0001_000

0001_001

0001_010

0001_011

50.0 100.0

3

150.0 300.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

6

25.0 50.0

0010_000

0010_001

0010_010

0010_011

50.0 100.0

4

200.0 400.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

8

25.0 50.0

0010_100

0010_101

0010_110

50.0 75.0

45.5 75.0

41.7 75.0

4

200.0 300.0

181.8 300.0

166.7 300.0

5

5.5

6

250.0 375.0

250.0 412.5

250.0 450.0

6

33.3 50.0

30.3 50.0

27.8 50.0

0011_000

0011_001

0011_010

0011_011

50.0 50.0

41.7 50.0

35.7 50.0

31.3 50.0

5

250.0 250.0

208.3 250.0

178.6 250.0

156.3 250.0

5

6

7

8

250.0 250.0

250.0 300.0

250.0 350.0

250.0 400.0

5

50.0 50.0

41.7 50.0

35.7 50.0

31.3 50.0

0100_000

0100_001

0100_010

0100_011

Reserved

41.7 50.0

35.7 50.0

31.3 50.0

6

250.0 300.0

214.3 300.0

187.5 300.0

6

7

8

250.0 300.0

250.0 350.0

250.0 400.0

6

41.7 50.0

35.7 50.0

31.3 50.0

0101_000

0101_001

50.0 100.0

2

100.0 200.0

2.5

3

125.0 250.0

150.0 300.0

4

25.0 50.0

24

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 14. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=1)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0101_010

0101_011

0101_100

71.4 100.0

62.5 100.0

55.6 100.0

2

142.9 200.0

125.0 200.0

111.1 200.0

3.5

4

250.0 350.0

250.0 400.0

250.0 450.0

4

35.7 50.0

31.3 50.0

27.8 50.0

4.5

0101_101

0101_110

0101_111

71.4 83.3

62.5 83.3

55.6 83.3

3

214.3 250.0

187.5 250.0

166.7 250.0

3.5

4

250.0 291.7

250.0 333.3

250.0 375.0

5

42.9 50.0

37.5 50.0

33.3 50.0

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 120.0

71.4 120.0

62.5 120.0

60.0 120.0

2.5

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

300.0 600.0

360.0 720.0

6

25.0 50.0

29.8 50.0

26.0 50.0

25.0 50.0

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 100.0

71.4 100.0

62.5 100.0

55.6 100.0

3

150.0 300.0

214.3 300.0

187.5 300.0

166.7 300.0

3

150.0 300.0

250.0 350.0

250.0 400.0

250.0 450.0

6

25.0 50.0

35.7 50.0

31.3 50.0

27.8 50.0

3.5

4

4.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

1000_110

Reserved

66.7 133.3

71.4 133.3

66.7 133.3

3

200.0 400.0

214.3 400.0

200.0 400.0

3

3.5

4

200.0 400.0

250.0 466.7

266.7 533.3

300.0 600.0

400.0 800.0

433.3 866.7

8

25.0 50.0

26.8 50.0

25.0 50.0

4.5

6

6.5

1001_000

Reserved

25

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 14. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=1)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1001_001

1001_010

1001_011

1001_100

1001_101

1001_110

1001_111

Reserved

71.4 114.3

62.5 114.3

57.1 114.3

50.0 85.7

45.5 85.7

42.9 85.7

3.5

250.0 400.0

218.8 400.0

200.0 400.0

175.0 300.0

159.1 300.0

150.0 300.0

3.5

4

250.0 400.0

250.0 457.1

257.1 514.3

250.0 428.6

250.0 471.4

257.1 514.3

8

6

31.3 50.0

27.3 50.0

25.0 50.0

29.2 50.0

26.5 50.0

25.0 50.0

4.5

5

5.5

6

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 150.0

2

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

300.0 600.0

6

25.0 50.0

3.5

4

1010_101

1010_110

1010_111

100.0 200.0

2

200.0 400.0

2.5

3

250.0 500.0

300.0 600.0

350.0 700.0

8

25.0 50.0

3.5

1011_000

1011_001

1011_010

1011_011

1011_100

1011_101

Reserved

80.0 160.0

2.5

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

360.0 720.0

8

25.0 50.0

3.5

4

4.5

1101_000

1101_001

1101_010

1101_011

1101_100

50.0 100.0

71.4 100.0

62.5 100.0

55.6 100.0

50.0 100.0

2.5

125.0 250.0

178.6 250.0

156.3 250.0

138.9 250.0

125.0 250.0

3

3.5

4

150.0 300.0

250.0 350.0

250.0 400.0

250.0 450.0

250.0 500.0

5

25.0 50.0

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

4.5

5

26

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 14. Clock Conﬁgurations for PCI Host Mode (PCI_MODCK=1)

1, 2

(continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

PCI Clock

(MHz)

3

Mode

CPM

CPU

(MHz)

PCI

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1101_101

1101_110

62.5 125.0

2

125.0 250.0

3

4

187.5 375.0

250.0 500.0

5

25.0 50.0

1110_000

1110_001

1110_010

1110_011

1110_100

71.4 100.0

62.5 100.0

55.6 100.0

50.0 100.0

3

214.3 300.0

187.5 300.0

166.7 300.0

150.0 300.0

3.5

4

250.0 350.0

250.0 400.0

250.0 450.0

250.0 500.0

275.0 550.0

6

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency

guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock

mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as

shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.

The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so

that the resulting conﬁguration does not exceed the frequency rating of the user’s device.

2

3

PCI_MODCK determines the PCI clock frequency range. Refer to Table 13 for higher range conﬁgurations.

MODCK_H = hard reset conﬁguration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).

MODCK[1-3] = three hardware conﬁguration pins.

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

3.1.1

PCI Agent Mode

Table 15 and Table 16 show conﬁgurations for PCI agent mode. The frequency values listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

conﬁguration does not exceed the frequency rating of the user’s device. Note that in PCI agent mode the

input clock is PCI clock.

27

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Clock Configuration Modes

1, 2

Table 15. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=0)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

50.0 66.7

62.5 66.7

50.0 66.7

59.5 66.7

53.6 66.7

50.0 66.7

2

3

4

100.0 133.3

150.0 200.0

187.5 200.0

150.0 200.0

178.6 200.0

214.3 266.6

200.0 266.6

2.5

3

125.0 166.7

150.0 200.0

250.0 266.6

180.0 240.0

250.0 280.0

250.0 311.1

240.0 320.0

2

50.0 66.7

62.5 66.7

60.0 80.0

71.4 80.0

71.4 88.9

80.0 106.7

3

4

3

2.5

3

3.5

3

2.5

Full Conﬁguration Modes

0001_001

0001_010

0001_011

0001_100

Reserved

62.5 66.7

2

125.0 133.3

8

250.0 266.6

4

31.3 33.3

0010_001

0010_010

0010_011

0010_100

50.0 66.7

59.5 66.7

52.1 66.7

50.0 66.7

3

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

3

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

2.5

60.0 80.0

71.4 80.0

62.5 80.0

60.0 80.0

3.5

4

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

0100_000

0100_001

0100_010

0100_011

Reserved

50.0 66.7

62.5 66.7

3

150.0 200.0

187.5 200.0

3

Reserved

4

150.0 200.0

250.0 266.6

3

50.0 66.7

62.5 66.7

28

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 15. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=0)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0100_100

55.6 66.7

3

166.7 200.0

4.5

250.0 300.0

3

55.6 66.7

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

50.0 66.7

5

250.0 333.3

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

2.5

100.0 133.3

3.5

4

4.5

5

5.5

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

50.0 66.7

53.6 66.7

50.0 66.7

4

200.0 266.6

214.3 266.6

200.0 266.6

3

200.0 266.6

250.0 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

71.4 88.9

66.7 88.9

3.5

4

4.5

0111_000

0111_001

0111_010

0111_011

50.0 66.7

3

150.0 200.0

2

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

2

75.0 100.0

2.5

3

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

50.0 66.7

59.5 66.7

52.1 66.7

50.0 66.7

3

150.0 200.0

178.6 200.0

156.3 200.0

150.0 200.0

2.5

3

150.0 200.0

180.0 240.0

250.0 280.0

250.0 320.0

270.0 360.0

2.5

60.0 80.0

71.4 80.0

62.5 80.0

60.0 80.0

3.5

4

4.5

1001_000

1001_001

1001_010

Reserved

29

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 15. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=0)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1001_011

1001_100

62.5 66.7

55.6 66.7

4

250.0 266.6

222.2 266.6

4

250.0 266.6

250.0 300.0

4

62.5 66.7

55.6 66.7

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

50.0 66.7

53.6 66.7

50.0 66.7

4

200.0 266.6

214.3 266.6

200.0 266.6

3

200.0 266.6

250.0 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

71.4 88.9

66.7 88.9

3.5

4

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

50.0 66.7

4

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

2.5

80.0 106.7

3.5

4

1011_101

1011_110

1011_111

50.0 66.7

4

200.0 266.6

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

2

100.0 133.3

3.5

1100_101

1100_110

1100_111

1101_000

50.0 66.7

6

300.0 400.0

4

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

3

100.0 133.3

4.5

5

5.5

1101_001

1101_010

1101_011

1101_100

50.0 66.7

6

300.0 400.0

3.5

4

420.0 559.9

480.0 639.9

540.0 719.9

600.0 799.9

2.5

120.0 160.0

4.5

5

1110_000

1110_001

50.0 66.7

5

250.0 333.3

2.5

3

312.5 416.6

375.0 500.0

2

125.0 166.7

30

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 15. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=0)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1110_010

1110_011

50.0 66.7

5

250.0 333.3

3.5

4

437.5 583.3

500.0 666.6

2

125.0 166.7

1110_100

1110_101

1110_110

1110_111

50.0 66.7

5

250.0 333.3

4

333.3 444.4

375.0 500.0

416.7 555.5

458.3 611.1

3

83.3 111.1

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency

guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock

mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as

shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.

The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so

that the resulting conﬁguration does not exceed the frequency rating of the user’s device.

2

3

PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for lower range conﬁgurations.

MODCK_H = hard reset conﬁguration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).

MODCK[1-3] = three hardware conﬁguration pins.

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

1, 2

Table 16. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=1)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

25.0 50.0

31.3 50.0

25.0 50.0

29.8 50.0

4

6

100.0 200.0

150.0 300.0

187.5 300.0

150.0 300.0

178.6 300.0

2.5

3

125.0 250.0

150.0 300.0

250.0 400.0

180.0 360.0

250.0 420.0

2

50.0 100.0

62.5 100.0

60.0 120.0

71.4 120.0

3

4

3

2.5

3.5

31

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 16. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=1)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0000_110

0000_111

26.8 50.0

25.0 50.0

8

214.3 400.0

200.0 400.0

3.5

3

250.0 466.7

240.0 480.0

3

71.4 133.3

80.0 160.0

2.5

Full Conﬁguration Modes

0001_001

0001_010

0001_011

0001_100

50.0 50.0

41.7 50.0

35.7 50.0

31.3 50.0

4

200.0 200.0

166.7 200.0

142.9 200.0

125.0 200.0

5

6

7

8

250.0 250.0

250.0 300.0

250.0 350.0

250.0 400.0

4

50.0 50.0

41.7 50.0

35.7 50.0

31.3 50.0

0010_001

0010_010

0010_011

0010_100

25.0 50.0

29.8 50.0

26.0 50.0

25.0 50.0

6

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

3

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

2.5

60.0 120.0

71.4 120.0

62.5 120.0

60.0 120.0

3.5

4

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

31.3 50.0

4

125.0 200.0

2.5

Reserved

4

104.3 166.7

3

41.7 66.7

46.9 50.0

41.7 50.0

4

187.5 200.0

166.7 200.0

250.0 266.7

250.0 300.0

3

62.5 66.7

55.6 66.7

4.5

0100_000

0100_001

0100_010

0100_011

0100_100

Reserved

25.0 50.0

35.7 50.0

31.3 50.0

27.8 50.0

6

150.0 300.0

214.3 300.0

187.5 300.0

166.7 300.0

3

150.0 300.0

250.0 350.0

250.0 400.0

250.0 450.0

3

50.0 100.0

71.4 100.0

62.5 100.0

55.6 100.0

3.5

4

4.5

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

25.0 50.0

35.7 50.0

31.3 50.0

27.8 50.0

25.0 50.0

5

125.0 250.0

178.6 250.0

156.3 250.0

138.9 250.0

125.0 250.0

2.5

3

125.0 250.0

150.0 300.0

250.0 350.0

250.0 400.0

250.0 450.0

250.0 500.0

2.5

50.0 100.0

71.4 100.0

62.5 100.0

55.6 100.0

50.0 100.0

3.5

4

4.5

5

32

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 16. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=1)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0101_110

25.0 50.0

5

125.0 250.0

5.5

275.0 550.0

2.5

50.0 100.0

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

25.0 50.0

26.8 50.0

25.0 50.0

8

200.0 400.0

214.3 400.0

200.0 400.0

3

200.0 400.0

250.0 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

71.4 133.3

66.7 133.3

3.5

4

4.5

0111_000

0111_001

0111_010

0111_011

25.0 50.0

6

150.0 300.0

2

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

2

75.0 150.0

2.5

3

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

25.0 50.0

29.8 50.0

26.0 50.0

25.0 50.0

6

150.0 300.0

178.6 300.0

156.3 300.0

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

250.0 420.0

250.0 480.0

270.0 540.0

2.5

60.0 120.0

71.4 120.0

62.5 120.0

60.0 120.0

3.5

4

4.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

4

31.3 50.0

27.8 50.0

8

250.0 400.0

222.2 400.0

250.0 400.0

250.0 450.0

4

62.5 100.0

55.6 100.0

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

25.0 50.0

26.8 50.0

25.0 50.0

8

200.0 400.0

214.3 400.0

200.0 400.0

3

200.0 400.0

250.0 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

71.4 133.3

66.7 133.3

3.5

4

4.5

33

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 16. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=1)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

25.0 50.0

8

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

2.5

80.0 160.0

3.5

4

1011_101

1011_110

1011_111

25.0 50.0

8

200.0 400.0

2.5

3

250.0 500.0

300.0 600.0

350.0 700.0

2

100.0 200.0

3.5

1100_101

1100_110

1100_111

1101_000

31.3 50.0

27.8 50.0

25.0 50.0

6

187.5 300.0

166.7 300.0

150.0 300.0

4

250.0 400.0

250.0 450.0

250.0 500.0

275.0 550.0

3

62.5 100.0

55.6 100.0

50.0 100.0

4.5

5

5.5

1101_001

1101_010

1101_011

1101_100

29.8 50.0

26.0 50.0

25.0 50.0

6

178.6 300.0

156.3 300.0

150.0 300.0

3.5

4

250.0 420.0

250.0 480.0

270.0 540.0

300.0 600.0

2.5

71.4 120.0

62.5 120.0

60.0 120.0

4.5

5

1110_000

1110_001

1110_010

1110_011

25.0 50.0

28.6 50.0

25.0 50.0

5

125.0 250.0

142.9 250.0

125.0 250.0

2.5

3

156.3 312.5

187.5 375.0

250.0 437.5

250.0 500.0

2

62.5 125.0

71.4 125.0

62.5 125.0

3.5

4

1110_100

1110_101

1110_110

1110_111

37.5 50.0

33.3 50.0

30.0 50.0

27.3 50.0

5

187.5 250.0

166.7 250.0

150.0 250.0

136.4 250.0

4

250.0 333.3

250.0 375.0

250.0 416.7

250.0 458.3

3

62.5 83.3

55.6 83.3

50.0 83.3

45.5 83.3

4.5

5

5.5

34

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Clock Configuration Modes

Table 16. Clock Conﬁgurations for PCI Agent Mode (PCI_MODCK=1)

1, 2

(continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency

guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock

mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as

shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz.

The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so

that the resulting conﬁguration does not exceed the frequency rating of the user’s device.

2

3

PCI_MODCK determines the PCI clock frequency range. Refer to Table 15 for higher range conﬁgurations.

MODCK_H = hard reset conﬁguration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual).

MODCK[1-3] = three hardware conﬁguration pins.

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

35

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

4

Pinout

The ﬁgure and table below show the pin assignments and pinout for the 516 PBGA package.

4.1

Pin Assignments

Figure 12 shows the pinout of the 516 PBGA package as viewed from the top surface.

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A

B

A

B

C

D

E

F

G

H

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Not to Scale

Figure 12. Pinout of the 516 PBGA Package (View from Top)

36

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

Table 17 shows the pinout of the MPC8272. Note that the pins in the ‘MPC8272/8271 only” column relate

to Utopia functionality.

1

Table 17. Pinout

Pin Name

Ball

MPC8272/MPC8248 and

MPC8272/MPC8271 only

MPC8271/MPC8247

BR

A19

D2

BG/IRQ6

ABB/IRQ2

TS

C1

D1

A0

A3

A1

B5

A2

D8

A3

C6

A4

A5

A6

B6

A7

C7

A8

B7

A9

A7

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

D9

E11

C9

B9

D11

A9

B10

A10

B11

A11

D12

A12

D13

B13

C13

C14

37

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

A26

B14

D14

E14

A14

B15

A15

B3

A27

A28

A29

A30

A31

TT0

TT1

E8

TT2

D7

TT3

C4

TT4

E7

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

E3

E4

E5

C3

D5

D3

ARTRY

DBG/IRQ7

DBB/IRQ3

D0

C2

F16

D18

AC1

AA1

V3

D1

D2

D3

R5

D4

P4

D5

M4

J4

D6

D7

G1

W6

Y3

D8

D9

D10

D11

V1

N6

38

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

P3

M2

J5

G3

AB3

Y1

T4

T3

P2

M1

J1

G4

AB2

W4

V2

T1

N5

L1

H1

G5

W5

W2

T5

T2

N1

K3

H2

F1

AA2

W1

U3

R2

39

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

D44

D45

D46

D47

D48

D49

D50

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

N2

L2

H4

F2

AB1

U4

U1

R3

N3

K2

H5

F4

AA3

U5

U2

P5

M3

K4

H3

E1

IRQ3/CKSTP_OUT/EXT_BR3

IRQ4/CORE_SRESET/EXT_BG3

IRQ5/TBEN/EXT_DBG3/CINT

PSDVAL

B16

C15

Y4

C19

AA4

AB6

D15

D16

C16

E17

B20

AE6

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

BADDR31/IRQ5/CINT

CPU_BR/INT_OUT

CS0

40

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

CS1

CS2

CS3

CS4

CS5

AD7

AF5

AC8

AF6

AD8

AC9

AB9

AB8

AC7

AF4

BCTL1/CS6/SMI

CS7/TLBISYNC

BADDR27/IRQ1

BADDR28/IRQ2

ALE/IRQ4

BCTL0

AF3

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4

PSDAMUX/PGPL5

PCI_HOST_EN

PCI_ARB_EN

AD6

AE5

AE3

AF2

AC6

AC5

AD4

AB5

AE2

AD3

AB4

AC3

AD2

AC2

AC21

AE22

AE23

AF12

AD15

AF16

AF15

DLL_ENABLE

PAR

FRAME

TRDY

IRDY

41

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

STOP

AE15

AE14

AC17

AD14

AD13

AE20

AF14

AD20

AE13

AF21

AF22

AE21

AB14

AC22

AF7

DEVSEL

IDSEL

PERR

SERR

REQ0

REQ1

GNT0

GNT1

GNT2

PCI_RST

INTA

REQ2

DLLOUT

AD0

AD1

AE10

AB10

AD10

AE9

AD2

AD3

AD4

AD5

AF8

AD6

AC10

AE11

AB11

AF10

AF9

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AB12

AC12

AD12

AF11

AB13

AE16

AF17

42

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

AD16

AC16

AF18

AB16

AD17

AF19

AB17

AF20

AE19

AC18

AB18

AD19

AD21

AC20

AE12

AF13

AC15

AE18

A17

C0/BE0

C1/BE1

C2/BE2

C3/BE3

IRQ0/NMI_OUT

TRST

E21

TCK

B22

TMS

C23

TDI

B24

TDO

A22

TRIS

B23

PORESET/PCI_RST

HRESET

C24

D22

SRESET

F22

RSTCONF

A24

MODCK1/RSRV/TC0/BNKSEL0

MODCK2/CSE0/TC1/BNKSEL1

MODCK3/CSE1/TC2/BNKSEL2

A20

C20

A21

43

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

CLKIN1

D21

AF25

AA22

AB23

2

PA8/SMRXD2

PA9/SMTXD2

PA10/MSNUM5

FCC1_UT_RXD0

PA11/MSNUM4

FCC1_UT_RXD1

FCC1_UT_RXD2

FCC1_UT_RXD3

FCC1_UT_RXD4

FCC1_UT_RXD5

FCC1_UT_RXD6

FCC1_UT_RXD7

AD26

AD25

2

PA12/MSNUM3

2

PA13/MSNUM2

AA24

2

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

PA16/FCC1_MII_HDLC_RXD1

W22

2

Y24

2

T22

2

PA17/FCC1_MII_HDLC_RXD0/

FCC1_MII_TRAN_RXD/FCC1_RMII_R

XD0

W26

2

PA18/FCC1_MII_HDLC_TXD0/FCC1_ FCC1_UT_TXD7

MII_TRAN_TXD/

FCC1_RMII_TXD0

V26

R23

2

PA19/FCC1_MII_HDLC_TXD1/FCC1_ FCC1_UT_TXD6

RMII_TXD1

2

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

FCC1_UT_TXD5

FCC1_UT_TXD4

FCC1_UT_TXD3

FCC1_UT_TXD2

FCC1_UT_TXD1

FCC1_UT_TXD0

FCC1_UT_RXCLAV

P25

N22

N26

N23

H26

2

PA23

PA24/MSNUM1

PA25/MSNUM0

G25

2

PA26/FCC1_MII_RMIIRX_ER

L22

2

PA27/FCC1_MII_RX_DV/FCC1_RMII_ FCC1_UT_RXSOC

CRS_DV

G24

2

PA28/FCC1_MII_RMII_TX_EN

PA29/FCC1_MII_TX_ER

FCC1_UT_RXENB

FCC1_UT_TXSOC

FCC1_UT_TXCLAV

FCC1_UT_TXENB

G23

2

B26

A25

PA30/FCC1_MII_CRS/FCC1_RTS

PA31/FCC1_MII_COL

G22

2

PB18/FCC2_MII_HDLC_RXD3/L1CLKOD2

PB19/FCC2_MII_HDLC_RXD2/L1RQD2

PB20/FCC2_MII_HDLC_RMII_RXD1

T25

P22

2

L25

44

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

2

PB21/FCC2_MII_HDLC_RMII_XD0/FCC2_TRAN_RXD

J26

2

PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/

FCC2_RMII_TXD0

U23

2

PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1

PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2

PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2

PB26/FCC2_MII_CRS/L1RXDB2

U26

M24

M23

2

H24

2

PB27/FCC2_MII_COL/L1TXDB2

E25

PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1

PB29/FCC2_MII_RMII_TX_EN

D26

2

K21

D24

2

PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV

PB31/FCC2_MII_TX_ER

2

E23

2

PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2

PC1/BRGO6/L1RQA2

AF23

2

AD23

2

PC4/SMRXD1/SI2_L1ST4/FCC2_CD

PC5/SMTXD1/SI2_L1ST3/FCC2_CTS

AB22

AE24

2

PC6/FCC1_CD/SI2_L1ST2

PC7/FCC1_CTS

FCC1_UT_RXADDR2

AF24

2

FCC1_UT_TXADDR2

AE26

AC24

AA23

AB25

2

PC8/CD4/RTS1/SI2_L1ST2/CTS3

PC9/CTS4/L1TSYNCA2

PC10/CD3/USB_RN

PC11/CTS3/USB_RP/L1TXD3A2

PC12/DONE3

2

V22

2

FCC1_UT_RXADDR1

FCC1_UT_TXADDR1

FCC1_UT_RXADDR0

FCC1_UT_TXADDR0

AA26

2

PC13/BRGO5

V23

2

PC14/CD1

W24

2

PC15/CTS1

U24

2

PC16/CLK16

T23

T26

2

PC17/CLK15/BRGO8/DONE2

PC18/CLK14/TGATE2

PC19/CLK13/BRGO7/TGATE1

PC20/CLK12/USBOE

PC21/CLK11/BRGO6/CP_INT

R26

2

P24

2

L26

L24

2

45

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

FCC1_UT_TXPRTY

2

PC22/CLK10/DONE3

L23

K24

K23

2

PC23/CLK9/BRGO5/DACK3/CD1

PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1

PC25/CLK7/BRGO4/DACK2/SPISEL

PC26/CLK6/TOUT3/TMCLK

2

F26

H23

2

PC27/CLK5/BRGO3/TOUT1

PC28/CLK4/TIN1/TOUT2/SPICLK

PC29/CLK3/TIN2/BRGO2/CTS1

PD7/SMSYN2

FCC1_UT_RXPRTY

K22

D25

2

F24

2

FCC1_UT_TXADDR3

AB21

AC26

2

PD14/I2CSCL

2

PD15/I2CSDA

Y23

2

PD16/SPIMISO

FCC1_UT_TXPRTY

FCC1_UT_RXPRTY

FCC1_UT_RXADDR4

FCC1_UT_TXADDR4

AA25

2

PD17/BRGO2/SPIMOSI

PD18/SPICLK

Y26

2

W25

2

PD19/SPISEL/BRGO1

PD20/RTS4/L1RSYNCA2

PD21/TXD4/L1RXD0A2

PD22/RXD4/L1TXD0A2

PD23/RTS3/USB_TP

PD24/TXD3/USB_TN

PD25/RXD3/USB_RXD

PD29/RTS1

V25

R24

2

P23

2

N25

2

K26

K25

2

J25

FCC1_UT_RXADDR3

C26

2

PD30/TXD1

E24

B25

2

PD31/RXD1

VCCSYN

C18

K6

VCCSYN1

CLKIN2

C21

AD24

3

SPARE0

4

THERMAL0

D19

4

THERMAL1

J3

46

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Pinout

1

Table 17. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 only

I/O power

B4, F3, J2, N4, AD1, AD5, AE8,

AC13, AD18, AB24, AB26, W23,

R25, M25, F25, C25, C22, B17,

B12, B8, E6, F6, H6, L5, L6, P6,

T6, U6, V5, Y5, AA6, AA8, AA10,

AA11, AA14, AA16, AA17, AB19,

AB20, W21, U21, T21, P21, N21,

M22, J22, H21, F21, F19, F17,

E16, F14, E13, E12, F10, E10, E9

Core Power

F5, K5, M5, AA5, AB7, AA13,

AA19, AA21, Y22, AC25, U22,

R22, L21, H22, E22, E20, E15,

F13, F11, F8, L3, V4, W3, AC11,

AD11, AB15, U25, T24, J24, H25,

F23, B19, D17, C17, D10, C10

Ground

AD22, E19, E2, K1, Y2, AE1, AE4,

AD9, AC14, AE17, AC19, AE25,

V24, P26, M26, G26, E26, B21,

C12, C11, C8, A8, B18, A18, A2,

B1, B2, A5, C5, D4, D6, G2, L4,

P1, R1, R4, AC4, AE7, AC23,Y25,

N24, J23, A23, D23, D20, E18,

A13, A16, K10, K11, K12, K13,

K14, K15, K16, K17, L10, L11, L12,

L13, L14, L15, L16, L17, M10,

M11, M12, M13, M14, M15, M16,

M17, N10, N11, N12, N13, N14,

N15, N16, N17, P10, P11, P12,

P13, P14, P15, P16, P17, R10,

R11,R12, R13, R14, R15, R16,

R17, T10, T11, T12, T13, T14, T15,

T16, T17, U10, U11, U12, U13,

U14, U15, U16, U17

1

2

Pinout ball assignments are subject to change. Motorola will indicate to Cisco when ball assignments are ﬁnalized.

The default conﬁguration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input.To prevent

excessive DC current, it is recommended either to pull unused pins to GND orVDDH, or to conﬁgure them as outputs.

3

4

Must be pulled down or left ﬂoating

This pin is not connected. It should be left ﬂoating.

47

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Package

5

Package

Figure 13 shows the side proﬁle of the PBGA package.

Wire bonds

Ball bond

Die

attach

Transfer molding compound

Plated substrate via

Screen-printed

solder mask

Cu substrate traces

DIE

Resin glass epoxy

1 mm pitch

Figure 13. Side View of the PBGA Package Remove

Table 18 provides package parameters. Figure 14 provides the mechanical dimensions and bottom surface

nomenclature of the 516 PBGA package.

Table 18. Package Parameters

Outline

(mm)

Pitch

(mm)

NominalUnmounted

Height (mm)

Type

Interconnects

27 x 27

PBGA

516

1

2.25

48

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

Package

Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA

49

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Ordering Information

6

Ordering Information

Figure 15 provides an example of the Motorola part numbering nomenclature for the MPC8272. In addition

to the processor frequency, the part numbering scheme also consists of a part modiﬁer that indicates any

enhancement(s) in the part from the original production design. Each part number also contains a revision

code that refers to the die mask revision number and is speciﬁed in the part numbering scheme for

identiﬁcation purposes only. For more information, contact a local Motorola sales ofﬁce.

MPC 82XX C VR XXX X

Die Revision Level

Product Code

Device Number

CPU/CPM/Bus Frequency (MHz)

B = 66

Temperature Range

Blank = 0 to 105 ˚C

C = -40 to 105 ˚C

E = 100

I = 200

M = 266

P = 300

T = 400

Package

ZQ = 516 PBGA (lead spheres)

VR = 516 PBGA (no lead spheres)

Figure 15. Motorola Part Number Key

7

Document Revision History

Table 19 lists signiﬁcant changes between revisions of this hardware speciﬁcation.

Table 19. Document Revision History

Date

Substantive Changes

Revision

0

5/2003

9/2003

NDA release

• Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine)

0.1

• Table 3: Addition of note 2 to V

IH

• Table 3: Changed I for 60x signals to 6.0 mA

OL

• Modiﬁcation of note 1 for Table 13, Table 14, Table 15, and Table 16

• Table 17: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned

to both CS5 and GND. AD8 is only assigned to CS5.

• Table 17: Addition of note 4 to Thermal0 (D19) and Thermal1(J3)

• Addition of ZQ package code to Figure 15

50

MPC8272 Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

51

MPC8272 Family Hardware Speciﬁcations

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

MOTOROLA

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P.O. Box 5405, Denver, Colorado 80217

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Motorola Japan Ltd.

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Tokyo 106-8573 Japan

Information in this document is provided solely to enable system and software implementers to use

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81-3-3440-3569

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Opportunity/Afﬁrmative Action Employer.

MPC8272EC


型号：	MPC8247ZQTIE
厂家：	MOTOROLA
描述：	Micro Peripheral IC, CMOS, PBGA516,
文件：	总52页 (文件大小：892K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC8247ZQTIE [MOTOROLA]

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