MPC826XACZUSPU [MOTOROLA]
MPC826xA (HiP4) Family Hardware Specifications; MPC826xA （ HiP4 ）系列硬件特定网络阳离子
| 型号： | MPC826XACZUSPU |
| 厂家： | 
MOTOROLA |
| 描述： | MPC826xA (HiP4) Family Hardware Specifications |
| 文件： | 总48页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
MPC8260AEC/D
Rev.0.7 5/2002
MPC826xA (HiP4) Family
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for HiP4-enhanced derivatives of the
PowerQUICC II™ MPC8260 communications processor (collectively referred to as the
MPC826xA).
The following topics are addressed:
Topic
Page
3
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “Power Considerations”
Section 1.2.4, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.3.2, “PCI Mode”
7
7
12
12
13
19
19
22
29
42
44
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 1 shows the functionality that defines each derivative of the HiP4-enhanced PowerQUICC II family.
Table 1. HiP4 PowerQUICC II Family Derivatives
Derivatives
Functionality
MPC8260A MPC8264A MPC8265A MPC8266A
HiP4 Process Enhancements
PCI Bridge
X
X
X
X
X
X
X
X
Transmission Convergence (TC) Layer
Inverse Multiplexing for ATM (IMA)
X
X
Until a revision of the current MPC8260 PowerQUICC II User’s Manual (Rev 0) is available, several
addendum documents supply information about the functionality of HiP4-enhanced PowerQUICC II
devices. Table 2 lists each device and its related documentation.
Table 2. HiP4 PowerQUICC II Documentation
Derivatives
Document
MPC8260A MPC8264A MPC8265A MPC8266A
MPC8260 PowerQUICC II User’s Manual, Rev 0
X
X
X
X
(order number: MPC8260UM/D)
MPC8260A (HiP4) Supplement to the MPC8260
PowerQUICC II User’s Manual (Preliminary)
(order number: MPC8260AUM/D)
X
X
X
X
PCI Bridge Functional Specification (Preliminary)
(order number: MPC8265AUMAD/D)
X
X
X
X
TC Layer Functional Specification (Preliminary)
(order number: MPC8264AUMAD/D)
X
X
IMA Functional Specification (Preliminary)
(order number: MPC8266AUMAD/D)
2
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
Figure 1 shows the block diagram for the HiP4 superset device, the MPC8266A.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
60x Bus
G2 Core
16 Kbytes
Bus Interface Unit
D-Cache
2,3
PCI Bus
32 bits, up to 66 MHz
60x-to-PCI
D-MMU
2,3
Bridge
or
60x-to-Local
Bridge
Local Bus
32 bits, up to 83 MHz
Communication Processor Module (CPM)
Memory Controller
Clock Counter
Timers
Serial
DMAs
32 Kbytes
Dual-Port RAM
Interrupt
Controller
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
System Functions
Baud Rate
Generators
IMA1,3
Microcode
I2C
MCC1 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
1,3
SPI
TC Layer Hardware
Time Slot Assigner
Serial Interface
Notes:
1. MPC8264A
2. MPC8265A
3. MPC8266A
Non-Multiplexed
I/O
3 MII
Ports
2 UTOPIA
Ports
8 TDM Ports
Figure 1. MPC8266A Block Diagram
1.1 Features
The major features of the MPC826xA family are as follows:
•
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 420 Dhrystones MIPS at
300 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
•
Separate power supply for internal logic and for I/O
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
•
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge (MPC8265A and MPC8266A only)
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
•
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
4
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
5
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
Additional features of the MPC826xA family are as follows:
•
CPM
— 32-Kbyte dual-port RAM
— Additional MCC host commands
— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support
inverse multiplexing for ATM capabilities (IMA) (MPC8264A and MPC8266A only)
•
•
CPM multiplexing
— FCC2 can also be connected to the TC layer.
TC layer (MPC8264A and MPC8266A only)
— Each of the 8 TDM channels is routed in hardware to a TC layer block
– Protocol-specific overhead bits may be discarded or routed to other controllers by the SI
– Performing ATM TC layer functions (according to ITU-T I.432)
– Transmit (Tx) updates
– Cell HEC generation
– Payload scrambling using self synchronizing scrambler (programmable by the user)
– Coset generation (programmable by the user)
– Cell rate by inserting idle/unassigned cells
– Receive (Rx) updates
– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA
parameters for the delineation state machine
– Payload descrambling using self synchronizing scrambler (programmable by the user)
– Coset removing (programmable by the user)
– Filtering idle/unassigned cells (programmable by the user)
– Performing HEC error detection and single bit error correction (programmable by user)
– Generating loss of cell delineation status/interrupt (LOC/LCD)
— Operates with FCC2 (UTOPIA 8)
— Provides serial loop back mode
— Cell echo mode is provided
— Supports both FCC transmit modes
– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.
– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.
The TC layer generates idle/unassigned cells to maintain the line bit rate.
6
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
– 16-bit counters count
– HEC error cells
– HEC single bit error and corrected cells
– Idle/unassigned cells filtered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
– Maskable interrupt is sent to the host when a counter expires
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported
•
PCI bridge (MPC8265A and MPC8266A only)
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I O standard
2
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
1.2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC826xA.
1.2.1 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC826xA. Table 3 shows the maximum
electrical ratings.
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 3. Absolute Maximum Ratings
1
Rating
Symbol
Value
Unit
2
Core supply voltage
VDD
VCCSYN
VDDH
VIN
-0.3 – 2.5
-0.3 – 2.5
V
V
2
PLL supply voltage
3
I/O supply voltage
-0.3 – 4.0
V
4
Input voltage
GND(-0.3) – 3.6
120
V
Junction temperature
T
˚C
˚C
j
Storage temperature range
T
(-55) – (+150)
STG
1
Absolute maximum ratings are stress ratings only; functional operation (see
Table 4) at the maximums is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage.
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time,
including during power-on reset.
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no
more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than
2.5 V during normal operation.
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including
during power-on reset.
2
3
4
Table 4 lists recommended operational voltage conditions.
1
Table 4. Recommended Operating Conditions
Rating
Symbol
Value
Unit
2
3
Core supply voltage
PLL supply voltage
I/O supply voltage
VDD
VCCSYN
VDDH
VIN
1.7 – 2.1 / 1.9 –2.1
V
V
2
3
1.7 – 2.1 /1.9–2.1
3.135 – 3.465
V
Input voltage
GND (-0.3) – 3.465
V
4
Junction temperature (maximum)
Ambient temperature
T
105
˚C
˚C
j
4
T
0–70
A
1
2
3
4
Caution: These are the recommended and tested operating conditions. Proper device
operating outside of these conditions is not guaranteed.
For devices operating at less than 233 MHz CPU, 166 MHz CPM, and 66 MHz bus
frequencies.
For devices operating at greater than or equal to 233 MHz CPU, 166 MHz CPM, and
66 MHz bus frequencies.
Note that for extended temperature parts the range is (-40) – 105 .
T
T
j
A
NOTE
VDDH and VDD must track each other and both must vary in the same
direction—in the positive direction (+5% and +0.1 Vdc) or in the negative
direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or V ).
CC
8
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 5 shows DC electrical characteristics.
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
Input low voltage
V
2.0
GND
2.4
GND
—
3.465
0.8
3.465
0.4
10
V
V
IH
V
IL
CLKIN input high voltage
V
V
IHC
CLKIN input low voltage
V
I
V
ILC
1
Input leakage current, V = VDDH
µA
µA
µA
µA
V
IN
IN
1
Hi-Z (off state) leakage current, V = VDDH
I
—
10
IN
OZ
Signal low input current, V = 0.8 V
I
—
1
IL
L
Signal high input current, V = 2.0 V
I
—
1
IH
H
Output high voltage, I = –2 mA
V
2.4
—
OH
OH
except XFC, UTOPIA mode, and open drain pins
In UTOPIA mode: I = -8.0mA
OH
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
In UTOPIA mode: I = 8.0mA
V
—
0.5
V
OL
OL
PA[0-31]
PB[4-31]
PC[0-31]
PD[4-31]
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
9
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 5. DC Electrical Characteristics (Continued)
Characteristic
Symbol
Min
Max
Unit
I
= 7.0mA
V
—
0.4
V
OL
OL
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
10
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Table 5. DC Electrical Characteristics (Continued)
Characteristic
Symbol
Min
Max
Unit
I
= 5.3mA
V
—
0.4
V
OL
OL
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
2
LWE[0–3]LSDDQM[0:3]/LBS[0–3]/PCI_CFG[0–3
2
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
2
2
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
2
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
2
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
= 3.2mA
OL
2
L_A14/PAR
2
L_A15/FRAME /SMI
2
L_A16/TRDY
2
L_A17/IRDY /CKSTP_OUT
2
L_A18/STOP
2
L_A19/DEVSEL
2
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
2
2
2
2
2
2
L_A24/REQ1 /HSEJSW
2
L_A25/GNT0
2
2
L_A26/GNT1 /HSLED
2
L_A27/GNT2 /HSENUM
2
L_A28/RST /CORE_SRESET
2
L_A29/INTA
2
L_A30/REQ2
L_A31
LCL_D(0-31)/AD(0-31)
2
2
LCL_DP(0-3)/C/BE(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
1
2
The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same
direction; that is, VDDH and VDD either both vary in the positive direction (+5% and +0.1 Vdc) or both vary in
the negative direction (-5% and -0.1 Vdc).
MPC8265A and MPC8266A only.
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
1.2.2 Thermal Characteristics
Table 6 describes thermal characteristics.
Table 6. Thermal Characteristics
Characteristics
Symbol
Value
Unit
Air Flow
1
2
Thermal resistance for TBGA
θ
θ
13.07
°C/W
°C/W
°C/W
°C/W
NC
JA
JA
JA
JA
1
9.55
1 m/s
NC
3
θ
θ
10.48
3
7.78
1 m/s
1
2
3
Assumes a single layer board with no thermal vias
Natural convection
Assumes a four layer board
1.2.3 Power Considerations
The average chip-junction temperature, T , in °C can be obtained from the following:
J
T = T + (P x θJA)
(1)
J
A
D
where
T = ambient temperature °C
A
θJA = package thermal resistance, junction to ambient, °C/W
P = P
+ P
I/O
D
INT
P
P
= I x V Watts (chip internal power)
DD DD
INT
= power dissipation on input and output pins (determined by user)
I/O
For most applications P < 0.3 x P . If P is neglected, an approximate relationship between P and T
I/O
INT
I/O
D
J
is the following:
P = K/(T + 273° C)
(2)
D
J
Solving equations (1) and (2) for K gives:
2
K = P x (T + 273° C) + θJA x P
D
(3)
D
A
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by solving
D
A
D
J
equations (1) and (2) iteratively for any value of T .
A
1.2.3.1 Layout Practices
Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground pin
CC
should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct
groups of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF
CC
by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V and ground should be kept to less than half an inch
CC
per capacitor lead.A four-layer board is recommended, employing two inner layers asVCC and GND planes.
12
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
All output pins on the MPC826xA have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be inputs
CC
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above P = 3W (when the ambient temperature is 70˚ C or
D
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that the
I/O power should be included when determining whether to use a heat sink.
1
Table 7. Estimated Power Dissipation for Various Configurations
2
P
(W)
INT
Bus
(MHz)
CPM
Core CPU
CPM
(MHz)
CPU
(MHz)
Vddl 1.8 Volts
Vddl 2.0 Volts
Multiplier Multiplier
Nominal Maximum Nominal Maximum
66.66
66.66
66.66
66.66
83.33
83.33
83.33
2
2.5
3
3
3
133
166
200
200
166
166
208
200
200
266
300
250
250
291
1.2
1.3
—
2
2.1
—
—
—
—
—
1.8
1.9
2.3
2.4
2.2
2.2
2.4
2.3
2.3
2.9
3.1
2.8
2.8
3.1
4
3
4.5
3
—
2
—
2
3
—
2.5
3.5
—
1
2
Test temperature = room temperature (25˚ C)
= I x V Watts
P
INT
DD
DD
1.2.4 AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC826xA device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 8.
1
Table 8. Output Buffer Impedances
Output Buffers
60x bus
Typical Impedance (Ω)
40
40
40
46
25
Local bus
Memory controller
Parallel I/O
PCI
1
These are typical values at 65˚ C. The impedance may vary
by ±25% with process and temperature.
MOTOROLA
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Electrical and Thermal Characteristics
Table 9 lists CPM output characteristics.
1
Table 9. AC Characteristics for CPM Outputs
Max Delay (ns) Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
Spec_num
Max/Min
Characteristic
sp36a/sp37a FCC outputs—internal clock (NMSI)
sp36b/sp37b FCC outputs—external clock (NMSI)
sp40/sp41 TDM outputs/SI
6
5.5
12
16
16
16
11
1
2
5
1
2
1
1
1
14
25
19
19
14
4
sp38a/sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
sp38b/sp39b Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
sp42/sp43 PIO/TIMER/DMA outputs
0.5
1
0.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of
the signal. Timings are measured at the pin.
Table 10 lists CPM input characteristics.
1
Table 10. AC Characteristics for CPM Inputs
Setup (ns)
Hold (ns)
Spec_num
Characteristic
66 MHz 83 MHz 66 MHz 83 MHz
sp16a/sp17a FCC inputs—internal clock (NMSI)
sp16b/sp17b FCC inputs—external clock (NMSI)
10
3
8
2.5
12
16
4
0
3
0
2
sp20/sp21
TDM inputs/SI
15
20
5
12
0
10
0
sp18a/sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
sp18b/sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)
5
4
sp22/sp23
PIO/TIMER/DMA inputs
10
8
3
3
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising
edge of CLKIN. Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
Figure 2 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Figure 2. FCC External Clock Diagram
14
MPC826xA (HiP4) Family Hardware Specifications
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Electrical and Thermal Characteristics
Figure 3 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
FCC output signals
sp36a/sp37a
Figure 3. FCC Internal Clock Diagram
2
Figure 4 shows the SCC/SMC/SPI/I C external clock.
Serial CLKin
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp19b
sp18b
sp38b/sp39b
2
Figure 4. SCC/SMC/SPI/I C External Clock Diagram
2
Figure 5 shows the SCC/SMC/SPI/I C internal clock.
BRG_OUT
SCC/SMC/SPI/I2C input signals
SCC/SMC/SPI/I2C output signals
sp19a
sp18a
sp38a/sp39a
2
Figure 5. SCC/SMC/SPI/I C Internal Clock Diagram
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Electrical and Thermal Characteristics
Figure 6 shows PIO, timer, and DMA signals.
CLKin
sp23
sp22
PIO/TIMER/DMA input signals
TIMER/DMA output signals
sp42/sp43
sp42/sp43
PIO output signals
Figure 6. PIO, Timer, and DMA Signal Diagram
Table 12 lists SIU input characteristics.
1
Table 11. AC Characteristics for SIU Inputs
Setup (ns)
Hold (ns)
Spec_num
Characteristic
66 MHz 83 MHz 66 MHz 83 MHz
sp11/sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
sp12/sp10 Data bus in normal mode
sp13/sp10 Data bus in ECC and PARITY modes
sp14/sp10 DP pins
6
5
8
7
5
5
4
6
6
4
1
1
1
1
1
1
1
1
1
1
sp15/sp10 All other pins
1
Input specifications are measured from the 50% level of the signal to the 50% level of
the rising edge of CLKIN. Timings are measured at the pin.
Table 12 lists SIU output characteristics.
1
Table 12. AC Characteristics for SIU Outputs
Max Delay (ns)
Characteristic
Min Delay (ns)
Spec_num
Max/Min
66 MHz 83 MHz 66 MHz 83 MHz
sp31/sp30 PSDVAL/TEA/TA
sp32/sp30 ADD/ADD_atr./BADDR/CI/GBL/WT
sp33a/sp30 Data bus
7
8
6
6.5
6.5
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6.5
8
sp33b/sp30 DP
sp34/sp30 memc signals/ALE
sp35/sp30 all other signals
6
5
6
5.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to
the 50% level of the signal. Timings are measured at the pin.
16
MPC826xA (HiP4) Family Hardware Specifications
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Electrical and Thermal Characteristics
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
Figure 7 shows TDM input and output signals.
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Figure 7. TDM Signal Diagram
Figure 8 shows the interaction of several bus signals.
CLKin
sp10
sp10
sp10
sp11
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp12
sp15
DATA bus normal mode
input signal
All other input signals
sp30
sp31
sp32
PSDVAL/TEA/TA output signals
sp30
sp30
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33a
sp35
DATA bus output signals
All other output signals
Figure 8. Bus Signals
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17
Electrical and Thermal Characteristics
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode input signals
sp10
sp14
DP mode input signal
sp33b/sp30
DP mode output signal
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 10. MEMC Mode Diagram
NOTE
Generally, all MPC826xA bus and system output signals are driven from
the rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
Table 13. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
1:3.5
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
8/10 CLKin
11/14 CLKin
18
MPC826xA (HiP4) Family Hardware Specifications
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Clock Configuration Modes
Figure 11 is a graphical representation of Table 13.
CLKin
CLKin
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T1
T1
T2
T3
T3
T3
T4
for 1:2.5
for 1:3.5
T2
T4
T2
T4
Figure 11. Internal Tick Spacing for Memory Controller Signals
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
1.3 Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the
MODCK[1–3] pins are sampled while HRESET is asserted. Table 14 shows the eight basic configuration
modes. Another 49 modes are available by using the configuration pin (RSTCONF) and driving four pins
on the data bus.
1.3.1 Local Bus Mode
Table 14 describes default clock modes for the MPC826xA.
Table 14. Clock Default Modes
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
MODCK[1–3]
Frequency
Factor
000
001
010
011
100
101
110
111
33 MHz
33 MHz
33 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
100 MHz
100 MHz
133 MHz
133 MHz
133 MHz
133 MHz
166 MHz
166 MHz
4
5
133 MHz
166 MHz
133 MHz
166 MHz
166 MHz
200 MHz
166 MHz
200 MHz
4
4
4
5
2
2.5
3
2
2.5
2.5
2.5
3
Table 15 describes all possible clock configurations when using the hard reset configuration sequence.
Note that clock configuration changes only after POR is asserted. Note also that basic modes are shown in
boldface type.
MOTOROLA
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19
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Configuration Modes
1
Table 15. Clock Configuration Modes
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0001_000
0001_001
0001_010
0001_011
0001_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
2
2
2
2
2
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0001_101
0001_110
0001_111
0010_000
0010_001
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_010
0010_011
0010_100
0010_101
0010_110
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_111
0011_000
0011_001
0011_010
0011_011
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0011_100
0011_101
0011_110
0011_111
0100_000
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
6
6
6
6
6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
20
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Clock Configuration Modes
Table 15. Clock Configuration Modes (Continued)
1
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0100_001
0100_010
0100_011
0100_100
0100_101
0100_110
Reserved
0100_111
0101_000
0101_001
0101_010
0101_011
0101_100
Reserved
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0110_011
0110_100
0110_101
0110_110
0110_111
0111_000
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0111_001
0111_010
0111_011
0111_100
0111_101
0111_110
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
MOTOROLA
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21
Clock Configuration Modes
Table 15. Clock Configuration Modes (Continued)
1
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
4
1100_000
66 MHz
66 MHz
66 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
Bypass
Bypass
Bypass
66 MHz
66 MHz
66 MHz
4
1100_001
4
1100_010
1
2
Because of speed dependencies, not all of the possible configurations in Table 15 are applicable.
The user should choose the input clock frequency and the multiplication factors such that the frequency of the
CPU is equal to or greater than150 MHz and the CPM ranges between 66–233 MHz.
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
3
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz input clock and MODCK_H–MODCK_L[0111–101] (with a core multiplication factor of 4 and a CPM
multiplication factor of 3). The resulting configuration equals the part’s maximum possible frequencies of
266 MHz CPU, 200 MHz CPM, and 66 MHz bus.
2. 50 MHz input clock and MODCK_H–MODCK_L[0111–101] to achieve a configuration of 200 MHz CPU,
150 MHz CPM, and 50 MHz bus.
3. 40 MHz input clock and MODCK_H–MODCK_L[0010–011] to achieve a configuration of 200 MHz CPU,
160 MHz CPM, and 40 MHz bus.
Note that with each example, any one of several values for MODCK_H–MODCK_L could possibly be used as
long as the resulting configuration does not exceed the part’s rating.
At this mode the CPU PLL is bypassed (the CPU frequency equals the bus frequency).
4
1.3.2 PCI Mode
This section pertains to the MPC8265A and the MPC8266A only.
In PCI mode only, MODCK_HI[0:3] and PCI_MODCK come from the following external pins:
•
•
PCI_MODCK = LGPL5
MODCK_HI[0:3] = {LGPL0,LGPL1,LGPL2,LGPL3}
NOTE
The minimum Tval = 2 when PCI_MODCK = 1 and minimum Tval = 1
when PCI_MODCK = 0; therefore, board designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
22
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clock Configuration Modes
Table 16. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)
Input Clock
MODCK[1–3] Frequency Multiplication
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
1
2
2
Factor
(Bus)
Factor
000
001
010
011
100
101
110
111
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
133 MHz
133 MHz
166 MHz
166 MHz
166 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
200 MHz
233 MHz
266 MHz
200 MHz
233 MHz
266 MHz
2/4
2/4
3/6
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
55/28 MHz
55/28 MHz
55/28 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2.5
2.5
2.5
3
3
3.5
4
3
3
3.5
4
3
1
2
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.)
Table 17 describes all possible clock configurations when using the MPC8265A or the MPC8266A’s
internal PCI bridge in host mode.
Table 17. Clock Configuration Modes in PCI Host Mode
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
0001_000
0001_001
0001_010
0001_011
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
3/6
3/6
3/6
3/6
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
0010_000
0010_001
0010_010
0010_011
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4/8
4/8
4/8
4/8
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
3
0011_000
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
5
5
5
5
33 MHz
33 MHz
33 MHz
33 MHz
3
0011_001
3
0011_010
3
0011_011
3
0100_000
33 MHz
33 MHz
33 MHz
6
6
6
200 MHz
200 MHz
200 MHz
5
6
7
166 MHz
200 MHz
233 MHz
6
6
6
33 MHz
33 MHz
33 MHz
3
0100_001
3
0100_010
MOTOROLA
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23
Clock Configuration Modes
Table 17. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
3
0100_011
33 MHz
6
200 MHz
8
266 MHz
6
33 MHz
0101_000
0101_001
0101_010
0101_011
0101_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2/4
2/4
2/4
2/4
2/4
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
0110_000
0110_001
0110_010
0110_011
0110_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
3.5
4
4.5
0111_000
0111_001
0111_010
0111_011
0111_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
4/8
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
3.5
4
4.5
1001_000
1001_001
1001_010
1001_011
1001_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
4/8
58/29 MHz
58/29 MHz
58/29 MHz
58/29 MHz
58/29 MHz
3.5
4
4.5
1010_000
1010_001
100 MHz
100 MHz
2
2
200 MHz
200 MHz
2
200 MHz
250 MHz
3/6
3/6
66/33 MHz
66/33 MHz
2.5
24
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Clock Configuration Modes
Table 17. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock
Frequency
CPM
Multiplication
Factor
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
PCI
Frequency
MODCK_H –
MODCK[1–3]
1
2
2
Factor
(Bus)
1010_010
1010_011
1010_100
100 MHz
100 MHz
100 MHz
2
2
2
200 MHz
200 MHz
200 MHz
3
3.5
4
300 MHz
350 MHz
400 MHz
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
1011_000
1011_001
1011_010
1011_011
1011_100
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
2.5
2.5
2.5
2.5
2.5
250 MHz
250 MHz
250 MHz
250 MHz
250 MHz
2
2.5
3
200 MHz
250 MHz
300 MHz
350 MHz
400 MHz
4/8
4/8
4/8
4/8
4/8
62/31 MHz
62/31MHz
62/31 MHz
62/31 MHz
62/31 MHz
3.5
4
4
1100_000
66MHz
66MHz
66MHz
2
2.5
3
133MHz
166MHz
200MHz
Bypass
Bypass
Bypass
66MHz
66MHz
66MHz
2/4
3/6
3/6
66/33 MHz
55/28 MHz
66/33 MHz
4
1100_001
4
1100_010
1
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible
(note that the three input clock frequencies are only three of many possible input clock frequencies):
1. 66 MHz input clock, MODCK_H–MODCK_L[0111–011] (with a core multiplication factor of 4 and a CPM
multiplication factor of 3), and PCI_MODCK = 0 (see note 2 below). The resulting configuration equals the
part’s maximum possible frequencies of 266 MHz CPU, 200 MHz CPM, 66 MHz 60x bus, and a PCI
frequency of 66 MHz.
2. 50 MHz input clock, MODCK_H–MODCK_L[0111–011], and PCI_MODCK = 0 (see note 2below) to
achieve a configuration of 200 MHz CPU, 150 MHz CPM, 50 MHz 60x bus, and a PCI frequency of 50 MHz.
3. 40 MHz input clock, MODCK_H–MODCK_L[0010–000], and PCI_MODCK = 0 (see note 2 below) to
achieve a configuration of 200 MHz CPU, 160 MHz CPM, 40 MHz 60x bus, and a PCI frequency of 40 MHz.
Note that with each of the examples, any one of several values for MODCK_H–MODCK_L could possibly be
used as long as the resulting configuration does not exceed the part’s rating.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.).
In this mode, PCI_MODCK must be “0”.
In this mode the Core PLL is bypassed (core frequency equals to bus frequency; for debug purpose only).
2
3
4
1
Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
2
MODCK[1–3] Frequency Multiplication
4
5
Factor
Frequency
3
3
(PCI)
Factor
000
001
010
011
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2/4
2/4
3/6
3/6
133 MHz
133 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
200 MHz
266 MHz
2
2
3
3
66 MHz
66 MHz
66 MHz
66 MHz
3
4
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
25
Clock Configuration Modes
Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000) (Continued)
1
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
2
MODCK[1–3] Frequency Multiplication
4
5
Factor
Frequency
3
3
(PCI)
Factor
100
101
110
111
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3/6
3/6
4/8
4/8
200 MHz
200 MHz
266 MHz
266 MHz
3
240 MHz
280 MHz
300 MHz
300 MHz
2.5
2.5
3
80 MHz
80 MHz
88 MHz
100 MHz
3.5
3.5
3
2.5
1
2
3
The user should verify that all buses and functions run frequencies that are within the supported ranges.
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2.
Core frequency = (60x bus frequency)(core multiplication factor)
4
5
Bus frequency = CPM frequency / bus division factor
Table 19 describes all possible clock configurations when using the MPC8265A or the MPC8266A’s
internal PCI bridge in agent mode.
1
Table 19. Clock Configuration Modes in PCI Agent Mode
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
MODCK_H –
MODCK[1–3]
Frequency Multiplication
4
5
Factor
Frequency
2,3
2
(PCI)
Factor
0001_001 66/33 MHz
0001_010 66/33 MHz
0001_011 66/33 MHz
0001_100 66/33 MHz
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4
4
4
4
33 MHz
33 MHz
33 MHz
33 MHz
0010_001 50/25 MHz
0010_010 50/25 MHz
0010_011 50/25 MHz
0010_100 50/25 MHz
3/6
3/6
3/6
3/6
150 MHz
150 MHz
150 MHz
150 MHz
3
180 MHz
210 MHz
240 MHz
270 MHz
2.5
2.5
2.5
2.5
60 MHz
60 MHz
60 MHz
60 MHz
3.5
4
4.5
0011_000 66/33 MHz
0011_001 66/33 MHz
0011_010 66/33 MHz
0011_011 66/33 MHz
0011_100 66/33 MHz
2/4
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
110MHz
132 MHz
154 MHz
176MHz
198 MHz
3
3
3
3
3
44 MHz
44 MHz
44 MHz
44 MHz
44 MHz
3.5
4
4.5
0100_000 66/33 MHz
0100_001 66/33 MHz
0100_010 66/33 MHz
0100_011 66/33 MHz
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
3
3
3
3
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
26
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Clock Configuration Modes
1
Table 19. Clock Configuration Modes in PCI Agent Mode (Continued)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
MODCK_H –
MODCK[1–3]
Frequency Multiplication
4
5
Factor
Frequency
2,3
2
(PCI)
Factor
0100_100 66/33 MHz
3/6
200 MHz
4.5
300 MHz
3
66 MHz
6
0101_000
0101_001
0101_010
0101_011
0101_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2.5
2.5
2.5
2.5
2.5
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
6
6
6
6
3.5
4
4.5
0110_000 50/25 MHz
0110_001 50/25 MHz
0110_010 50/25 MHz
0110_011 50/25 MHz
0110_100 50/25 MHz
4/8
4/8
4/8
4/8
4/8
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3
3
3
3
3
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
0111_000 66/33 MHz
0111_001 66/33 MHz
0111_010 66/33 MHz
0111_011 66/33 MHz
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
2
200 MHz
250 MHz
300 MHz
350 MHz
2
2
2
2
100 MHz
100 MHz
100 MHz
100 MHz
2.5
3
3.5
1000_000 66/33 MHz
1000_001 66/33 MHz
1000_010 66/33 MHz
1000_011 66/33 MHz
1000_100 66/33 MHz
1000_101 66/33 MHz
3/6
3/6
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
160 MHz
200 MHz
240 MHz
280 MHz
320 MHz
360 MHz
2.5
2.5
2.5
2.5
2.5
2.5
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
3.5
4
4.5
1001_000 66/33 MHz
1001_001 66/33 MHz
1001_010 66/33 MHz
1001_011 66/33 MHz
1001_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4
4
4
4
4
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
1010_000 66/33 MHz
1010_001 66/33 MHz
4/8
4/8
266 MHz
266 MHz
2.5
3
222 MHz
266 MHz
3
3
88 MHz
88 MHz
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
27
Clock Configuration Modes
Table 19. Clock Configuration Modes in PCI Agent Mode (Continued)
1
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
MODCK_H –
MODCK[1–3]
Frequency Multiplication
4
5
Factor
Frequency
2,3
2
(PCI)
Factor
1010_010 66/33 MHz
1010_011 66/33 MHz
1010_100 66/33 MHz
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
3.5
4
300 MHz
350 MHz
400 MHz
3
3
3
88 MHz
88 MHz
88 MHz
4.5
1011_000 66/33 MHz
1011_001 66/33 MHz
1011_010 66/33 MHz
1011_011 66/33 MHz
1011_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2
2.5
3
212MHz
265 MHz
318 MHz
371 MHz
424 MHz
2.5
2.5
2.5
2.5
2.5
106 MHz
106 MHz
106 MHz
106 MHz
106 MHz
3.5
4
7
1100_000
1100_001
1100_010
66/33MHz
66/33MHz
66/33MHz
2/4
3/6
3/6
133MHz
200MHz
200MHz
Bypass
Bypass
Bypass
66MHz
80MHz
66MHz
2
2.5
3
66 MHz
80 MHz
66 MHz
7
7
1
2
The user should verify that all buses and functions run frequencies that are within the supported ranges.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency
is divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2.
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so
that the resulting configuration does not exceed the frequency rating of the user’s part.
3
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are
possible (note that the three input clock frequencies are only three of many possible input clock
frequencies):
1. 50 MHz input clock, MODCK_H–MODCK_L[0110–011] (with a core multiplication factor of 4, a CPM
multiplication factor of 4, and a bus division factor of 3), and PCI_MODCK = 0 (see note 2 above). The
PCI frequency is 50 MHz and the resulting configuration equals the part’s maximum possible frequencies
of 266 MHz CPU, 200 MHz CPM, and 66 MHz 60x bus.
2. 66 MHz input clock, MODCK_H–MODCK_L[0100–001], and PCI_MODCK = 1 (see note 2 above) to
achieve a PCI frequency of 33 MHz and a configuration of 200MHz CPU, 200 MHz CPM, and 66 MHz
60x bus.
3. 40 MHz input clock, MODCK_H–MODCK_L[1001–011], and PCI_MODCK = 0 (see note 2 above) to
achieve a PCI frequency of 40 MHz and a configuration of 160 MHz CPU, 160 MHz CPM, and 40 MHz
60x bus.
Note that with each of the examples, any one of several values for MODCK_H–MODCK_L could possibly
be used as long as the resulting configuration does not exceed the part’s rating.
Core frequency = (60x bus frequency)(core multiplication factor)
Bus frequency = CPM frequency / bus division factor
In this mode, PCI_MODCK must be “1”.
4
5
6
7
In this mode the Core PLL is bypassed (core frequency equals bus frequency; for debug purpose only).
28
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
1.4 Pinout
This section provides the pin assignments and pinout list for the MPC826xA.
1.4.1 Pin Assignments
Figure 12 shows the pinout of the MPC826xA’s 480 TBGA package as viewed from the top surface.
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 12. Pinout of the 480 TBGA Package as Viewed from the Top Surface
Figure 13 shows the side profile of the TBGA package to indicate the direction of the top surface view.
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
29
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
View
Pressure Sensitive
Adhesive
Copper Heat Spreader
(Oxidized for Insulation)
Etched
Cavity
Die
Attach
Polymide Tape
Die
Glob-Top Filled Area
Soldermask
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Figure 13. Side View of the TBGA Package
Table 20 shows the pinout list of the MPC826xA. Table 21 defines conventions and acronyms used in
Table 20.
Table 20. Pinout List
Pin Name
Ball
BR
W5
F4
E2
E3
G1
H5
H2
H1
J5
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
L5
L4
L3
L2
L1
M5
N5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
30
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
TT0
TT1
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
N4
N3
N2
N1
P4
P3
P2
P1
R1
R3
R5
R4
F1
G4
G3
G2
F2
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A16
A13
E12
D9
A6
B5
A20
D1
D2
D3
D4
D5
D6
D7
D8
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
31
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
D9
E17
B15
B13
A11
E9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
B7
B4
D19
D17
D15
C13
B11
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
C8
E7
A3
D18
A17
A14
B12
32
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
D44
A10
D8
D45
D46
B6
D47
C4
D48
C18
E16
B14
C12
B10
A7
D49
D50
D51
D52
D53
D54
C6
D55
D5
D56
B18
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
B22
A22
E21
D21
C21
B21
A21
E20
V3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
TA
C22
V5
TEA
GBL/IRQ1
W1
U2
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
U3
Y4
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
33
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
CPU_BG/BADDR31/IRQ5
U4
CPU_DBG
R2
CPU_BR
Y3
CS0
F25
C29
E27
E28
F26
F27
F28
G25
D29
E29
F29
G28
T5
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
B24
A24
B23
A23
D22
H28
H27
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
1
1
34
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
H26
G29
D27
C28
E26
D25
C26
B27
D28
N27
T29
1
1
LSDA10/LGPL0/PCI_MODCKH0
1
LSDWE/LGPL1/PCI_MODCKH1
1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
1
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
1
LGPL5/LSDAMUX/PCI_MODCK
LWR
1
L_A14/PAR
1
L_A15/FRAME /SMI
1
L_A16/TRDY
R27
R26
R29
R28
W29
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
J29
1
L_A17/IRDY /CKSTP_OUT
1
L_A18/STOP
1
L_A19/DEVSEL
1
L_A20/IDSEL
1
L_A21/PERR
1
L_A22/SERR
1
L_A23/REQ0
1
1
1
L_A24/REQ1 /HSEJSW
1
L_A25/GNT0
1
1
L_A26/GNT1 /HSLED
1
L_A27/GNT2 /HSENUM
1
L_A28/RST /CORE_SRESET
1
L_A29/INTA
1
L_A30/REQ2
1
L_A31/DLLOUT
1
LCL_D0/AD0
1
LCL_D1/AD1
1
LCL_D2/AD2
J28
1
LCL_D3/AD3
J27
1
LCL_D4/AD4
J26
1
LCL_D5/AD5
J25
1
LCL_D6/AD6
K25
L29
1
LCL_D7/AD7
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
35
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
1
1
LCL_D8/AD8
LCL_D9/AD9
L27
L26
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
L25
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
W27
W26
W25
Y29
Y28
Y25
AA29
AA28
L28
LCL_D31/AD31
1
1
1
1
1
LCL_DP0/C0 /BE0
1
LCL_DP1/C1 /BE1
N28
T28
W28
T1
1
LCL_DP2/C2 /BE2
1
LCL_DP3/C3 /BE3
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
D1
TRST
TCK
TMS
TDI
AH3
AG5
AJ3
AE6
AF5
TDO
36
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
TRIS
AB4
PORESET
AG6
HRESET
AH5
SRESET
AF6
QREQ
AA3
RSTCONF
AJ4
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
W2
W3
W4
AB2
CLKIN1
AH4
PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3
AC29
AC25
AE28
AG29
AG28
AG26
AE24
AH25
AF23
AH23
AE22
AH22
AJ21
AH20
AG19
AF18
AF17
AE16
AJ16
AG15
AJ13
AE13
AF12
AG11
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2
PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4
PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2
PA6/L1RSYNCA1
PA7/SMSYN2/L1TSYNCA1/L1GNTA1
PA8/SMRXD2/L1RXD0A1/L1RXDA1
PA9/SMTXD2/L1TXD0A1
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
37
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER
PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV
AH9
AJ8
AH7
AF7
AD5
AF1
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS AD3
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL
PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS
PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2
PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2
PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1
PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1
PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1
AB5
AD28
AD26
AD25
AE26
AH27
AG24
AH24
AJ24
AG22
AH21
AG20
AF19
AJ18
AJ17
AE14
AF13
AG12
AH11
PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1
PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2
PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1
PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1
PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18
PB17/FCC3_MII_RX_DV/L1RQA1/CLK17
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/
L1TXD2A1
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2
AH16
AE15
AJ9
AE9
AJ7
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2
AH6
AE3
AE2
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/
FCC2_MII_TX_EN
38
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
AC5
AC4
AB26
AD29
AE29
AE27
AF27
AF24
AJ26
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2
PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR2/
FCC1_UTM_RXCLAV1
PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/
FCC1_UTM_TXCLAV1
AJ25
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3
AF22
AE21
AF20
AE19
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE18
PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0
PC16/CLK16/TIN4
AH18
AH17
AG16
AF15
AJ15
AH14
AG13
AH12
AJ11
AG10
AE10
AF9
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
PC19/CLK13/BRGO7
PC20/CLK12/TGATE1
PC21/CLK11/BRGO6
PC22/CLK10/DONE1
PC23/CLK9/BRGO5/DACK1
PC24/FCC2_UT8_TXD3/CLK8/TOUT4
PC25/FCC2_UT8_TXD2/CLK7/BRGO4
PC26/CLK6/TOUT3/TMCLK
AE8
AJ6
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/FCC2_UT8_TXD3/CLK2/TOUT1
PC31/CLK1/BRGO1
AG2
AF3
AF2
AE1
AD1
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
39
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2
PD5/FCC1_UT16_TXD3/DONE1
AC28
AD27
AF29
PD6/FCC1_UT16_TXD4/DACK1
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2 AF28
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1
PD12/SI1_L1ST2/L1RXDB1
AG25
AH26
AJ27
AJ23
AG23
AJ22
AE20
AJ20
AG18
AG17
PD13/SI1_L1ST1/L1TXDB1
PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/S AF16
PICLK
PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/FCC1_UTM_TXCLAV3/S AH15
PISEL/BRGO1
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1
AJ14
AH13
AJ12
AE12
AF10
AG9
AH8
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1
AG7
AE4
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1_UTM_RXCLAV2
AG1
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1
AD4
AD2
AB3
B9
PD31/RXD1
VCCSYN
VCCSYN1
GNDSYN
AB1
AE11
U5
1,2
CLKIN2
3
SPARE4
1,4
PCI_MODE
AF25
40
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Pinout
Table 20. Pinout List (Continued)
Pin Name
Ball
3
SPARE6
V4
5
5
THERMAL0
THERMAL1
I/O power
AA1
AG4
AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C16, C20, C23, E10, A28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power
Ground
U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25,Y26,V25,
T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1
2
MPC8265A and MPC8266A only.
On PCI devices (MPC8265A and MPC8266A) this pin should be used as CLKIN2. On non-PCI devices
(MPC8260A and MPC8264A) this is a spare pin that must be pulled down or left floating.
Must be pulled down or left floating.
On PCI devices (MPC8265A and MPC8266A) this pin should be asserted if the PCI function is desired or pulled
up or left floating if PCI is not desired. On non-PCI devices (MPC8260A and MPC8264A) this is a spare pin that
must be pulled up or left floating.
3
4
5
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at
www.motorola.com/semiconductors.
Symbols used in Table 20 are described in Table 21.
Table 21. Symbol Legend
Symbol
Meaning
OVERBAR
UTM
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the UTOPIA master interface.
Indicates that a signal is part of the UTOPIA slave interface.
Indicates that a signal is part of the 8-bit UTOPIA interface.
Indicates that a signal is part of the 16-bit UTOPIA interface.
Indicates that a signal is part of the media independent interface.
UTS
UT8
UT16
MII
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
41
Package Description
1.5 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC826xA.
1.5.1 Package Parameters
Package parameters are provided in Table 22. The package type is a 37.5 x 37.5 mm, 480-lead TBGA.
Table 22. Package Parameters
Parameter
Package Outline
Value
37.5 x 37.5 mm
Interconnects
Pitch
480 (29 x 29 ball array)
1.27 mm
Nominal unmounted package height 1.55 mm
42
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Package Description
1.5.2 Mechanical Dimensions
Figure 14 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
maximum solder ball diameter,
parallel to primary data A.
4. Primary data A and the seating
plane are defined by the spherical
crowns of the solder balls.
Millimeters
Dim
Min
Max
A
A1
A2
A3
b
1.45
0.60
0.85
0.25
0.65
1.65
0.70
0.95
—
0.85
D
37.50 BSC
D1
e
35.56 REF
1.27 BSC
37.50 BSC
35.56 REF
E
E1
Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
43
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Ordering Information
1.6 Ordering Information
Figure 15 provides an example of the Motorola part numbering nomenclature for the MPC826xA. In
addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates
any enhancement(s) in the part from the original production design. Each part number also contains a
revision code that refers to the die mask revision number and is specified in the part numbering scheme for
identification purposes only. For more information, contact your local Motorola sales office.
MPC 826X A C ZU XXX X
Product Code
Die Revision Level
Device Number
Processor Frequency
(CPU/CPM/Bus)
Process Technology
(None = 0.29 micron
A = 0.25 micron)
Package
(ZU = 480 TBGA)
Temperature Range
(Blank = 0 to 105 ˚C
C = -40 to 105 ˚C
Figure 15. Motorola Part Number Key
1.7 Document Revision History
Table 23 lists significant changes in each revision of this document.
Table 23. Document Revision History
Document Revision
Substantive Changes
0
Initial version
0.1
0.2
Table 10, sp20/sp21: 66 MHz setup and hold times are 15 and 20 respectively. Delete ‘(10).’
• Revision of Table 7, “Power Dissipation”
• Modifications to Figure 8, Table 4,Table 12, Table 13, and Table 18
• Modification to pinout diagram, Figure 12
• Additional revisions to text and figures throughout
0.3
• Note 3 for Table 3
• Section 1.2.1, “DC Electrical Characteristics”: Removal of “Warning” recommending use of
bootstrap diodes. They are not needed.
• sp12 in Table 11, sp32 in Table 12
• Note 2 for Table 16 and Table 17
• Addition of note at beginning of Section 1.3.2, “PCI Mode”
• Note 1 for Table 18 and Table 19
• Additions to pinout, Table 20 for balls: B27, C28, D25, D27, E26, G29, H26–28, N25, P29,
AF25, AA25, AB27
44
MPC826xA (HiP4) Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
Table 23. Document Revision History (Continued)
Document Revision
Substantive Changes
0.4
• Note 2 for Table 4 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
• Table 19: core and bus frequency values for the following ranges of MODCK_HMODCK:
0011_000 to 0011_100 and 1011_000 to 1011_1000
• Table 20: notes added to pins at AE11, AF25, U5, and V4.
0.5
• Table 20: modified notes to pins AE11 and AF25.
• Table 20: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.6
0.7
• Table 20: modified notes to pins AE11 and AF25.
• Section 1.1, “Features”: minimum supported core frequency of 150 MHz
• Section 1.1, “Features”: updated performance values (under “Dual-issue integer core”)
• Table 4: Notes 2 and 3
• Addition of note on page 8:VDDH and VDD tracking
• Table 15: Note 3
• Table 17: Note 1
• Table 19: Note 3
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
45
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
46
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Document Revision History
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
47
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© Motorola, Inc. 2001
MPC8260AEC/D
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