MPC92429FA [MOTOROLA]
400 MHz Low Voltage PECL Clock Synthesizer; 400 MHz的低电压PECL时钟合成器
| 型号： | MPC92429FA |
| 厂家： | 
MOTOROLA |
| 描述： | 400 MHz Low Voltage PECL Clock Synthesizer |
| 文件： | 总12页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order Number: MPC92429/D
Rev 0, 09/2003
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
400 MHz Low Voltage PECL
Clock Synthesizer
MPC92429
The MPC92429 is a 3.3V compatible, PLL based clock synthesizer
targeted for high performance clock generation in mid-range to
high-performance telecom, networking and computing applications. With
output frequencies from 25 MHz to 400 MHz and the support of differential
PECL output signals the device meets the needs of the most demanding
clock applications.
400 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
Features
• 25 MHz to 400 MHz synthesized clock output signal
• Differential PECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• 3.3V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32 lead LQFP and 28 PLCC packaging
• SiGe Technology
FN SUFFIX
28--LEAD PLCC PACKAGE
CASE 776
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MC12429 and MPC9229
Functional Description
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. The frequency of the internal crystal
oscillator is divided by 16 and then multiplied by the PLL. The VCO within
the PLL operates over a range of 200 to 400 MHz. Its output is scaled by a
divider that is configured by either the serial or parallel interfaces. The
crystal oscillator frequency f
post-divider N determine the output frequency.
, the PLL feedback-divider M and the PLL
XTAL
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be⋅M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specified VCO frequency range (200 to 400 MHz). The M-value must be
programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50Ω to V
– 2.0V. The
CC
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
Motorola, Inc. 2003
MPC92429
XTAL_IN
XTAL_OUT
Ref
VCO
XTAL
÷16
÷1
÷2
÷4
÷8
00
01
10
11
FOUT
FOUT
10 -- 20 MHz
PLL
200--400 MHz
OE
FB
Sync
÷0 to ÷511
9-Bit M-Divider
Test
TEST
3
2
9
V
CC
M-Latch
N-Latch
T-Latch
LE
P/S
P_LOAD
S_LOAD
0
1
0
1
Bit 3-4
Bit 5-13
Bit 0-2
S_DATA
S_CLOCK
14 Bit Shift Register
V
CC
M[0:8]
N[1:0]
OE
Figure 1. MPC92429 Logic Diagram
24
22
23
21
19
25
20
24 23 22 21 20 19 18 17
S_CLOCK
N[1]
N[0]
M[8]
M[7]
26
27
18
17
16
15
14
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
GND
TEST
VCC
S_DATA
S_LOAD
VCC_PLL
NC
M[3]
M[2]
M[1]
M[0]
28
1
VCC
MPC92429
MPC92429
GND
FOUT
FOUT
VCC
M[6]
M[5]
M[4]
2
3
4
P_LOAD
NC
13
12
OE
XTAL_IN
XTAL_OUT
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
Figure 2. MPC92429 28--Lead PLCC Pinout
Figure 3. MPC92429 32--Lead LQFP Pinout
(Top View)
(Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC92429
Table 1. Pin Configuration
Pin
XTAL_IN, XTAL_OUT
FOUT, FOUT
TEST
I/O
Default
Type
Analog
LVPECL
Function
Crystal oscillator interface
Differential clock output
Output
Output
Input
LVCMOS Test and device diagnosis output
LVCMOS Serial configuration control input.
S_LOAD
0
1
This inputs controls the loading of the configuration latches with the contents of
the shift register. The latches will be transparent when this signal is high, thus the
data must be stable on the high-to-low transition.
P_LOAD
Input
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive
S_DATA
S_CLOCK
M[0:8]
Input
Input
Input
0
0
1
LVCMOS Serial configuration data input.
LVCMOS Serial configuration clock input.
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
OE
Input
Input
1
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
LVCMOS Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the F
output. OE = L low stops F
in the logic low state
OUT
OUT
(F
OUT
= L, FOUT = H)
GND
Supply
Supply
Supply
Supply
Ground
Negative power supply (GND)
V
CC
V
CC
Positive power supply for I/O and core. All V pins must be connected to the
CC
positive power supply for correct operation
VCC_PLL
Supply
Supply
V
CC
PLL positive power supply (analog power supply)
Table 2. Output frequency range and PLL Post-divider N
N
Output division
Output frequency range
1
0
0
1
1
0
0
1
0
1
1
2
4
8
200 - 400 MHz
100 - 200 MHz
50 - 100 MHz
25 - 50 MHz
TIMING SOLUTIONS
3
MOTOROLA
MPC92429
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
V
Condition
V
TT
Output Termination Voltage
ESD protection (Machine Model)
ESD protection (Human Body Model)
Latch-Up Immunity
V
- 2
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
JA
LQFP 32 Thermal resistance junction to ambient
JESD 51-3, single layer test board
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θ
JC
LQFP 32 Thermal resistance junction to case
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
a
Table 4. Absolute Maximum Ratings
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.9
Unit
V
Condition
V
CC
Supply Voltage
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
V
V
+ 0.3
V
IN
CC
CC
V
OUT
+ 0.3
V
I
IN
±20
mA
mA
°C
I
±50
OUT
T
-65
125
S
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (V = 3.3V ± 5%, T = 0°C to +70°C)
CC
A
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS control inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE)
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
V
V
LVCMOS
LVCMOS
V = V or GND
IN
IH
CC
V
0.8
IL
a
I
IN
Input Current
±200
µA
CC
b
Differential clock output F
OUT
c
c
V
Output High Voltage
V
V
--1.02
V
V
--0.74
V
V
LVPECL
LVPECL
OH
CC
CC
c
V
Output Low Voltage
Test and diagnosis output TEST
Output High Voltage
--1.95
--1.60
OL
CC
CC
V
OH
2.0
V
V
I
I
= -0.8 mA
= 0.8 mA
OH
c
V Output Low Voltage
Supply current
0.55
OL
OL
I
Maximum PLL Supply Current
Maximum Supply Current
20
mA
mA
V
Pins
CC_PLL
CC_PLL
I
100
All V Pins
CC
CC
a. Inputs have pull-down resistors affecting the input current.
b. Outputs terminated 50Ω to V = V - 2V.
TT
CC
c. The MPC92429 TEST output levels are compatible to the MC12429 output levels.
MOTOROLA
4
TIMING SOLUTIONS
MPC92429
a
Table 6. AC Characteristics (V = 3.3V ± 5%, T = 0°C to +70°C)
CC
A
Symbol
Characteristics
Min
10
Typ
Max
20
Unit
MHz
MHz
Condition
f
Crystal interface frequency range
XTAL
b
f
VCO frequency range
Output Frequency
200
400
VCO
MAX
f
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
200
100
50
400
200
100
50
MHz
MHz
MHz
MHz
25
DC
Output duty cycle
45
0.05
0
50
55
0.3
10
%
ns
t , t
Output Rise/Fall Time
20% to 80%
r
f
c
f
Serial interface programming clock frequency
MHz
ns
S_CLOCK
t
Minimum pulse width
Setup Time
(S_LOAD, P_LOAD)
50
P,MIN
t
S
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
t
S
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
t
Period Jitter
25
10
ps
JIT(PER)
t
Maximum PLL Lock Time
ms
LOCK
a. AC characteristics apply for parallel output termination of 50Ω to V
TT.
b. The input frequency f
and the PLL feedback divider M must match the VCO frequency range: f
= f
XTAL
⋅ M ÷ 4.
XTAL
VCO
c. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See application section for more details.
TIMING SOLUTIONS
5
MOTOROLA
MPC92429
Programming the MPC92429
to match the VCO frequency range of 200 to 400 MHz in order
to achieve stable PLL operation:
Programming the MPC92429 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
M
M
= f
MAX
÷ f and
XTAL
VCO,MAX
(2)
(3)
MIN
VCO,MIN
= f
÷ f
XTAL
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M=200
and M = 400. Table 7 shows the usable VCO frequency and
f
= (f
÷ 16) ⋅ (M) ÷ (N) or
(1)
OUT
XTAL
M
divider range for other example input frequencies.
where f
is the crystal frequency, M is the PLL
XTAL
Assuming that a 16 MHz input frequency is used, equation 1
reduces to:
feedback-divider and N is the PLL post-divider. The input
frequency and the selection of thefeedback dividerM islimited
by the VCO-frequency range. f
and M must be configured
f
= M ÷ N
(4)
XTAL
OUT
Table 7. MPC92429 Frequency Operating Range
VCO frequency for an crystal interface frequency of
Output frequency for f
=16 MHz and for N =
XTAL
M
M[8:0]
10
12
14
16
18
20
1
2
4
16
160
170
180
190
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
510
010100000
010101010
010110100
010111110
011001000
011010010
011011100
011100110
011110000
011111010
100000100
100001110
100011000
100100010
100101100
100110110
101000000
101001010
101010100
101011110
101101000
101110010
101111100
110000110
110010000
110011010
110100100
110101110
110111000
111000010
111111110
800
850
810
855
900
950
800
840
900
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550
1600
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
50
52.5
55
25
945
26.25
27.50
28.75
30
880
990
805
840
920
1035
1080
1125
1170
1215
1260
1305
1350
1395
1440
1485
1530
1575
57.5
60
960
875
100
62.5
65
31.25
32.50
33.75
35
910
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
810
840
945
67.5
70
980
870
1015
1050
1085
1120
1155
1190
1225
1260
1295
1330
1365
1400
1435
1470
1505
1540
1575
72.5
75
36.25
37.5
38.75
40
900
930
77.5
80
800
825
960
990
82.5
85
41.25
42.5
43.75
45
850
1020
1050
1080
1110
1140
1170
1200
1230
1260
1290
1320
1350
1530
875
87.5
90
900
925
92.5
95
46.25
47.5
48.75
50
950
975
97.5
100
1000
1025
1050
1075
1100
1125
1275
MOTOROLA
6
TIMING SOLUTIONS
MPC92429
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Using the test and diagnosis output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
Table 8. Output Frequency Range for f
= 16 MHz
XTAL
N
F
OUT
F
OUT
range
F step
OUT
represents F
, the CMOS output is not able to toggle fast
OUT
enough for higher output frequencies and shouldonly beused
for test and diagnosis. The T2, T1 and T0 control bits are
preset to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter–free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter of the
PECL output pair. In normal operations,jitter specificationsare
only guaranteed if the TEST output is static. The serial
configuration port can be used to select one of the alternate
functions for this pin. Most of the signals available on the TEST
output pin are useful only for performance verification of the
MPC92429 itself. However the PLL bypass mode may be of
interest at the board level for functional debug. When T[2:0] is
set to 110 the MPC92429 isplaced inPLL bypassmode. Inthis
mode the S_CLOCK input is fed directly into the M and N
1
0
0
1
1
0
0
1
0
1
Value
1
2
4
8
M
200 - 400 MHz
100 - 200 MHz
50 - 100 MHz
25 - 50 MHz
1 MHz
M÷2
M÷4
M÷8
500 kHz
250 kHz
125 kHz
Example frequency calculation for an 16 MHz input
frequency
If an output frequency of 131 MHz was desired the following
steps would be taken to identify the appropriate M and N
values. According to Table 8, 131 MHz falls in the frequency
set by an value of 2 so N[1:0] = 01. For N = 2 the output
dividers. The N divider drives the F
differential pair and the
OUT
M counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
frequency is F
= M ÷ 2 and M = F
x 2. Therefore M =
OUT
OUT
2 x 131 = 262, so M[8:0] = 100000110. Following this
procedure a user can generate any whole frequency between
25 MHz and 400 MHz. Note than for N > 2 fractional values of
can be realized. The size of the programmable frequency
steps (and thus the indicator of the fractional output
frequencies achievable) will be equal to:
functional test or debug. Bypassing the PLL and driving F
OUT
directly gives the user more control on the test clocks sent
through the clock tree. Figure 6 shows the functional setup of
the PLL bypass mode. Because the S_CLOCK is a CMOS
level the input frequency is limited to 200 MHz. This means the
fastest the F
pin can be toggled via the S_CLOCK is 100
OUT
MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1).
Note that the M counter output on the TEST output will not be
a 50% duty cycle.
f
= f
÷ 16 ÷ N
(5)
STEP
XTAL
Using the parallel and serial interface
Table 9. Test and Debug Configuration for TEST
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition will
latch the information present on the M[8:0] and N[1:0] inputs
into the M and N counters. When the P_LOAD signal is LOW
the input latches will be transparent and any changes on the
M[8:0] and N[1:0] inputs will affect the FOUT output pair. To
use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and the
M register with the final eight bits of the data stream on the
S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. Figure
4 illustrates the timing diagram for both a parallel and a serial
load of the MPC92429 synthesizer. M[8:0] and N[1:0] are
normally specified once at power–up through the parallel
interface, and then possibly again through the serial interface.
This approach allows the application to come up at one
frequency and then change or fine–tune the clock as theability
to control the serial interface becomes available.
T[2:0]
TEST output
T2
0
T1
0
T0
0
a
14-bit shift register out
Logic 1
f ÷ 16
XTAL
0
0
1
0
1
0
0
1
1
M-Counter out
1
0
0
FOUT
1
0
1
Logic 0
1
1
0
M-Counter out in PLL-bypass mode
1
1
1
FOUT ÷ 4
a. Clocked out at the rate of S_CLOCK
a
Table 10. Debug Configuration for PLL bypass
Output
Configuration
F
OUT
S_CLOCK ÷ N
b
TEST
M-Counter out
a. T[2:0]=110. AC specifications do not apply in PLL bypass
mode
b. clocked out at the rate of S_CLOCK÷(4⋅N)
TIMING SOLUTIONS
7
MOTOROLA
MPC92429
S_CLOCK
S_DATA
S_LOAD
M0
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1
First
Bit
Last
Bit
M[8:0]
N[1:0]
M,
N
P_LOAD
Figure 4. Serial Interface Timing Diagram
Power Supply Filtering
R = 10-15 Ω
F
The MPC92429 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL pin impacts the device characteristics. The
MPC92429 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system environment
where it is more difficult to minimize noise on the power
supplies a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the
VCC_PLL pin for the MPC92429. Figure 5 illustrates a typical
power supply filter scheme. The MPC92429 is most
susceptible to noise with spectral content in the 1 kHz to
1 MHz range. Therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the final
filter design is the DC voltage drop that will be seen between
the VCC supply and the MPC92429 pin of the MPC92429.
From the data sheet, the VCC_PLL current (the current
sourced through the VCC_PLL pin) is maximum 20 mA,
assuming that a minimum of 2.835 V must be maintained on
the VCC_PLL pin. The resistor shown in Figure 5 must have
a resistance of 10-15 Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor its overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL. Generally,
the resistor/capacitor filter will be cheaper, easier to implement
and provide an adequate level of supply filtering. A higherlevel
of attenuation can be achieved by replacing the resistor with
an appropriate valued inductor. A 1000 µH choke will show a
significant impedance at 10 kHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the VCC_PLL pin, a low DC resistance inductor
is required (less than 15 Ω).
VCC_PLL
V
CC
C
C
C = 22 µF
2
1
F
MPC92429
V
CC
C , C = 0.01...0.1 µF
1
2
Figure 5. V
Power Supply Filter
CC PLL
Layout Recommendations
The MPC92429 provides sub–nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC92429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 6 is the low impedance connections
between VCC and GND for the bypass capacitors. Combining
good quality general purpose chip capacitors with good PCB
layout techniques will produce effective capacitor resonances
at frequencies adequate to supply the instantaneous
switching current for the MPC92429 outputs. It is imperative
that low inductance chip capacitors are used; it is equally
important that the board layout does not introduce back all of
the inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors. Note the dotted lines circling
the crystal oscillator connection to the device. The oscillator is
a series resonant circuit and the voltage amplitude across the
crystal is relatively small. It is imperative that no actively
switching signals cross under the crystal as crosstalk energy
coupled to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on–board oscillator. Although the MPC92429
has several design features to minimize the susceptibility to
MOTOROLA
8
TIMING SOLUTIONS
MPC92429
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in whichoverall
performance is being degraded due to system power supply
noise. The power supply filter and bypass schemes discussed
in this section should be adequate to eliminate power supply
noise related problems in most designs.
surface mount crystals are recommended, but not required.
Because the series resonant design is affected by capacitive
loading on the xtal terminals loading variation introduced by
crystals from different vendors could be a potential issue. For
crystals with a higher shunt capacitance it may be required to
place a resistance across the terminals to suppress the third
harmonic. Although typically not required it is a good idea to
layout the PCB with the provision of adding this external
resistor. The resistor value will typically be between 500 and
1KΩ.
C1
C1
The oscillator circuit is a series resonant circuit and thus for
optimum performance a series resonant crystal should be
used. Unfortunately most crystals are characterized in a
parallel resonant mode. Fortunately there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result a parallel resonant crystal can be
used with the MPC92429 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified, a few hundred ppm
translates to kHz inaccuracies. In a general computer
application this level of inaccuracy is immaterial. Table 11
below specifies the performance requirements of the crystals
to be used with the MPC92429.
1
C
C2
F
Xtal
= V
CC
= GND
= Via
Table 11. Recommended Crystal Specifications
Parameter
Value
Fundamental AT Cut
Series Resonance*
±75ppm at 25°C
±150pm 0 to 70°C
0 to 70°C
Figure 6. PCB Board Layout Recommendation for
the PLCC28 Package
Crystal Cut
Resonance
Using the On--Board Crystal Oscillator
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
The MPC92429 features a fully integrated on--board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is advised
to mount the crystal as close to the MPC92429 as possible to
avoid any board level parasitics. To facilitate co--location
Shunt Capacitance
5--7pF
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
50 to 80Ω
100µW
5ppm/Yr (First 3 Years)
*
See accompanying text for series versus parallel resonant
discussion.
TIMING SOLUTIONS
9
MOTOROLA
MPC92429
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776--02
ISSUE D
M
S
S
0.007 (0.180)
T
L-M
N
B
Z
Y BRK
D
- N -
M
S
S
0.007 (0.180)
T
L-M
N
U
- M -
- L -
W
D
S
S
S
0.010 (0.250)
T
L-M
N
X
G1
V
28
1
VIEW D -D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L-M
L-M
N
M
S
S
H
0.007 (0.180)
T
L-M
N
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
- T -
VIEW S
J
PLANE
M
S
S
0.007 (0.180)
T
L-M
N
F
G1
S
S
S
0.010 (0.250)
T
L-M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
0.485
0.485
0.165
0.090
0.013
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
2.29
2.79
0.33
1.27 BSC
0.48
0.050 BSC
0.026
0 . 0 2 0
0 . 0 2 5
0.450
0.450
0.042
0.042
0.042
- - -
0.032
- - -
- - -
0.66
0 . 5 1
0 . 6 4
11.43
11.43
1.07
1.07
1.07
- - -
0.81
- - -
- - -
0.456
0.456
0.048
0.048
0.056
0 . 0 2 0
11.58
11.58
1.21
1.21
1.42
0 . 5 0
2
10
2
10
_
_
_
10.42
1 . 0 2
_
10.92
- - -
G1 0.410
K1 0 . 0 4 0
0.430
- - -
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MOTOROLA
10
TIMING SOLUTIONS
MPC92429
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
ISSUE B
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
25
1
F
F
A
B
E1/2
E1
6
E
4
DETAIL G
E/2
DETAIL G
17
8
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D
4
D/2
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
4X
D
0.20
C
A-B
D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
H
28X e
32X
0.1 C
SEATING
PLANE
C
DETAIL AD
BASE
PLATING
METAL
b1
c
c1
MILLIMETERS
DIM MIN
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
A
A1
A2
b
1.40
0.05
1.35
0.30
0.30
0.09
0.09
b
5
8
_
8X (θ1 )
M
0.20
C
A-B
D
R R2
b1
c
SECTION F-F
R R1
c1
D
9.00 BSC
D1
e
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
E
GAUGE PLANE
E1
L
0.50
0.70
L1
θ
1.00 REF
(S)
0
7
_
_
A1
_
L
θ
θ1
R1
R2
S
12 REF
_
0.08
0 . 0 8
0.20
- - -
(L1)
0.20 REF
DETAIL AD
TIMING SOLUTIONS
11
MOTOROLA
MPC92429
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can anddo vary in differentapplications andactual performancemay vary over time. All operatingparameters, including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective
owners.
E Motorola Inc. 2003
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MPC92429/D
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