MPC9653AFA [MOTOROLA]
PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MPC9653AFA |
| 厂家： | 
MOTOROLA |
| 描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC9653A/D
3.3 V 1:8 LVCMOS PLL Clock
Generator
MPC9653A
The MPC9653A is a 3.3 V compatible, 1:8 PLL based clock generator
and zero-delay buffer targeted for high performance low-skew clock distri-
bution in mid-range to high-performance telecom, networking and comput-
ing applications. With output frequencies up to 125 MHz and output skews
less than 150 ps the device meets the needs of the most demanding clock
applications.
LOW VOLTAGE
3.3 V LVCMOS 1:8
Features
• 1:8 PLL based low-voltage clock generator
PLL CLOCK GENERATOR
• Supports zero-delay operation
• 3.3 V power supply
• Generates clock signals up to 125 MHz
• PLL guaranteed to lock down to 145 MHz, output frequency = 36.25 MHz
• Maximum output skew of 150 ps
• Differential LVPECL reference clock input
• External PLL feedback
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
• Drives up to 16 clock lines
• 32-lead LQFP packaging
• 32-lead Pb-free package available
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MPC953 and MPC9653
Functional Description
The MPC9653A utilizes PLL technology to frequency lock its outputs
onto an input reference clock. Normal operation of the MPC9653A requires
the connection of the QFB output to the feedback input to close the PLL
feedback path (external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device and VCO_SEL
selects the operating frequency range of 25 to 62.5 MHz or 50 to 125 MHz.
The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or
AC SUFFIX
32 LEAD LQFP PACKAGE-Pb-free
CASE 873A
divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency
range. The internal VCO of the MPC9653A is running at either 4x or 8x of the reference clock frequency. The MPC9653A is
guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25 MHz.
The MPC9653A has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as a
zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected
input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass
configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The
outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL
to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase
locked loop, enabling the PLL to recover to normal operation.
The MPC9653A is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines.
For series terminated transmission lines, each of the MPC9653A outputs can drive one or two traces giving the devices an effective
fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.
REV 2
© Motorola, Inc. 2004
MPC9653A/D
VCC
2⋅25k
Q0
Q1
Q2
Q3
Q4
0
1
÷1
÷2
0
1
0
1
PCLK
PCLK
÷4
Ref
&
VCO
PLL*
200-500 MHz
VCC
25k
Q5
FB_IN
FB
Q6
VCC
3⋅25k
Q7
PLL_EN
QFB
VCO_SEL
BYPASS
MR/OE
25k
* PLL will lock @ 145 MHz
Figure 1. MPC9653A Logic Diagram
24 23 22 21 20 19 18 17
16
25
26
27
28
29
30
31
32
Q5
GND
15
14
13
VCC
Q6
Q0
VCC
QFB
GND
GND
Q7
MPC9653A
12
11
10
9
VCC
MR/OE
PCLK
PLL_EN
BYPASS
VCO_SEL
1
2
3
4
5
6
7
8
Figure 2. MPC9653A 32-Lead Package Pinout (Top View)
2
TIMING SOLUTIONS
MPC9653A/D
Table 1 . PIN CONFIGURATION
Pin
PCLK, PCLK
FB_IN
I/O
Input
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Function
PECL reference clock signal
Input
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
VCO_SEL
BYPASS
PLL_EN
MR/OE
Input
Input
Input
Input
Output enable/disable (high-impedance tristate) and device reset
Clock outputs
Q0-7
Output
Output
Supply
Supply
QFB
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
GND
VCC_PLL
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for
the analog power supply pin VCC_PLL. Please see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply
for correct operation
Table 2. FUNCTION TABLE
Control
Default
0
1
Selects the VCO outputa
PLL_EN
1
Test mode with PLL bypassed. The reference clock (PCLK) is
substituted for the internal VCO output. MPC9653A is fully
static and no minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
BYPASS
1
Test mode with PLL and output dividers bypassed. The
reference clock (PCLK) is directly routed to the outputs.
MPC9653A is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Selects the output dividers.
VCO_SEL
MR/OE
1
0
VCO ÷ 1 (High frequency range). fREF = fQ0-7 = 4 ⋅ fVCO
VCO ÷ 2 (Low output range). fREF = fQ0-7 = 8 ⋅ fVCO
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of the
device. During reset the PLL feedback loop is open. The
VCO is tied to its lowest frequency. The length of the reset
pulse should be greater than one reference clock cycle
(PCLK).
a. PLL operation requires BYPASS = 1 and PLL_EN = 1.
TIMING SOLUTIONS
3
MPC9653A/D
Table 3. GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
Condition
VTT
VCC ÷ 2
V
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
200
2000
200
V
V
mA
pF
CPD
Power Dissipation Capacitance
10
Per output
Inputs
CIN
Input Capacitance
4.0
pF
Table 4. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
3.9
VCC+0.3
VCC+0.3
±20
V
VIN
VOUT
IIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
-0.3
-0.3
V
V
mA
mA
°C
IOUT
TS
±50
Storage Temperature
-65
125
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5. DC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)
Symbol
VIH
Characteristics
Input high voltage
Min
Typ
Max
VCC + 0.3
0.8
Unit
V
Condition
LVCMOS
2.0
VIL
Input low voltage
V
LVCMOS
LVPECL
VPP
Peak-to-peak input voltage(PCLK)
Common Mode Range(PCLK)
Output High Voltage
300
1.0
2.4
mV
V
a
VCMR
VCC-0.6
LVPECL
IOH = -24 mAb
VOH
VOL
V
Output Low Voltage
0.55
0.30
V
V
IOL = 24 mA
IOL = 12 mA
ZOUT
IIN
Output impedance
14 - 17
5.0
W
c
Input Current
±200
10
µA
VIN = VCC or GND
VCC_PLL Pin
ICC_PLL
Maximum PLL Supply Current
mA
mA
d
ICCQ
Maximum Quiescent Supply Current
10
All VCC Pins
a.
V
CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and
the input swing lies within the VPP (DC) specification.
b. The MPC9653A is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. The MPC9653A meets
the VOH and VOL specification of the MPC953 (VOH > VCC -0.6 V at IOH = -20 mA and VOL > 0.6V at IOL = 20 mA).
c. Inputs have pull-down or pull-up resistors affecting the input current.
d. OE/MR = 1 (outputs in high-impedance state).
4
TIMING SOLUTIONS
MPC9653A/D
Table 6. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)a
Symbol
Characteristics
Input reference frequency
PLL mode, external feedback
Min
Typ
Max
Unit
Condition
fREF
÷4 feedbackb
÷8 feedbackc
50
25
125
62.5
MHz PLL locked
MHz PLL locked
Input reference frequency in PLL bypass moded
VCO operating frequency rangee,m
0
200
500
MHz
MHz
fVCO
fVCOlock
fMAX
200
VCO lock frequency rangen
145
500
MHz
Output Frequency
÷4 feedbackb
÷8 feedbackc
50
25
125
62.5
MHz PLL locked
MHz PLL locked
VPP
VCMRf
tPW, MIN
t(∅)
Peak-to-peak input voltage
Common Mode Range
PCLK
PCLK
450
1.2
2
1000
mV
V
LVPECL
LVPECL
VCC-0.75
Input Reference Pulse Widthg
Propagation Delay (static phase offset)h
Propagation Delay
ns
ps
PCLK to FB_IN
-75
125
PLL locked
tPD
PLL and divider bypass (BYPASS = 0), PCLK to Q0-7
PLL disable (BYPASS = 1 and PLL_EN = 0), PCLK to Q0-7
1.2
3.0
3.3
7.0
ns
ns
tsk(O)
Output-to-output Skewi
150
1.5
ps
ns
tsk(PP)
Device-to-device Skew in PLL and divider bypassj
BYPASS = 0
DC
Output duty cycle
45
50
55
%
PLL locked
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
7.0
6.0
100
100
25
ns
ns
ps
ps
ps
I/O Phase Jitterk
RMS (1 σ)
BW
PLL closed loop bandwidthl
PLL mode, external feedback
÷ 4 feedbackb
÷ 8 feedbackc
0.8 - 4
0.5 - 1.3
MHz
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
b. ÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS = 1 and MR/OE = 0.
c. ÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS = 1 and MR/OE = 0.
d. In bypass mode, the MPC9653A divides the input reference clock.
e. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
f. CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and
the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅)
V
.
g. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% - DCREF,MIN
.
E.g. at fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
h. Valid for fREF = 50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(∅) [ps] = 50 ps ± (1÷(120 ⋅ fREF)).
i.
j.
See application section for part-to-part skew calculation in PLL zero-delay mode.
For a specified temperature and voltage, includes output skew.
k. I/O phase jitter is reference frequency dependent. See application section for details.
l.
-3 dB point of PLL transfer characteristics.
m.
n.
f
f
VCO is frequency range where AC parameters are guaranteed.
VCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO
.
TIMING SOLUTIONS
5
MPC9653A/D
APPLICATIONS INFORMATION
Programming the MPC9653A
are supported: 25 to 62.5 MHz and 50 to 125 MHz. Table 9 il-
lustrates the configurations supported by the MPC9653A. PLL
zero-delay is supported if BYPASS=1, PLL_EN=1 and the input
frequency is within the specified PLL reference frequency
The MPC9653A supports output clock frequencies from 25
to 125 MHz. Two different feedback divider configurations can
be used to achieve the desired frequency operation range. The
feedback divider (VCO_SEL) should be used to situate the
VCO in the frequency lock range between 200 and 500 MHz for
stable and optimal operation. Two operating frequency ranges
range.
Table 7. MPC9653A Configurations (QFB connected to FB_IN)
BYPASS
PLL_EN
VCO_SEL
Operation
Frequency
Ratio
Output range (fQ0-7
)
VCO
n/a
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Test mode: PLL and divider bypass
Test mode: PLL bypass
fQ0-7 = fREF
fQ0-7 = fREF ÷ 4
fQ0-7 = fREF ÷ 8
fQ0-7 = fREF
fQ0-7 = fREF
0-200 MHz
0-50 MHz
n/a
Test mode: PLL bypass
0-25 MHz
n/a
PLL mode (high frequency range)
PLL mode (low frequency range)
50 to 125 MHz
25 to 62.5 MHz
fVCO = fREF ⋅ 4
fVCO = fREF ⋅ 8
Power Supply Filtering
The minimum values for RF and the filter capacitor CF are de-
The MPC9653A is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA_PLL power supply impacts the device characteristics,
fined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 3, “VCC_PLL Power Supply Filter”, the filter
for instance I/O jitter. The MPC9653A provides separate power
supplies for the output buffers (VCC) and the phase-locked loop
cut-off frequency is around 4 kHz and the noise attenuation at
100 kHz is better than 42 dB.
(VCCA_PLL) of the device. The purpose of this design technique
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look in-
ductive and thus increases with increasing frequency. The par-
allel capacitor combination shown ensures that a low imped-
ance path to ground exists for frequencies well above the band-
width of the PLL. Although the MPC9653A has several design
features to minimize the susceptibility to power supply noise
(isolated power and grounds and fully differential PLL) there still
may be applications in which overall performance is being de-
graded due to system power supply noise. The power supply fil-
ter schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
is to isolate the high switching noise digital outputs from the rel-
atively sensitive internal analog phase-locked loop. In a digital
system environment where it is more difficult to minimize noise
on the power supplies a second level of isolation may be re-
quired. The simple but effective form of isolation is a power sup-
ply filter on the VCC_PLL pin for the MPC9653A. Figure 3 illus-
trates a typical power supply filter scheme. The MPC9653A fre-
quency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
Using the MPC9653A in zero-delay applications
sheet the ICCA current (the current sourced through the VCC_PLL
Nested clock trees are typical applications for the
MPC9653A. Designs using the MPC9653A as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9653A clock driver allows for its use as a zero delay buffer.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the de-
vice (the propagation delay through the device is virtually elim-
inated). The maximum insertion delay of the device in zero-de-
lay applications is measured between the reference clock input
and any output. This effective delay consists of the static phase
offset, I/O jitter (phase or long-term jitter), feedback path delay
and the output-to-output skew error relative to the feedback out-
put.
pin) is typically 5 mA (10 mA maximum), assuming that a mini-
mum of 2.985V must be maintained on the VCC_PLL pin.
RF = 5-15 Ω
CF = 22 µF
RF
VCC_PL
MPC9653A
VCC
CF
10 nF
VCC
33...100 nF
Figure 3. VCC_PLL Power Supply Filter
6
TIMING SOLUTIONS
MPC9653A/D
Calculation of part-to-part skew
The MPC9653A zero delay buffer supports applications
where critical clock signal timing can be maintained across sev-
eral devices. If the reference clock inputs of two or more
MPC9653A are connected together, the maximum overall tim-
ing uncertainty from the common PCLK input to any output is:
case timing uncertainty from input to any output of -197 ps to
297 ps (at 125 MHz reference frequency) relative to PCLK:
t
SK(PP) = [-17ps...117ps] + [-150ps...150ps] +
[(10ps @ -3)...(10ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [-197ps...297ps] + tPD, LINE(FB)
tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) ? CF
Due to the frequency dependence of the I/O jitter, Figure 5,
“Max. I/O Jitter versus frequency”, can be used for a more pre-
cise timing performance analysis.
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
30
20
10
PCLKCommon
tPD,LINE(FB)
—t(∅)
QFBDevice 1
tJIT(∅)
FB = ÷ 8
FB = ÷ 4
Any QDevice 1
0
+tSK(O)
25 35
45 55 65 75 85 95 105 115 125
Reference frequency [MHz]
+t(∅)
Figure 5. Maximum I/O Jitter versus frequency
QFBDevice2
tJIT(∅)
Any QDevice 2
+tSK(O)
Driving Transmission Lines
The MPC9653A clock driver was designed to drive high
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive ei-
ther parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to Mo-
torola application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50 Ω
resistance to VCC ÷ 2.
Max. skew
tSK(PP)
Figure 4. MPC9653A maximum device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 10.
Table 8. Confidence Factor CF
CF
Probability of clock edge within the distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9653A clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 6, “Single versus Dual
Transmission Lines”, illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC9653A clock
driver is effectively doubled due to its capability to drive multiple
lines.
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (± 3σ) is assumed, resulting in a worst
TIMING SOLUTIONS
7
MPC9653A/D
3.0
2.5
2.0
1.5
1.0
0.5
0
MPC9653A
OUTPUT
BUFFER
OutA
D = 3.8956
t
OutB
D = 3.9386
ZO = 50 Ω
t
RS = 36 Ω
14 Ω
OutA
IN
In
MPC9653A
OUTPUT
BUFFER
Z
O = 50 Ω
RS = 36 Ω
RS = 36 Ω
OutB0
OutB1
14 Ω
IN
ZO = 50 Ω
2
4
6
8
10
12
14
Figure 6. Single versus Dual Transmission Lines
TIME (nS)
Figure 7. Single versus Dual Waveforms
The waveform plots in Figure 7, “Single versus Dual Line
Termination Waveforms”, show the simulation results of an out-
put driving a single line versus two lines. In both cases the drive
capability of the MPC9653A output buffer is more than sufficient
to drive 50 Ω transmission lines on the incident edge. Note from
the delay measurements in the simulations a delta of only 43ps
exists between the two differently loaded outputs. This sug-
gests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC9653A. The
output waveform in Figure 7 “Single versus Dual Line Termina-
tion Waveforms” shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the driv-
er. The parallel combination of the 36Ω series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the two
lines will equal:
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be un-
comfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 8, “Optimized Dual Line Termination”, should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
MPC9653A
OUTPUT
BUFFER
Z
Z
O = 50Ω
O = 50Ω
RS = 22Ω
RS = 22Ω
14 Ω
VL = VS (Z0 ÷ (RS+R0 +Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
VL = 3.0 (25 ÷ (18+14+25)
= 1.31 V
Figure 8. Optimized Dual Line Termination
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0ns).
MPC9653A DUT
ZO = 50 Ω
Differential
Pulse Generator
ZO = 50 Ω
Z = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 9. PCLK MPC9653A AC test reference
8
TIMING SOLUTIONS
MPC9653A/D
VCC
VCC ÷ 2
PCLK
PCLK
FB_IN
V
= 0.8 V
PP
VCMR
VCC -1.3 V
=
GND
VCC
VCC ÷ 2
VCC
VCC ÷ 2
GND
GND
tSK(O)
t(PD)
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a single device
Figure 10. Output-to-output Skew tSK(O)
Figure 11. Propagation delay (t(PD), static phase offset)
test reference
VCC
PCLK
VCC ÷ 2
GND
tP
FB_IN
T0
DC = tP/T0 x 100%
TJIT(∅) = |T0-T1mean|
The time from the PLL controlled edge to the non controlled edge,
divided by the time between PLL controlled edges, expressed as a
percentage
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 13. I/O Jitter
Figure 12. Output Duty Cycle (DC)
TJIT(CC) = |TN-TN+1
|
T
JIT(PER) = |TN-1/f0|
TN
TN+1
T0
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles
Figure 14. Cycle-to-cycle Jitter
Figure 15. Period Jitter
VCC = 3.3 V
2.4
0.55
tF
tR
Figure 16. Output Transition Time Test Reference
TIMING SOLUTIONS
9
MPC9653A/D
OUTLINE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
FA SUFFIX
LQFP PACKAGE
AC SUFFIX
LQFP PACKAGE-Pb-free
CASE 873A-03
ISSUE B
10
TIMING SOLUTIONS
MPC9653A/D
NOTES
TIMING SOLUTIONS
11
MPC9653A/D
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