MTW16N40E [MOTOROLA]
TMOS POWER FET 16 AMPERES 400 VOLTS RDS(on) = 0.24 OHM; TMOS功率FET 16安培400伏的RDS（on ） = 0.24 OHM
| 型号： | MTW16N40E |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET 16 AMPERES 400 VOLTS RDS(on) = 0.24 OHM |
| 文件： | 总8页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTW16N40E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
16 AMPERES
400 VOLTS
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
R
= 0.24 OHM
DS(on)
D
•
•
•
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
G
CASE 340K–01, Style 1
TO–247AE
•
•
•
Diode is Characterized for Use in Bridge Circuits
S
I
and V
Specified at Elevated Temperature
DSS
Isolated Mounting Hole Reduces Mounting Hardware
DS(on)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
400
Unit
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
GS
= 1.0 MΩ)
V
DGR
400
Gate–Source Voltage — Continuous
— Non–Repetitive (t ≤ 10 ms)
V
± 20
± 40
Vdc
Vpk
GS
V
GSM
p
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (t ≤ 10 µs)
I
I
16
9.0
56
Adc
Apk
D
D
I
p
DM
Total Power Dissipation
Derate above 25°C
P
D
180
1.4
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
–55 to 150
870
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 100 Vdc, V
= 10 Vdc, I = 16 Apk, L = 6.8 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
— Junction to Ambient
R
θJC
R
θJA
0.70
40
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola, Inc. 1996
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0 Vdc, I = 250 µAdc)
400
—
—
420
—
—
Vdc
mV/°C
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
mAdc
DSS
(V
DS
(V
DS
= 400 Vdc, V
= 320 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
0.25
1.0
GS
GS
J
Gate–Body Leakage Current (V
= ± 20 Vdc, V
= 0)
DS
I
—
—
100
nAdc
Vdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V
= V , I = 0.25 mAdc)
2.0
—
3.0
7.0
4.0
—
DS
GS
D
Temperature Coefficient (Negative)
mV/°C
Ohm
Vdc
Static Drain–Source On–Resistance (V
= 10 Vdc, I = 8.0 Adc)
R
V
—
0.225
0.24
GS
D
DS(on)
Drain–Source On–Voltage (V
= 10 Vdc)
GS
DS(on)
(I = 16 Adc)
—
—
—
—
4.8
4.3
D
(I = 8.0 Adc, T = 125°C)
D
J
Forward Transconductance (V
= 15 Vdc, I = 8.0 Adc)
g
FS
8.0
10
—
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
2570
330
82
3600
460
iss
(V
= 25 Vdc, V
= 0 Vdc,
DS
DD
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
164
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
29
62
76
57
66
50
70
ns
d(on)
(V
= 200 Vdc, I = 16 Adc,
Rise Time
D
t
r
V
R
= 10 Vdc,
= 9.1 Ω)
GS
Turn–Off Delay Time
Fall Time
t
170
95
d(off)
G
t
f
Gate Charge
(See Figure 8)
Q
93
nC
T
(V
DS
= 320 Vdc, I = 16 Adc,
D
Q
Q
Q
—
—
—
17
31
30
—
—
—
1
2
3
V
= 10 Vdc)
GS
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
V
Vdc
ns
SD
(I = 16 Adc, V
= 0 Vdc)
S
GS
= 0 Vdc, T = 125°C)
—
—
1.0
0.9
1.6
—
(I = 16 Adc, V
S
GS
J
Reverse Recovery Time
(See Figure 9)
t
—
—
—
—
340
228
112
4.3
—
—
—
—
rr
t
a
(I = 16 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
S
t
b
Reverse Recovery Stored Charge
Q
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
—
—
5.0
13
—
—
nH
nH
D
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
40
30
25
20
15
T
= 25
°C
V
= 10 V
8 V
V
= 50 V
J
GS
DS
35
7 V
30
25
6.5 V
6 V
20
15
10
5
100°C
10
5
4.5 V
16
T
= –55°C
25°C
J
0
0
0
2
4
6
8
10
12
14
18
20
0
2
4
6
8
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.75
0.6
0.32
0.30
0.28
V
= 10 V
T
= 25°C
GS
J
T
= 100°C
J
0.45
0.3
0.26
0.24
V
= 10 V
GS
25°C
0.15
0
–55°C
15 V
16
0.22
0.20
0
5
10
15
20
25
30
0
4
8
12
20
24
28
32
I
, DRAIN CURRENT (AMPS)
I , DRAIN CURRENT (AMPS)
D
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
100
10
V = 0 V
GS
V
= 10 V
GS
= 8 A
I
D
T
= 125°C
J
100°C
1.0
–50
–25
0
25
50
75
100
C)
125
150
0
50
100
150
200
250
300
350
400
T , JUNCTION TEMPERATURE (
°
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off–state condition when cal-
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
) can be made from a rudimentary analysis of
G(AV)
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
GG
R
= the gate drive resistance
G
and Q and V
are read from the gate charge curve.
GSP
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
10000
5000
T
J
= 25°C
V
= 0 V
T
= 25°C
V
= 0 V
GS
J
GS
C
iss
4500
4000
3500
3000
2500
2000
1500
1000
C
iss
C
C
iss
rss
C
oss
1000
C
rss
C
oss
500
0
10
V
= 0 V
5
DS
C
rss
100
0
5
10
15
20
25
0
50
100
150
200
V
V
DS
GS
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
15
12
9
10000
1000
350
280
V
= 200 V
= 16 A
= 10 V
= 25°C
DD
I
T
= 16 A
= 25°C
D
J
I
V
T
D
GS
QT
J
V
210
140
GS
Q2
Q1
t
d(off)
6
100
10
t
t
r
f
3
70
0
Q3
t
d(on)
V
DS
10 15 20 25 30 35 40 45 50 55 60 65
, TOTAL GATE CHARGE (nC)
0
0
1
10
R , GATE RESISTANCE (OHMS)
G
100
1000
5
Q
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
8
V
= 0 V
GS
= 25°C
7
6
5
T
J
4
3
2
1
0
0.50 0.54
0.58
0.62
0.66
0.70
0.74
0.78
0.82
0.86
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature
tion temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded and the transition time
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
aged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
900
800
100
V
= 20 V
GS
SINGLE PULSE
= 25
I
= 16 A
D
10
µ
s
T
°C
C
700
600
500
400
20
10
100
µ
s
1 ms
2
1
10 ms
dc
300
200
THERMAL LIMIT
PACKAGE LIMIT
100
0
0.2
0.1
R
LIMIT
DS(on)
1
2
10
20
100
200
1000
25
50
75
100
125
C)
150
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
T , STARTING JUNCTION TEMPERATURE (
°
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
JC θJC
θ
0.05
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
t
READ TIME AT t
0.01
SINGLE PULSE
1
1
t
T
– T = P
R (t)
(pk) θJC
2
J(pk)
C
DUTY CYCLE, D = t /t
1 2
0.01
0.00001
0.0001
0.001
0.01
t, TIME (ms)
0.1
1.0
10
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
–T–
E
–Q–
M
M
0.25 (0.010)
T B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–B–
C
4
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
U
L
MILLIMETERS
INCHES
DIM
A
B
C
D
E
MIN
19.7
15.3
4.7
1.0
1.27 REF
2.0
5.5 BSC
2.2
0.4
14.2
MAX
20.3
15.9
5.3
MIN
MAX
0.799
0.626
0.209
0.055
A
K
0.776
0.602
0.185
0.039
0.050 REF
0.079
R
1
2
3
1.4
F
2.4
0.094
–Y–
G
H
J
K
L
0.216 BSC
P
2.6
0.8
14.8
0.087
0.016
0.559
0.102
0.031
0.583
5.5 NOM
0.217 NOM
P
3.7
3.55
5.0 NOM
5.5 BSC
3.0
4.3
3.65
0.146
0.140
0.197 NOM
0.217 BSC
0.118 0.134
0.169
0.144
V
H
Q
R
U
V
F
J
G
D
3.4
M
S
0.25 (0.010)
Y
Q
STYLE 1:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
CASE 340K–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
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