MTY25N60E [MOTOROLA]
TMOS POWER FET 25 AMPERES 600 VOLTS RDS(on) = 0.21 OHM; TMOS功率FET 25安培600伏的RDS（on ） = 0.21 OHM
| 型号： | MTY25N60E |
| 厂家： | 
MOTOROLA |
| 描述： | TMOS POWER FET 25 AMPERES 600 VOLTS RDS(on) = 0.21 OHM |
| 文件： | 总8页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MTY25N60E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
25 AMPERES
600 VOLTS
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also offers a drain–to–source diode with fast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
R
= 0.21 OHM
DS(on)
•
•
•
Avalanche Energy Specified
Diode is Characterized for Use in Bridge Circuits
I
and V Specified at Elevated Temperature
DSS
DS(on)
D
G
CASE 340G–02, STYLE 1
TO–264
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
600
Unit
Vdc
Vdc
Drain–Source Voltage
V
DSS
Drain–Gate Voltage (R
GS
= 1 MΩ)
V
DGR
600
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (t ≤ 10 ms)
V
±20
±40
Vdc
Vpk
GS
V
GSM
p
Drain Current — Continuous @ T = 25°C
I
25
65
Adc
Apk
C
D
Drain Current — Single Pulse (t ≤ 10 µs)
I
DM
p
Total Power Dissipation
Derate above 25°C
P
D
300
2.38
Watts
W/°C
Operating and Storage Temperature Range
T , T
stg
–55 to 150
3000
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 100 Vdc, V = 10 Vdc, Peak I = 25 Apk, L = 10 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
R
0.42
40
°C/W
°C
θJC
θJA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
260
L
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
V
(BR)DSS
(V
GS
= 0, I = 250 µA)
600
—
—
714
—
—
Vdc
mV/°C
D
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
µAdc
DSS
(V
DS
(V
DS
= 600 Vdc, V
= 600 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
—
—
—
—
10
200
GS
GS
J
Gate–Body Leakage Current (V
= ±20 Vdc, V
DS
= 0)
I
—
—
100
nAdc
GS
GSS
ON CHARACTERISTICS (1)
Gate Threshold Voltage
V
GS(th)
(V
DS
= V , I = 250 µAdc)
2
—
—
7
4
—
Vdc
mV/°C
GS
D
Threshold Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (V = 10 Vdc, I = 12.5 Adc)
R
V
—
—
0.21
Ohm
Vdc
GS
= 10 Vdc)
D
DS(on)
Drain–Source On–Voltage (V
GS
DS(on)
(I = 25 Adc)
—
—
5.2
—
6
7
D
(I = 12.5 Adc, T = 125°C)
D
J
Forward Transconductance (V
DS
= 15 Vdc, I = 12.5 Adc)
g
18
—
—
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
—
—
—
7300
700
110
10220
1100
250
iss
(V
= 25 Vdc, V = 0 Vdc,
GS
DS
DD
Output Capacitance
C
oss
f = 1.0 MHz)
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
—
—
—
—
—
—
—
—
32
90
60
175
300
200
350
—
ns
d(on)
(V
= 300 Vdc, I = 25 Adc,
Rise Time
D
t
r
V
R
= 10 Vdc,
= 4.7 Ω)
GS
G
Turn–Off Delay Time
Fall Time
t
170
110
240
30
d(off)
t
f
Gate Charge
(See Figure 8)
Q
Q
Q
Q
nC
T
1
2
3
(V
DS
= 480 Vdc, I = 25 Adc,
D
V
= 10 Vdc)
GS
110
65
—
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 25 Adc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
S
GS
—
—
0.9
0.8
1.2
—
(I = 25 Adc, V
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
—
—
—
—
620
310
—
—
—
—
rr
t
a
(I = 25 Adc, V
= 0 Vdc,
dI /dt = 100 A/µs)
S
GS
S
t
310
b
Reverse Recovery Stored Charge
Q
10.42
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
—
—
4.5
7.5
—
—
nH
nH
D
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
50
40
30
20
10
50
6 V
V
= 10 V
GS
V
≥ 10 V
T
= 25
°C
DS
J
40
30
20
10
0
8 V
5 V
100°C
T
= –55°C
J
4 V
25°C
0
0
2
4
6
8
10
12
14
16
18
20
2
2.5
3
3.5
4
4.5
5
5.5
6
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.5
0.4
0.3
0.2
0.1
0
0.26
0.24
0.22
0.2
V
= 10 V
GS
T
= 25°C
J
T
= 100°C
J
25°C
V
= 10 V
GS
15 V
–55°C
0.18
0
10
20
30
40
50
0
10
20
30
40
50
I
, DRAIN CURRENT (AMPS)
I , DRAIN CURRENT (AMPS)
D
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
2.5
2
10000
1000
100
10
V
= 10 V
GS
= 12.5 A
T
= 125
°C
J
I
D
100°C
1.5
1
V
= 0 V
GS
25°C
0.5
0
1
–50
–25
0
25
50
75
100
C)
125
150
0
100
200
300
400
500
600
T , JUNCTION TEMPERATURE (
°
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
J
DS
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
iss
culating t
and is read at a voltage corresponding to the
d(on)
on–state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
the drive circuit so that
) can be made from a rudimentary analysis of
G(AV)
t = Q/I
G(AV)
During the rise and fall time interval when switching a resis-
tive load, V remains virtually constant at a level known as
GS
the plateau voltage, V
. Therefore, rise and fall times may
SGP
be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
= the gate drive resistance
GG
GG
R
G
and Q and V
GSP
are read from the gate charge curve.
2
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V
/(V
GG GG
– V
)]
GSP
d(on)
G
iss
In (V
/V
GG GSP
)
d(off)
G
iss
24000
20000
16000
12000
8000
4000
0
100000
V
= 0 V
V
= 0 V
DS
GS
V
= 0 V
T
= 25°C
GS
J
C
T
= 25°C
iss
J
C
10000
1000
100
iss
C
rss
C
C
iss
oss
C
oss
C
rss
C
rss
10
10
5
0
5
10
15
20
25
10
100
1000
V
V
DS
GS
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Figure 7a. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
12
10
8
600
500
400
300
10000
1000
100
V
= 300 V
= 25 A
= 10 V
= 25°C
DD
QT
I
V
T
D
GS
J
V
GS
6
t
d(off)
Q2
Q1
t
f
r
T
= 25°C
= 25 A
J
4
200
t
I
D
2
t
100
0
d(on)
V
DS
Q3
0
10
0
50
100
150
200
250
1
10
, GATE RESISTANCE (OHMS)
G
100
Q , TOTAL GATE CHARGE (nC)
R
g
Figure 8. Gate Charge versus Gate–to–Source Voltage
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
25
V
= 0 V
GS
= 25°C
20
15
10
T
J
5
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
tion temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (I
)
DM
) is exceeded and the transition time
(I
), the energy rating is specified at rated continuous cur-
DM
nor rated voltage (V
DSS
rent (I ), in accordance with industry custom. The energy rat-
D
(t ,t ) do not exceed 10 µs. In addition the total power aver-
r f
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
aged over a complete switching cycle must not exceed
(T
– T )/(R ).
J(MAX)
C
θJC
rents below rated continuous I can safely be assumed to
A Power MOSFET designated E–FET can be safely used
D
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
equal the values indicated.
5
SAFE OPERATING AREA
100
10
1
3000
2500
I
= 25 A
V
= 20 V
D
GS
SINGLE PULSE
= 25
10 µs
T
°C
C
2000
1500
1000
500
0
100 µs
1 ms
10 ms
dc
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
1000
25
50
75
100
125
C)
150
V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (
°
DS
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
0.1
P
(pk)
R
(t) = r(t) R
JC θJC
0.1
0.05
θ
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.02
0.01
t
READ TIME AT t
T
1
1
t
– T = P R (t)
(pk) θJC
2
SINGLE PULSE
J(pk)
C
DUTY CYCLE, D = t /t
1 2
0.01
1.0E–05
1.0E–04
1.0E–03
1.0E–02
t, TIME (s)
1.0E–01
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
t
a
b
TIME
0.25 I
t
S
p
I
S
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
M
M
0.25 (0.010)
T B
–T–
–Q–
U
NOTES:
–B–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
C
E
MILLIMETERS
INCHES
N
DIM
A
B
C
D
E
MIN
2.8
19.3
4.7
0.93
1.9
2.2
MAX
2.9
20.3
5.3
1.48
2.1
2.4
MIN
MAX
1.142
0.800
0.209
0.058
0.083
0.102
1.102
0.760
0.185
0.037
0.075
0.087
A
K
L
1
2
3
R
F
G
H
J
K
L
N
P
Q
R
U
W
5.45 BSC
0.215 BSC
–Y–
2.6
0.43
17.6
11.0
3.95
2.2
3.1
2.15
6.1
3.0
0.78
18.8
11.4
4.75
2.6
3.5
2.35
6.5
0.102
0.017
0.693
0.433
0.156
0.087
0.122
0.085
0.240
0.110
0.118
0.031
0.740
0.449
0.187
0.102
0.137
0.093
0.256
0.125
P
W
F 2 PL
G
J
H
2.8
3.2
D 3 PL
0.25 (0.010)
M
S
Y
Q
STYLE 1:
PIN 1. GATE
2. DRAIN
3. SOURCE
CASE 340G–02
TO–264
ISSUE E
Motorola TMOS Power MOSFET Transistor Device Data
7
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MTY25N60E/D
◊
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