PC33879DWB/R2 [MOTOROLA]
Configurable Octal Serial Switch with Open Load Detect Current Disable; 可配置8路串联开关，负载开路检测电流关闭
| 型号： | PC33879DWB/R2 |
| 厂家： | 
MOTOROLA |
| 描述： | Configurable Octal Serial Switch with Open Load Detect Current Disable |
| 文件： | 总20页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33879
Rev 3.0, 06/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33879
Configurable Octal Serial Switch
with Open Load Detect Current
Disable
The 33879 device is an 8-output hardware-configurable, high-side/low-side
switch with 16-bit serial input control. Two of the outputs may be controlled
directly via microprocessor for PWM applications. The 33879 incorporates
SMARTMOS technology, with CMOS logic, bipolar/MOS analog circuitry, and
DMOS power MOSFETs. The 33879 controls various inductive, incandescent,
or LED loads by directly interfacing with a microcontroller. The circuit’s
innovative monitoring and protection features include very low standby
currents, cascade fault reporting, internal +45 V clamp voltage for low-side
configuration, -20 V high-side configuration, output-specific diagnostics, and
independent overtemperature protection.
CONFIGURABLE OCTAL SERIAL
SWITCH WITH OPEN LOAD
DETECT CURRENT DISABLE
Features
EK (Pb-FREE) SUFFIX
DWB SUFFIX
CASE 1437-01
32-LEAD SOICW-EP
• Designed to Operate 5.5 V < VPWR < 26.5 V
• 16-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible
• Outputs Are Current Limited (0.5 A to 1.0 A) to Drive Incandescent
Lamps
• Output Voltage Clamp, +45 V (Low Side) and -20 V (High Side) During
Inductive Switching
• On/Off Control of Open Load Detect Current (LED Application)
• Internal Reverse Battery Protection on VPWR
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
• Loss of Ground or Supply Will Not Energize Loads or Damage IC
• Maximum 5.0 µA IPWR Standby Current at 13.0 V VPWR
PC33879DWB/R2
PC33879EK/R2
32 SOICW-EP
-40°C to 125°C
• RDS(ON) of 1.0 Ω at 25°C Typical
• Short Circuit Detect and Current Limit with Automatic Retry
• Independent Overtemperature Protection
• Motorola Now Offers Pb-Free Packaging with the Suffix EK
33879 Simplified Application Diagram
V
PWR
V
BAT
+5.0 V
33879
V
V
D1
D2
D3
D4
S1
S2
S3
S4
MCU
DD PWR
A0
EN
DI
SCLK
CS
High-Side Drive
MOSI
SCLK
CS
MISO
PWM1
PWM2
DO
H-Bridge Configuration
V
M
IN5
IN6
D5
D6
D7
D8
S5
S6
S7
S8
BAT
V
BAT
Low-Side Drive
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
V
VPWR
DD
~50 µA
__
Overvoltage
Shutdown/POR
Sleep State
CS
Internal
Bias
Power Supply
Charge
Pump
SCLK
DI
GND
DO
OV, POR, SLEEP
SPI and
Interface
Logic
EN
IN5
IN6
Typical of all 8 output drivers
TLIM
D1
D2
D3
D4
D7
D8
~110 kΩ
~50 µA
Drain
Outputs
Open
SPI Bit 0
Gate
Load
Detect
Current
Drive
Enable
Control
Current
Limit
~80 µA
SPI Bit 4
IN5
+
–
S1
S2
S3
S4
S7
S8
~50 µA
+
–
–
+
Source
Outputs
Open/Short ~3.5 V Open/Short
Comparator
Threshold
D5
D6
Drain
Outputs
Open
TLIM
Load
Detect
Current
~80 µA
Gate
Drive
Control
Current
Limit
+
–
S5
S6
Source
Outputs
+
–
–
+
~3.5 V Open/Short
Threshold
Open/Short
Comparator
Figure 1. 33879 Simplified Internal Block Diagram
33879
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GND
VDD
S8
NC
D8
S2
D2
NC
NC
S1
DO
VPWR
NC
S7
D7
S4
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
D4
8
NC
NC
S3
D3
D5
S5
IN5
CS
9
10
11
12
13
14
15
16
D1
D6
S6
IN6
EN
SCLK
DI
PIN FUNCTION DESCRIPTION
Pin
1
Pin Name
GND
Formal Name
Definition
Ground
Digital ground.
2
VDD
Logic Supply Voltage
Logic supply for SPI interface. With V
low the device will be in sleep mode.
DD
3
S8
Source Output 8
Not Connected
Output eight MOSFET source pins.
No internal connection to this pin.
4, 8, 9, 24,
25, 30
NC
5
D8
S2
Drain Output 8
Source Output 2
Drain Output 2
Source Output 1
Drain Output 1
Drain Output 6
Source Output 6
Command Input 6
Enable Input
Output eight MOSFETdrain pin.
Output two MOSFET source pin.
Output two MOSFET drain pin.
Output one MOSFET source pin.
Output one MOSFET drain pin.
Output six MOSFET drain pin.
Output six MOSFET source pin.
6
7
D2
10
11
12
13
14
15
16
17
18
S1
D1
D6
S6
IN6
EN
SCLK
DI
PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
IC Enable. Active high. With EN low, the device is in sleep mode.
SPI control clock input pin.
SPI Clock
Serial Data Input
SPI Chip Select
SPI control data input pin from MCU to the 33879. Logic [1] activates output.
SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be
transferred in.
CS
19
20
21
22
23
26
27
28
29
31
IN5
S5
Command Input 5
Source Output 5
Drain Output 5
Drain Output 3
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
Output five MOSFET source pin.
D5
Output five MOSFET drain pin.
D3
Output three MOSFET drain pin.
S3
Output three MOSFET source pin.
Output four MOSFET drain pin.
D4
S4
Output four MOSFET source pin.
D7
Output seven MOSFET drain pin.
Output seven MOSFET source pin.
S7
VPWR
Power supply pin to the 33879. V
has internal reverse battery protection.
PWR
32
DO
Serial Data Output
SPI control data output pin from the 33879 to the MCU. DO=0 no fault, DO=1 specific
output has fault.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
V
Supply Voltage (Note 1)
V
-0.3 to 7.0
V
V
V
DD
DD
–
DC
DC
DC
CS, DI, DO, SCLK, IN5, IN6, and EN (Note 1)
Supply Voltage (Note 1)
-0.3 to 7.0
-16 to 40
50
V
V
PWR
PWR
Output Clamp Energy (Note 2)
E
mJ
V
CLAMP
ESD Voltage
V
±2000
±200
ESD1
ESD2
Human Body Model (Note 3)
Machine Model (Note 4)
V
Storage Temperature
TSTG
-55 to 150
-40 to 125
-40 to 150
-40 to 150
1.7
°C
°C
°C
°C
W
Operating Case Temperature
Operating Junction Temperature
Maximum Junction Temperature
Power Dissipation (Note 5)
T
C
T
J
T
J
P
D
Thermal Resistance
°C/W
R
R
71
θJA
Junction-to-Ambient
1.2
Between the Die and the Exposed Die Pad
θJC
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
5. Maximum power dissipation at T = 25°C with no heatsink used.
A
33879
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage Range
Fully Operational
V
V
PWR(fo)
5.5
–
–
26.5
24
Supply Current
I
14
mA
PWR(on)
Sleep State Supply Current
or EN ≤ 0.8 V, VPWR = 13 V
I
µA
PWR(ss)
V
–
2.0
5.0
DD
Sleep State Supply Current
I
µA
VDD(ss)
EN ≤ 0.8 V, VDD = 5.5 V
–
2.0
28.5
1.5
5.0
32
V
V
V
V
Overvoltage Shutdown Threshold Voltage
Overvoltage Shutdown Hysteresis Voltage
Undervoltage Shutdown Threshold Voltage
Undervoltage Shutdown Hysteresis Voltage
VPWR(OV)
27
V
V
PWR
PWR
PWR
PWR
V
0.2
3.0
300
2.5
5.0
700
PWR(OV-hys)
VPWR(UV)
4.0
V
VPWR(UV-hys)
500
mV
Logic Supply Voltage
V
3.1
250
0.8
0.3
–
400
2.5
–
5.5
700
3.0
1.5
V
µA
V
DD
Logic Supply Current
I
DD
Logic Supply Sleep State Threshold Voltage
Logic Supply Sleep State Hysteresis (Note 6)
Notes
V
DD(SS)
V
V
DD(SS-hys)
6. This parameter is guaranteed by design but is not production tested.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT
Drain-to-Source ON Resistance
R
Ω
DS(ON)
–
–
–
–
1.0
–
1.4
–
I
I
I
= 0.350 A, T = 125°C, V
= 13 V
PWR
OUT
OUT
OUT
J
= 0.350 A, T = 25°C, V
= 13 V
= 13 V
PWR
J
PWR
–
= 0.350 A, T = -40°C, V
J
Output Self Limiting Current High-Side and Low-Side Configurations
I
0.5
2.5
35
–
1.0
4.2
70
A
V
OUT(LIM)
Output Fault Detection Voltage Threshold (Note 7)
Outputs Programmed OFF
V
OUT(flt-th)
OUT(flt-th)
OUT(flt-th)
3.5
55
Output Fault Detection Current @ Threshold, High-Side Configuration
Outputs Programmed OFF
I
I
µA
µA
µA
Output Fault Detection Current @ Threshold, Low-Side Configuration
Outputs Programmed OFF
20
30
50
Output OFF Open Load Detection Current, High-Side Configuration
I
I
OCO
OCO
V
= 16 V, VSource = 0 V, Outputs Programmed OFF
65
100
160
Drain
Output OFF Open Load Detection Current, Low-Side Configuration
= 16 V, VSource = 0 V, Outputs Programmed OFF
µA
V
V
40
40
-15
–
75
45
-20
–
135
55
Drain
Output Clamp Voltage Low-Side Drive
= 10 mA
V
OC(LSD)
OC(HSD)
OUT(LKG)
OUT(LKG)
I
D
Output Clamp Voltage High-Side Drive
= -10 mA
V
V
I
-25
7.0
S
Output Leakage Current High-Side and Low-Side Configurations
= 0 V, V = 16 V, V = 0 V
I
I
µA
µA
V
DD
Drain
Source
Output Leakage Current Low-Side Configuration
= 5.0 V, V = 16 V, V = 0 V,
V
DD
Drain
Source
–
–
5
Open Load Detection Current Disabled
Output Leakage Current High-Side Configuration
I
µA
OUT(LKG)
V
= 5.0 V, V
= 16 V, V
= 0 V,
DD
Drain
Source
–
–
–
20
185
15
Open Load Detection Current Disabled
Overtemperature Shutdown (Note 8)
Overtemperature Shutdown Hysteresis (Note 8)
Notes
T
155
5.0
°C
°C
LIM
T
10
LIM(hys)
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
8. This parameter is guaranteed by design but is not production tested.
33879
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.
Typical values, where applicable, reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic High-Voltage Thresholds (Note 9)
Input Logic Low-Voltage Thresholds (Note 9)
V
0.7 x VDD
GND - 0.3
–
–
VDD + 0.3
0.2 x VDD
V
V
IH
V
IL
IN5, IN6, EN Input Logic Current
IN5, IN6, EN = 0 V
I
I
I
µA
IN5, IN6, EN
-10
30
–
45
45
–
10
100
100
10
IN5, IN6 Pull-Down Current
0.8 V to 5.0 V
I
I
µA
µA
µA
µA
IN5, IN6,
EN Pull-Down Current
EN = 5.0 V
I
EN
30
SCLK, DI Input, Tri-State DO Output
0 V to 5.0 V
I
I
I
SCK, DI, TriDO
-10
-10
CS Input Current
CS = VDD
I
I
CS
CS
–
10
CS Pull-Up Current
CS = 0 V
µA
µA
-30
–
–
–
-100
10
CS Leakage Current to VDD
I
CS(LKG)
CS = 5.0 V, V
= 0 V
DD
DO High-State Output Voltage
= -1.6 mA
V
V
V
DOHIGH
I
V
- 0.4
DD
–
VDD
DO-HIGH
DO Low-State Output Voltage
= 1.6 mA
V
DOLOW
I
–
–
–
0.4
20
DO-LOW
Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (Note 10)
Notes
C
–
pF
IN
9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
10. This parameter is guaranteed by design but not production tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Units
POWER OUTPUT TIMING
Output Slew Rate Low-Side Configuration (Note 11)
= 620 Ω, CL = 200 pF
V/µs
V/µs
V/µs
V/µs
tSR(rise)
tSR(fall)
tSR(rise)
tSR(fall)
R
0.1
0.1
0.1
0.1
1.0
0.5
0.5
0.3
0.3
15
1.0
1.0
1.0
1.0
50
LOAD
Output Slew Rate Low-Side Configuration (Note 11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Rise Time High-Side Configuration (Note 11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Fall Time High-Side Configuration (Note 11)
= 620 Ω, CL = 200 pF
R
LOAD
Output Turn ON Delay Time, High-Side and Low-Side Configuration
(Note 12)
µs
µs
tDLY(on)
tDLY(off)
tFAULT
Output Turn OFF Delay Time, High-Side and Low-Side Configuration
(Note 12)
1.0
30
–
100
300
Output Fault Delay Time (Note 13)
Power-ON Reset Delay
100
µs
µs
t
POR
Delay Time Required from Rising Edge of EN and V
to SPI Active
100
100
–
–
–
–
DD
Low-State Duration on V
or EN for Reset
t
µs
DD
RESET
V
or EN ≤ 0.2 V
DD
Notes
11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points. CL Capacitor
is connected from Drain or Source output to Ground.
12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points.
13. Duration of fault before fault bit is set. Duration between access times must be greater than 300 µs to read faults.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Units
DIGITAL INTERFACE TIMING (Note 14)
Recommended Frequency of SPI Operation (Note 14)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
fSPI
–
100
50
16
20
–
4.0
–
–
–
–
–
–
–
MHz
ns
t
LEAD
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
DI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time (Note 15)
t
–
ns
LAG
t
–
ns
DI(su)
t
–
ns
DI(HOLD)
5.0
ns
t
t
r(DI)
f(DI)
DI, CS, SCLK Signal Fall Time (Note 15)
–
–
–
–
5.0
–
–
ns
ns
ns
ns
Time from Falling Edge of CS to DO Low Impedance (Note 16)
Time from Rising Edge of CS to DO High Impedance (Note 17)
Time from Rising Edge of SCLK to DO Data Valid (Note 18)
Notes
t
55
55
55
DO(EN)
t
–
DO(DIS)
t
25
VALID
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5V/3.1V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin
18. Time required to obtain valid data out from DO following the rise of SCLK.
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Timing Diagrams
CS
0.2 V
DD
t
t
lag
lead
0.7 V
0.2 V
DD
DD
SCLK
t
t
DI(hold)
DI(su)
0.7 V
0.2 V
DD
DD
DI
MSB in
t
t
DO(dis)
DO(en)
t
valid
0.7 V
0.2 V
DD
DD
DO
MSB out
LSB out
Figure 2. SPI Timing Diagram
t
f(DI)
t
< 50 ns
50%
< 50 ns
3.3/5.0 V
r(DI)
V
= 5.0 V
DD
0.7 V
DD
0.2 V
SCLK
DD
0 V
33879
Under
Test
SCLK
DO
C = 200 pF
V
OH
0.7 V
DD
L
0.2 V
0.7 V
DO
DD
V
V
OL
t
r(DO)
(Low-to-High)
DO
t
valid
OH
NOTE: C represents the total capacitance of the test
L
DD
(High-to-Low)
fixture and probe.
0.2 V
DD
V
OL
Figure 3. Valid Data Delay Time and Valid Time Test Circuit
Figure 4. Valid Data Delay Time and Valid Time Waveforms
t
f(CS)
t
r(CS)
<50 ns
90%
<50 ns
0.7 V
3.3/5.0 V
0 V
CS
DO
DD
0.2 V
10%
DD
t
t
DO(en)
DO(dis)
V
Tri-State
90%
(Tri-State to Low)
10%
V
OL
t
t
DO(en)
DO(dis)
V
OH
90%
V
Tri-State
DO
10%
(Tri-State to High)
Figure 5. Enable and Disable Time Waveforms
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Typical Electrical Characteristics
20
19
18
17
16
15
14
1.4
V
@ 13 V
PWR
V
@ 18 V
PWR
High Side Drive
1.2
1.0
0.8
0.6
0.4
-40 -25
0
25
50
75
100 125
-40 -25
0
25
50
75
100 125
TA, Ambient Temperature (°C)
TA, Ambient Temperature (°C)
Figure 6. IPWR vs. Temperature
Figure 9. RDS(ON) vs. Temperature at 350 mA
7
1.4
1.2
1.0
0.8
0.6
0.4
0.2
T = 25°C
A
High Side Drive
V
@ 13 V
PWR
6
5
4
3
2
1
-40 -25
0
25
50
75
100 125
Ambient Temperature (°C)
0
5
10
15
20
25
T
VPWR (V)
A,
Figure 10. RDS(ON) vs. VPWR at 350 mA
Figure 7. Sleep State IPWR vs. Temperature
140
120
100
80
T
= 25°C
A
60
40
20
0
5
10
VPWR
15
20
25
Figure 8. Sleep State IPWR vs. VPWR
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Typical Electrical Characteristics (continued)
140
120
100
80
5.0
T
= 25°C
A
V
@ 16 V
PWR
Open Load Detect Enabled
4.5
4.0
3.5
3.0
2.5
2.0
60
40
20
0
-40 -25
0
25
50
75
100 125
5
10
15
20
25
T
A, Ambient Temperature (°C)
TA, Ambient Temperature (°C)
Figure 11. Open Load Detection Current at Threshold
Figure 12. Open Load Detection Threshold vs.
Temperature
33879
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SYSTEM/APPLICATION INFORMATION
FUNCTIONAL PIN DESCRIPTION
follows a first-in, first-out protocol with both input and output
words transferring the most significant bit (MSB) first.
CS Pin
The system MCU selects the 33879 with which to
communicate through the use of the chip select CS pin. Logic
low on CS enables the data output (DO) driver and allows data
to be transferred from the MCU to the 33879 and vice versa.
Data clocked into the 33879 is acted upon on the rising edge of
CS.
EN Pin
The EN pin on the 33879 enables the device. With the EN pin
high, output drivers may be activated and open/short fault
detection performed and reported. With the EN pin low, all
outputs become inactive, Open Load Detection Current is
disabled, and the device enters sleep mode. The 33879 will
perform Power-ON Reset on rising edge of the enable signal.
To avoid any spurious data, it is essential the high-to-low
transition of the CS signal occur only when SPI clock (SCLK) is
in a logic low state.
IN5 and IN6 Pins
SCLK Pin
The IN5 and IN6 command inputs allow outputs five and six
to be used in PWM applications. The IN5 and IN6 pins are
OR-ed with the Serial Peripheral Interface (SPI) command input
bits. For SPI control of outputs five and six, the IN5 and IN6 pins
should be grounded or held low by the microprocessor. When
using IN5 or IN6 to PWM the output, the control SPI bit must be
logic [0]. Maximum PWM frequency for each output is 2.0 kHz.
The SCLK pin clocks the internal shift registers of the 33879.
The serial data input (DI) pin is latched into the input shift
register on the falling edge of the SCLK. The serial data output
(DO) pin shifts data out of the shift register on the rising edge of
the SCLK signal. False clocking of the shift register must be
avoided to ensure validity of data. It is essential that the SCLK
pin be in a logic low state when the CS pin makes any transition.
For this reason, it is recommended the SCLK pin is commanded
to a logic low state when the device is not accessed (CS in logic
high state). With CS in a logic high state, signals present on
SCLK and DI are ignored and the DO output is tri-state.
VDD Pin
The VDD input pin is used to determine logic levels on the
microprocessor interface (SPI) pins. Current from VDD is used
to drive DO output and the pull-up current for CS. VDD must be
DI Pin
applied for normal mode operation. The 33879 device will
perform Power-ON Reset with the application of VDD.
The DI pin is used for serial instruction data input. DI
information is latched into the input register on the falling edge
of SCLK. A logic high state present on DI will program a specific
output on. The specific output will turn on with the rising edge of
the CS signal. Conversely, a logic low state present on the DI
pin will program the output off. The specific output will turn off
with the rising edge of the CS signal. To program the eight
outputs and Open Load Detection Current on or off, send the DI
data beginning with the Open Load Detection Current bits,
followed by output eight, output seven, and so on to output one.
For each falling edge of the SCLK while CS is logic low, a data
bit instruction (on or off) is loaded into the shift register per the
data bit DI state. Sixteen bits of entered information is required
to fill the input shift register.
V
Pin
PWR
The VPWR pin is battery input and Power-ON Reset to the
33879 IC. The VPWR pin has internal reverse battery protection.
All internal logic current is provided from the VPWR pin. The
33879 will perform Power-ON Reset with the application of
VPWR.
D1–D8 Pins
The D1 to D8 pins are the open-drain outputs of the 33879.
For high-side drive configurations, the drain pins are connected
to battery supply. In low-side drive configurations, the drain pins
are connected to the low side of the load. All outputs may be
configured individually as desired. When configured as low-side
drive, the 33879 limits the positive inductive transient to 45 V.
DO Pin
The DO pin is the output from the shift register. The DO pin
remains tri-state until the CS pin is in a logic low state. All faults
on the 33879 device are reported as logic [1] through the DO
data pin. Regardless of the configuration of the driver, open
loads and shorted loads are reported as logic [1]. Conversely,
normal operating outputs with non-faulted loads are reported as
logic [0]. Outputs programmed with Open Load Detection
Current disabled will report logic [0] in the off state. The first
eight positive transitions of SCLK will report logic [0] followed by
the status of the eight output drivers. The DI/DO shifting of data
S1–S8 Pins
The S1 to S8 pins are the source outputs of the 33879. For
high-side drive configurations, the source pins are connected
directly to the load. In low-side drive configurations, the source
is connected to ground. All outputs may be configured
individually as desired. When high-side drive is used, the 33879
will limit the negative inductive transient to negative 20 V.
33879
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MCU INTERFACE DESCRIPTION
Figure 14 illustrates the daisy chain configuration using the
Introduction
33879. Data from the MCU is clocked daisy chain through each
device while the CS bit is commanded low by the MCU. During
each clock cycle, output status from the daisy chain is
transferred to the MCU via the Master In Slave Out (MISO) line.
On rising edge of CS, command data stored in the input register
is then transferred to the output driver.
The 33879 is an 8-output hardware-configurable power
switch with 16-bit serial control. A simplified block diagram of
the 33879 is shown in Figure 1 on page 2.
The 33879 device uses high-efficiency up-drain power
DMOS output transistors exhibiting low drain-to-source ON
resistance (RDS(ON) = 1.0 Ω at 25°C typical) and dense CMOS
control logic. All outputs have independent voltage clamps to
provide fast inductive turn-off and transient protection.
SCLK
Parallel Port
In operation, the 33879 functions as an 8-output serial switch
serving as a MCU bus expander and buffer with fault
33879
CS
33879
33879
CS SCLK
CS SCLK
management and fault reporting features. In doing so, the
device directly relieves the MCU of the fault management
functions. This device directly interfaces to an MCU using a SPI
for control and diagnostic readout. Figure 13 illustrates the
basic SPI configuration between an MCU and one 33879.
MC68HCxx
Microcontroller
with
MISO
DO
DI
DO
DI
DO
DI
SPI Interface
8 Outputs
8 Outputs
8 Outputs
MC68HCxx
Microcontroller
33879
MOSI
Figure 14. 33879 SPI System Daisy Chain
DI
MOSI
MISO
Multiple 33879 devices can be controlled in a parallel input
fashion using the SPI. Figure 15 illustrates the control of
24 loads using three dedicated parallel MCU ports for chip
select.
Shift Register
16 Bits
Shift Register
16 Bits
DO
33879
SCLK
CS
MOSI
Receive
Buffer
DI
To
Logic
SCLK
SCLK
MISO
8 Outputs
DO
CS
Parallel
Ports
MC68HCxx
Microcontroller
with
33879
SPI Interface
Figure 13. SPI Interface with Microcontroller
DI
SCLK
DO
All inputs are compatible with 5.0 V and 3.3 V CMOS logic
levels and incorporate positive logic. When a SPI bit is
programmed to a logic [0], the corresponding output will be
OFF. Conversely, when a SPI bit is programmed to logic [1] the
output being controlled will be ON. Diagnostics are treated in a
similar manner. Outputs with a fault will feed back (via DO) a
logic [1] to the microcontroller, while normal operating outputs
will provide a logic [0].
8 Outputs
8 Outputs
CS
33879
DI
A
Parallel
Ports
SCLK
DO
B
C
CS
Figure 15. Parallel Input SPI Control
33879
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SPI DEFINITION
On each SPI communication, a 16-bit command word is sent
33879 will perform on rising edge of CS. The Fault Register,
shown in Table 2, defines the previous state status of the output
driver. Table 3 identifies the type of fault and the method by
which the fault is communicated to the microprocessor.
to the 33879 and a 16-bit status word is received from the
33879. The MSB is sent and received first. As Table 1 shows,
the Command Register defines the position and operation the
Table 1. Command Register Definition
MSB
LSB
Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF ON/OFF
Open
Load
Detect
8
Open
Load
Detect
7
Open
Load
Detect
6
Open
Load
Detect
5
Open
Load
Detect
4
Open
Load
Detect
3
Open
Load
Detect
2
Open
Load
Detect
1
OUT 8
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
0 = Bits 0 to 7, Output commanded OFF.
1 = Bits 0 to 7, Output commanded ON.
1 = Bits 8 to 15 Open Load Detection Current ON.
0 = Bits 8 to 15, Open Load Detection Current OFF.
Table 2. Fault Register Definition
MSB
LSB
Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
OUT 8
Status
OUT 7
Status
OUT 6
Status
OUT 5
Status
OUT 4
Status
OUT 3
Status
OUT 2
Status
OUT 1
Status
0 = Bits 0 to 7, No Fault at Output.
1 = Bits 0 to 7, Output Short-to-Battery, Short-to-GND, Open Load,
or T
Bits 8 to 15 will always return “0”.
.
LIM
Table 3. Fault Operation
Serial Output (DO) Pin Reports
Overtemperature
Fault reported by serial output (DO) pin.
DO pin reports short to battery/supply or overcurrent condition.
Not reported.
Overcurrent
Output ON Open Load Fault
Output OFF Open Load Fault
DO pin reports output OFF open load condition only with Open Load Detection Current enabled.
DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled.
Device Shutdowns
Overvoltage
Total device shutdown at V
= 27 V–30 V. Resumes normal operation with proper voltage. All
PWR
outputs assuming the previous state upon recovery from overvoltage.
Overtemperature
Only the output experiencing an overtemperature shuts down. Output assumes previous state upon
recovery from overtemperature.
33879
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DEVICE OPERATION
SPI Integrity Check
Power Supply
The 33879 device has been designed with ultra-low sleep
mode currents. The device may enter sleep mode via the EN
pin or the VDD pin. In the sleep mode (EN or VDD ≤ 0.8 V), the
Checking the integrity of the SPI communication with the
initial power-up of the VDD and EN pins is recommended. After
initial system start-up or reset, the MCU will write one 32-bit
pattern to the 33879. The first 16 bits read by the MCU will be
8 logic [0]s followed by the fault status of the outputs. The
second 16 bits will be the same bit pattern sent by the MCU. By
the MCU receiving the same bit pattern it sent, bus integrity is
confirmed. Please note the second 16-bit pattern the MCU
sends to the device is the command word and will be
transferred to the outputs with rising edge of CS.
current consumed by the VPWR pin is less than 5.0 µA.
Placing the 33879 in sleep mode resets the internal registers
to the Power-ON Reset state. The reset state is defined as all
outputs off and Open Load Detection Current disabled.
To place the 33879 in the sleep mode, either command all
outputs off and apply logic low to the EN input pin or remove
power from the VDD supply pin. Prior to removing VDD from the
Important A SCLK pulse count strategy has been
implemented to ensure integrity of SPI communications. SPI
messages consisting of 16 SCLK pulses and multiples of
8 clock pulses thereafter will be acknowledged. SPI messages
consisting of other than 16 + multiples of 8 SCLK pulses will be
ignored by the device.
device, it is recommended that all control inputs from the MCU
be low.
Paralleling of Outputs
Using MOSFETs as an output switch conveniently allows the
paralleling of outputs for increased current capability. RDS(ON) of
Overtemperature Fault
MOSFETs have an inherent positive temperature coefficient
that provides balanced current sharing between outputs without
destructive operation. This mode of operation may be desirable
in the event the application requires lower power dissipation or
the added capability of switching higher currents. Performance
of parallel operation results in a corresponding decrease in
Overtemperature detection and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system clock or any other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down owing to an overtemperature fault, no other
outputs are affected. The MCU recognizes the fault by a one in
the fault status register. After the 33879 device has cooled
below the switch point temperature and 15°C hysteresis, the
output will activate unless told otherwise by the MCU via SPI to
shut down.
RDS(ON) while the output OFF Open Load Detection Currents
and the output current limits increase correspondingly.
Paralleling outputs from two or more different IC devices is
possible but not recommended.
Fault Logic Operation
Fault logic of the 33879 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs faulted
and Open Load Detection Current enabled, all status bits being
received by the MCU will be zero. When outputs are faulted (off
state open circuit or on state short circuit/overtemperature), the
status bits being received by the MCU will be one. The
distinction between open circuit fault and short/
Overvoltage Fault
An overvoltage condition on the VPWR pin will cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltage
threshold on the VPWR pin is specified as 27 V to 30 V, with
1.0 V typical hysteresis. A VPWR overvoltage detection is global,
causing all outputs to be turned OFF.
overtemperature is completed via the command word. For
example, when a zero command bit is sent and a one fault is
received in the following word, the fault is open/short-to-battery
for high-side drive or open/short-to-ground for low-side drive. In
the same manner, when a one command bit is sent and a one
fault is received in the following word, the fault is a short-to-
ground/overtemperature for high-side drive or short-to-battery/
overtemperature for low-side drive. The timing between two
write words must be greater than 300 µs to allow adequate time
to sense and report the proper fault status.
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting
of an open load when the corresponding output is disabled
(input bit programmed to a logic low state). The Output OFF
Open Load fault is detected by comparing the drain-to-source
voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
33879
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An output OFF open load fault is indicated when the drain-to-
source voltage is less than the output threshold voltage
Output Voltage Clamp
Each output of the 33879 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 45 V for low-side drive configurations and -20 V for
high-side drive configurations. The total energy clamped (EJ)
(VOUT(flt-th)) of 2.5 V to 4.0 V. Hence, the 33879 will declare the
load open in the OFF state when the output drain-to-source
voltage is less than VOUT(flt-th)
.
This device has an internal 80 µA current source connected
from drain to source of the output MOSFET. The current source
may be programmed on or off via SPI. The Power-ON Reset
state for the current source is “off” and must be enabled via SPI.
To achieve low sleep mode quiescent currents, the Open Load
Detection Current source of each driver is switched off when
can be calculated by multiplying the current area under the
current curve (IA) times the clamp voltage (VCL) (see
Figure 16).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.35 A, indicates the maximum energy
per output to be 50 mJ at 150°C junction temperature.
VDD or EN is removed.
During output switching, especially with capacitive loads, a
false output OFF open load fault may be triggered. To prevent
this false fault from being reported, an internal fault filter of
100 µs to 300 µs is incorporated. A false fault reporting is a
function of the load impedance, RDS(ON), COUT of the MOSFET,
Drain-to-Source Clamp
Voltage (V
= 45 V)
Drain Voltage
CL
Drain Current
Clamp Energy
as well as the supply voltage, VPWR. The rising edge of CS
(I = 0.3 A)
(E = I x V )
CL
D
J
A
triggers the built-in fault delay timer. The timer will time out
before the fault comparator is enabled and the fault is detected.
Once the condition causing the open load fault is removed, the
device will resume normal operation. The open load fault,
however, will be latched in the output DO register for the MCU
to read.
Drain-to-Source ON
Voltage (V
)
Current
Area (I
DS(ON)
)
A
Time
GND
Drain-to-Source ON
Voltage (V
)
DS(ON)
BAT
VS
Shorted Load Fault
GND
Time
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or an output
experiencing a current greater than the current limit.
Current
Area (I )
A
Clamp Energy
(E = I x V )
CL
J
A
There are two safety circuits progressively in operation
during load short conditions that provide system protection:
Source Current
1. The device’s output current is monitored in an analog
fashion using SENSEFET approach and current limited.
(I = 0.3 A)
S
Source Clamp Voltage
Source Voltage
(V
= -15 V)
CL
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will remain off until cooled. The device
will then reassert the output automatically. The cycle will
continue until fault is removed or the command bit
instructs the output off. Shorted load faults will be
reported properly through SPI regardless of Open Load
Detection Current enable bits.
Figure 16. Output Voltage Clamping
SPI Configurations
The SPI configuration on the 33879 device is consistent with
other devices in the Octal Serial Switch (OSS) family. This
device may be used in serial SPI or parallel SPI with the 33298
and 33291. Different SPI configurations may be provided. For
more information, contact Motorola Analog Products Division or
local Motorola representative.
Undervoltage Shutdown
An undervoltage condition on VDD or VPWR will result in the
shutdown of all outputs. The VDD undervoltage threshold is
between 0.8 V and 3.0 V. VPWR undervoltage threshold is
Reverse Battery
The 33879 has been designed with reverse battery
protection on the VPWR pin.
between 3.0 V and 5.0 V. When the supplies fall below their
respective thresholds, all outputs are turned OFF. As both
supplies returns to normal levels, internal logic is reset and the
device resumes normal operation.
All outputs consist of a power MOSFET with an integral
substrate diode. During the reverse battery condition, current
will flow through the load via the substrate diode. Under this
circumstance, relays may energize and lamps will turn on.
Where load reverse battery protection is desired, a reverse
battery blocking diode must be placed in series with the load.
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PACKAGE DIMENSIONS
EK (Pb-FREE) SUFFIX
DWB SUFFIX
32-LEAD SOIC WIDE BODY EXPOSED PAD
PLASTIC PACKAGE
CASE 1437-01
ISSUE O
10.3
7.6
7.4
C
B
2.65
2.35
5
9
30X
1
32
0.65
PIN 1 ID
4
11.1
10.9
C
L
NOTES:
9
B
B
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURRS. MOLD FLASH,
PROTRUSION OR GATE BURRS SHALL NOT EXCEED
0.15 mm PER SIDE. THIS DIMENSION IS DETERMINED
AT THE PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
16
17
SEATING
PLANE
A
5.15
2X 16 TIPS
32X
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND
PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER
SIDE. THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4
mm PER SIDE. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD
SHALL NOT LESS THAN 0.07 mm.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.10 mm AND 0.3 mm FROM
THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. THIS DIMENSION IS
0.10
A
0.3
A B C
A
A
(0.29)
BASE METAL
C
C
0.25
0.19
(0.203)
0.38
0.22
PLATING
6
0.3
A B C
M
M
DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
0.13
C A
B
8
5.3
4.7
SECTION A-A
ROTATED 90 CLOCKWISE
°
6.4
R0.08 MIN
0.25
GAUGE PLANE
5.7
°
0
0.1
0.0
0.3
A
B C
MIN
0.9
0.5
°
°
8
0
SECTION B-B
VIEW C-C
33879
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NOTES
33879
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
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provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
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© Motorola, Inc. 2004
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