PPC7457RX867NB [MOTOROLA]
PPC7457RX1000NB;
| 型号： | PPC7457RX867NB |
| 厂家： | 
MOTOROLA |
| 描述： | PPC7457RX1000NB PC |
| 文件： | 总12页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Advance Information
MPC7457RXNXPNS
Rev.2, 10/2003
MPC7457 Part Number
Specification for the
MPC74x7RXnnnnNx Series
Motorola Part
Numbers Affected:
This document describes part-number-specific changes to recommended operating conditions
and revised electrical specifications, as applicable, from those described in the general
MPC7457 RISC Microprocessor Hardware Specifications (Order No. MPC7457EC). The
MPC7457 and MPC7447 are implementations of the PowerPC™ microprocessor family of
reduced instruction set computer (RISC) microprocessors.
PPC7457RX1000NB
PPC7457RX867NB
PPC7457RX733NB
PPC7457RX600NB
PPC7447RX1000NB
PPC7447RX867NB
MC7447RX1000NB
MC7447RX867NB
MC7447RX733NB
MC7447RX600NB
Specifications provided in this document supersede those in the MPC7457 RISC
Microprocessor Hardware Specifications, Rev. 2 or later, for the part numbers listed in
Table A only. This document is primarily concerned with the MPC7457; however, unless
otherwise noted, all information herein also applies to the MPC7447 part numbers listed in
Table A. Specifications not addressed herein are unchanged. Because this document is
frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola
sales office for the latest version.
Note that headings and table numbers in this document are not consecutively numbered. They
are intended to correspond to the heading or table affected in the general hardware
specification.
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Part numbers addressed in this document are listed in Table A.
Table A. Part Numbers Addressed by this Data Sheet
Operating Conditions
Motorola
Part Number
Significant Differences from
Hardware Specification
CPU
Frequency
(MHz)
T
j
(°C)
V
DD
PPC7457RX1000NB
PPC7447RX1000NB
MC7447RX1000NB
PPC7457RX867NB
PPC7447RX867NB
MC7447RX867NB
PPC7457RX733NB
MC7447RX733NB
PPC7457RX600NB
MC7447RX600NB
1000
1.1 V ± 50 mV 0 to 105 Modified core frequency and voltage to reduce
power consumption, modified processor bus AC
timing.
867
733
600
Note: The P prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may
be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the
qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
2
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series MOTOROLA
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Features
1.2 Features
This section summarizes changes to the features of the MPC7457 described in the MPC7457 RISC
Microprocessor Hardware Specifications.
•
Power management
— 1.1-V processor core
1.3 General Parameters
•
Core power supply: 1.1 V ± 50 mV DC nominal
1.5.1 DC Electrical Characteristics
Table 4 provides the recommended operating conditions for the MPC7457 part numbers described herein.
Table 4. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Value
Core supply voltage
PLL supply voltage
V
1.1 V ± 50 mV
1.1 V ± 50 mV
V
V
DD
AV
DD
Note: These are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
3
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General Parameters
Table 7 provides the power consumption for the MPC7457 part numbers described herein.
Table 7. Power Consumption for MPC7457
Processor (CPU) Frequency
Unit
Notes
600 MHz
733 MHz
867 MHz
1000 MHz
Full-Power Mode
Typical
5.3
7.9
6.3
9.1
7.3
8.3
W
W
1, 3
1, 2
Maximum
10.3
11.5
Doze Mode
—
Typical
—
—
—
W
4
Nap Mode
Typical
Typical
1.3
1.2
1.3
1.3
1.2
1.3
1.2
W
W
1, 2
1, 2
Sleep Mode
1.2
Deep Sleep Mode (PLL Disabled)
1.1 1.1
Typical
1.1
1.1
W
1, 3
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power
(OV and GV ) or PLL supply power (AV ). OV and GV power is system dependent, but is typically <5%
DD
DD
DD
DD
DD
of V power. Worst case power consumption for AV < 3 mW.
DD
DD
2. Maximum power is the maximum measured at nominal V and maximum operating junction temperature (see
DD
Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution
units maximally busy.
3. Typical power is an average value measured at the nominal recommended V (see Table 4) and 65°C while
DD
running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep
mode. As a result, power consumption for this mode is not tested.
4
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series MOTOROLA
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General Parameters
Table 8 provides the clock AC timing specifications for the MPC7457 part numbers described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See Table 4.
Maximum Processor Core Frequency
Characteristic
Symbol
600 MHz
733 MHz
867 MHz
1000 MHz
Unit
Notes
Min
500
Max
Min
500
Max
Min
500
Max
Min
Max
1000
Processor frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
Note:
f
600
733
867
500
MHz
MHz
MHz
ns
1
1
core
f
1000 1200 1000 1466 1000 1733 1000 2000
VCO
f
t
33
167
30
33
167
30
33
167
30
33
167
30
SYSCLK
SYSCLK
6.0
6.0
6.0
6.0
1. Caution: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid
PLL_CFG[0:4] settings.
MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
5
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General Parameters
1.5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7457 part numbers described
herein.
1
Table 9. Processor Bus AC Timing Specifications
At recommended operating conditions. See Table 4.
All Speed Grades
2
Parameter
Symbol
Unit
Notes
Min
Max
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
ns
t
2.0
2.0
2.0
—
—
—
AVKH
t
DVKH
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],
BMODE[0:1], BVSEL, L3VSEL
t
IVKH
t
2.0
—
8
8
MVKH
Input hold times:
ns
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1]
BMODE[0:1], BVSEL, L3VSEL
t
0
0
0
—
—
—
AXKH
t
DXKH
t
IXKH
t
0
—
MXKH
Output valid times:
ns
ns
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
t
t
t
—
—
—
2.0
2.0
2.0
KHAV
KHDV
KHOV
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
t
t
t
0.5
0.5
0.5
—
—
—
KHAX
KHDX
KHOX
SYSCLK to output enable
t
0.5
—
—
ns
ns
KHOE
SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)
t
3.5
KHOZ
SYSCLK to TS high impedance after precharge
Maximum delay to ARTRY/SHD0/SHD1 precharge
t
—
—
1
1
t
t
3, 4, 5
KHTSPZ
SYSCLK
t
3, 5,
6, 7
KHARP
SYSCLK
6
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series MOTOROLA
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General Parameters
1
Table 9. Processor Bus AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
All Speed Grades
2
Parameter
Symbol
Unit
Notes
Min
Max
SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge
t
—
2
t
3, 5
6, 7
KHARPZ
SYSCLK
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge
of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the
midpoint of the signal in question. All output timings assume a purely resistive 50-Ω load (see Figure 4 in the
MPC7457 RISC Microprocessor Hardware Specifications). Input and output timings are measured at the pin;
time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t
for inputs and
(signal)(state)(reference)(state)
t
for outputs. For example, t
symbolizes the time input signals (I) reach the valid state
(reference)(state)(signal)(state)
IVKH
(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
symbolizes the
KHOV
time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).
3. t
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by
SYSCLK
the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then
precharged high before returning to high impedance, as shown in Figure 6 in the MPC7457 RISC Microprocessor
Hardware Specifications. The nominal precharge width for TS is 0.5 × t
, that is, less than the minimum
SYSCLK
t
period, to ensure that another master asserting TS on the following clock will not contend with the
SYSCLK
precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge. The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 t
; that is, it should be high impedance, as shown in Figure 6 in the MPC7457 RISC Microprocessor
SYSCLK
Hardware Specifications, before the first opportunity for another master to assert ARTRY. Output valid and output
hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of
TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for
up to an entire cycle (crossing a bus cycle boundary) before being three-stated again.The nominal precharge width
for SHD0 and SHD1 is 1.0 t
. The edges of the precharge vary depending on the programmed ratio of core
SYSCLK
to bus (PLL configurations).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These
parameters represent the input setup and hold times for each sample.These values are guaranteed by design and
not tested. These inputs must remain stable after the second sample. See Figure 5 in the MPC7457 RISC
Microprocessor Hardware Specifications for sample timing.
MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
7
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General Parameters
1.5.2.3 L3 Clock AC Specifications
Devices described by this part number specification conform to the L3 clock AC timing specifications
provided in the MPC7457 RISC Microprocessor Hardware Specifications. Refer to the hardware
specifications for additional information.
1.5.2.4 L3 Bus AC Specifications
Devices described by this part number specification conform to the L3 clock AC timing specifications
provided in the MPC7457 RISC Microprocessor Hardware Specifications. Refer to the hardware
specifications for additional information.
8
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series MOTOROLA
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Ordering Information
1.11 Ordering Information
1.11.1 Part Numbers Addressed by This Specification
Table 22 provides the ordering information for the MPC7457 parts described in this document.
Table 22. Part Marking Nomenclature
xxx
74x7
RX
nnnn
x
x
Product
Code
Part
Identifier
Processor
Frequency
Package
Application Modifier
Revision Level
1
2
PPC
7457
RX = CBGA
1000
867
N: 1.1 V ± 50 mV
B: 1.1: PVR = 8002 0101
0° to 105°C
733
600
7447
7447
1000
867
MC
1000
867
733
600
Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other
specifications may support other maximum core frequencies.
2. The P prefix in a Motorola part number designates a “Pilot Production Prototype” as defined by Motorola SOP
3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes
may be shipped, written authorization from the customer must be on file in the applicable sales office
acknowledging the qualification status and the fact that product changes may still occur while shipping pilot
production prototypes.
MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
9
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Ordering Information
1.11.3 Part Marking
Parts are marked as the example shown in Figure 29.
PPC7457
MC7447
RX1000NB
RX1000NB
MMMMMM
ATWLYYWWA
CCCCC
MMMMMM
ATWLYYWWA
CCCCC
7457
BGA
7447
BGA
Notes:
MMMMMM is the 6-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 29. Motorola Part Marking for BGA Devices
10
MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series MOTOROLA
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Document Revision History
Document Revision History
Table B provides a revision history for this part number specification.
Table B. Document Revision History
Rev. No.
Substantive Change(s)
0
0.1
1
Initial release.
Edited introductory paragraphs to clarify which part numbers are affected by this specification.
Corrected product code in part numbers on page 1 and in Table A.
Updated power consumption specifications in Table 7.
Corrected product code in Section 1.11 and Table 21.
2
Added “MC7447...” part numbers to reflect qualification status.
Table 8: Increased maximum system bus frequency (f
) to 167 MHz.
SYSCLK
Table 9: Corrected numerous errors in lists of pins associated with t
, t
, t
, and t
.
KHOV KHOX IVKH
IXKH
Updated (improved) AC timing parameters based on latest characterization data.
Added 867, 733, and 600 MHz speed grades.
Removed Tables 10, 13, and 14: devices described by this specification conform to the AC timing found
in the MPC7457 hardware specifications.
Corrected typo in Figure 29: 7447 device was incorrectly marked...RX10000NB.
MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series
11
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MPC7457RXNXPNS
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