SC931FAR2 [MOTOROLA]
PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, TQFP-32;
| 型号： | SC931FAR2 |
| 厂家： | 
MOTOROLA |
| 描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, TQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The SC931 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock applications. With output
frequencies of up to 140MHz and output skews of 300ps the SC931 is ideal for the most demanding clock distribution designs.
The device employs a fully differential PLL design to minimize cycle to cycle and long term jitter. This parameter is of significant
importance when the clock driver is providing the reference clock for PLL’s on board todays microprocessors and ASiC’s. The
device offers 6 low skew outputs, and a choice between internal or external feedback. The feedback option adds to the flexibility
of the device, providing numerous input to output frequency relationships.
• Differential LVPECL Reference Input
• Fully Integrated PLL
• Output Shut Down Mode
• Output Frequency up to 140MHz
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
• Compatible with PowerPC and Intel Microprocessors
• 32–Lead TQFP Packaging
• Power Down Mode
• ±100ps Typical Cycle–to–Cycle Jitter
The SC931 offers two power saving features for power conscious portable or “green” designs. The power down pin will
seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life.
The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the
power–down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock
outputs while leaving a subset active to allow for total processor shut down while maintaining system monitors to “wake up” the
system when signaled. During shut down, the PLL will remain locked, if internal feedback is used, so that wake up time will be
minimized. The shut down and power down pins can be combined for the ultimate in power savings. The Shut_Dn pins are
synchronized to the clock internal to the chip to eliminate the possibility of generating runt pulses.
An internal feedback divide by 8 of the VCO frequency is compared with the input reference provided. The internal VCO is
running at 8x the input reference clock. The outputs can be configured to run at 4x, 2x, 1.25x or 0.66x the input reference
frequency. If the external feedback is selected, one of the SC931’s outputs must be connected to the Ext_FB pin. Using the
external feedback, numerous input/output frequency relationships can be developed.
The SC931 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or
LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission lines.
For series terminated applications, each output can drive two 50Ω transmission lines, effectively increasing the fanout to 1:12.
The device is packaged in a 32–lead TQFP package to provide the optimum combination of board density and cost.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
6/98
REV 0
Motorola, Inc. 1998
SC931
FUNCTION TABLES
TCLK_Sel
Reference
0
1
PECL_CLK
TCLK
24
23
22
21
20
19
18
17
PLL_En
PLL Status
GNDO
Qa1
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
GNDO
Qc1
0
1
Test Mode
PLL Enabled
Qa0
Qc0
ExtFB_Sel
Reference
VCCO
Div_Sela
Div_Selb
Div_Selc
NC
VCCO
Ext_FB
Shut_Dn1
Shut_Dn0
NC
0
1
Int. ÷8
Ext_FB
SC931
Power_Dn
PLL Status
0
1
VCO/1
VCO/2
Div_Sela,b,c
Qa
Qb
Qc
1
2
3
4
5
6
7
8
0
1
÷2
÷4
÷2
÷4
÷4
÷6
MR/Tristate
PLL Status
0
1
Disabled
Enabled
Shut_Dn1 Shut_Dn0
Div_Seln
Figure 1. 32–Lead Pinout (Top View)
0
0
1
1
0
1
0
1
Qb & Qc Low, Qa Toggle
Qa & Qb Low, Qc Toggle
Qb Low, Qa & Qc Toggle
All Toggle
(Pullup)
(Pullup)
Power_Dn
PLL_En
(Pulldown)
(Pullup)
TCLK_Sel
TCLK
SC931
(Pullup)
Qa0
PECL_CLK
÷
2/
÷
4
4
PHASE
DETECTOR
VCO
(None)
PECL_CLK
Ext_FB
Qa1
÷2
LPF
(Pullup)
Qb0
Qb1
÷2/
÷
÷8
(Pulldown)
ExtFB_Sel
(Pulldown)
(Pulldown)
Div_Sela
Div_Selb
Qc0
Qc1
÷4/÷6
(Pullup)
Shut_Dn0
Shut_Dn1
Div_Selc
DISABLE
LOGIC
(Pullup)
(Pulldown)
POWER–ON RESET
(Pullup)
MR/Tristate
Figure 2. Logic Diagram
MOTOROLA
2
SC931
VCO
VCO/2
Power_Dn
Qa (
Qb (
Qc (
÷2)
÷4)
÷6)
Figure 3. Power_Dn Timing Diagram
Qa
Qb
Qc
SHUT_DN0
SHUT_DN1
Qa (
Qb (
Qc (
÷2)
÷4)
÷6)
SHUT_DN0
SHUT_DN1
Figure 4. Shut_Dn Timing Diagram
3
MOTOROLA
SC931
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
DD
I
IN
±20
mA
°C
T
Stor
Storage Temperature Range
–40
125
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
PLL INPUT REFERENCE CHARACTERISTICS (T = 0 to 70°C)
A
Symbol
Characteristic
TCLK Input Rise/Falls
Min
Max
3.0
Unit
ns
Condition
t , t
r f
f
Reference Input Frequency
Reference Input Duty Cycle
10
25
Note 1.
75
MHz
%
ref
f
refDC
1. Maximum input reference frequency is limited by the VCO lock range and the feedback divider.
DC CHARACTERISTICS (T = 0° to 70°C, V
= 3.3V ±5%)
CC
A
Symbol
Characteristic
Input HIGH Voltage
Min
Typ
Max
3.6
Unit
V
Condition
V
V
V
V
2.0
IH
Input LOW Voltage
0.8
V
IL
Output HIGH Voltage
Output LOW Voltage
Input Current
2.4
V
I
I
= –20mA (Note 2.)
= 20mA (Note 2.)
OH
OL
OH
0.5
±120
85
V
OL
I
I
I
µA
mA
mA
pF
pF
Note 3.
IN
Maximum Core Supply Current
Maximum PLL Supply Current
65
15
CC
20
CCPLL
C
C
4
IN
25
Per Output
pd
2. The SC931 outputs can drive series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines on the incident edge (see Applications Info
CC
section).
3. Inputs have pull–up/pull–down resistors which affect input current.
MOTOROLA
4
SC931
SC931 AC CHARACTERISTICS (T = 0° to 70°C, V
= 3.3V ±5%)
Min
A
CC
Symbol
Characteristic
Crystal Oscillator Frequency Range
Input Reference Frequency
Typ
Max
20
Unit
MHz
MHz
ps
Condition
f
f
t
10
Note NO TAG, Note 6.
Ref = TCLK
xtal
Note 6.
Note 6.
ref
os
Output–to–Output Skew
(Note 4.)
Same Frequency
Diff Frequency
Same Frequency
Diff Frequency
200
300
300
450
300
400
400
600
f
f
f
f
≤ 100MHz
≤ 100MHz
> 100MHz
> 100MHz
max
max
max
max
f
f
VCO Lock Range
Power_Dn = 0
100
280
MHz
MHz
VCO
Maximum Output Frequency
Qa, Qb (÷2)
Qa, Qb, Qc (÷4)
Qc (÷6)
140
80
47
Note 4.
max
t
t
TCLK to EXT_FB Delay
–600
–100
400
ps
ps
f
= 50MHz, FB = ÷4
pd
ref
Output Duty Cycle (Note 4.)
t
/2
t
/2
t
/2
pw
CYCLE
–750
CYCLE
±500
CYCLE
+750
t , t
r f
Output Rise/Fall Time (Note 4.)
Output Disable Time
0.1
2.0
2.0
1.0
8.0
10
ns
ns
ns
ps
ms
0.8 to 2.0V
50Ω to V /2
t
t
t
t
, t
PLZ PHZ
CC
Output Enable Time
50Ω to V /2
PZL
jitter
lock
CC
Cycle–to–Cycle Jitter (Peak–to–Peak)
Maximum PLL Lock Time
±100
Note 5.
10
4. Measured with 50Ω to V /2 termination.
CC
5. See Applications Info section for more jitter information.
6. Input reference frequency is bounded by VCO lock range and feedback divide selection.
5
MOTOROLA
SC931
APPLICATIONS INFORMATION
Programming the SC931
The relationship between the input reference and the
output frequency is also very flexible. Table 2 shows the
multiplication factors between the inputs and outputs when
the internal feedback option is used. For external feedback
Table 1 can be used to determine the multiplication factor,
there are too many potential combinations to tabularize the
external feedback condition. Figure 5 and Figure 6 illustrate
some programming possibilities, although not exhaustive it is
representative of the potential applications.
The SC931 clock driver outputs can be configured into
several frequency relationships, in addition the external
feedback option allows for a great deal of flexibility in
establishing unique input to output frequency relationships.
The output dividers for the three output groups allows the
user to configure the outputs into 1:1, 2:1, 3:1, 3:2 and 3:2:1
frequency ratios. The use of even dividers ensures that the
output duty cycle is always 50%. Table 1 illustrates the
various output configurations, the table describes the outputs
using the VCO frequency as a reference. As an example for a
3:2:1 relationship the Qa outputs would be set at VCO/2, the
Qb’s at VCO/4 and the Qc’s at VCO/6. These settings will
provide output frequencies with a 3:2:1 relationship.
The division settings establish the output relationship, but
one must still ensure that the VCO will be stable given the
frequency of the outputs desired. The VCO lock range can be
found in the specification tables. The feedback frequency
and the Power_Dn pin can be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL is such that for output frequencies between 25 and
140MHz the SC931 can generally be configured into a stable
region.
Table 1. Programmable Output Frequency Relationships
(Power_Dn = ‘0’)
INPUTS
OUTPUTS
Qb
Div_Sela Div_Selb Div_Selc
Qa
Qc
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/2 VCO/2 VCO/4
VCO/2 VCO/2 VCO/6
VCO/2 VCO/4 VCO/4
VCO/2 VCO/4 VCO/6
VCO/4 VCO/2 VCO/4
VCO/4 VCO/2 VCO/6
VCO/4 VCO/4 VCO/4
VCO/4 VCO/4 VCO/6
Table 2. Input Reference/Output Frequency Relationships (Internal Feedback Only)
INPUTS
OUTPUTS
Qb
Qa
Qc
Div_Sela
Div_Selb
Div_Selc
Power_Dn=0 Power_Dn=1 Power_Dn=0 Power_Dn=1 Power_Dn=0 Power_Dn=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4x
4x
4x
4x
2x
2x
2x
2x
2x
2x
2x
2x
x
x
x
x
4x
4x
2x
2x
4x
4x
2x
2x
2x
2x
x
2x
4/3x
2x
4/3x
2x
4/3x
2x
4/3x
x
2/3x
x
2/3x
x
2/3x
x
2/3x
x
2x
2x
x
x
SC931
SC931
2
2
2
2
‘0’
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
‘1’
‘1’
‘0’
‘0’
Div_Sela
Div_Selb
Div_Selc
Qa
Qb
Qc
66.66MHz (Processor)
Qa
Qb
Qc
33.33MHz
33.33MHz
33.33MHz
‘1’
‘0’
‘0’
33.33MHz (PCI)
33.33MHz (PCI)
ExtFB_Sel
2
2
16.66MHz
Input Ref
16.66MHz
Input Ref
Figure 5. Dual Frequency Configuration
Figure 6. Single Frequency Configuration
MOTOROLA
6
SC931
OUTLINE DIMENSIONS
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
MIN MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
DIM
A
A1
B
B1
C
D
E
F
G
H
J
SECTION AE–AE
E
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
0.300
1.350
0.300
0.012
0.053
0.012
W
0.800 BSC
0.031 BSC
Q
H
K
X
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
K
M
N
P
12 REF
12 REF
DETAIL AD
0.090
0.160
0.004
0.006
0.400 BSC
0.016 BSC
Q
R
1
5
1
5
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
V1
W
X
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
7
MOTOROLA
SC931
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
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