SCM6341ZP12A [MOTOROLA]
128K x 24 Bit Static Random Access Memory; 128K ×24位的静态随机存取存储器
| 型号： | SCM6341ZP12A |
| 厂家： | 
MOTOROLA |
| 描述： | 128K x 24 Bit Static Random Access Memory |
| 文件： | 总10页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MCM6341/D
SEMICONDUCTOR TECHNICAL DATA
MCM6341
Advance Information
128K x 24 Bit Static Random
Access Memory
The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable
(G) pins, allowing for greater system flexibility and eliminating bus contention
problems.
ZP PACKAGE
PBGA
CASE 999–02
The MCM6341 is available in a 119–bump PBGA package.
PIN NAMES
•
•
•
•
•
•
•
Single 3.3 V ± 10% Power Supply
A . . . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2, E3 . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . . . . No Connection
Fast Access Time: 10/11/12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 280/275/270/260 mA Maximum, Active AC
Commercial Temperature (0°C to 70°C) and
Industrial Temperature (– 40°C to + 85°C) Options
V
DD
V
SS
. . . . . . . . . . . . . + 3.3 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . . . Ground
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
COLUMN I/O
COLUMN DECODER
DQ
DQ
INPUT
DATA
CONTROL
A
A
A
A
A
A
A
A
DQ
DQ
E1
E2
E3
W
G
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
2/18/98
Motorola, Inc. 1998
PIN ASSIGNMENT
1
2
3
4
5
6
7
A
B
C
D
E
NC
NC
DQ
DQ
DQ
DQ
DQ
DQ
A
A
A
A
A
A
A
A
NC
E1
NC
A
NC
DQ
DQ
DQ
DQ
DQ
DQ
NC
E2
E3
NC
V
V
V
V
V
DD
DD
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
SS
DD
DD
SS
F
V
V
V
V
DD
SS
SS
DD
G
V
V
V
V
SS
DD
DD
SS
H
V
V
V
V
V
DD
SS
SS
SS
SS
DD
J
K
L
V
V
V
V
V
V
V
DD
SS
DD
DD
SS
DD
DQ
V
V
V
V
V
V
V
V
V
DQ
DD
SS
SS
SS
SS
SS
SS
SS
DD
DQ
DQ
DQ
DQ
V
V
V
V
DQ
DQ
DQ
DQ
SS
DD
DD
SS
M
N
P
V
V
V
V
DD
SS
SS
DD
V
V
V
V
SS
DD
DD
SS
V
V
V
V
DD
SS
SS
DD
R
T
DQ
NC
A
NC
A
NC
W
NC
A
NC
A
DQ
NC
NC
NC
NC
U
A
A
G
A
A
119–BUMP PBGA
TOP VIEW
MCM6341
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1
H
X
X
L
E2
X
E3
X
X
H
L
G
X
X
X
H
L
W
X
X
X
H
H
L
Mode
Not Selected
Not Selected
Not Selected
Output Disabled
Read
I/O Pin
High–Z
High–Z
High–Z
High–Z
Cycle
—
Current
, I
I
I
I
SB1 SB2
L
—
, I
SB1 SB2
X
—
, I
SB1 SB2
H
H
H
—
I
I
I
DDA
DDA
DDA
L
L
D
Read
Write
out
L
L
X
Write
High–Z
ABSOLUTE MAXIMUM RATINGS (See Note)
This device contains circuitry to protect the
Rating
Symbol
Value
– 0.5 to + 5.0
– 0.5 to V + 0.5
Unit
V
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid ap-
plication of any voltage higher than maximum
ratedvoltagestothesehigh–impedancecircuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
Power Supply Voltage Relative to V
V
DD
SS
Voltage Relative to V
for Any Pin
V , V
in out
V
SS
DD
Except V
DD
Output Current (per I/O)
I
mA
± 20
out
Power Dissipation
P
D
1.0
W
Temperature Under Bias
Commercial
Industrial
T
bias
– 10 to + 85
– 45 to + 90
°C
Storage Temperature — Plastic
T
stg
– 55 to + 150
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM6341
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
(T = – 40 to + 85°C for Industrial Temperature Offering)
A
A
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
Supply Voltage (Operating Voltage Range)
Input High Voltage
V
DD
3.6
V
IH
2.2
V
+ 0.3**
V
DD
Input Low Voltage
V
IL
—
0.8
V
– 0.5*
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 2.0 ns).
IH IH
DD
DD
DC CHARACTERISTICS (See Note)
Parameter
Input Leakage Current (All Inputs, V = 0 to V
Symbol
Min
—
Max
± 1.0
± 1.0
0.4
Unit
µA
µA
V
)
I
lkg(I)
in
DD
= 0 to V
Output Leakage Current (E = V , V
)
I
lkg(O)
—
IH out
DD
Output Low Voltage (I
= + 8.0 mA)
V
OL
—
OL
Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
—
V
OH
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
POWER SUPPLY CURRENTS (See Note)
– 40 to
+ 85°C
Parameter
Symbol
0 to 70°C
Unit
AC Active Supply Current
(I = 0 mA, V = max)
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
I
280
275
270
260
290
285
280
270
mA
DD
out
DD
AC Standby Current (V
DD
= max, E = V
No other restrictions on other inputs)
,
MCM6341–10
MCM6341–11
MCM6341–12
MCM6341–15
I
50
50
50
45
55
55
55
50
mA
mA
IH
SB1
CMOS Standby Current (E ≥ V
– 0.2 V, V ≤ V
in
+ 0.2 V or ≥ V – 0.2 V)
DD
I
20
20
DD
SS
SB2
(V
DD
= max, f = 0 MHz)
NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
C
4
5
6
8
pF
in
C
ck
Input/Output Capacitance
DQ
C
5
8
pF
I/O
MCM6341
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 3.3 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
DD
(T = – 40 to + 85°C for Industrial Temperature Offering)
A
A
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Parameter
Read Cycle Time
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Min
10
—
—
—
3
Max
—
10
10
5
Min
11
—
—
—
3
Max
—
11
11
6
Min
12
—
—
—
3
Max
—
12
12
6
Min
15
—
—
—
3
Max
—
15
15
7
t
4
AVAV
Address Access Time
t
AVQV
Enable Access Time
t
5
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Output Enable Low to Output Active
Enable High to Output High–Z
Output Enable High to Output High–Z
t
t
—
—
—
5
—
—
—
6
—
—
—
6
—
—
—
7
t
3
3
3
3
6, 7, 8
6, 7, 8
6, 7, 8
6, 7, 8
ELQX
GLQX
EHQZ
GHQZ
t
t
0
0
0
0
0
0
0
0
t
0
5
0
6
0
6
0
7
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, t
to device.
max
t
min, and t
max
t min, both for a given device and from device
GLQX
EHQZ
ELQX
GHQZ
7. Transition is measured ± 200 mV from steady–state voltage.
8. This parameter is sampled and not 100% tested.
9. Device is continuously selected (E ≤ V , G ≤ V ).
IL
IL
R
= 50 Ω
L
OUTPUT
Z
= 50 Ω
0
V
= 1.5 V
L
Figure 1. AC Test Load
MCM6341
5
MOTOROLA FAST SRAM
READ CYCLE 1 (See Note 9)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
READ CYCLE 2 (See Notes 3 and 5)
t
AVAV
A (ADDRESS)
t
ELQV
E (CHIP ENABLE)
t
t
t
t
EHQZ
ELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
t
GLQV
GHQZ
t
GLQX
HIGH–Z
DATA VALID
AVQV
I
DD
SUPPLY CURRENT
I
SB
MCM6341
MOTOROLA FAST SRAM
6
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
11
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
5
AVAV
Address Setup Time
t
—
—
—
—
ns
AVWL
Address Valid to End of Write
t
9
—
10
9
—
10
9
—
12
10
—
ns
AVWH
AVWH
Address Valid to End of Write (G
High)
t
8
—
—
—
—
ns
Write Pulse Width
t
t
9
8
—
—
10
9
—
—
10
9
—
—
12
10
—
—
ns
ns
WLWH
WLEH
t
Write Pulse Width (G High)
WLWH
t
WLEH
DVWH
WHDX
Data Valid to End of Write
Data Hold Time
t
t
4
0
0
3
0
—
—
5
5
0
0
3
0
—
—
6
5
0
0
3
0
—
—
6
6
0
0
3
0
—
—
7
ns
ns
ns
ns
ns
Write Low to Data High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
6, 7, 8
6, 7, 8
WLQZ
t
—
—
—
—
—
—
—
—
WHQX
t
WHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured ± 200 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. At any given voltage and temperature, t
max < t
min both for a given device and from device to device.
WHQX
WLQZ
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLWH
t
WLEH
W (WRITE ENABLE)
D (DATA IN)
t
t
t
WHDX
AVWL
DVWH
DATA VALID
t
t
WLQZ
WHQX
HIGH–Z
HIGH–Z
Q (DATA OUT)
MCM6341
MOTOROLA FAST SRAM
7
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15
Parameter
Write Cycle Time
Symbol
Unit
ns
Notes
Min
10
0
Max
—
Min
11
0
Max
—
Min
12
0
Max
—
Min
15
0
Max
—
t
5
AVAV
Address Setup Time
t
—
—
—
—
ns
AVEL
Address Valid to End of Write
t
9
—
10
9
—
10
9
—
12
10
—
ns
AVEH
AVEH
Address Valid to End of Write (G
High)
t
8
—
—
—
—
ns
Enable Pulse Width
t
t
9
8
—
—
10
9
—
—
10
9
—
—
12
10
—
—
ns
ns
6, 7
6, 7
ELEH,
ELWH
Enable Pulse Width (G High)
t
t
ELEH,
ELWH
Data Valid to End of Write
Data Hold Time
t
4
0
0
—
—
—
5
0
0
—
—
—
5
0
0
—
—
—
6
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
t
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If E goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
7. If E goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)
t
AVAV
A (ADDRESS)
t
AVEH
t
ELEH
E (CHIP ENABLE)
t
t
t
EHAX
AVEL
ELWH
W (WRITE ENABLE)
D (DATA IN)
t
DVEH
DATA VALID
t
EHDX
HIGH–Z
Q (DATA OUT)
MCM6341
MOTOROLA FAST SRAM
8
ORDERING INFORMATION
(Order by Full Part Number)
xCM 6341 XX XX XX
Motorola Memory Prefix
Part Number
Shipping Method (PBGA Standard)
Speed (10 = 10 ns, 11 = 11 ns, 12 = 12 ns,
15 = 15 ns)
Package (ZP = PBGA)
Full Commercial Part Numbers — MCM6341ZP10
MCM6341ZP11
Full Industrial Temperature Part Numbers — SCM6341ZP10A
SCM6341ZP12A
SCM6341ZP15A
MCM6341ZP12
MCM6341ZP15
PACKAGE DIMENSIONS
ZP PACKAGE
119–PBGA
CASE 999–02
0.20
4X
119X
b
B
D
M
0.3
A
A
B C
E
C
M
0.15
7
6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. ALL DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
D1
D2
K
L
M
N
P
R
T
16X e
MILLIMETERS
U
DIM
A
A1
A2
A3
D
D1
D2
E
E1
E2
b
MIN
–––
0.50
1.30
0.80
22.00 BSC
20.32 BSC
19.40 19.60
14.00 BSC
7.62 BSC
MAX
2.40
0.70
1.70
1.00
6X
e
E2
E1
BOTTOM VIEW
TOP VIEW
0.25
A
A
A3
A2
0.35
11.90
0.60
1.27 BSC
12.10
0.90
0.20
A
e
A
SEATING
PLANE
SIDE VIEW
A1
A
MCM6341
9
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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