SN54LS194A [MOTOROLA]
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER; 4位双向通用移位寄存器
| 型号： | SN54LS194A |
| 厂家： | 
MOTOROLA |
| 描述： | 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER |
| 文件： | 总6页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS194A
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The SN54/74LS194A is a High Speed 4-Bit Bidirectional Universal Shift
Register. As a high speed multifunctional sequential building block, it is useful
in a wide variety of applications. It may be used in serial-serial, shift left, shift
right, serial-parallel, parallel-serial, and parallel-parallel data register trans-
fers. The LS194A is similar in operation to the LS195A Universal Shift
Register, with added features of shift left without external connections and
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped
process to achieve high speeds and is fully compatible with all Motorola TTL
families.
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY
• Typical Shift Frequency of 36 MHz
• Asynchronous Master Reset
J SUFFIX
CERAMIC
CASE 620-09
• Hold (Do Nothing) Mode
• Fully Synchronous Serial or Parallel Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
16
1
N SUFFIX
PLASTIC
CONNECTION DIAGRAM DIP (TOP VIEW)
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
PIN NAMES
LOADING (Note a)
HIGH
LOW
S , S
Mode Control Inputs
Parallel Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
0
1
3
P –P
0
D
D
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
SR
SL
CP
MR
Q –Q
0
3
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-360
SN54/74LS194A
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS194A 4-Bit Bidirectional Shift Regis-
ter. The LS194A is similar in operation to the Motorola LS195A
Universal Shift Register when used in serial or parallel data
register transfers. Some of the common features of the two
devices are described below:
Q
outputs respectively following the next LOW to HIGH
3
transition of the clock.
The asynchronous Master Reset (MR), when LOW, over-
rides all other input conditions and forces the Q outputs LOW.
Special logic features of the LS194A design which increase
the range of application are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations taking
place in less than 15 ns (typical) making the device especially
usefulfor implementing very high speed CPUs, or the memory
buffer registers.
Two mode control inputs (S , S ) determine the synchro-
nous operation of the device. As shown in the Mode Selection
Table, data can be entered and shifted from left to right (shift
0 1
right, Q º Q , etc.) or right to left (shift left, Q º Q , etc.), or
0
1
3
2
parallel data can be entered loading all four bits of the register
simultaneously. When both S and S ,are LOW, the existing
0
1
data is retained in a “do nothing” mode without restricting the
HIGH to LOW clock transition.
D-type serial data inputs (D , D ) are provided on both
SR SL
The four parallel data inputs (P , P , P , P ) are D-type
thefirstandlaststagestoallowmultistageshiftrightorshiftleft
data transfers without interfering with parallel load operation.
0
1
2
3
inputs. When both S and S are HIGH, the data appearing on
0
1
P , P , P , and P inputs is transferred to the Q , Q , Q , and
0
1
2
3
0
1
2
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
L
S
S
0
D
D
P
n
Q
Q
Q
Q
1
SR
SL
0
1
2
3
Reset
X
X
X
X
X
X
L
L
L
L
Hold
H
I
I
X
X
q
0
q
1
q
2
q
3
Shift Left
H
H
h
h
I
I
X
X
I
h
X
X
q
1
q
1
q
2
q
2
q
3
q
3
L
H
Shift Right
H
H
I
I
h
h
I
h
X
X
X
X
L
H
q
0
q
0
q
1
q
1
q
q
2
2
Parallel Load
H
h
h
X
X
P
n
P
0
P
1
P
2
P
3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
p
(q ) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
n
n
FAST AND LS TTL DATA
5-361
SN54/74LS194A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
OL
20
0.1
µA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–100
23
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–20
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Clock Frequency
25
36
MHz
MAX
t
t
Propagation Delay,
Clock to Output
14
17
22
26
PLH
PHL
V
C
= 5.0 V
ns
ns
CC
= 15 pF
L
Propagation Delay,
MR to Output
t
19
30
PHL
FAST AND LS TTL DATA
5-362
SN54/74LS194A
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Symbol
Parameter
Clock or MR Pulse Width
Mode Control Setup Time
Data Setup Time
Unit
ns
Test Conditions
Min
20
30
20
0
Typ
Max
t
t
t
t
t
W
ns
s
ns
V
CC
= 5.0 V
s
Hold time, Any Input
Recovery Time
ns
h
25
ns
rec
DEFINITIONS OF TERMS
SETUP TIME(t ) —is defined as the minimum time required
s
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
RECOVERY TIME (t ) — is defined as the minimum time
rec
HOLD TIME (t ) — is defined as the minimum time following
h
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
required between the end of the reset pulse and the clock
transitionfromLOWtoHIGHinordertorecognizeandtransfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width and f
max
Figure 3. Setup (t ) and Hold (t ) Time for Serial Data
s
h
(D , D ) and Parallel Data (P , P , P , P )
SR SL
0
1
2
3
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
Figure 4. Setup (t ) and Hold (t ) Time for S Input
s
h
FAST AND LS TTL DATA
5-363
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-364
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