SN54LS293J [MOTOROLA]
DECADE COUNTER; 4-BIT BINARY COUNTER; 十进制计数器; 4位二进制计数器
| 型号： | SN54LS293J |
| 厂家： | 
MOTOROLA |
| 描述： | DECADE COUNTER; 4-BIT BINARY COUNTER |
| 文件： | 总7页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS290
SN54/74LS293
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit ripple type
counters partitioned into two sections. Each counter has a divide-by-two sec-
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP)to form BCD,
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
• Corner Power Pin Versions of the LS90 and LS93
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
• Input Clamp Diodes Limit High Speed Termination Effects
J SUFFIX
CERAMIC
CASE 632-08
14
1
CONNECTION DIAGRAM DIP (TOP VIEW)
N SUFFIX
PLASTIC
CASE 646-06
14
NOTE:
1
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
LS290
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LS293
PIN NAMES
LOADING (Note a)
HIGH
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
CP
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Clock (Active LOW going edge) Input to ÷2 Section.
Clock (Active LOW going edge) Input to ÷5 Section (LS290).
Clock (Active LOW going edge) Input to ÷8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from ÷2 Section (Notes b & c)
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0
Q1, Q2, Q3
Outputs from ÷5 & ÷8 Sections (Note b)
10 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q Outputs are guaranteed to drive the full fan-out plus the CP Input of the device.
0
1
FAST AND LS TTL DATA
5-466
SN54/74LS290 SN54/74LS293
LOGIC SYMBOL
LS290
LS293
LOGIC DIAGRAMS
LS290
LS293
FAST AND LS TTL DATA
5-467
SN54/74LS290 SN54/74LS293
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
externally connected to the Q output. The CP input
0 0
receives the incoming count and a BCD count sequence is
produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q
3
output must be externally connected to the CP input. The
0
input count is then applied to the CP input and a
1
divide-by-ten square wave is obtained at output Q .
0
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnectionsare required. The first flip-flop is used as a
binary element for the divide-by-two function (CP as the
0
or strobes. The Q output of each device is designed and
inputand Q astheoutput). TheCP inputisusedtoobtain
0
0 1
specified to drive the rated fan-out plus the CP input of the
binary divide-by-five operation at the Q output.
3
1
device.
A gated AND asynchronous Master Reset (MR MR ) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
1
2
LS293
A. 4-Bit Ripple Counter — The output Q must be externally
0
connected to input CP . The input count pulses are applied
1
Master Set (MS
MS ) is provided on the LS290 which
1
2
to input CP . Simultaneous division of 2, 4, 8, and 16 are
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
0
performed at the Q , Q , Q , and Q outputs as shown in
the truth table.
0
1
2
3
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP . Simultaneous frequency divisions of 2, 4, and
8 are available at the Q , Q and Q outputs. Independent
use of the first flip-flop is available if the reset function
coincides with reset of the 3-bit ripple-through counter.
1
1
2,
3
LS290
A. BCD Decade (8421) Counter — the CP input must be
1
LS290 MODE SELECTION
LS293 MODE SELECTION
RESET/SET INPUTS
OUTPUTS
RESET INPUTS
OUTPUTS
MR
MR
MS
MS
Q
Q
Q
Q
MR
MR
Q
Q
Q
Q
3
1
2
1
2
0
1
2
3
1
2
0
1
2
H
H
X
L
X
L
H
H
X
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
L
L
L
L
Count
Count
Count
Count
L
Count
Count
Count
X
L
L
X
X
TRUTH TABLE
OUTPUT
LS290
COUNT
BCD COUNT SEQUENCE
Q
Q
Q
Q
3
0
1
2
OUTPUT
0
1
2
3
4
5
6
7
8
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
COUNT
L
H
H
L
Q
Q
Q
Q
3
L
0
1
2
0
1
2
3
4
5
6
7
8
9
L
H
L
H
L
H
L
H
L
H
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
9
L
10
11
12
13
14
15
H
H
L
L
H
H
L
L
NOTE: Output Q is connected to Input CP
0
1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
H
Note: Output Q connected to input CP .
0
1
FAST AND LS TTL DATA
5-468
SN54/74LS290 • SN54/74LS293
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
OL
20
µA
V
V
= MAX, V = 2.7 V
IN
CC
I
IH
0.1
mA
= MAX, V = 7.0 V
IN
CC
Input LOW Current
MS, MR
–0.4
–2.4
–3.2
–1.6
I
IL
CP
mA
V
CC
= MAX, V = 0.4 V
IN
0
CP (LS290)
1
CP (LS293)
1
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
15
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-469
SN54/74LS290 SN54/74LS293
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V, C = 15 pF)
L
A
Limits
LS290
Typ
LS293
Typ
Symbol
Parameter
CP Input Clock Frequency
Unit
MHz
MHz
Min
Max
Min
Max
f
f
32
16
32
16
MAX
0
CP Input Clock Frequency
1
MAX
t
t
Propagation Delay,
10
12
16
18
10
12
16
18
PLH
PHL
ns
ns
ns
ns
ns
CP Input to Q Output
0
0
t
t
32
34
48
50
46
46
70
70
PLH
PHL
CP Input to Q Output
0
3
t
t
10
14
16
21
10
14
16
21
PLH
PHL
CP Input to Q Output
1
1
t
t
21
23
32
35
21
23
32
35
PLH
PHL
CP Input to Q Output
1
2
t
t
21
23
32
35
34
34
51
51
PLH
PHL
CP Input to Q Output
1
3
t
t
t
MS Input to Q and Q Outputs
20
26
26
30
40
40
ns
ns
ns
PHL
PHL
PHL
0
3
MS Input to Q and Q Outputs
1
2
MR Input to Any Output
26
40
AC SETUP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
LS290
LS293
Symbol
Parameter
Unit
ns
Min
15
30
15
15
25
Max
Min
15
Max
t
t
t
t
t
CP
CP
W
W
W
W
rec
0 Pulse Width
30
ns
1 Pulse Width
MS Pulse Width
ns
MR Pulse Width
15
25
ns
Recovery Time MR to CP
ns
RECOVERY TIME (t ) is defined as the minimum time required between the end of the reset pulse and the clock transition form HIGH-to-LOW in order to
rec
recognize and transfer HIGH data to the Q outputs.
AC WAVEFORMS
Figure 1
PLH
*The number of Clock Pulses required between the t
and t
measurements can be determined from the appropriate Truth Tables.
PHL
Figure 2
Figure 3
FAST AND LS TTL DATA
5-470
Case 751A-02 D Suffix
14-Pin Plastic
SO-14
-A-
14
1
8
7
P
C
-B-
R X 45°
G
K
J
M
F
D
°
°
°
°
Case 632-08 J Suffix
14-Pin Ceramic Dual In-Line
-A-
14
1
8
7
-B-
C
L
-T-
K
M
F
G
N
J
D
°
°
°
°
Case 646-06 N Suffix
14-Pin Plastic
14
1
8
B
7
A
F
L
C
J
N
K
G
H
D
M
°
°
°
°
FAST AND LS TTL DATA
5-471
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◊
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