SN54LS395J [MOTOROLA]
Parallel In Parallel Out, LS Series, 4-Bit, Right Direction, True Output, TTL, CDIP16, CERAMIC, DIP-16;
| 型号： | SN54LS395J |
| 厂家： | 
MOTOROLA |
| 描述： | Parallel In Parallel Out, LS Series, 4-Bit, Right Direction, True Output, TTL, CDIP16, CERAMIC, DIP-16 移位寄存器 输出元件 |
| 文件： | 总6页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LS395
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate
in either a synchronous parallel load or a serial shift-right mode, as
determined by the Select input. An asynchronous active LOW Master Reset
(MR) input overrides the synchronous operations and clears the register. An
active HIGH Output Enable (OE) input controls the 3-state output buffers, but
does not interfere with the other operations. The fourth stage also has a
conventional output for linking purposes in multi-stage serial operations.
4-BIT SHIFT REGISTER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
• Shift Left or Parallel 4-Bit Register
• 3-State Outputs
• Input Clamp Diodes Limit High-Speed Termination Effects
J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW)
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
16
1
PIN NAMES
LOADING (Note a)
HIGH
LOW
ORDERING INFORMATION
P –P
0
Parallel Inputs
Serial Data Input
Mode Select Input
Clock (Active LOW) Input
Master Reset (Active LOW) Input
Output Enable (Active HIGH) Input
3-State Register Outputs
Register Output
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
3
D
SN74LSXXXJ
Ceramic
S
S
SN74LSXXXN Plastic
SN74LSXXXD SOIC
CP
MR
OE
O –O
0
3
3
5 U.L.
Q
LOGIC SYMBOL
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
FAST AND LS TTL DATA
5-551
SN74LS395
LOGIC DIAGRAM
FUNCTION DESCRIPTION
The SN74LS395 contains four D-type edge-triggered
flip-flops and auxiliary gating to select a D input either from a
S input is LOW, a CP HIGH-LOW transition transfers data in
Q to Q , Q to Q , and Q to Q . A left-shift is accomplished
by connecting the outputs back to the P inputs, but offset one
n
place to the left, i.e., O to P , O to P and O to P , with P
3 2 2 1 1 0 3
0
1
1
2
2
3
Parallel (P ) input or from the preceding stage. When the
n
Select input is HIGH, the P inputs are enabled. A LOW signal
n
on the S input enables the serial inputs for shift-right opera-
tions, as indicated in the Truth Table.
acting as the linking input from another package.
When the OE input is HIGH, the output buffers are disabled
and the Q –Q outputs are in a high impedance condition.
State changes are initiated by HIGH-to-LOW transitions on
0
3
the Clock Pulse (CP) input. Signals on the P , D and S inputs
Theshifting, parallelloadingorresettingoperationscanstillbe
accomplished, however.
n
s
can change when the Clock is in either state, provided that the
recommended set-up and hold times are observed. When the
MODE SELECT — TRUTH TABLE
Inputs @ t
Outputs @ t
n+1
n
Operating Mode
Asynchronous Reset
MR
CP
S
D
P
O
O
O
O
3
s
n
0
1
2
L
H
X
X
L
X
H
X
X
L
H
L
L
L
Shift, SET First Stage
O
O
O
0n
1n
2n
Shift, RESET First Stage
Parallel Load
H
H
L
H
L
X
X
L
O
P
O
P
O
P
3
0n
1
1n
2
2n
P
n
P
0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
t ,
= time before and after CP HIGH-to-LOW transition
n n + 1
NOTE:
When OE is HIGH, outputs O –O are in the high impedance state; however, this does not affect other operations or the Q output.
0
3
3
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
Supply Voltage
T
Operating Ambient Temperature Range
Output Current — High
°C
A
I
I
–0.4
8.0
mA
mA
OH
Output Current — Low
OL
FAST AND LS TTL DATA
5-552
SN74LS395
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
0.8
V
V
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
= MIN, I = –18 mA
IN
IK
CC
= MIN, I
OH
= MAX, V = V
IN
CC
IH
2.7
OH
or V per Truth Table
IL
V
V
= V
CC
MIN,
= V or V
IL IH
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
OL
V
OL
Output LOW Voltage
per Truth Table
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.4 V
O
OZH
= MAX, V = 0.4 V
OZL
O
µA
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
–0.1
–0.4
–100
mA
mA
mA
= MAX, V = 7.0 V
IN
I
I
Input LOW Current
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
–20
= MAX
OS
Power Supply Current
Total, Output HIGH
mA
mA
V
= MAX, OE = GND, CP = GND
CC
31
34
I
CC
V
CC
= MAX, OE = 4.5 V, CP
Total, Output LOW
momentary 3.0 V then GND
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
45
Symbol
Parameter
Unit
MHz
ns
Test Conditions
Min
Max
f
t
Maximum Input Clock Frequency
Propagation Delay, Clear to Output
30
MAX
22
35
PHL
V
C
= 5.0 V
= 15 pF
CC
L
t
t
Propagation Delay, Low to High
Propagation Delay, High to Low
15
25
30
30
PLH
PHL
ns
ns
ns
t
t
15
17
25
25
PZH
PZL
Output Enable Time
Output Disable Time
t
t
12
11
20
17
PLZ
PHZ
C
= 5.0 pF
L
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock Pulse Width
Unit
ns
Test Conditions
Min
16
Max
t
t
t
t
W
Setup Time, Mode Select
Setup Time, All Others
Data Hold Time
40
ns
s
V
CC
= 5.0 V
20
ns
s
10
ns
h
FAST AND LS TTL DATA
5-553
SN74LS395
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
LOAD SERIAL DATA
SHIFT RIGHT
LOAD PARALLEL DATA
*The Data Input is D for S = LOW and P for S = HIGH.
S
n
Figure 1
Figure 2
≥
≈
≈
Figure 4
Figure 3
AC LOAD CIRCUIT
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
Closed
Open
t
PZH
t
Closed
Closed
Closed
PZL
PLZ
PHZ
t
Closed
Closed
t
Ω
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-554
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-555
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相关型号：
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LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP20, CERAMIC, DIP-20
MOTOROLA
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