SN54LS90J [MOTOROLA]
DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER; 十进制计数器;除以十二个月的计数器; 4位二进制计数器
| 型号： | SN54LS90J |
| 厂家： | 
MOTOROLA |
| 描述： | DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER |
| 文件： | 总6页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
LOW POWER SCHOTTKY
• Low Power Consumption . . . Typically 45 mW
• High Count Rates . . . Typically 42 MHz
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
J SUFFIX
CERAMIC
CASE 632-08
14
1
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
N SUFFIX
HIGH
LOW
PLASTIC
CASE 646-06
CP
CP
CP
Clock (Active LOW going edge) Input to
÷2 Section
0.5 U.L.
1.5 U.L.
0
1
1
14
1
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
0.5 U.L.
0.5 U.L.
2.0 U.L.
1.0 U.L.
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
D SUFFIX
SOIC
CASE 751A-02
MR , MR
1
MS , MS
Master Reset (Clear) Inputs
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
2
2
14
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷ 8 (LS93) Sections (Note b)
1
1
Q
0
Q , Q , Q
1 3
2
ORDERING INFORMATION
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
c. The Q Outputs are guaranteed to drive the full fan-out plus the CP input of the device.
0
1
d. To insure proper operation the rise (t ) and fall time (t ) of the clock must be less than 100 ns.
r
f
LOGIC SYMBOL
LS92
LS90
LS93
6
1
7
2
MS
14
1
CP
CP
14
1
CP
0
14
1
CP
CP
0
0
CP
1
1
1
MR
Q Q Q Q
0 1 2 3
MR
Q Q Q Q
0 1 2 3
MR
Q Q Q Q
0 1 2 3
1 2
1
2
7
1
2
2
3
12
9
8 11
2
3
12
9
8
11
6
12 11
= PIN 5
9
8
V
= PIN 5
V
V
= PIN 5
CC
CC
GND = PIN 10
NC = PINS 2, 3, 4, 13
CC
GND = PIN 10
NC = PIN 4, 6, 7, 13
GND = PIN 10
NC = PINS 4, 13
FAST AND LS TTL DATA
5-90
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS90
6
MS
1
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
MR
MR
CP
1
1
2
0
MS
2
7
NC
S
S
S
D
S
D
D
D
J
Q
J
Q
Q
R
Q
Q
J
Q
Q
14
Q
0
CP
CP
K
CP
K
CP
S
CP
K
0
Q
3
NC
CC
Q
C
C
C
C
D
D
D
D
GND
V
1
2
Q
1
MS
1
2
CP
1
8
Q
2
MS
MR
MR
1
2
12
9
8
11
3
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
= PIN 5
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
V
CC
GND = PIN 10
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS92
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
CP
1
0
NC
NC
NC
NC
J
Q
Q
J
Q
J
Q
J
Q
Q
14
Q
0
CP
0
CP
K
CP
K
CP
K
CP
K
Q
Q
Q
1
C
C
C
C
D
D
D
D
GND
V
CC
1
CP
1
Q
2
MR
1
2
6
MR
MR
1
2
8
12
11
9
8
MR
Q
3
7
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
= PIN 5
GND = PIN 10
NOTE:
V
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
CC
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS93
1
2
3
4
5
6
7
14
13
12
11
10
9
CP
MR
MR
CP
1
1
2
0
J
Q
Q
J
Q
J
Q
Q
J
Q
Q
NC
14
CP
CP
0
CP
K
CP
K
CP
K
CP
K
Q
0
Q
D
C
C
C
C
D
D
D
Q
3
NC
1
2
GND
V
CC
1
Q
1
NC
MR
MR
1
2
12
9
8
11
3
8
Q
2
NC
Q
Q
Q
Q
3
0
1
2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
= PIN 5
GND = PIN 10
V
CC
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-91
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnectionsare required. The first flip-flop is used as a
binary element for the divide-by-two function (CP as the
0
inputand Q astheoutput). TheCP inputisusedtoobtain
0
1
binary divide-by-five operation at the Q output.
3
LS92
A. Modulo 12, Divide-By-Twelve Counter — The CP input
1
must be externally connected to the Q output. The CP in-
0
0
put receives the incoming count and Q produces a sym-
3
should not be used for clocks or strobes. The Q output of
0
metrical divide-by-twelve square wave output.
each device is designed and specified to drive the rated
fan-out plus the CP input of the device.
A gated AND asynchronous Master Reset (MR • MR ) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
1
B. Divide-By-Two and Divide-By-Six Counter —No external
interconnectionsare required. The first flip-flop is used as a
1
2
binary element for the divide-by-two function. The CP in-
1
put is used to obtain divide-by-three operation at the Q
1
Master Set (MS • MS ) is provided on the LS90 which
1
2
and Q outputs and divide-by-six operation at the Q out-
2
3
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
put.
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS93
A. 4-Bit Ripple Counter — The output Q must be externally
0
connected to input CP . The input count pulses are applied
1
LS90
to input CP . Simultaneous divisions of 2, 4, 8, and 16 are
0
performed at the Q , Q , Q , and Q outputs as shown in
A. BCD Decade (8421) Counter — The CP input must be ex-
1
0
1
2
3
the truth table.
ternallyconnectedtotheQ output.TheCP inputreceives
0
0
the incoming count and a BCD count sequence is pro-
duced.
B. 3-Bit Ripple Counter— The input count pulses are applied
to input CP . Simultaneous frequency divisions of 2, 4, and
1
8 are available at the Q , Q , and Q outputs. Independent
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q
3
1
2
3
use of the first flip-flop is available if the reset function coin-
cides with reset of the 3-bit ripple-through counter.
output must be externally connected to the CP input. The
0
inputcount is then applied to the CP input and a divide-by-
1
ten square wave is obtained at output Q .
0
FAST AND LS TTL DATA
5-92
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LS90
LS92 AND LS93
MODE SELECTION
MODE SELECTION
RESET/SET INPUTS
MR MR MS MS
OUTPUTS
RESET
INPUTS
OUTPUTS
Q
Q
Q
Q
3
1
2
1
2
0
1
2
MR MR
Q
Q
Q
Q
3
1
2
0
1
2
H
H
X
L
X
L
H
H
X
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
H
L
H
H
L
L
L
L
L
Count
Count
Count
Count
Count
Count
Count
L
X
L
L
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
LS90
LS92
TRUTH TABLE
LS93
TRUTH TABLE
BCD COUNT SEQUENCE
OUTPUT
COUNT
OUTPUT
OUTPUT
COUNT
COUNT
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
3
0
1
2
3
0
1
2
3
0
1
2
0
1
2
3
4
5
6
7
8
9
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
0
1
2
3
4
5
6
7
8
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
0
1
2
3
4
5
6
7
8
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
9
10
11
9
L
10
11
12
13
14
15
H
H
L
L
H
H
NOTE: Output Q is connected to Input
0
CP for BCD count.
H
L
1
NOTE: Output Q is connected to Input
0
CP .
1
H
NOTE: Output Q is connected to Input
0
CP .
1
FAST AND LS TTL DATA
5-93
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
54, 74
–0.4
mA
mA
OH
54
74
4.0
8.0
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.5
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.5
2.7
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.5
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
IN
OL
V
Output LOW Voltage
Input HIGH Current
OL
per Truth Table
OL
20
µA
V
V
= MAX, V = 2.7 V
IN
CC
I
IH
0.1
mA
= MAX, V = 7.0 V
IN
CC
Input LOW Current
MS, MR
–0.4
–2.4
–3.2
–1.6
I
IL
CP
mA
V
CC
= MAX, V = 0.4 V
IN
0
CP (LS90, LS92)
1
CP (LS93)
1
I
I
Short Circuit Current (Note 1)
Power Supply Current
–20
–100
15
mA
mA
V
V
= MAX
= MAX
OS
CC
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-94
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V, C = 15 pF)
L
A
Limits
LS92
Typ
LS90
Typ
LS93
Typ
Min
32
Max
Min
32
Max
Min
32
Max
Unit
MHz
MHz
Symbol
Parameter
CP Input Clock Frequency
f
f
MAX
0
CP Input Clock Frequency
1
16
16
16
MAX
t
t
Propagation Delay,
10
12
16
18
10
12
16
18
10
12
16
18
PLH
PHL
ns
ns
ns
ns
ns
CP Input to Q Output
0
0
t
t
32
34
48
50
32
34
48
50
46
46
70
70
PLH
PHL
CP Input to Q Output
0
3
t
t
10
14
16
21
10
14
16
21
10
14
16
21
PLH
PHL
CP Input to Q Output
1
1
t
t
21
23
32
35
10
14
16
21
21
23
32
35
PLH
PHL
CP Input to Q Output
1
2
t
t
21
23
32
35
21
23
32
35
34
34
51
51
PLH
PHL
CP Input to Q Output
1
3
t
t
t
MS Input to Q and Q Outputs
20
26
26
30
40
40
ns
ns
ns
PLH
PHL
PHL
0
3
MS Input to Q and Q Outputs
1
2
MR Input to Any Output
26
40
26
40
AC SETUP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
LS92
LS90
LS93
Min
15
30
15
15
25
Max
Min
15
Max
Min
Max
Symbol
Parameter
CP Pulse Width
Unit
ns
t
15
30
W
W
W
W
rec
0
t
t
t
t
CP Pulse Width
1
30
ns
MS Pulse Width
ns
MR Pulse Width
15
25
15
25
ns
Recovery Time MR to CP
ns
RECOVERY TIME (t ) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
rec
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP
1.3 V
1.3 V
1.3 V
t
W
t
t
PLH
PHL
Q
1.3 V
1.3 V
Figure 1
*The number of Clock Pulses required between the t
and t measurements can be determined from the appropriate Truth Tables.
PHL
PLH
MR & MS
1.3 V
1.3 V
PLH
1.3 V
1.3 V
MS
CP
t
t
t
t
rec
W
W
rec
1.3 V
1.3 V
CP
Q
t
t
PHL
Q
• Q
3
(LS90)
0
1.3 V
1.3 V
Figure 2
Figure 3
FAST AND LS TTL DATA
5-95
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