SN74LS173ANS [MOTOROLA]
LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16;
| 型号： | SN74LS173ANS |
| 厂家： | 
MOTOROLA |
| 描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16 输出元件 |
| 文件： | 总6页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS173A
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
The SN54/74LS173A is a high-speed 4-Bit Register featuring 3-state
outputs for use in bus-organized systems. The clock is fully edge-triggered
allowing either a load from the D inputs or a hold (retain register contents)
4-BIT D-TYPE REGISTER
WITH 3-STATE OUTPUTS
depending on the state of the Input Enable Lines (IE , IE ). A HIGH on either
1
2
Output Enable line (OE , OE ) brings the output to a high impedance state
1
2
LOW POWER SCHOTTKY
without affecting the actual register contents. A HIGH on the Master Reset
(MR) input resets the Register regardless of the state of the Clock (CP), the
Output Enable (OE , OE ) or the Input Enable (IE , IE ) lines.
1
• Fully Edge-Triggered
• 3-State Outputs
2
1
2
J SUFFIX
CERAMIC
CASE 620-09
• Gated Input and Output Enables
• Input Clamp Diodes Limit High-Speed Termination Effects
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
N SUFFIX
PLASTIC
CASE 648-08
16
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
D SUFFIX
SOIC
CASE 751B-03
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
PIN NAMES
LOADING (Note a)
HIGH
LOW
D –D
Data Inputs
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
LOGIC SYMBOL
0
3
2
IE –IE
Input Enable (Active LOW)
Output Enable (Active LOW) Inputs
Clock Pulse (Active HIGH Going Edge)
Input
0.5 U.L.
0.5 U.L.
0.5 U.L.
1
OE –OE
1
2
CP
MR
Q –Q
0
Master Reset Input (Active HIGH)
Outputs (Note b)
0.5 U.L.
65 (25) U.L. 15 (7.5) U.L.
0.25 U.L.
3
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
FAST AND LS TTL DATA
5-316
SN54/74LS173A
LOGIC DIAGRAM
TRUTH TABLE
MR
CP
IE
1
IE
2
D
Q
n
n
H
L
L
L
L
L
x
L
x
x
H
x
L
L
x
x
x
H
L
L
x
x
x
x
L
H
L
Q
Q
Q
n
n
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
L
H
When either OE , or OE are HIGH, the output is in the off state (High Impedance);
1
2
however this does not affect the contents or sequential operation of the register.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
54
74
–55
0
25
25
125
70
°C
A
I
I
54
74
–1.0
–2.6
mA
mA
OH
54
74
12
24
OL
FAST AND LS TTL DATA
5-317
SN54/74LS173A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.4
–1.5
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
54
74
2.4
2.4
= MIN, I
OH
= MAX, V = V
IN
CC
IH
OH
or V per Truth Table
IL
3.1
V
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
I
I
= 12 mA
= 24 mA
CC
IN
OL
V
OL
Output LOW Voltage
per Truth Table
OL
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.7 V
O
OZH
= MAX, V = 0.4 V
OZL
O
µA
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
–0.4
–130
30
= MAX, V = 0.4 V
IN
IL
Short Circuit Current (Note 1)
Power Supply Current
–30
= MAX
= MAX
OS
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
f
Maximum Input Clock Frequency
30
50
MHz
MAX
t
t
Propagation Delay,
Clock to Output
17
22
25
30
PLH
PHL
ns
ns
ns
V
C
R
= 5.0 V
= 45 pF,
= 667 Ω
CC
L
L
t
Propagation Delay, MR to Output
Output Enable Time
26
35
PHL
t
t
15
18
23
27
PZH
PZL
t
t
11
11
17
17
C
R
= 5.0 pF,
= 667 Ω
PLZ
PHZ
L
L
Output Disable Time
ns
AC SETUP REQUIREMENTS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Clock or MR Pulse Width
Data Enable Setup Time
Data Setup Time
Unit
ns
Test Conditions
Min
20
35
17
0
Max
t
t
t
t
t
W
ns
s
ns
V
CC
= 5.0 V
s
Hold Time, Any Input
Recovery Time
ns
h
10
ns
rec
FAST AND LS TTL DATA
5-318
SN54/74LS173A
AC WAVEFORMS
Figure 1
Figure 2
≥
≈
Figure 3
Figure 4
AC LOAD CIRCUIT
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
Closed
Open
t
PZH
t
Closed
Closed
Closed
PZL
PLZ
PHZ
t
Closed
Closed
t
Ω
*Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-319
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
-A-
16
1
9
8
P
C
-B-
R X 45°
G
-T-
J
M
F
D
°
°
°
°
K
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
1
9
B
S
8
F
L
C
K
-T-
M
H
J
G
D
°
°
°
°
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
-A-
16
9
-B-
1
8
L
C
-T-
K
M
N
E
J
F
G
D
°
°
°
°
FAST AND LS TTL DATA
5-320
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