SN74LS323ND [MOTOROLA]
Parallel In Parallel Out, LS Series, 8-Bit, Bidirectional, True Output, TTL, PDIP20, 738-01;
| 型号： | SN74LS323ND |
| 厂家： | 
MOTOROLA |
| 描述： | Parallel In Parallel Out, LS Series, 8-Bit, Bidirectional, True Output, TTL, PDIP20, 738-01 移位寄存器 存储 触发器 逻辑集成电路 光电二极管 输出元件 |
| 文件： | 总5页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS323
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
The SN54/74LS323 is an 8-Bit Universal Shift/Storage Register with
3-stateoutputs. ItsfunctionissimilartotheSN54/74LS299withtheexception
of Synchronous Reset. Parallel load inputs and flip-flop outputs are
multiplexed to minimize pin count. Separate inputs and outputs are provided
8-BIT SHIFT/STORAGE REGISTER
WITH 3-STATE OUTPUTS
for flip-flops Q and Q to allow easy cascading.
0
7
LOW POWER SCHOTTKY
Four operation modes are possible: hold (store), shift left, shift right, and
parallel load. All modes are activated on the LOW-to-HIGH transition of the
Clock.
• Common I/O for Reduced Pin Count
• Four Operation Modes: Shift Left, Shift Right, Parallel Load and Store
• Separate Continuous Inputs and Outputs from Q and Q Allow Easy
Cascading
0
7
J SUFFIX
CERAMIC
CASE 732-03
• Fully Synchronous Reset
• 3-State Outputs for Bus Oriented Applications
• Input Clamp Diodes Limit High-Speed Termination Effects
• ESD > 3500 Volts
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
CONNECTION DIAGRAM DIP (TOP VIEW)
V
S
DS
Q
I/O
I/O
I/O
I/O
CP DS
0
DW SUFFIX
SOIC
CASE 751D-03
CC
20
1
7
7
7
5
3
1
19
18
17
16
15
14
13
12
11
20
1
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Ceramic
1
2
3
4
5
6
8
9
10
7
S
0
OE OE
I/O I/O
I/O
I/O
Q
SR GND
1
2
6
4
2
0
0
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP
Clock Pulse (active positive going edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3-State) (Note c)
3-State Output Enable (active LOW) Inputs
Serial Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
DS
DS
0
7
n
I/O
65 (25) U.L.
15 (7.5) U.L.
OE , OE
0.5 U.L.
10 U.L.
1 U.L.
0.25 U.L.
5 (2.5) U.L.
1
2
Q , Q
0
7
1
S , S
Mode Select Inputs
0
SR
Synchronous Reset (active LOW) Input
0.5 U.L.
0.25 U.L.
NOTES:
a) 1 TTL LOAD = 40 µA HIGH/1.6 mA LOW.
b) The output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial Temperature Ranges.
c) The output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial Temperature Ranges.
The output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial Temperature Ranges.
FAST AND LS TTL DATA
5-1
SN54/74LS323
S
S
LOGIC DIAGRAM
1 19
0
1
18
DS
7
DS
0
11
9
SR
CP
12
8
D
D
D
D
D
D
D
D
CP
CP
CP
CP
CP
CP
CP
CP
17
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
Q
7
2
3
OE
OE
1
2
7
13
6
14
5
15
4
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
FUNCTIONAL DESCRIPTION
The logic diagram and truth table indicate the functional
characteristics of the SN54/74LS323 Universal Shift/Storage
Register. This device is similar in operation to the
SN54/74LS299 except for synchronous reset. A partial list of
the common features are described below:
2. When S = S = 1, I/O –I/O are parallel inputs to flip-flops
0 1 0 7
Q –Q respectively, and the outputs of Q –Q are in the
0
7
0
7
high impedance state regardless of the state of OE or
1
OE .
2
An important unique feature of the SN54/74LS323 is a fully
Synchronous Reset that requires only to be stable at least one
setup time prior to the positive transition of the Clock Pulse.
1. They use eight D-type edge-triggered flip-flops that re-
spond only to the LOW-to-HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control(S ,S )anddatainputs(DS ,DS ,I/O –I/O )may
0
1
0
7
0
7
be stable at least a setup time prior to the positive transition
of the Clock Pulse.
TRUTH TABLE
INPUTS
RESPONSE
SR
S
1
S
0
OE
OE
CP DS
DS
7
1
2
0
L
L
L
X
X
H
X
X
H
H
X
X
X
H
X
X
X
X
X
X
X
Synchronous Reset; Q = Q = LOW
I/O voltage undetermined
0
7
L
L
L
X
X
L
L
L
L
L
X
X
X
X
Synchronous Reset; Q = Q = LOW
0 7
I/O voltage LOW
H
H
L
L
H
H
X
L
X
L
D
D
X
X
Shift Right; Dº Q ; Q º Q ; etc.
0
0
1
Shift Right; Dº Q & I/O ; Q º Q & I/O ; etc.
0
0
0
1
1
H
H
H
H
L
L
X
L
X
L
X
X
D
D
Shift Left; Dº Q ; Q º Q ; etc.
7 7 6
Shift Left; Dº Q & I/O ; Q º Q & I/O ; etc.
7
7
7
6
6
H
H
H
X
X
X
X
Parallel Load I/O º Q
n n
H
H
L
L
L
L
H
X
X
H
X
X
X
X
X
X
Hold; I/O Voltage Undetermined
Hold; I/O = Q
H
L
L
L
L
X
X
X
n
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
FAST AND LS TTL DATA
5-2
SN54/74LS323
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°C
I
I
Output Current — High
Output Current — Low
Q , Q
54, 74
–0.4
mA
mA
OH
0
7
Q , Q
54
74
4.0
8.0
OL
0
7
7
Q , Q
0
I
Output Current — High
Output Current — Low
I/O –I/O
54
74
–1.0
–2.6
mA
mA
OH
OL
0
7
7
I/O –I/O
0
I
I/O –I/O
54
74
12
24
0
7
7
I/O –I/O
0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65
3.2
–1.5
V
V
V
V
V
V
= MIN, I = –18 mA
IN
IK
CC
CC
54
74
54
74
2.4
2.4
2.5
2.7
V
= MIN, I
= MAX
= MAX
OH
OH
OH
I/O –I/O
0
7
3.1
3.4
Output HIGH Voltage
Q , Q
V
V
I
= MIN, I
OH
OL
CC
0
7
3.4
V
CC
= V MIN,
CC
54, 74
74
0.25
0.35
0.4
0.5
0.4
0.5
V
V
V
V
= 12 mA
= 24 mA
= 4.0 mA
= 8.0 mA
OL
Output LOW Voltage
I/O –I/O
V
= V or V
IL IH
V
IN
per Truth Table
0
7
I
I
I
OL
OL
OL
V
V
= V
MIN,
54, 74
74
CC
IN
CC
Output LOW Voltage
Q –Q
= V or V
V
OL
IL IH
0
7
per Truth Table
I
Output Off Current HIGH
I/O –I/O
OZH
OZL
40
µA
V
= MAX, V
= 2.7 V
CC
CC
OUT
OUT
0
7
I
Output Off Current LOW
I/O –I/O
–400
20
µA
µA
µA
V
= MAX, V
= 0.4 V
0
7
Others
S , S ,
I/O –I/O
0
V
CC
= MAX, V = 2.7 V
IN
0
1
40
7
I
Input HIGH Current
Input LOW Current
IH
Others
0.1
0.2
mA
mA
mA
mA
mA
mA
mA
mA
V
CC
V
CC
V
CC
= MAX, V = 7.0 V
IN
S , S
0
1
I/O –I/O
0
0.1
= MAX, V = 5.5 V
IN
7
Others
–0.4
–0.8
–100
–130
53
I
I
= MAX, V = 0.4 V
IN
IL
S , S
0
1
Q , Q
–20
–30
V
CC
V
CC
V
CC
= MAX
= MAX
= MAX
o
7
OS
Short Circuit Current
(Note 1)
I/O –I/O
0
7
I
Power Supply Current
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-3
SN54/74LS323
AC CHARACTERISTICS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Min
Typ
Max
Symbol
Parameter
Unit
Test Conditions
f
Maximum Clock Frequency
25
35
MHz
MAX
C
= 15 pF
L
t
t
Propagation Delay, Clock
26
22
39
33
PHL
PLH
ns
ns
ns
ns
to Q or Q
0
7
t
t
Propagation Delay, Clock
to I/O –I/O
25
17
39
25
PHL
PLH
0
7
C
L
R
L
= 45 pF,
= 667 Ω
t
t
14
20
21
30
PZH
PZL
Output Enable Time
Output Disable Time
t
t
10
10
15
15
PHZ
PLZ
C
= 5.0 pF
L
AC SETUP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
Min
25
15
20
20
35
0
Max
Symbol
Parameter
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clear Pulse Width LOW
Data Setup Time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
t
t
t
t
t
t
t
t
W
W
W
s
V
CC
= 5.0 V
Select Setup Time
Data Hold Time
s
h
Select Hold Time
10
20
h
Recovery Time
rec
FAST AND LS TTL DATA
5-4
SN54/74LS323
3-STATE WAVEFORMS
1.3 V
1.3 V
V
V
V
IN
1.3 V
1.3 V
IN
t
t
PLH
PHL
t
t
PHL
PLH
1.3 V
1.3 V
V
OUT
1.3 V
1.3 V
OUT
Figure 1
Figure 2
V
E
V
V
E
1.5 V
1.5 V
t
1.5 V
1.5 V
V
E
E
t
t
PZL
PLZ
t
PHZ
PZH
≥
V
≈
OH
1.5 V
0.5 V
V
OUT
1.5 V
≈
V
1.5 V
OL
1.5 V
V
0.5 V
OUT
Figure 3
Figure 4
AC LOAD CIRCUIT
V
CC
R
L
SWITCH POSITIONS
SYMBOL
SW1
Open
SW2
Closed
Open
SW1
t
PZH
t
Closed
Closed
Closed
PZL
PLZ
PHZ
TO OUTPUT
UNDER TEST
t
Closed
Closed
t
5 kΩ
C *
SW2
L
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-5
相关型号：
SN74LS323NDS
LS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP20, 738-01
MOTOROLA
SN74LS323NS
Parallel In Parallel Out, LS Series, 8-Bit, Bidirectional, True Output, TTL, PDIP20, 738-01
MOTOROLA
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