SN74LS569NS [MOTOROLA]
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP20, 738-01;
| 型号： | SN74LS569NS |
| 厂家： | 
MOTOROLA |
| 描述： | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP20, 738-01 计数器 逻辑集成电路 光电二极管 输出元件 |
| 文件： | 总8页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54/74LS569A
FOUR-BIT UP/DOWN COUNTER
WITH THREE-STATE OUTPUTS
The SN54/74LS569A is designed as programmable up/down BCD and
Binary counters respectively. These devices have 3-state outputs for use in
bus organized systems. With the exception of output enable (OE) and
asynchronous clear (ACLR), all functions occur on the positive edge of the
clock pulse (CP).
FOUR-BIT UP/DOWN COUNTER
WITH THREE-STATE OUTPUTS
LOW POWER SCHOTTKY
When the LOAD input is LOW, the outputs will be programmed by the
parallel data inputs (A, B, C, D) on the next clock edge. Enabling of the
counters occurs only when CEP and CET are LOW and LOAD is HIGH.
Direction of the count is controlled by the up-down input (U/D), HIGH counts
up and LOW counts down. High-speed counting and cascading is implement-
ed by internal look-ahead carry logic and an active LOW ripple carry output
(RCO). On the LS569A, the RCO is LOW at binary 15 during up-count and
during down-count it is also LOW at binary 0. During normal cascading
operation RCO connected to the succeeding block at CET is the only
requisite. When counting and when RCO is LOW, the clocked carry output
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to the LOW
time of the clock pulse. Two active LOW reset lines are provided, a master
reset asynchronous clear (ACLR) and a synchronous clear (SCLR). When in
a HIGH state, the output control (OE) input forces the counter output into a
HIGH impedance state and when LOW, the counter outputs are enabled.
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
• ESD > 3500 Volts
DW SUFFIX
SOIC
CASE 751D-03
CONNECTION DIAGRAM (TOP VIEW)
20
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Note: Pin 1 is marked
for orientation.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
Operating Ambient Temperature Range
Output Current — High Except RCO, CCO
54
74
–55
0
25
25
125
70
°C
A
I
54
74
–1.0
–2.6
mA
OH
I
I
Output Current — High RCO, CCO
54, 74
–0.44
mA
mA
OH
Output Current — Low Except RCO, CCO
54
74
12
24
OL
I
Output Current — Low, RCO, CCO
54
74
4.0
8.0
mA
OL
FAST AND LS TTL DATA
5-573
SN54/74LS569A
FUNCTION TABLE
INPUTS
LOAD CET CEP U/D ACLR SCLR OE RCO CCO
OUTPUTS
CP
D
C
B
A
Y
D
Y
C
Y
B
Y
A
↑
↑
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
L
L
H
L
L
L
X
H
H
L
X
X
H
H
H
H
H
H
H
H
L
L
L
L
A/R
A/R
H
A/R
A/R
H
(Q – CP) + 1
Count Up
Count Down
T
(Q – CP) – 1
T
NC NC NC NC Count Inhibit
NC NC NC NC Count Inhibit
A/R
H
Ω
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
L
L
H
L
H
X
L
H
X
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
Overflow
Overflow
Overflow Inhibit
Underflow
Underflow
H
H
↑
↑
H
H
Underflow Inhibit
↑
↑
L
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
L
X
X
L
H
X
X
L
H
X
X
X
H
L
L
L
H
L
L
L
X
H
H
H
H
H
L
L
L
L
X
H
L
L
L
L
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Load Example
Clear (Synchronous)
Clear (Synchronous)
Clear (Synchronous)
Clear (Synchronous)
Asynchronous Clear
Asynchronous Clear
Asynchronous Clear
Asynchronous Clear
Output Disabled
↑
↑
X
L
L
H
H
H
H
X
L
L
H
X
H
H
L
L
H
X
X
X
X
H
H
X
Hi-Z
(Q — CP) = Output state prior to clock edge
T
NC = No change
A/R = Assumes required output state;
X = Don’t care
High except during Overflow and Underflow
LOGIC DIAGRAM
FAST AND LS TTL DATA
5-574
SN54/74LS569A
DEFINITION OF FUNCTIONAL TERMS
A, B, C, D
The four programmable data inputs.
ACLR
Asynchronous Clear. Master reset of
counters to zero when ACLR is LOW,
independent of the clock.
CEP
Count Enable Parallel. Can be used to
enable and inhibit counting in high speed
cascaded operation. CEP must be LOW to
count.
SCLR
OE
Synchronous clear of counters to zero on
the next clock edge when SCLR is LOW.
CET
CP
Count Enable Trickle. Enables the ripple
carry output for cascaded operation. Must
be LOW to count.
A HIGH on the output control sets the four
counter outputs in the high impedance, and
a LOW, enables the output.
Clock Pulse. All synchronous functions
occurontheLOW-to-HIGHtransitionof the
clock.
Y , Y , Y , Y
The four counter outputs.
A
B
C
D
RCO
RippleCarry Output. OutputwillbeLOWon
the maximum count on up-count. Upon
down-count, RCO is LOW at 0000.
LOAD
U/D
Enables parallel load of counter outputs
from data inputs on the next clock edge.
Must be HIGH to count.
CCO
Clock Carry Output. While counting and
RCO is LOW, CCO will follow the clock
HIGH-LOW-HIGH transition.
Up/Down Count Control. HIGH counts up
and LOW counts down.
LOW-POWER SCHOTTKY INPUT/OUTPUT
CURRENT INTERFACE CONDITIONS
Note: Actual current flow direction shown
FAST AND LS TTL DATA
5-575
SN54/74LS569A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
2.0
V
IH
54
74
0.7
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
YA–
–0.65
3.4
–1.5
V
V
V
V
V
V
CC
= MIN, I = –18 mA
IN
IK
54
74
54
74
2.4
2.4
2.5
2.7
Output HIGH Voltage
YD
3.1
V
= MIN, I
= MAX, V = V
IN
CC
OH
IH
V
OH
or V per Truth Table
IL
3.5
RCO,
CCO
3.5
V
= V
CC
MIN,
= V or V
IL IH
54, 74
74
0.25
0.35
0.4
0.5
V
V
CC
V
IN
V
OL
Output LOW Voltage
I = I MAX
OL OL
per Truth Table
I
I
Output Off Current HIGH
Output Off Current LOW
20
–20
20
µA
µA
V
V
V
V
= MAX, V = 2.7 V
OZH
CC
CC
CC
CC
O
= MAX, V = 0.4 V
OZL
O
µA
= MAX, V = 2.7 V
IN
I
Input HIGH Current
IH
IL
0.1
mA
mA
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
Others
CET
–0.4
–0.8
–100
–130
43
I
Input LOW Current
V
CC
= MAX, V = 0.4 V
IN
RCO, CCO
Others
–20
–30
Short Circuit Current
(Note 1)
I
I
V
V
= MAX
= MAX
OS
CC
Power Supply Current, 3-State
CC
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C)
A
Limits
Typ
Symbol
Parameter
Unit
Test Conditions
Min
Max
FAST AND LS TTL DATA
5-576
f
Maximum Toggle Frequency
35
MHz
ns
MAX
t
t
Propagation Delay
Clock to Q
15
20
PLH
PHL
t
t
Propagation Delay
CET to RCO
14
15
PLH
PHL
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
Propagation Delay
U/D to RCO
20
24
PLH
PHL
t
t
Propagation Delay
Clock to RCO
20
25
PLH
PHL
V
C
R
= 5.0 V
= 45 pF
= 667 Ω
CC
L
L
t
t
Propagation Delay
CET to CCO
16
28
PLH
PHL
t
t
Propagation Delay
CEP to CCO
16
26
PLH
PHL
t
t
Propagation Delay
Clock to CCO
15
17
PLH
PHL
t
t
Propagation Delay
ACLR to Q
22
32
PLH
PHL
t
t
15
20
PZH
PZL
Output Enable Time
Output Disable Time
t
t
20
27
PHZ
PLZ
C
= 5.0 pF
L
FAST AND LS TTL DATA
5-577
SN54/74LS569A
AC SETUP REQUIREMENTS (T = 25°C, V
CC
= 5.0 V)
A
Limits
Typ
Symbol
Parameter
Clock Pulse Width (Low)
Setup Time, A, B, C, D
Setup Time, SCLR
Setup Time, LOAD
Setup Time, U/D
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Min
20
20
20
25
30
20
0
Max
t
t
t
t
t
t
t
t
W
s
s
s
V
CC
= 5.0 V
s
Setup Time, CET, CEP
Hold Time, Any Inputs
ACLR
s
h
15
rec
MICROPROGRAMMABLE DUAL-EVENT 8-BIT COUNTERS
FAST AND LS TTL DATA
5-578
Case 751D-03 DW Suffix
20-Pin Plastic
SO-20 (WIDE)
-A-
20
1
11
10
-B-
P
G
R X 45°
C
-T-
M
J
F
°
°
°
°
K
D
Case 732-03 J Suffix
20-Pin Ceramic Dual In-Line
20
11
10
1
B
C
A
L
F
N
K
J
M
H
G
D
°
°
°
°
Case 738-03 N Suffix
20-Pin Plastic
-A-
20
1
11
10
B
C
L
-T-
K
E
N
M
J
G
F
D
°
°
°
°
FAST AND LS TTL DATA
5-579
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