UC2843BD1 [MOTOROLA]
HIGH PERFORMANCE CURRENT MODE CONTROLLERS; 高性能电流模式控制器
| 型号： | UC2843BD1 |
| 厂家： | 
MOTOROLA |
| 描述： | HIGH PERFORMANCE CURRENT MODE CONTROLLERS |
| 文件： | 总16页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by UC3842B/D
HIGH PERFORMANCE
CURRENT MODE
CONTROLLERS
The UC3842B, UC3843B series are high performance fixed frequency
current mode controllers. They are specifically designed for Off–Line and
dc–to–dc converter applications offering the designer a cost–effective
solution with minimal external components. These integrated circuits feature
a trimmed oscillator for precise duty cycle control, a temperature
compensated reference, high gain error amplifier, current sensing
comparator, and a high current totem pole output ideally suited for driving a
power MOSFET.
N SUFFIX
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line and surface mount
(SO–8) plastic package as well as the 14–pin plastic surface mount (SO–14).
The SO–14 package has separate power and ground pins for the totem pole
output stage.
PLASTIC PACKAGE
8
CASE 626
1
D1 SUFFIX
PLASTIC PACKAGE
8
CASE 751
(SO–8)
1
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX843B is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
D SUFFIX
PLASTIC PACKAGE
14
CASE 751A
(SO–14)
• Trimmed Oscillator for Precise Frequency Control
• Oscillator Frequency Guaranteed at 250 kHz
• Current Mode Operation to 500 kHz
1
PIN CONNECTIONS
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
1
2
3
4
8
7
6
5
Compensation
Voltage Feedback
Current Sense
V
ref
V
CC
Output
R /C
Gnd
T
T
(Top View)
Compensation
1
2
3
4
5
6
7
14
13
12
11
10
9
V
ref
NC
NC
Voltage Feedback
V
V
CC
NC
Current Sense
NC
C
Output
Gnd
Simplified Block Diagram
8
R /C
Power Ground
T
T
V
7(12)
CC
(Top View)
V
V
CC
ref
5.0V
Reference
Undervoltage
Lockout
8(14)
ORDERING INFORMATION
Operating
R
R
V
ref
V
C
Undervoltage
Lockout
Device
Package
Temperature Range
7(11)
UC384XBD
UC384XBD1
UC384XBN
UC284XBD
UC284XBD1
UC284XBN
UC384XBVD
UC384XBVD1
UC384XBVN
SO–14
SO–8
Plastic
SO–14
SO–8
R
/C
Output
T
T
T
= 0° to +70°C
A
Oscillator
6(10)
4(7)
Latching
PWM
Power
Ground
5(8)
Voltage
Feedback
Input
+
–
T
= – 25° to +85°C
= –40° to +105°C
A
Plastic
SO–14
SO–8
2(3)
Error
Amplifier
Current
Sense
Input
Output
Compensation
1(1)
3(5)
T
A
Plastic
Gnd
5(9)
X indicates either a 2 or 3 to define specific device part
numbers.
Pin numbers in parenthesis are for the D suffix SO–14 package.
Motorola, Inc. 1996
Rev 1
UC3842B, 43B UC2842B, 43B
MAXIMUM RATINGS
Rating
Symbol
(I + I )
Value
Unit
mA
A
Total Power Supply and Zener Current
Output Current, Source or Sink (Note 1)
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
30
CC
Z
I
O
1.0
5.0
W
µJ
V
in
– 0.3 to + 5.5
10
V
I
O
mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SO–14 Case 751A
Maximum Power Dissipation @ T = 25°C
Thermal Resistance, Junction–to–Air
D1 Suffix, Plastic Package, SO–8 Case 751
P
862
145
mW
°C/W
A
D
R
R
R
θJA
Maximum Power Dissipation @ T = 25°C
P
702
178
mW
°C/W
A
D
θJA
Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ T = 25°C
P
1.25
100
W
°C/W
A
D
θJA
Thermal Resistance, Junction–to–Air
Operating Junction Temperature
T
+150
°C
°C
J
Operating Ambient Temperature
UC3842B, UC3843B
T
A
0 to + 70
UC2842B, UC2843B
UC3842BV, UC3843BV
– 25 to + 85
–40 to +105
Storage Temperature Range
T
stg
– 65 to +150
°C
ELECTRICAL CHARACTERISTICS (V
CC
= 15 V [Note 2], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values T is
T
T
A
A
the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
UC284XB
Typ
UC384XB, XBV
Typ
Characteristics
REFERENCE SECTION
Symbol
Min
Max
Min
Max
Unit
Reference Output Voltage (I = 1.0 mA, T = 25°C)
V
ref
4.95
–
5.0
2.0
3.0
0.2
–
5.05
20
25
–
4.9
–
5.0
2.0
3.0
0.2
–
5.1
20
25
–
V
mV
mV
mV/°C
V
O
J
Line Regulation (V
CC
= 12 V to 25 V)
Reg
line
load
S
Load Regulation (I = 1.0 mA to 20 mA)
O
Reg
T
–
–
Temperature Stability
–
–
Total Output Variation over Line, Load, and Temperature
Output Noise Voltage (f = 10 Hz to 10 kHz, T = 25°C)
V
ref
4.9
–
5.1
–
4.82
–
5.18
–
V
n
50
50
µV
J
Long Term Stability (T = 125°C for 1000 Hours)
S
–
5.0
– 85
–
–
5.0
–
mV
mA
A
Output Short Circuit Current
I
– 30
–180
– 30
– 85
–180
SC
OSCILLATOR SECTION
Frequency
f
kHz
OSC
T = 25°C
49
48
225
52
–
250
55
56
275
49
48
225
52
–
250
55
56
275
J
A
T
= T
to T
high
T
low
T = 25°C (R = 6.2 k, C = 1.0 nF)
J
T
Frequency Change with Voltage (V
= 12 V to 25 V)
∆f
∆f
/∆V
/∆T
–
–
0.2
1.0
1.0
–
–
–
0.2
0.5
1.0
–
%
%
CC
Frequency Change with Temperature
= T to T
OSC
OSC
T
A
low
Oscillator Voltage Swing (Peak–to–Peak)
Discharge Current (V = 2.0 V)
high
V
–
1.6
–
–
1.6
–
V
OSC
I
mA
OSC
dischg
T = 25°C
7.8
7.5
–
8.3
–
–
8.8
8.8
–
7.8
7.6
7.2
8.3
–
–
8.8
8.8
8.8
J
T
= T
= T
to T
to T
(UC284XB, UC384XB)
(UC384XBV)
A
A
low
low
high
high
T
NOTES: 1. Maximum Package power dissipation limits must be observed.
2. Adjust V above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
T
T
= 0°C for UC3842B, UC3843B
= –25°C for UC2842B, UC2843B
= –40°C for UC3842BV, UC3843BV
T
T
T
= +70°C for UC3842B, UC3843B
= +85°C for UC2842B, UC2843B
= +105°C for UC3842BV, UC3843BV
low
low
low
high
high
high
2
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
ELECTRICAL CHARACTERISTICS (V
CC
= 15 V [Note 2], R = 10 k, C = 3.3 nF. For typical values T = 25°C, for min/max values T is
the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
T
T
A
A
UC284XB
UC384XB, XBV
Characteristics
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V = 2.5 V)
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
V
I
2.45
–
2.5
– 0.1
90
2.55
–1.0
–
2.42
–
2.5
– 0.1
90
2.58
V
µA
O
FB
Input Bias Current (V
= 5.0 V)
– 2.0
FB
IB
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)
A
VOL
65
0.7
60
65
0.7
60
–
–
–
dB
O
Unity Gain Bandwidth (T = 25°C)
BW
1.0
70
–
1.0
70
MHz
dB
J
Power Supply Rejection Ratio (V
= 12 V to 25 V)
PSRR
–
CC
Output Current
mA
Sink (V = 1.1 V, V
Source (V = 5.0 V, V
O
= 2.7 V)
I
Sink
Source
2.0
– 0.5
12
–1.0
–
–
2.0
– 0.5
12
–1.0
–
–
O
FB
= 2.3 V)
I
FB
Output Voltage Swing
V
High State (R = 15 k to ground, V
= 2.3 V)
FB
= 2.7 V)
V
OH
V
OL
5.0
6.2
–
5.0
6.2
–
L
Low State (R = 15 k to V , V
L
ref FB
(UC284XB, UC384XB)
–
–
0.8
–
1.1
–
–
–
0.8
0.8
1.1
1.2
(UC384XBV)
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 4 & 5)
(UC284XB, UC384XB)
A
V/V
V
V
2.85
–
3.0
–
3.15
–
2.85
2.85
3.0
3.0
3.15
3.25
(UC384XBV)
Maximum Current Sense Input Threshold (Note 4)
(UC284XB, UC384XB)
V
th
0.9
–
1.0
–
1.1
–
0.9
0.85
1.0
1.0
1.1
1.1
(UC384XBV)
Power Supply Rejection Ratio
PSRR
–
70
–
–
70
–
dB
V
CC
= 12 V to 25 V, Note 4
Input Bias Current
I
–
–
– 2.0
150
–10
300
–
–
– 2.0
150
–10
300
µA
IB
Propagation Delay (Current Sense Input to Output)
t
ns
PLH(In/Out)
OUTPUT SECTION
Output Voltage
V
V
Low State (I
(I
= 20 mA)
= 200 mA) (UC284XB, UC384XB)
(UC384XBV)
= 20 mA) (UC284XB, UC384XB)
(UC384XBV)
= 200 mA)
V
–
–
–
13
–
12
0.1
1.6
–
13.5
–
0.4
2.2
–
–
–
–
–
–
13
12.9
12
0.1
1.6
1.6
13.5
13.5
13.4
0.4
2.2
2.3
–
–
–
Sink
Sink
OL
High State (I
V
OH
Source
(I
13.4
–
Source
Output Voltage with UVLO Activated
= 6.0 V, I = 1.0 mA
V
–
0.1
1.1
–
0.1
1.1
OL(UVLO)
V
CC
Sink
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)
t
r
–
–
50
50
150
150
–
–
50
50
150
150
ns
ns
L
J
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)
t
f
L
J
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (V
UCX842B, BV
)
V
V
V
CC
th
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
UCX843B, BV
Minimum Operating Voltage After Turn–On (V
UCX842B, BV
)
V
CC(min)
CC
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
UCX843B, BV
NOTES: 2. Adjust V
above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
T
T
= 0°C for UC3842B, UC3843B
= –25°C for UC2842B, UC2843B
= –40°C for UC3842BV, UC3843BV
T
T
T
= +70°C for UC3842B, UC3843B
= +85°C for UC2842B, UC2843B
= +105°C for UC3842BV, UC3843BV
= 0 V.
low
low
low
high
high
high
4. This parameter is measured at the latch trip point with V
FB
∆V Output Compensation
5. Comparator gain is defined as: A
V
∆V Current Sense Input
3
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
ELECTRICAL CHARACTERISTICS (V
CC
= 15 V [Note 2], R = 10 k, C = 3.3 nF, for typical values T = 25°C, for min/max values T
T
T
A
A
is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
UC284XB
Typ
UC384XB, BV
Typ
Characteristics
Symbol
Min
Max
Min
Max
Unit
PWM SECTION
Duty Cycle
%
Maximum (UC284XB, UC384XB)
Maximum (UC384XBV)
Minimum
DC
94
–
–
96
–
–
–
–
0
94
93
–
96
96
–
–
–
0
(max)
DC
(min)
TOTAL DEVICE
Power Supply Current
I
+ I
mA
V
CC
C
Startup (V
Startup (V
Operating (Note 2)
= 6.5 V for UCX843B,
14 V for UCX842B, BV)
–
0.3
0.5
–
0.3
0.5
CC
CC
–
12
36
17
–
–
12
36
17
–
Power Supply Zener Voltage (I
= 25 mA)
V
30
30
CC
Z
NOTES: 2. Adjust V
above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
T
T
T
= 0°C for UC3842B, UC3843B
= –25°C for UC2842B, UC2843B
= –40°C for UC3842BV, UC3843BV
T
T
T
= +70°C for UC3842B, UC3843B
= +85°C for UC2842B, UC2843B
= +105°C for UC3842BV, UC3843BV
low
low
low
high
high
high
Figure 1. Timing Resistor
versus Oscillator Frequency
Figure 2. Output Deadtime
versus Oscillator Frequency
80
50
100
1. C = 10 nF
4
T
2. C = 5.0 nF
50
T
3
3. C = 2.0 nF
T
2
4. C = 1.0 nF
T
20
5. C = 500 pF
T
20
10
6. C = 200 pF
T
1
7. C = 100 pF
T
8.0
5.0
7
6
5
5.0
V
= 15 V
2.0
0.8
CC
= 25°C
V
= 15 V
= 25°C
2.0
1.0
CC
T
A
T
A
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
f
, OSCILLATOR FREQUENCY (kHz)
f , OSCILLATOR FREQUENCY (kHz)
OSC
OSC
Figure 3. Oscillator Discharge Current
versus Temperature
Figure 4. Maximum Output Duty Cycle
versus Timing Resistor
9.0
8.5
8.0
7.5
7.0
100
90
80
70
60
50
40
V
V
= 15 V
CC
= 2.0 V
OSC
I
= 7.5 mA
dischg
I
= 8.8 mA
dischg
V
C
= 15 V
= 3.3 nF
= 25°C
CC
T
T
A
– 55
– 25
0
25
50
75
C)
100
125
0.8 1.0
2.0
3.0
4.0
5.0 6.0 7.0 8.0
T , AMBIENT TEMPERATURE (
°
R , TIMING RESISTOR (kΩ)
A
T
4
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 5. Error Amp Small Signal
Transient Response
Figure 6. Error Amp Large Signal
Transient Response
2.55 V
2.50 V
2.45 V
V
= 15 V
= –1.0
V
= 15 V
CC
CC
A = –1.0
V
3.0 V
2.5 V
A
V
A
T
= 25
°C
T = 25°C
A
2.0 V
0.5
µs/DIV
1.0 µs/DIV
Figure 7. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 8. Current Sense Input Threshold
versus Error Amp Output Voltage
100
80
60
40
20
1.2
1.0
0.8
0.6
0.4
0.2
0
0
V
V
R
= 15 V
= 2.0 V to 4.0 V
= 100 K
CC
O
L
V
= 15 V
CC
30
60
90
120
Gain
T
= 25°C
A
T
= 25°C
A
T
= 125°C
Phase
1.0 M
A
T
= –55
4.0
°C
A
0
150
180
– 20
10
100
1.0 k
10 k
100 k
10 M
0
2.0
6.0
8.0
f, FREQUENCY (Hz)
V
, ERROR AMP OUTPUT VOLTAGE (V)
O
Figure 9. Reference Voltage Change
versus Source Current
Figure 10. Reference Short Circuit Current
versus Temperature
0
– 4.0
– 8.0
–12
110
90
V
R
= 15 V
0.1 Ω
CC
L
V
= 15 V
CC
≤
T
= –55°C
A
T
= 125°C
A
–16
70
– 20
– 24
T
= 25°C
A
50
0
20
40
60
80
100
120
– 55
– 25
0
25
50
75
C)
100
125
I
, REFERENCE SOURCE CURRENT (mA)
T , AMBIENT TEMPERATURE (
°
ref
A
5
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 11. Reference Load Regulation
Figure 12. Reference Line Regulation
V
= 15 V
= 1.0 mA to 20 mA
= 25°C
CC
V
= 12 V to 25
CC
= 25°C
I
T
O
T
A
A
2.0 ms/DIV
2.0 ms/DIV
Figure 13. Output Saturation Voltage
versus Load Current
Figure 14. Output Waveform
0
–1.0
– 2.0
Source Saturation
(Load to Ground)
V
µ
= 15 V
CC
s Pulsed Load
120 Hz Rate
V
CC
T
V
C
= 15 V
= 1.0 nF
= 25°C
80
CC
L
90%
= 25°C
A
T
A
T
= – 55°C
A
3.0
2.0
1.0
0
T
= – 55°C
A
T
= 25°C
A
10%
Sink Saturation
Gnd
600
(Load to V
)
CC
0
200
400
800
50 ns/DIV
I
, OUTPUT LOAD CURRENT (mA)
O
Figure 15. Output Cross Conduction
Figure 16. Supply Current versus Supply Voltage
25
20
15
10
5
V
C
= 30 V
= 15 pF
= 25°C
CC
L
T
A
R
C
T
T
V
FB
I
Sense
T
A
0
0
10
20
, SUPPLY VOLTAGE (V)
30
40
100 ns/DIV
V
CC
6
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
PIN FUNCTION DESCRIPTION
Pin
8–Pin
14–Pin
Function
Description
1
2
1
3
Compensation
This pin is the Error Amplifier output and is made available for loop compensation.
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3
4
5
7
Current
Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
R /C
T
The Oscillator frequency and maximum Output duty cycle are programmed by
T
connecting resistor R to V and capacitor C to ground. Operation to 500 kHz
T
ref
T
is possible.
5
6
Gnd
This pin is the combined control circuitry and power ground.
10
Output
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7
8
12
14
8
V
This pin is the positive supply of the control IC.
CC
V
ref
This is the reference output. It provides charging current for capacitor C through resistor R .
T T
Power
Ground
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the
control circuitry.
11
V
C
The Output high state (V ) is set by the voltage applied to this pin. With a separate power
OH
source connection, it can reduce the effects of switching transient noise on the control circuitry.
This pin is the control circuitry ground return and is connected back to the power source ground.
No connection. These pins are not internally connected.
9
Gnd
NC
2,4,6,13
7
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
OPERATING DESCRIPTION
or at the beginning of a soft–start interval (Figures 23, 24).
The Error Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
The UC3842B, UC3843B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost–effective solution
with minimal external components. A representative block
diagram is shown in Figure 17.
voltage (V
) to reach the comparator’s 1.0 V clamp level:
OH
3.0 (1.0 V) + 1.4 V
R
≈
= 8800 Ω
f(min)
0.5 mA
Oscillator
The oscillator frequency is programmed by the values
Current Sense Comparator and PWM Latch
selected for the timing components R and C . Capacitor C
is charged from the 5.0 V reference through resistor R to
T
approximately 2.8 V and discharged to 1.2 V by an internal
T
T
T
The UC3842B, UC3843B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin 1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
Current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground–referenced sense
current sink. During the discharge of C , the oscillator
T
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in a
low state, thus producing a controlled amount of output
deadtime. Figure 1 shows R versus Oscillator Frequency
T
and Figure 2, Output Deadtime versus Frequency, both for
given values of C . Note that many values of R and C will
T
T
T
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated to within
±6% at 50 kHz. Also because of industry trends moving the
UC384X into higher and higher frequency applications, the
UC384XB is guaranteed to within ±10% at 250 kHz. These
internal circuit refinements minimize variations of oscillator
frequency and maximum output duty cycle. The results are
shown in Figures 3 and 4.
resistor R in series with the source of output switch Q1. This
S
voltage is monitored by the Current Sense Input (Pin 3) and
compared to a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at pin 1 where:
V
– 1.4 V
(Pin 1)
3 R
S
I
pk
=
In many noise–sensitive applications it may be desirable
to frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 20. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi–unit
synchronization is shown in Figure 21. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved.
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
1.0 V
I
=
pk(max)
R
S
Error Amplifier
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 7). The
non–inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is –2.0 µA which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop
compensation (Figure 31). The output voltage is offset by two
diode drops (≈1.4 V) and divided by three before it connects
to the non–inverting input of the Current Sense Comparator.
This guarantees that no drive pulses appear at the Output
order to keep the power dissipation of R to a reasonable
S
level. A simple method to adjust this voltage is shown in
Figure 22. The two external diodes are used to compensate
the internal diodes, yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
clamp
pk(max)
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 26).
(Pin 6) when pin 1 is at its lowest state (V ). This occurs
when the power supply is operating and the load is removed,
OL
8
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 17. Representative Block Diagram
V
V
in
CC
V
CC
7(12)
36V
V
ref
Reference
Regulator
8(14)
(See
Text)
+
–
V
R
R
CC
UVLO
V
Internal
Bias
C
2.5V
R
C
T
7(11)
+
3.6V
V
ref
UVLO
–
Output
Q1
Oscillator
4(7)
6(10)
T
+
1.0mA
S
Power Ground
2R
Q
Voltage
Feedback
Input
PWM
Latch
R
5(8)
2(3)
1(1)
R
Error
Amplifier
1.0V
Current Sense Input
Output/
Compensation
Current Sense
Comparator
3(5)
R
S
Gnd
5(9)
Pin numbers adjacent to terminals are for the 8–pin dual–in–line package.
Pin numbers in parenthesis are for the D suffix SO–14 package.
= Sink Only Positive True Logic
Figure 18. Timing Diagram
Capacitor C
T
Latch
“Set” Input
Output/
Compensation
Current Sense
Input
Latch
“Reset” Input
Output
Small R /Large C
T
Large R /Small C
T
T
T
9
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
possible using heavy copper runs to minimize radiated EMI.
Undervoltage Lockout
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other
noise–generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulator’s closed loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (V ) and the reference output (V ) are each
CC
ref
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX842B,
and 8.4 V/7.6 V for the UCX843B. The V comparator upper
ref
and lower thresholds are 3.6 V/3.4 V. The large hysteresis
and low startup current of the UCX842B makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843B is intended for lower voltage dc–to–dc converter
applications. A 36 V zener is connected as a shunt regulator
shows the phenomenon graphically. At t , switch conduction
0
begins, causing the inductor current to rise at a slope of m .
1
This slope is a function of the input voltage divided by the
inductance. At t , the Current Sense Input reaches the
1
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m ,
from V
to ground. Its purpose is to protect the IC from
2
CC
excessive voltage that can occur during system startup. The
until the next oscillator cycle. The unstable condition can be
shown if a perturbation is added to the control voltage,
resulting in a small ∆I (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t ) is increased by ∆I + ∆I m /m .
minimum operating voltage (V ) for the UCX842B is 11 V
and 8.2 V for the UCX843B.
CC
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
2
2
1
The minimum current at the next cycle (t ) decreases to (∆I +
3
∆I m /m ) (m /m ). This perturbation is multiplied by m /m
2
1
2
1
2
1
on each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m /m is greater than 1, the converter will be unstable. Figure
The SO–14 surface mount package provides separate
2
1
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
∆I perturbation will decrease to zero on succeeding cycles.
pins for V (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
C
This compensating ramp (m ) must have a slope equal to or
becomesparticularlyusefulwhenreducingtheI
clamp
3
pk(max)
slightly greater than m /2 for stability. With m /2 slope
level. The separate V supply input allows the designer
2
2
C
compensation, the average inductor current follows the
control voltage, yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
inputs (Figure 32).
added flexibility in tailoring the drive voltage independent of
V
. A zener clamp is typically connected to this input when
CC
driving power MOSFETs in systems where V
is greater
CC
than 20 V. Figure 25 shows proper power and control ground
connections in a current–sensing power MOSFET
application.
Figure 19. Continuous Current Waveforms
Reference
(A)
∆I
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at T = 25°C on the UC284XB, and ±2.0% on the
J
Control Voltage
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short–
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
m
m
2
1
Inductor
Current
m
m
2
1
l
l
m
m
m
m
2
1
2
1
l
l
Oscillator Period
Design Considerations
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to V , V ,
t
t
t
t
3
0
1
2
(B)
Control Voltage
m
3
∆I
m
1
m
2
Inductor
Current
Oscillator Period
t
CC
C
and V may be required depending upon circuit layout. This
ref
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
t
t
4
5
6
10
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 20. External Clock Synchronization
Figure 21. External Duty Cycle Clamp and
Multi–Unit Synchronization
V
ref
8(14)
R
8(14)
R
R
Bias
R
R
A
B
Bias
R
T
R
8
4
5.0k
5.0k
5.0k
External
Sync
Input
3
Osc
6
Osc
4(7)
C
T
+
R
4(7)
0.01
+
5
2
Q
2R
7
2R
S
R
2(3)
1(1)
EA
47
R
2(3)
EA
C
MC1455
1
1(1)
5(9)
5(9)
To Additional
UCX84XBs
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of C to go more than 300 mV below ground.
1.44
2R )C
R
B
T
f
D
(max)
R
2R
B
(R
A
A
B
Figure 22. Adjustable Reduction of Clamp Level
Figure 23. Soft–Start Circuit
V
V
in
CC
7(12)
5.0V Ref
8(14)
5.0V Ref
R
R
8(14)
Bias
R
R
+
–
Bias
+
–
7(11)
6(10)
+
–
Q1
Osc
Osc
4(7)
2(3)
+
4(7)
V
+
Clamp
1.0V
S
R
R
R
1.0mA
2
1
S
R
1.0 mA
2R
Q
Q
2R
R
5(8)
3(5)
EA
1.0V
5(9)
2(3)
1(1)
EA
R
1.0M
Comp/Latch
R
S
1(1)
5(9)
C
t
≈ 3600C in µF
Soft–Start
1.67
R
R
2
R
Where: 0
≤
V
≤
1.0 V
1
–3
+ 0.33x10
Clamp
V
≈
Clamp
R
1
2
R
R
2
1
1
V
Clamp
I
pk(max)
R
S
11
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 24. Adjustable Buffered Reduction of
Figure 25. Current Sensing Power MOSFET
Clamp Level with Soft–Start
V
V
in
CC
V
V
in
CC
R
I
r
pk DS(on)
S
V
(12)
Pin 5
7(12)
r
R
S
DM(on)
If: SENSEFET = MTP10N10M
= 200
R
S
5.0V Ref
5.0V Ref
Then :
V
0.075 I
pk
Pin
5
8(14)
4(7)
+
–
+
–
R
Bias
D
SENSEFET
R
7(11)
6(10)
(11)
(10)
+
–
+
–
Q1
S
K
G
Osc
V
+
Clamp
M
S
R
1.0 mA
2R
S
R
Q
Q
5(8)
3(5)
EA
(8)
(5)
2(3)
1(1)
R
Comp/Latch
1.0V
5(9)
Comp/Latch
R
2
Power Ground:
To Input Source
Return
R
R
S
S
R
1/4 W
C
1
MPSA63
Control Circuitry Ground:
To Pin (9)
1.67
Where: 0
≤
V
R
≤ 1.0 V
V
Clamp
Clamp
R
R
2
1
1
Virtually lossless current sensing can be achieved with the implementation of
SENSEFET power switch. For proper operation during over–current conditions,
a
a
reduction of the I clamp level must be implemented. Refer to Figures 22 and 24.
V
V
V
R
C
Clamp
R
S
pk(max)
C
1
2
R
2
t
In
1
I
pk(max)
Soft-Start
R
3
1
Clamp
Figure 26. Current Waveform Spike Suppression
Figure 27. MOSFET Parasitic Oscillations
V
V
V
V
in
CC
in
CC
7(12)
7(12)
5.0V Ref
5.0V Ref
+
–
+
–
7(11)
7(11)
+
–
+
–
R
Q1
Q1
g
6(10)
5(8)
6(10)
S
R
S
R
Q
Q
5(8)
3(5)
3(5)
R
Comp/Latch
Comp/Latch
C
R
S
R
S
Series gate resistor R will damp any high frequency parasitic oscillations
g
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
caused by the MOSFET input capacitance and any series wiring inductance in
the gate–source circuit.
12
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 28. Bipolar Transistor Drive
Figure 29. Isolated MOSFET Drive
I
B
V
in
V
V
in
CC
+
0
7(12)
Isolation
Boundary
Base Charge
Removal
–
5.0V Ref
+
–
V
Waveforms
+
GS
C1
+
0
–
7(11)
Q1
+
–
Q1
0
–
6(10)
50% DC
V
25% DC
6(10)
5(8)
S
R
1.4
5(8)
(Pin1)
N
N
S
Q
I
k
p
3
R
S
p
R
3(5)
Comp/Latch
3(5)
R
S
C
R
S
N
S
N
P
Thetotempoleoutputcanfurnishnegativebasecurrentforenhancedtransistor
turn–off, with the addition of capacitor C
.
1
Figure 30. Latched Shutdown
Figure 31. Error Amplifier Compensation
From V
2.5V
O
+
8(14)
R
1.0mA
R
i
2R
Bias
2(3)
R
EA
R
C
R
f
f
R
d
Osc
1(1)
4(7)
+
R
≥ 8.8 k
f
5(9)
1.0 mA
2R
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
R
EA
2(3)
1(1)
From V
2.5V
O
+
1.0mA
R
p
2R
MCR
101
2N
3905
R
2(3)
i
5(9)
R
EA
2N
3903
C
C
R
f
f
p
R
d
1(1)
5(9)
The MCR101 SCR must be selected for a holding of < 0.5 mA @ T
be used in place of the SCR as shown. All resistors are 10 k.
. The simple two transistor circuit can
A(min)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
13
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
Figure 32. Slope Compensation
V
V
in
CC
7(12)
36V
5.0V Ref
+
–
8(14)
R
T
R
R
Bias
MPS3904
+
–
7(11)
6(10)
Osc
R
Slope
From V
4(7)
2(3)
O
C
T
+
–m
S
R
1.0mA
R
R
i
2R
Q
5(8)
3(5)
EA
R
C
1.0V
f
Comp/Latch
R
f
d
m
R
1(1)
S
– 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
Figure 33. 27 W Off–Line Flyback Regulator
L1
MBR1635
2200
5.0V/4.0A
4.7
Ω
+
T1
4.7k
+
+
250
MDA
202
3300
pF
1000
56k
115 Vac
5.0V RTN
12V/0.3A
MUR110
1000
1N4935
1N4935
L2
10
+
+
+
+
68
7(12)
+
+
47
±12V RTN
100
1000
10
L3
1N4937
5.0V Ref
–12V/0.3A
0.01
8(14)
10k
R
R
+
–
MUR110
680pF
2.7k
Bias
7(11)
+
–
1N4937
22
Osc
4(7)
2(3)
MTP
4N50
4700pF
6(10)
+
1N5819
S
R
18k
Q
5(8)
3(5)
EA
100
pF
150k
1.0k
Comp/Latch
4.7k
0.5
1(1)
470pF
5(9)
L1 – 15
L2, L3 – 25
µ
µ
H at 5.0 A, Coilcraft Z7156
H at 5.0 A, Coilcraft Z7157
Test
Conditions
Results
T1 – Primary: 45 Turns #26 AWG
Secondary
Wound
±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar
Line Regulation: 5.0 V
V
= 95 to 130 Vac
∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
in
±12V
Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound
Secondary Feedback: 10 Turns #30 AWG (2 strands)
Bifiliar Wound
Core: Ferroxcube EC35–3C8
Bobbin: Ferroxcube EC35PCB1
Load Regulation: 5.0 V
V
V
= 115 Vac,
= 1.0 A to 4.0 A
out
= 115 Vac,
∆ = 300 mV or ± 3.0%
∆ = 60 mV or ± 0.25%
in
I
±12V
in
I
= 100 mA to 300 mA
out
Gap:
≈ 0.10” for a primary inductance of 1.0 mH
Output Ripple:
Efficiency
5.0 V
±12V
V
= 115 Vac
40 mV
80 mV
in
pp
pp
V
in
= 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted
14
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 626–05
8
5
NOTES:
ISSUE K
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
1
4
MILLIMETERS
INCHES
F
DIM
A
B
C
D
F
MIN
9.40
6.10
3.94
0.38
1.02
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
–A–
0.370
0.240
0.155
0.015
0.040
NOTE 2
L
G
H
J
K
L
2.54 BSC
0.100 BSC
C
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
J
–T–
SEATING
PLANE
7.62 BSC
0.300 BSC
N
M
N
–––
0.76
10
1.01
–––
0.030
10
0.040
M
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
D1 SUFFIX
PLASTIC PACKAGE
CASE 751–06
(SO–8)
ISSUE T
NOTES:
D
A
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
C
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
1
5
4
M
M
0.25
B
H
E
h X 45
MILLIMETERS
B
e
DIM
A
A1
B
C
D
E
e
H
h
MIN
1.35
0.10
0.35
0.19
4.80
3.80
MAX
1.75
0.25
0.49
0.25
5.00
4.00
A
C
SEATING
PLANE
L
1.27 BSC
0.10
5.80
0.25
0.40
0
6.20
0.50
1.25
7
A1
B
L
M
S
S
0.25
C
B
A
15
MOTOROLA ANALOG IC DEVICE DATA
UC3842B, 43B UC2842B, 43B
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
ISSUE F
–A–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–B–
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
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