UC2845N [MOTOROLA]
HIGH PERFORMANCE CURRENT MODE CONTROLLERS; 高性能电流模式控制器
| 型号： | UC2845N |
| 厂家： | 
MOTOROLA |
| 描述： | HIGH PERFORMANCE CURRENT MODE CONTROLLERS |
| 文件： | 总14页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by UC3844/D
HIGH PERFORMANCE
CURRENT MODE
CONTROLLERS
The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for Off–Line and
dc–to–dc converter applications offering the designer a cost effective
solution with minimal external components. These integrated circuits feature
an oscillator, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole output
ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
a latch for single pulse metering, and a flip–flop which blanks the output off
every other oscillator cycle, allowing output deadtimes to be programmed for
50% to 70%.
N SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
D SUFFIX
These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX845 is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
PLASTIC PACKAGE
14
CASE 751A
(SO–14)
1
PIN CONNECTIONS
• Current Mode Operation to 500 kHz Output Switching Frequency
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation
• Latching PWM for Cycle–By–Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Input Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with Motorola SENSEFET Products
Compensation
Voltage Feedback
Current Sense
1
2
8
7
V
ref
V
CC
3
4
6
5
Output
Gnd
R
/C
T
T
(Top View)
1
14
13
Compensation
NC
V
ref
2
NC
3
4
12
11
Voltage Feedback
NC
V
V
CC
C
5
6
10
9
Current Sense
NC
Output
Gnd
Simplified Block Diagram
R
/C
7
8
Power Ground
T
T
V
7(12)
CC
(Top View)
V
V
CC
ref
8(14)
5.0V
Reference
Undervoltage
Lockout
ORDERING INFORMATION
Operating
R
R
V
ref
V
C
Undervoltage
Lockout
Temperature Range
Device
Package
SO–14
SO–14
Plastic
Plastic
SO–14
SO–14
Plastic
Plastic
7(11)
UC3844D
UC3845D
UC3844N
UC3845N
UC2844D
UC2845D
UC2844N
UC2845N
R
4(7)
C
Output
6(10)
T
T
Flip
Flop
&
Latching
PWM
Oscillator
T
= 0° to +70°C
A
Voltage
Feedback
PWR GND
5(8)
+
–
2(3)
Current
Sense
3(5)
Error
Amplifier
1(1)
Output
Comp.
T
= – 25° to +85°C
A
Gnd
5(9)
Pin numbers in parenthesis are for the D suffix SO–14 package.
Motorola, Inc. 1996
Rev 1
UC3844, 45 UC2844, 45
MAXIMUM RATINGS
Rating
Symbol
(I + I )
Value
Unit
mA
A
Total Power Supply and Zener Current
Output Current, Source or Sink (Note 1)
Output Energy (Capacitive Load per Cycle)
Current Sense and Voltage Feedback Inputs
Error Amp Output Sink Current
30
CC
Z
I
O
1.0
5.0
W
µJ
V
in
– 0.3 to + 5.5
10
V
I
O
mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, Case 751A
Maximum Power Dissipation @ T = 25°C
Thermal Resistance Junction–to–Air
N Suffix, Plastic Package, Case 626
P
862
145
mW
°C/W
A
D
R
θJA
Maximum Power Dissipation @ T = 25°C
Thermal Resistance Junction–to–Air
P
1.25
100
W
°C/W
A
D
R
θJA
Operating Junction Temperature
T
+ 150
°C
°C
J
Operating Ambient Temperature
UC3844, UC3845
T
A
0 to + 70
UC2844, UC2845
– 25 to + 85
Storage Temperature Range
T
stg
– 65 to + 150
°C
ELECTRICAL CHARACTERISTICS (V
unless otherwise noted.)
= 15 V, [Note 2], R = 10 k, C = 3.3 nF, T = T
to T [Note 3],
high
CC
T
T
A
low
UC284X
Typ
UC384X
Typ
Characteristics
Symbol
Min
Max
Min
Max
Unit
REFERENCE SECTION
Reference Output Voltage (I = 1.0 mA, T = 25°C)
V
ref
4.95
–
5.0
2.0
3.0
0.2
–
5.05
20
4.9
–
5.0
2.0
3.0
0.2
–
5.1
20
V
mV
mV
mV/°C
V
O
J
Line Regulation (V
CC
= 12 V to 25 V)
Reg
line
load
S
Load Regulation (I = 1.0 mA to 20 mA)
O
Reg
T
–
25
–
25
Temperature Stability
–
–
–
–
Total Output Variation over Line, Load, Temperature
Output Noise Voltage (f = 10 Hz to kHz, T = 25°C)
V
ref
4.9
–
5.1
–
4.82
–
5.18
–
V
n
50
50
µV
J
Long Term Stability (T = 125°C for 1000 Hours)
S
–
5.0
– 85
–
–
5.0
– 85
–
mV
mA
A
Output Short Circuit Current
I
– 30
– 180
– 30
– 180
SC
OSCILLATOR SECTION
Frequency
f
kHz
osc
T = 25°C
47
46
52
–
57
60
47
46
52
–
57
60
J
A
T
= T
to T
high
low
Frequency Change with Voltage (V
= 12 V to 25 V)
∆f
∆
osc/ V
–
–
0.2
5.0
1.0
–
–
–
0.2
5.0
1.0
–
%
%
CC
Frequency Change with Temperature
= T to T
∆f
∆
osc/ T
T
A
low
Oscillator Voltage Swing (Peak–to–Peak)
Discharge Current (V = 2.0 V, T = 25°C)
high
V
osc
–
–
1.6
–
–
–
–
1.6
–
–
V
I
dischg
10.8
10.8
mA
osc
J
NOTES: 1. Maximum Package power dissipation limits must be observed.
2. Adjust V above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
T
T
= –20°C for UC3844, UC3845
= –25°C for UC2844, UC2845
T
T
= +70°C for UC3844, UC3845
= +85°C for UC2844, UC2845
low
low
high
high
2
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
ELECTRICAL CHARACTERISTICS (V
unless otherwise noted,)
= 15 V, [Note 2], R = 10 k, C = 3.3 nF, T = T
to T
[Note 3],
high
CC
T
T
A
low
UC284X
Typ
UC384X
Characteristics
Symbol
Min
Max
Min
Typ
Max
Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (V = 2.5 V)
V
I
2.45
–
2.5
–0.1
90
2.55
–1.0
–
2.42
–
2.5
–0.1
90
2.58
–2.0
–
V
µA
O
FB
Input Bias Current (V
= 2.7 V)
FB
Open Loop Voltage Gain (V = 2.0 V to 4.0 V)
IB
A
VOL
BW
65
0.7
60
65
0.7
60
dB
O
Unity Gain Bandwidth (T = 25°C)
1.0
70
–
1.0
70
–
MHz
dB
J
Power Supply Rejection Ratio (V
= 12 V to 25 V)
PSRR
–
–
CC
Output Current
mA
Sink (V = 1.1 V, V
Source (V = 5.0 V, V
O
= 2.7 V)
I
Sink
Source
2.0
–0.5
12
–1.0
–
–
2.0
–0.5
12
–1.0
–
–
O
FB
= 2.3 V)
I
FB
Output Voltage Swing
V
High State (R = 15 k to ground, V
= 2.3 V)
FB
= 2.7 V)
V
OH
V
OL
5.0
–
6.2
0.8
–
1.1
5.0
–
6.2
0.8
–
1.1
L
Low State (R = 15 k to V , V
L
ref FB
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 4 & 5)
Maximum Current Sense Input Threshold (Note 4)
Power Supply Rejection Ratio
A
2.85
0.9
3.0
1.0
3.15
1.1
2.85
0.9
3.0
1.0
3.15
1.1
V/V
V
V
V
th
PSRR
dB
V
= 12 V to 25 V (Note 4)
–
–
–
70
–
–
–
–
70
–
CC
Input Bias Current
I
–2.0
150
–10
300
–2.0
150
–10
300
µA
IB
Propagation Delay (Current Sense Input to Output)
t
ns
PLH(IN/OUT)
OUTPUT SECTION
Output Voltage
V
Low State (I
= 20 mA)
= 200 mA)
= 20 mA)
= 200 mA)
V
–
–
12
12
0.1
1.6
13.5
13.4
0.4
2.2
–
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.2
–
Sink
Sink
Sink
Sink
OL
(I
High State (I
(I
V
OH
–
–
Output Voltage with UVLO Activated
= 6.0 V, I = 1.0 mA
V
OL(UVLO)
V
V
CC
–
–
–
0.1
50
50
1.1
150
150
–
–
–
0.1
50
50
1.1
150
150
Sink
Output Voltage Rise Time (C = 1.0 nF, T = 25°C)
t
r
ns
ns
L
J
Output Voltage Fall Time (C = 1.0 nF, T = 25°C)
t
f
L
J
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX844
UCX845
V
V
V
th
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
Minimum Operating Voltage After Turn–On
UCX844
UCX845
V
CC(min)
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
PWM SECTION
Duty Cycle
Maximum
Minimum
%
DC
46
–
48
–
50
0
47
–
48
–
50
0
max
DC
min
TOTAL DEVICE
Power Supply Current (Note 2)
Startup:
I
mA
V
CC
(V
(V
CC
= 6.5 V for UCX845A,
14 V for UCX844) Operating
–
–
0.5
12
1.0
17
–
–
0.5
12
1.0
17
CC
Power Supply Zener Voltage (I = 25 mA)
V
30
36
–
30
36
–
CC
Z
NOTES: 2. Adjust V
above the Startup threshold before setting to 15 V.
CC
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
T
T
= –20°C for UC3844, UC3845
= –25°C for UC2844, UC2845
T
T
= +70°C for UC3844, UC3845
= +85°C for UC2844, UC2845
= 0 V.
low
low
high
high
FB
4. This parameter is measured at the latch trip point with V
∆V Output Compensation
5. Comparator gain is defined as: A
V
∆V Current Sense Input
3
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 1. Timing Resistor versus
Oscillator Frequency
Figure 2. Output Deadtime versus
Oscillator Frequency
100
50
75
70
65
V
T
= 15 V
= 25°C
CC
A
1.0 nF
2.0 nF
20
5.0 nF
C
= 10 nF
T
10
60
55
50
5.0
2.0
100 pF
200 pF
NOTE: Output switches
at one–half the oscillator
frequency.
500 pF
1.0
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
f
, OSCILLATOR FREQUENCY (Hz)
f
osc
, OSCILLATOR FREQUENCY (Hz)
osc
Figure 3. Error Amp Small Signal
Transient Response
Figure 4. Error Amp Large Signal
Transient Response
V
= 15 V
= –1.0
V
= 15 V
CC
CC
A = –1.0
V
A
V
A
2.55 V
3.0 V
2.5 V
2.0 V
T
= 25
°C
T = 25°C
A
2.5 V
2.45 V
0.5
µs/DIV
1.0 µs/DIV
Figure 5. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 6. Current Sense Input Threshold
versus Error Amp Output Voltage
100
80
60
40
20
1.2
0
V
V
R
= 15 V
= 2.0 V to 4.0 V
= 100 K
CC
O
L
V
= 15 V
CC
1.0
0.8
0.6
0.4
0.2
0
30
Gain
T
= 25°C
A
60
T
= 25°C
A
90
T
= 125°C
Phase
1.0 M
A
T
= –55
4.0
°C
120
A
0
150
180
– 20
10
100
1.0 k
10 k
100 k
10 M
0
2.0
6.0
8.0
f, FREQUENCY (Hz)
V
, ERROR AMP OUTPUT VOLTAGE (V)
O
4
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 7. Reference Voltage Change
versus Source Current
Figure 8. Reference Short Circuit Current
versus Temperature
0
–4.0
–8.0
–12
–16
–20
–24
110
V
= 15 V
CC
V
R
= 15 V
≤ 0.1 Ω
CC
L
90
70
T
= 125°C
A
T
= –55°C
A
T
= 25°C
A
50
–55
0
20
40
60
80
100
120
–25
0
25
50
75
C)
100
125
I
, REFERENCE SOURCE CURRENT (mA)
T , AMBIENT TEMPERATURE (
°
ref
A
Figure 9. Reference Load Regulation
Figure 10. Reference Line Regulation
V
= 15 V
= 1.0 mA to 20 mA
= 25°C
CC
V
= 12 V to 25 V
CC
= 25°C
I
T
O
T
A
A
2.0 ms/DIV
2.0 ms/DIV
Figure 11. Output Saturation Voltage
versus Load Current
Figure 12. Output Waveform
0
–1.0
–2.0
Source Saturation
(Load to Ground)
V
= 15 V
CC
V
CC
80
µs Pulsed Load
120 Hz Rate
V
C
= 15 V
= 1.0 nF
= 25°C
CC
L
T
= 25°C
A
90%
T
A
T
= –55°C
A
3.0
2.0
1.0
0
T
= –55°C
A
T
= 25°C
A
10%
Sink Saturation
Gnd
600
(Load to V
)
CC
50 ns/DIV
0
200
400
800
I
, OUTPUT LOAD CURRENT (mA)
O
5
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 14. Supply Current versus
Supply Voltage
Figure 13. Output Cross Conduction
25
20
15
10
5
V
= 30 V
= 15 pF
= 25°C
CC
L
C
T
A
R
C
= 10 k
= 3.3 nF
= 0 V
= 0 V
T
T
V
I
T
FB
Sense
= 25°C
A
0
0
10
20
30
40
100 ns/DIV
V
, SUPPLY VOLTAGE (V)
CC
PIN FUNCTION DESCRIPTION
Pin
8–Pin
14–Pin
Function
Description
This pin is Error Amplifier output and is made available for loop compensation.
1
2
1
3
Compensation
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3
4
5
7
Current Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
R /C
T
The Oscillator frequency and maximum Output duty cycle are programmed by connecting
T
resistor R to V and capacitor C to ground. Operation to 1.0 MHz is possible.
T
ref
T
5
6
–
Gnd
This pin is combined control circuitry and power ground (8–pin package only).
10
Output
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin. The output switches at one–half the oscillator frequency.
7
8
–
12
14
8
V
This pin is the positive supply of the control IC.
CC
V
ref
This is the reference output. It provides charging current for capacitor C through resistor R .
T T
Power Ground
This pin is a separate power ground return (14–pin package only) that is connected back to the
power source. It is used to reduce the effects of switching transient noise on the control circuitry.
–
11
V
C
The Output high state (V
a separate power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
) is set by the voltage applied to this pin (14–pin package only). With
OH
–
–
9
Gnd
NC
This pin is the control circuitry ground return (14–pin package only) and is connected to back to
the power source ground.
2,4,6,13
No connection (14–pin package only). These pins are not internally connected.
6
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
OPERATING DESCRIPTION
Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
The UC3844, UC3845 series are high performance, fixed
frequency, current mode controllers. They are specifically
designed for Off–Line and dc–to–dc converter applications
offering the designer a cost effective solution with minimal
external components. A representative block diagram is
shown in Figure 15.
voltage (V
) to reach the comparator’s 1.0 V clamp level:
OH
3.0 (1.0 V) + 1.4 V
R
≈
= 8800 Ω
f(min)
0.5 mA
Oscillator
Current Sense Comparator and PWM Latch
The oscillator frequency is programmed by the values
The UC3844, UC3845 operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the inductor current on a cycle–by–cycle basis. The current
Sense Comparator PWM Latch configuration used ensures
that only a single pulse appears at the Output during any
given oscillator cycle. The inductor current is converted to a
selected for the timing components R and C . Capacitor C
is charged from the 5.0 V reference through resistor R to
T
approximately 2.8 V and discharged to 1.2 V by an internal
T
T
T
current sink. During the discharge of C , the oscillator
T
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in a
low state, thus producing a controlled amount of output
deadtime. An internal flip–flop has been incorporated in the
UCX844/5 which blanks the output off every other clock cycle
by holding one of the inputs of the NOR gate high. This in
voltage by inserting the ground referenced sense resistor R
S
in series with the source of output switch Q1. This voltage is
monitored by the Current Sense Input (Pin 3) and compared
a level derived from the Error Amp Output. The peak inductor
current under normal operating conditions is controlled by the
voltage at pin 1 where:
combination with the C discharge period yields output
T
deadtimes programmable from 50% to 70%. Figure 1 shows
R
versus Oscillator Frequency and figure 2, Output
T
Deadtime versus Frequency, both for given values of C .
Note that many values of R and C will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency.
T
T
T
V
– 1.4 V
(Pin 1)
3 R
S
I
pk
=
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 17. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 18. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved to realize output deadtimes of greater than 70%
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
1.0 V
I
=
pk(max)
R
S
Error Amplifier
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 5). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 µA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 28). The output voltage is offset by two
diode drops (≈ 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
order to keep the power dissipation of R to a reasonable
S
level. A simple method to adjust this voltage is shown in
Figure 19. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the I
voltage.
clamp
pk(max)
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 23.
when Pin 1 is at its lowest state (V ). This occurs when the
OL
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 20, 21). The Error
7
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 15. Representative Block Diagram
V
V
in
CC
V
CC
7(12)
36V
V
+
–
ref
Reference
Regulator
8(14)
V
+
CC
R
R
Internal
Bias
UVLO
–
2.5V
+
V
C
–
+
R
T
7(11)
V
ref
UVLO
3.6V
–
Q1
Output
6(10)
Oscillator
4(7)
2(3)
T
Q
Q
+
C
T
1.0mA
Power Ground
5(8)
S
+
–
–
+
R
Voltage Feedback
Input
PWM
Latch
2R
Error
R
Current Sense Input
3(5)
1.0V
Output
Compensation
Amplifier
Current Sense
Comparator
1(1)
R
S
Gnd
5(9)
+
–
Sink Only
Positive True Logic
=
Pin numbers in parenthesis are for the D suffix SO–14 package.
Figure 16. Timing Diagram
Capacitor C
T
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
Large R /Small C
Small R /Large C
T T
T
T
8
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Undervoltage Lockout
added flexibility in tailoring the drive voltage independent of
A zener clamp is typically connected to this input when
V
Two undervoltage lockout comparators have been
incorporated to guartantee that the IC is fully functional before
the output stage is enabled. The positive power supply
CC.
driving power MOSFETs in systems where V
is greater the
CC
20 V. Figure 22 shows proper power and control ground
connections in a current sensing power MOSFET
application.
terminal (V
and the reference output (V ) are each
CC
ref
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
Reference
respective thresholds are crossed. The V
comparator
CC
upper and lower thresholds are 16 V/10 V for the UCX844,
and 8.4 V/7.6 V for the UCX845. The V comparator upper
The 5.0 V bandgap reference is trimmed to ± 1.0%
tolerance at T = 25°C on the UC284X, and ± 2.0% on the
J
ref
UC384X. Its primary purpose is to supply charging current to
the oscillator timing capacitor. The reference has short circuit
protection and is capable of providing in excess of 20 mA for
powering additional control system circuitry.
and lower thresholds are 3.6 V/3/4 V. The large hysteresis
and low startup current of the UCX844 makes it ideally suited
in off–line converter applications where efficient bootstrap
startup techniques later required (Figure 29). The UCX845 is
intended for lower voltage dc–to–dc converter applications. A
Design Considerations
36 V zener is connected as a shunt regulator from V
to
CC
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
ground. Its purpose is to protect the IC from excessive
voltage that can occur during system startup. The minimum
operating voltage for the UCX844 is 11 V and 8.2 V for the
UCX845.
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ± 1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever and undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
bypass capacitors (0.1 µF) connected directly to V , V ,
CC
C
and V may be required depending upon circuit layout. This
ref
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
The SO–14 surface mount package provides separate
pins for V (output supply) and Power Ground. Proper
C
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomesparticularlyusefulwhenreducingtheI
clamp
pk(max)
level. The separate V supply input allows the designer
C
Figure 18. External Duty Cycle Clamp and
Multi–Unit Synchronization
Figure 17. External Clock Synchronization
V
ref
8(14)
R
R
8(14)
R
R
Bias
R
R
A
R
T
Bias
4
8
B
5.0k
6
Osc
+
External
Sync
Input
Osc
+
4(7)
R
S
–
C
T
3
0.01
+
4(7)
5
2
Q
+
–
+
–
+
–
2R
R
7
EA
47
2(3)
1(1)
2R
R
5.0k
1
EA
2(3)
1(1)
C
MC1455
5(9)
5(9)
To Additional
UCX84XA’s
R
B
1.44
(R + 2R )C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f =
D
=
max
R
+ 2R
B
A
B
A
9
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 19. Adjustable Reduction of Clamp Level
Figure 20. Soft–Start Circuit
V
CC
V
in
7(12)
5.0V
+
–
ref
5.0V
ref
8(14)
R
R
+
8(14)
R
R
Bias
+
–
–
Bias
+
+
–
+
7(11)
6(10)
5(8)
–
–
Q1
Osc
Osc
T
+
4(7)
2(3)
T
+
4(7)
V
Clamp
S
1.0mA
2R
+
–
1.0mA
2R
S
Q
–
+
–
Q
R
–
+
R2
R
EA
+
EA
2(3)
1(1)
R
Comp/Latch
R
1.0V
1.0V
3(5)
1(1)
t
C
R
S
R1
5(9)
5(9)
3600C in µF
Soft–Start
1.67
2
R
R
2
V
1
Clamp
–3
+ 0.33 x 10
V
Clamp
I
pk(max)
≈
R
+ R
R
1
2
S
R
R
+ 1
Where: 0
≤
V
≤
1.0 V
Clamp
1
Figure 21. Adjustable Buffered Reduction of
Figure 22. Current Sensing Power MOSFET
Clamp Level with Soft–Start
V
CC
R
I
r
S
pk DS(on)
V
V
in
CC
V
5 ≈
V
(12)
Pin
in
r
+ R
DM(on)
S
7(12)
If: SENSEFET = MTP10N10M
+
–
R
= 200
5.0V
ref
S
+
–
+
5.0V
ref
Then: V
SENSEFET
5 = 0.075 I
pk
+
pin
8(14)
4(7)
R
R
–
+
D
–
Bias
–
+
+
–
(11)
(10)
(8)
+
S
7(11)
6(10)
5(8)
–
–
Q1
Osc
G
T
K
T
M
+
V
Clamp
S
S
Q
1.0mA
2R
–
+
–
R
Q
+
–
R
Power Ground
To Input Source
Return
+
Comp/Latch
EA
2(3)
1(1)
Comp/Latch
R
R2
(5)
R
1.0V
3(5)
S
1/4 W
R
S
Control CIrcuitry
Ground:
To Pin (9)
5(9)
–3
MPSA63
C
R1
1.67
2
R
R
2
V
1
Clamp
+ 0.33 x 10
R
+ R
R
R
1
2
Virtually lossless current sensing can be achieved with the implement of a SENSEFET
power switch. For proper operation during over current conditions, a reduction of the
+ 1
1
V
I
clamp level must be implemented. Refer to Figures 19 and 21.
Clamp
pk(max)
I
≈
Where: 0
V
≤
V
≤ 1.0 V
pk(max)
Clamp
C
R
S
R
R
C
1
2
t
= – In
1 –
Softstart
3V
R
+ R
Clamp
1 2
Figure 23. Current Waveform Spike Suppression
V
CC
V
in
7(12)
+
5.0V
ref
–
+
–
+
–
+
7(11)
6(10)
5(8)
–
Q1
T
S
Q
–
R
+
R
Comp/Latch
3(5)
The addition of the RC filter will eliminate
instabilitycaused by the leading edge spike on
the current waveform.
C
R
S
10
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 24. MOSFET Parasitic Oscillations
Figure 25. Bipolar Transistor Drive
V
I
CC
B
V
in
V
in
7(12)
+
0
+
–
5.0V
ref
Base Charge
Removal
+
–
–
+
C
1
–
+
7(11)
6(10)
5(8)
R
–
Q1
g
Q1
T
6(1)
S
Q
–
R
5(8)
3(5)
+
Comp/Latch
3(5)
R
R
S
S
The totem–pole output can furnish negative base current for enhanced
Series gate resistor R will damp any high frequency parasitic oscillations
g
causedbytheMOSFETinputcapacitanceandanyserieswiringinductance
in the gate–source circuit.
transistor turn–off, with the addition of capacitor C .
1
Figure 26. Isolated MOSFET Drive
Figure 27. Latched Shutdown
V
V
CC
in
7(12)
8(14)
R
R
+
–
Isolation
Boundary
Bias
5.0V
ref
+
–
+
V
Waveforms
GS
–
Q1
+
Osc
7(11)
6(10)
5(8)
+
0
–
+
0
+
–
4(7)
1.0mA
2R
–
T
+
–
50% DC
V
25% DC
S
EA
– 1.4
N
N
2(3)
1(1)
(pin 1)
P
S
Q
–
I
=
R
R
pk
+
3 R
S
R
Comp/Latch
3(5)
C
N
S
R
S
N
p
2N
3905
MCR
101
5(9)
2N
3903
The MCR101 SCR must be selected for a holding of less than 0.5 mA at
. The simple two transistor circuit can be used in place of the SCR as
T
A(min)
shown. All resistors are 10 k.
Figure 28. Error Amplifier Compensation
From V
O
From V
O
2.5V
+
2.5V
+
R
i
1.0mA
2R
2(3)
1.0mA
2R
+
R
p
2(3)
R
–
+
–
i
EA
R
C
d
I
R
EA
f
R
C
R
I
R
d
f
R
C
p
1(1)
1(1)
5(9)
R
≥
8.8 k
5(9)
f
ErrorAmpcompensationcircuitforstabilizinganycurrent–modetopologyexcept
for boost and flyback converters operating with continuous inductor current.
Error Amp compensation circuit for stabilizing current–mode boost and flyback
topologies operating with continuous inductor current.
11
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 29. 27 Watt Off–Line Flyback Regulator
L1
MBR1635
2200
+
4.7Ω
3300pF
MDA
202
4.7k
250
5.0V/4.0A
T1
+
+
+
+
1000
56k
115Vac
5.0V RTN
12V/0.3A
MUR110
1000
1N4935
68
1N4935
L2
10
7(12)
+
+
±
12V RTN
47
100
1000
10
L3
8(14)
+
–
+
+
5.0V
ref
–12V/0.3A
+
0.01
MUR110
680pF
1N4937
Bias
+
–
+
33k
7(11)
1N4937
2.7k
4(7)
2(3)
22
Ω
Osc
T
S
6(10)
+
MTP
4N50
1.0nF
1N5819
18k
+
–
Q
–
+
5(8)
3(5)
R
EA
Comp/Latch
4.7k
1.0k
470pF
1(1)
0.5Ω
5(9)
T1 – Primary: 45 Turns # 26 AWG
T1 – Secondary 12 V: 9 Turns # 30 AWG
±
T1 – (2 strands) Bifiliar Wound
T1 – Secondary 5.0 V: 4 Turns (six strands)
T1 – #26 Hexfiliar Wound
T1 – Secondary Feedback: 10 Turns #30 AWG
T1 – (2 strands) Bifiliar Wound
Test
Conditions
= 95 Vac to 130 Vac
Results
Line Regulation: 5.0 V
V
in
∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
± 12 V
T1 – Core: Ferroxcube EC35–3C8
T1 – Bobbin: Ferroxcube EC35PCB1
Load Regulation: 5.0 V
V
V
= 115 Vac, I
= 115 Vac, I
= 1.0 A to 4.0 A
= 100 mA to 300 mA ∆ = 60 mV or ± 0.25%
∆ = 300 mV or ± 3.0%
in
in
out
out
T1 – Gap
≈
0.01” for a primary inductance of 1.0 mH
± 12 V
L1 – 15
µH at 5.0 A, Coilcraft Z7156.
Output Ripple:
5.0 V
V
in
= 115 Vac
40 mV
80 mV
pp
pp
L2, L3 – 25
µH at 1.0 A, Coilcraft Z7157.
± 12 V
Efficiency
V
in
= 115 Vac
70%
All outputs are at nominal load currents, unless otherwise noted.
12
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
Figure 30. Step–Up Charge Pump Converter
V
= 15V
in
+
UC3845
Output Load Regulation
(open loop configuration)
7(12)
47
I
(mA)
V
(V)
O
O
34V
8(14)
+
Reference
Regulator
0
2
9
18
36
29.9
28.8
28.3
27.4
24.4
–
V
+
1N5819
CC
UVLO
R
R
Internal
Bias
–
2.5V
+
7(11)
6(10)
5(8)
–
+
10k
V
ref
UVLO
3.6V
–
15 10
1N5819
4(7)
Oscillator
V
2 (V )
in
O
+
+
T
47
+
1.0nF
Connect to
Pin 2 for
closed loop
operation.
0.5mA
S
R2
2R
+
–
Q
2(3)
1(1)
–
+
R
PWM
Latch
Error
Amplifier
R
1.0V
3(5)
R2
R2
V
R1
O = 2.5
+ 1
Current Sense
Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series
resistor may be required when using tantalum or other low ESR capacitors. The converter’s output can provide
excellent line and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Voltage–Inverting Charge Pump Converter
V
= 15V
in
+
UC3845
7(12)
47
34V
8(14)
+
Reference
Regulator
–
V
+
CC
UVLO
R
R
Internal
Bias
–
2.5V
+
7(11)
–
+
10k
V
ref
UVLO
3.6V
–
15 10
1N5819
+
4(7)
6(10)
+
Oscillator
V
– (V )
in
O
T
1N5819
47
+
1.0nF
0.5mA
5(8)
S
2R
+
–
Q
2(3)
1(1)
–
+
R
PWM
Latch
Output Load Regulation
Error
R
1.0V
3(5)
I
(mA)
V
(V)
O
O
Amplifier
0
2
9
18
32
–14.4
–13.2
–12.5
–11.7
–10.6
Current Sense
Comparator
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.
13
MOTOROLA ANALOG IC DEVICE DATA
UC3844, 45 UC2844, 45
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
–B–
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
1
4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
F
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
9.40
6.10
3.94
0.38
1.02
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
–A–
NOTE 2
0.370
0.240
0.155
0.015
0.040
L
C
G
H
J
K
L
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
J
–T–
SEATING
PLANE
7.62 BSC
0.300 BSC
N
M
N
–––
10
–––
10
M
0.76
1.01
0.030
0.040
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A–
ISSUE F
14
1
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B–
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
0.25 (0.010)
B
7
MILLIMETERS
INCHES
G
DIM
A
B
C
D
F
G
J
K
M
P
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
C
0.337
0.150
0.054
0.014
0.016
–T–
SEATING
PLANE
J
M
1.27 BSC
0.050 BSC
K
D 14 PL
0.25 (0.010)
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
T
B
A
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
R
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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