XPC860DHZP33C1 [MOTOROLA]
32-BIT, 33MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357;
| 型号： | XPC860DHZP33C1 |
| 厂家： | 
MOTOROLA |
| 描述： | 32-BIT, 33MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357 时钟 外围集成电路 |
| 文件： | 总64页 (文件大小：785K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC860EC/D
(Motorola Order Number)
10/1999
REV. 4
ª
Advance Information
MPC860 Family Hardware
SpeciÞcations
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing speciÞcations for the MPC860 family. These same
speciÞcations also apply to the MPC860P. In this document, the term ÔMPC860Õ generally
refers to all MPC860 family members including the MPC860P.
This document contains the following topics:
Topic
Page
Section 1.1, ÒOverviewÓ
2
Section 1.2, ÒFeaturesÓ
2
Section 1.3, ÒElectrical and Thermal CharacteristicsÓ
Section 1.4, ÒThermal CharacteristicsÓ
Section 1.5, ÒPower ConsiderationsÓ
5
6
7
Section 1.6, ÒBus Signal TimingÓ
8
Section 1.7, ÒIEEE 1149.1 Electrical SpeciÞcationsÓ
Section 1.8, ÒCPM Electrical CharacteristicsÓ
Section 1.9, ÒMechanical Data and Ordering InformationÓ
Section 1.10, ÒDocument Revision HistoryÓ
33
35
57
62
This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product
without notice.
© Motorola Inc., 1998. All rights reserved.
1.1 Overview
The MPC860 PowerPCª Quad Integrated Communications Controller (PowerQUICCª) is a versatile
one-chip integrated microprocessor and peripheral combination designed for a variety of controller
applications. It particularly excels in both communications and networking systems. The PowerQUICC unit
is referred to as the MPC860 in this manual.
The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad Integrated
ª
Communications Controller (QUICC ), referred to here as the QUICC. The CPU on the MPC860 is a 32-
bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and
data caches. The communications processor module (CPM) from the MC68360 QUICC has been enhanced
2
by the addition of the inter-integrated controller (I C) channel. Digital signal processing (DSP) functionality
has been added to the CPM. The memory controller has been enhanced, enabling the MPC860 to support
any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also been integrated.
1.2 Features
The following list summarizes the key MPC860 features:
¥
¥
Embedded PowerPC core
Single-issue, 32-bit version of the core (compatible the PowerPC architecture deÞnition) with 32,
32-bit general-purpose registers (GPRs)
Ñ The core performs branch prediction with conditional prefetch, without conditional execution
Ñ 4-Kbyte data cache and 4-Kbyte instruction cache
Ñ Instruction and data caches are two-way, set-associative, physical address, least recently used
(LRU) replacement, lockable on-line granularity
Ñ MMUs with 32 entry TLB, fully associative instruction and data TLBs
Ñ MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
Ñ Advanced on-chip-emulation debug mode
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
¥
¥
¥
¥
Complete static design (0Ð40 MHz operation)
Memory controller (eight banks)
Ñ Contains complete dynamic RAM (DRAM) controller
Ñ Each bank can be a chip select or RAS to support a DRAM bank
Ñ Up to 15 wait states programmable per memory bank
Ñ Glueless interface to DRAM, SIMMS, SRAM, EPROM, ßash EPROM, and other memory
devices.
Ñ DRAM controller programmable to support most size and speed memory interfaces
Ñ Four CAS lines, four WE lines, one OE line
Ñ Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Ñ Variable block sizes (32 KbyteÐ256 Mbyte)
2
MPC860 Hardware SpeciÞcations
MOTOROLA
Ñ Selectable write protection
Ñ On-chip bus arbitration logic
General-purpose timers
¥
¥
Ñ Four 16-bit timers or two 32-bit timers
Ñ Gate mode can enable/disable counting
Ñ Interrupt can be masked on reference match and event capture
System integration unit (SIU)
Ñ Bus monitor
Ñ Software watchdog
Ñ Periodic interrupt timer (PIT)
Ñ Low-power stop mode
Ñ Clock synthesizer
Ñ PowerPC decrementer, time base, and real-time clock (RTC)
Ñ Reset controller
Ñ IEEE 1149.1 test access port (JTAG)
Interrupts
¥
¥
Ñ Seven external interrupt request (IRQ) lines
Ñ 12 port pins with interrupt capability
Ñ 23 internal interrupt sources
Ñ Programmable priority between SCCs
Ñ Programmable highest priority request
Communications processor module (CPM)
Ñ RISC communications processor (CP)
Ñ Communication-speciÞc commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT
MODE, and RESTART TRANSMIT)
Ñ Supports continuous mode transmission and reception on all serial channels
Ñ Up to 5 Kbytes of dual-port RAM
Ñ 16 serial DMA (SDMA) channels
Ñ Three parallel I/O registers with open-drain capability
On-chip 16x16 multiply accumulate controller (MAC)
Ñ One operation per clock (two clock latency, one clock blockage)
Ñ MAC operates concurrently with other instructions
Ñ FIR loop: four clocks per four multiplies
Four baud-rate generators (BRGs)
¥
¥
¥
Ñ Independent (can be connected to any SCC or SMC)
Ñ Allow changes during operation
Ñ Autobaud support option
Four serial communications controllers (SCCs)
MOTOROLA
MPC860 Hardware SpeciÞcations
3
Ñ Ethernet/IEEE 802.3 optional on SCC1Ð4, supporting full 10-Mbps operation (Available only
on specially programmed devices)
Ñ HDLC/SDLC (all channels supported at 2 Mbps)
Ñ HDLC bus (implements an HDLC-based local area network (LAN))
Ñ Asynchronous HDLC to support PPP (point-to-point protocol)
Ñ AppleTalk
Ñ Universal asynchronous receiver transmitter (UART)
Ñ Synchronous UART
Ñ Serial infrared (IrDA)
Ñ Binary synchronous communication (BISYNC)
Ñ Totally transparent (bit streams)
Ñ Totally transparent (frame based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
Ñ UART
¥
¥
Ñ Transparent
Ñ General circuit interface (GCI) controller
Ñ Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
Ñ Supports master and slave modes
Ñ Supports multimaster operation on the same bus
2
¥
¥
One I C (inter-integrated circuit) port
Ñ Supports master and slave modes
Ñ Multiple-master environment support
Time-slot assigner (TSA)
Ñ Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
Ñ Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user deÞned
Ñ 1- or 8-bit resolution
Ñ Allows independent transmit and receive routing, frame synchronization, clocking
Ñ Allows dynamic changes
Ñ Can be internally connected to six serial channels (four SCCs and two SMCs)
Parallel interface port (PIP)
¥
¥
Ñ Centronics interface support
Ñ Supports fast connection between compatible ports on the MPC860 or the MC68360
PCMCIA interface
Ñ Master (socket) interface, release 2.1 compliant
Ñ Supports two independent PCMCIA sockets
Ñ 8 memory or I/O windows supported
4
MPC860 Hardware SpeciÞcations
MOTOROLA
¥
Low power support
Ñ Full onÑAll units fully powered
Ñ DozeÑCore functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
Ñ SleepÑAll units disabled except RTC and PIT, PLL active for fast wake up
Ñ Deep sleepÑAll units disabled including PLL except RTC and PIT
Ñ Power down modeÑ All units powered down except PLL, RTC, PIT, time base and
decrementer
¥
Debug interface
Ñ Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
Ñ Supports conditions: = ¹ < >
Ñ Each watch-point can generate a break-point internally
3.3 V operation with 5-V TTL compatibility
357-pin ball grid array (BGA) package
¥
¥
1.3 Electrical and Thermal Characteristics
This section provides the AC and DC electrical speciÞcations and thermal characteristics for the MPC860.
Table 4 provides the maximum ratings.
Table 4. Maximum Ratings
(GND = 0V)
Rating
Symbol
VDDH
VDDL
KAPWR
VDDSYN
Value
Unit
1
Supply voltage
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
V
V
V
V
2
Input voltage
V
GND-0.3 to VDDH + 2.5V
0
95
-40
V
in
3
Temperature (standard)
T
ûC
ûC
ûC
ûC
ûC
A(min)
T
j(max)
3
Temperature (extended)
T
A(min)
T
T
95
j(max)
stg
Storage temperature range
-55 to +150
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical speciÞcations in Table 7. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device.
Caution: All inputs that tolerate 5 V cannot be more than 2.5 V greater than the supply voltage.This restriction applies
to power-up and normal operation (that is, if the MPC860 is unpowered, voltage greater than 2.5 V must not be applied
to its inputs).
3
Minimum temperatures are guaranteed as ambient temperature, T Maximum temperatures are guaranteed as
A.
junction temperature, T
j
This device contains circuitry protecting against damage due to high-static voltage or electrical Þelds;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
MOTOROLA
MPC860 Hardware SpeciÞcations
5
inputs are tied to an appropriate logic voltage level (for example, either GND or V ). Table 5 provides the
CC
package thermal characteristics for the MPC860.
1.4 Thermal Characteristics
Table 5 shows the thermal characteristics for the MPC860.
Table 5. Thermal Characteristics
Characteristic
Symbol
Value
Unit
1
2
Thermal resistance for BGA
qJA
qJA
qJA
qJC
47
°C/W
°C/W
°C/W
°C/W
3
30
15
4
Thermal Resistance for BGA (junction-to-case)
4.9
1
For more information on the design of thermal vias on multilayer boards and BGA layout considerations in
general, refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Motorola sales
ofÞce.
2
Assumes natural convection and a single layer board (no thermal vias).
3
Assumes natural convection, a multilayer board with thermal vias, 1-W MPC860 dissipation, and a board
temperature rise of 20°C above ambient.
4
Assumes natural convection, a multilayer board with thermal vias,1-W MPC860 dissipation, and a board
temperature rise of 10°C above ambient.
TJ = TA + (PD qJA
)
¥
P
D = (VDD IDD) + PI/O
¥
where:
PI/O is the power dissipation on pins.
Table 6 provides power dissipation information.
Table 6. Power Dissipation (P )
D
1
2
Die Revision
Frequency
25 MHz
Typical
450
Maximum
Unit
mW
A.3 and previous
550
40 MHz
50 MHz
33 MHz
50 MHz
66 MHz
700
870
375
575
750
850
mW
mW
mW
mW
mW
1050
TBD
TBD
TBD
B.1 and later
1
Maximum power dissipation is measured at 3.65V.
Typical power dissipation is measured at 3.3V.
2
Table 7 provides the DC electrical characteristics for the MPC860.
Table 7. DC Electrical Specifications
Symbol
Characteristic
Min
Max
Unit
Operating voltage at 40 MHz or less
VDDH,
3.0
3.6
V
VDDL, VDDSYN
KAPWR (power-down mode) 2.0
KAPWR (all other operating VDDH - 0.4 VDDH
modes)
3.6
V
V
6
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 7. DC Electrical Specifications (Continued)
Characteristic
Operating voltage at 40 MHz or higher
Symbol
Min
3.135
Max
3.465
Unit
VDDH,
VDDL, KAPWR, VDDSYN
KAPWR (power-down mode) 2.0
KAPWR (all other operating VDDH - 0.4 VDDH
modes)
V
3.6
V
V
Input High Voltage (all inputs except EXTAL and EXTCLK) VIH
2.0
GND
5.5
0.8
V
V
Input Low Voltage
VIL
EXTAL, EXTCLK Input High Voltage
VIHC
0.7*(VCC) VCC+0.3 V
Input Leakage Current, Vin = 5.5V (Except TMS, TRST,
DSCK and DSDI pins)
Input Leakage Current, Vin = 3.6V (Except TMS, TRST,
DSCK, and DSDI)
Input Leakage Current, Vin = 0V (Except TMS, TRST,
DSCK and DSDI pins)
I
I
I
Ñ
Ñ
Ñ
100
µA
µA
µA
in
In
In
10
10
Input Capacitance
Output High Voltage, IOH = -2.0 mA, VDDH = 3.0V
Except XTAL, XFC, and Open drain pins
C
VOH
Ñ
2.4
20
Ñ
pF
V
in
Output Low Voltage
VOL
Ñ
0.5
V
IOL = 2.0 mA CLKOUT
1
IOL = 3.2 mA
2
IOL = 5.3 mA
IOL = 7.0 mA TXD1/PA14, TXD2/PA12
IOL = 8.9 mA TS, TA, TEA, BI, BB, HRESET, SRESET
1
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/
VFLS(0:1), IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/
PTR/AT3, RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/
BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/
BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0,
REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/
I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1/SDACK1/PB23, SMSYN2/SDACK2/PB22, SMTXD2/
L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/
L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/
L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, SDACK2/
L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/L1TSYNCA/PC5, L1RSYNCA/PC4, PD15, PD14, PD13, PD12, PD11,
PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3
2
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/
IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/
GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1,
OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30)
1.5 Power Considerations
The average chip-junction temperature, T , in °C can be obtained from the equation:
J
T = T + (P
q )(1)
JA
J
A
¥
D
where
TA = Ambient temperature, ¡C
qJA = Package thermal resistance, junction to ambient, ¡C/W
PD = PINT + PI/O
MOTOROLA
MPC860 Hardware SpeciÞcations
7
PINT = IDD x VDD, wattsÑchip internal power
PI/O = Power dissipation on input and output pinsÑuser determined
For most applications PI/O < 0.3 PINT and can be neglected. If PI/O is neglected, an approximate relationship
¥
between PD and TJ is:
PD = K Ö (TJ + 273¡C)(2)
Solving equations (1) and (2) for K gives:
2
K = PD ¥ (TA + 273¡C) + qJA ¥ PD (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving
equations (1) and (2) iteratively for any value of TA.
1.5.1 Layout Practices
Each VCC pin on the MPC860 should be provided with a low-impedance path to the boardÕs supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The VCC power supply should be bypassed to ground using at least four 0.1
µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip VCC and GND should be kept to less than half an inch
per capacitor lead.A four-layer board is recommended, employing two inner layers asVCC and GND planes.
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reßections caused by these fast output switching
times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths
of six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
1.6 Bus Signal Timing
Table 8 provides the bus operation timing for the MPC860 (devices marked with date code 9829 and later)
at 33 MHz and 50 MHz. Timing information for other bus speeds can be interpolated by equation using the
MPC860 Electrical SpeciÞcations Spreadsheet v2.0 found at http://www.mot.com/netcomm. For devices
marked with date codes earlier than 9829, refer to the MPC860 Electrical SpeciÞcations Spreadsheet v1.1.
The maximum bus speed supported by the MPC860 is 50 MHz. Higher-speed parts must be operated in half-
speed bus mode (for example, an MPC860 used at 66 MHz must be conÞgured for a 33 MHz bus).
The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays. For loads other than 50 pF, maximum delays can be derated by 1 ns per 10 pF. Derating
calculations can also be performed using either version of the MPC860 Electrical SpeciÞcations
Spreadsheet.
When operating at frequencies other than the frequency marked on the part, new bus timing must be
calculated for all frequency-dependent AC parameters. Frequency-dependent AC parameters are those with
an entry in the ÔFFACT.Õ column. AC parameters without an FFactor entry are not frequency-dependent and
therefore do not need to be recalculated.
8
MPC860 Hardware SpeciÞcations
MOTOROLA
To calculate the AC parameters for a frequency F, the following equation should be applied to each one of
the above parameters:
for minima:
FFACTOR(1000 - 20 x F)
D = D
+
50
F
where
D is the parameter value in nanoseconds for the frequency required
F is the operation frequency in MHz
D50 is the parameter deÞned for 50 MHz
FFACTOR is the one deÞned for each on of the parameters in the table.
Table 8 shows the bus operation timings for the MPC860.
Table 8. Bus Operation Timings
50 MHz
1
33 MHz
Num
Characteristic
Unit
FFACT.
Min
Max
Min
Max
B1 CLKOUT period
B1a EXTCLK to CLKOUT phase skew (EXTCLK > 15 MHz
and MF <= 2)
B1b EXTCLK to CLKOUT phase skew (EXTCLK > 10 MHz
and MF < 10)
20
30.30
ns
ns
-0.90 0.90 -0.90
0.90
2.30
0.60
-2.30 2.30 -2.30
ns
ns
B1c CLKOUT phase jitter (EXTCLK > 15 MHz and MF <= 2) -0.60 0.60 -0.60
2
2
B1d CLKOUT phase jitter
-2.00 2.00 -2.00
2.00
0.50
2.00
3.00
0.50
ns
%
%
%
%
2
B1e CLKOUT frequency jitter (MF < 10)
B1f CLKOUT frequency jitter (10 < MF < 500)
B1g CLKOUT frequency jitter (MF > 500)
B1h Frequency jitter on EXTCLK
0.50
2.00
3.00
0.50
2
2
3
B2 CLKOUT pulse width low
B3 CLKOUT width high
B4 CLKOUT rise time
B5 CLKOUT fall time
B6
8.00
8.00
12.12
12.12
ns
ns
ns
ns
4.00
4.00
4.00
4.00
B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST,
D(0:31), DP(0:3) invalid
B7a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR
invalid
5.00
5.00
7.58
7.58
7.58
ns
ns
ns
ns
ns
ns
ns
0.250
0.250
0.250
0.250
0.250
0.250
0.250
B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2) IWP(0:2), 5.00
4
LWP(0:1), STS invalid
B8 CLKOUT to A(0:31), BADDR(28:30) RD/WR, BURST,
D(0:31), DP(0:3) valid
B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP, PTR
valid
5.00 11.75 7.58 14.33
5.00 11.75 7.58 14.33
5.00 11.75 7.58 14.33
5.00 11.75 7.58 14.33
B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2),
4
FRZ, LWP(0:1), STS Valid
B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST,
D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR
High-Z
B10
B11 CLKOUT to TS, BB assertion
5.00 11.00 7.58 13.58
ns
0.250
MOTOROLA
MPC860 Hardware SpeciÞcations
9
Table 8. Bus Operation Timings (Continued)
1
50 MHz
33 MHz
Num
Characteristic
Unit
FFACT.
Min
Max
Min
Max
B11a CLKOUT to TA, BI assertion (when driven by the
memory controller or PCMCIA interface)
2.50
9.25
2.50
9.25
ns
B12 CLKOUT to TS, BB negation
B12a CLKOUT to TA, BI negation (when driven by the
memory controller or PCMCIA interface)
B13 CLKOUT to TS, BB High-Z
B13a CLKOUT to TA, BI High-Z (when driven by the memory 2.50 15.00 2.50 15.00
controller or PCMCIA interface)
5.00 11.75 7.58 14.33
2.50 11.00 2.50 11.00
ns
ns
0.250
0.250
5.00 19.00 7.58 21.58
ns
ns
B14 CLKOUT to TEA assertion
B15 CLKOUT to TEA High-Z
B16 TA, BI valid to CLKOUT (setup time)
B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time)
B16b BB, BG, BR, valid to CLKOUT (setup time)
2.50 10.00 2.50 10.00
2.50 15.00 2.50 15.00
ns
ns
ns
ns
ns
ns
ns
ns
9.75
10.00
8.50
1.00
2.00
6.00
9.75
10.00
8.50
1.00
2.00
6.00
5
B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time).
B17a CLKOUT to KR, RETRY, CR valid (hold time)
B18 D(0:31), DP(0:3) valid to CLKOUT rising edge (setup
6
time)
B19 CLKOUT rising edge to D(0:31), DP(0:3) valid (hold
1.00
4.00
2.00
1.00
4.00
2.00
ns
ns
6
time)
B20 D(0:31), DP(0:3) valid to CLKOUT falling edge (setup
7
time)
B21 CLKOUT falling edge to D(0:31), DP(0:3) valid (hold
7
Time)
B22 CLKOUT rising edge to CS asserted GPCM ACS = 00
B22a CLKOUT falling edge to CS asserted GPCM ACS = 10,
TRLX = 0
5.00 11.75 7.58 14.33
8.00 8.00
ns
ns
0.250
B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, 5.00 11.75 7.58 14.33
TRLX = 0, EBDF = 0
B22c CLKOUT falling edge to CS asserted GPCM ACS = 11, 7.00 14.13 10.86 17.99
TRLX = 0, EBDF = 1
ns
ns
ns
0.250
0.375
B23 CLKOUT rising edge to CS negated GPCM read
access, GPCM write access ACS = 00, TRLX = 0 &
CSNT = 0
2.00
8.00
2.00
8.00
B24 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS 3.00
= 10, TRLX = 0.
B24a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS 8.00
= 11 TRLX = 0
5.58
ns
ns
0.250
0.500
13.15
B25 CLKOUT rising edge to OE, WE(0:3) asserted
B26 CLKOUT rising edge to OE negated
B27 A(0:31) and BADDR(28:30) to CS asserted GPCM ACS 23.00
= 10, TRLX = 1
9.00
9.00
9.00
9.00
ns
ns
ns
2.00
2.00
35.88
1.250
1.500
B27a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS 28.00
= 11, TRLX = 1
B28 CLKOUT rising edge to WE(0:3) negated GPCM write
access CSNT = 0
43.45
ns
ns
ns
ns
9.00
9.00
B28a CLKOUT falling edge to WE(0:3) negated GPCM write
access TRLX = 0, CSNT = 1, EBDF = 0
B28b CLKOUT falling edge to CS negated GPCM write
access TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11,
EBDF = 0
5.00 11.75 7.58 14.33
11.75 14.33
0.250
0.250
10
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 8. Bus Operation Timings (Continued)
1
50 MHz
33 MHz
Min Max
7.00 14.13 10.86 17.99
Num
Characteristic
Unit
FFACT.
Min
Max
B28c CLKOUT falling edge to WE(0:3) negated GPCM write
access TRLX = 0, CSNT = 1 write access TRLX = 0,
CSNT = 1, EBDF = 1
ns
0.375
B28d CLKOUT falling edge to CS negated GPCM write
access TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1
14.13
17.99
ns
0.375
B29 WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM
write access, CSNT = 0, EBDF = 0
B29a WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM
write access, TRLX = 0, CSNT = 1, EBDF = 0
B29b CS negated to D(0:31), DP(0:3), High Z GPCM write
access, ACS = 00, TRLX = 0 & CSNT = 0
B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write
access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11
EBDF = 0
3.00
8.00
3.00
8.00
5.58
13.15
5.58
ns
ns
ns
ns
0.250
0.500
0.250
0.500
13.15
B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM
write access, TRLX = 1, CSNT = 1, EBDF = 0
B29e CS negated to D(0:31), DP(0:3) High-Z GPCM write
access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11
EBDF = 0
28.00
28.00
43.45
43.45
ns
ns
1.500
1.500
B29f WE(0:3) negated to D(0:31), DP(0:3) High Z GPCM
write access, TRLX = 0, CSNT = 1, EBDF = 1
B29g CS negated to D(0:31), DP(0:3) High-Z GPCM write
access, TRLX = 0, CSNT = 1 ACS = 10 or ACS = 11,
EBDF = 1
5.00
5.00
8.86
8.86
ns
ns
0.375
0.375
B29h WE(0:3) negated to D(0:31), DP(0:3) High Z GPCM
write access, TRLX = 1, CSNT = 1, EBDF = 1
B29i CS negated to D(0:31), DP(0:3) High-Z GPCM write
access, TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11,
EBDF = 1
24.50
24.50
38.67
38.67
ns
ns
1.375
1.375
B30 CS, WE(0:3) negated to A(0:31), BADDR(28:30) Invalid 3.00
5.58
ns
ns
0.250
0.500
8
GPCM write access
B30a WE(0:3) negated to A(0:31), BADDR(28:30) Invalid
GPCM, write access, TRLX = 0, CSNT = 1, CS negated
to A(0:31) invalid GPCM write access TRLX = 0, CSNT
=1 ACS = 10, or ACS == 11, EBDF = 0
8.00
13.15
B30b WE(0:3) negated to A(0:31) Invalid GPCM
BADDR(28:30) invalid GPCM write access, TRLX = 1,
CSNT = 1. CS negated to A(0:31) Invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11
EBDF = 0
28.00
43.45
ns
1.500
B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid
GPCM write access, TRLX = 0, CSNT = 1. CS negated
to A(0:31) invalid GPCM write access, TRLX = 0, CSNT
= 1 ACS = 10, ACS == 11, EBDF = 1
B30d WE(0:3) negated to A(0:31), BADDR(28:30) invalid
GPCM write access TRLX = 1, CSNT =1, CS negated to
A(0:31) invalid GPCM write access TRLX = 1, CSNT =
1, ACS = 10 or 11, EBDF = 1
4.50
24.50
1.50
8.36
38.67
1.50
ns
ns
ns
0.375
1.375
B31 CLKOUT falling edge to CS valid - as requested by
control bit CST4 in the corresponding word in the UPM
6.00
6.00
MOTOROLA
MPC860 Hardware SpeciÞcations
11
Table 8. Bus Operation Timings (Continued)
1
50 MHz
33 MHz
Min Max
5.00 11.75 7.58 14.33
Num
Characteristic
Unit
ns
FFACT.
Min
Max
B31a CLKOUT falling edge to CS valid - as requested by
control bit CST1 in the corresponding word in the UPM
0.250
B31b CLKOUT rising edge to CS valid - as requested by
control bit CST2 in the corresponding word in the UPM
1.50
8.00
1.50
8.00
ns
B31c CLKOUT rising edge to S valid- as requested by control 5.00 11.75 7.58 14.33
bit CST3 in the corresponding word in the UPM
ns
0.250
0.375
B31d CLKOUT falling edge to CS valid, as requested by
control bit CST1 in the corresponding word in the UPM
EBDF = 1
9.40 14.13 13.26 17.99
ns
B32 CLKOUT falling edge to BS valid- as requested by
control bit BST4 in the corresponding word in the UPM
B32a CLKOUT falling edge to BS valid - as requested by
control bit BST1 in the corresponding word in the UPM,
EBDF = 0
1.50
6.00
1.50
6.00
ns
ns
5.00 11.75 7.58 14.33
0.250
B32b CLKOUT rising edge to BS valid - as requested by
control bit BST2 in the corresponding word in the UPM
B32c CLKOUT rising edge to BS valid - as requested by
control bit BST3 in the corresponding word in the UPM
B32d CLKOUT falling edge to BS valid- as requested by
control bit BST1 in the corresponding word in the UPM,
EBDF = 1
1.50
8.00
1.50
8.00
ns
ns
ns
5.00 11.75 7.58 14.33
9.40 14.13 13.26 17.99
0.250
0.375
B33 CLKOUT falling edge to GPL valid - as requested by
control bit GxT4 in the corresponding word in the UPM
B33a CLKOUT rising edge to GPL Valid - as requested by
control bit GxT3 in the corresponding word in the UPM
B34 A(0:31), BADDR(28:30), and D(0:31) to CS valid - as
requested by control bit CST4 in the corresponding
word in the UPM
B34a A(0:31), BADDR(28:30), and D(0:31) to CS valid - as
requested by control bit CST1 in the corresponding
word in the UPM
1.50
6.00
1.50
6.00
ns
ns
ns
5.00 11.75 7.58 14.33
0.250
0.250
3.00
8.00
5.58
13.15
ns
0.500
B34b A(0:31), BADDR(28:30), and D(0:31) to CS valid - as
requested by CST2 in the corresponding word in UPM
B35 A(0:31), BADDR(28:30) to CS valid - as requested by
control bit BST4 in the corresponding word in the UPM
B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid - As
Requested by BST1 in the corresponding word in the
UPM
13.00
3.00
8.00
20.73
5.58
ns
ns
ns
0.750
0.250
0.500
13.15
B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid - as
requested by control bit BST2 in the corresponding word
in the UPM
B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as
requested by control bit GxT4 in the corresponding word
in the UPM
13.00
3.00
20.73
5.58
ns
ns
0.750
0.250
9
B37 UPWAIT valid to CLKOUT falling edge
6.00
1.00
7.00
7.00
6.00
1.00
7.00
7.00
ns
ns
ns
ns
9
B38 CLKOUT falling edge to UPWAIT valid
10
B39 AS valid to CLKOUT rising edge
B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT
rising edge
B41 TS valid to CLKOUT rising edge (setup time)
B42 CLKOUT rising edge to TS valid (hold time)
7.00
2.00
7.00
2.00
ns
ns
12
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 8. Bus Operation Timings (Continued)
1
50 MHz
33 MHz
Min Max
Num
Characteristic
Unit
FFACT.
Min
Max
B43 AS negation to memory controller signals negation
TBD
ns
1
2
3
The values in the 33 MHz column are derived from the 50 MHz values.
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (I.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (I.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for
BG output is relevant when the MPC860 is selected to work with internal bus arbiter.
5
The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The
timing for BG input is relevant when the MPC860 is selected to work with external bus arbiter.
6
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
7
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
for read accesses controlled by chip-selects under control of the UPM in the Memory Controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings speciÞed
in B37 and B38 are speciÞed to enable the freeze of the UPM output signals as described in Figure 16.
10
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is speciÞed in order to allow the
behavior speciÞed in Figure 19.
MOTOROLA
MPC860 Hardware SpeciÞcations
13
Figure 1 is the control timing diagram.
2.0 V
2.0 V
CLKOUT
0.8 V
0.8 V
A
B
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
Outputs
Inputs
A
B
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
D
C
2.0 V
0.8 V
2.0 V
0.8 V
Inputs
A
B
C
D
Maximum output delay specification
Minimum output hold time
Minimum input setup time specification
Minimum input hold time specification
Figure 1. Control Timing
Figure 2 provides the timing for the external clock.
CLKOUT
B1
B1
B3
B2
B4
B5
Figure 2. External Clock Timing
14
MPC860 Hardware SpeciÞcations
MOTOROLA
Figure 3 provides the timing for the synchronous output signals.
CLKOUT
B8
B7
B9
Output
Signals
B8a
B8b
B7a
B7b
B9
Output
Signals
Output
Signals
Figure 3. Synchronous Output Signals Timing
Figure 4 provides the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B11
B12
B12a
B15
TS, BB
TA, BI
TEA
B13a
B11a
B14
Figure 4. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing
MOTOROLA
MPC860 Hardware SpeciÞcations
15
Figure 5 provides the timing for the synchronous input signals.
CLKOUT
B16
B17
B17a
B17
TA, BI
B16a
TEA, KR,
RETRY, CR
B16b
BB, BG, BR
Figure 5. Synchronous Input Signals Timing
16
MPC860 Hardware SpeciÞcations
MOTOROLA
Figure 6 provides normal case timing for input data.
CLKOUT
B16
B17
B19
TA
B18
D[0:31],
DP[0:3]
Figure 6. Input Data Timing in Normal Case
Figure 7 provides the timing for the input data controlled by the UPM in the memory controller.
CLKOUT
TA
B20
B21
D[0:31],
DP[0:3]
Figure 7. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 8 through Figure 11 provide the timing for the external bus read controlled by various GPCM factors.
MOTOROLA
MPC860 Hardware SpeciÞcations
17
CLKOUT
TS
B11
B8
B12
A[0:31]
CSx
B22
B23
B25
B26
B19
OE
B28
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 8. External Bus Read Timing (GPCM ControlledÑACS = 00)
CLKOUT
TS
B11
B8
B12
A[0:31]
CSx
B23
B22a
B24
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 9. External Bus Read Timing (GPCM ControlledÑTRLX = 0, ACS = 10)
18
MPC860 Hardware SpeciÞcations
MOTOROLA
CLKOUT
TS
B11
B8
B12
B22b
B22c
A[0:31]
CSx
B23
B24a
B25
B26
B19
OE
B18
D[0:31],
DP[0:3]
Figure 10. External Bus Read Timing (GPCM ControlledÑTRLX = 0, ACS = 11)
CLKOUT
TS
B11
B12
B8
A[0:31]
CSx
B23
B22a
B27
B26
B19
OE
B27a
B22b B22c
B18
D[0:31],
DP[0:3]
Figure 11. External Bus Read Timing (GPCM ControlledÑTRLX = 1, ACS = 10, ACS = 11)
MOTOROLA
MPC860 Hardware SpeciÞcations
19
Figure 12 through Figure 14 provide the timing for the external bus write controlled by various GPCM
factors.
CLKOUT
B11
B8
B12
TS
A[0:31]
CSx
B30
B22
B23
B25
B28
WE[0:3]
OE
B26
B29b
B29
B8
B9
D[0:31],
DP[0:3]
Figure 12. External Bus Write Timing (GPCM ControlledÑTRLX = 0, CSNT = 0)
20
MPC860 Hardware SpeciÞcations
MOTOROLA
CLKOUT
TS
B11
B8
B12
B30a B30c
B23
A[0:31]
CSx
B22
B28b B28d
B25
B29c B29g
WE[0:3]
OE
B26
B29a B29f
B28a B28c
B8
B9
D[0:31],
DP[0:3]
Figure 13. External Bus Write Timing (GPCM ControlledÑTRLX = 0, CSNT = 1)
MOTOROLA
MPC860 Hardware SpeciÞcations
21
CLKOUT
TS
B11
B12
B8
B30b B30d
A[0:31]
CSx
B22
B28b B28d
B23
B25
B29e B29i
B29d B29h
WE[0:3]
OE
B26
B29b
B8
B28a B28c
B9
D[0:31],
DP[0:3]
Figure 14. External Bus Write Timing (GPCM ControlledÑTRLX = 1, CSNT = 1)
22
MPC860 Hardware SpeciÞcations
MOTOROLA
Figure 15 provides the timing for the external bus controlled by the UPM.
CLKOUT
B8
A[0:31]
B31a
B31d
B31c
B31
B31b
CSx
B34
B34a
B34b
B32a B32d
B32c
B33a
B32
B32b
BS_A[0:3],
BS_B[0:3]
B35 B36
B35b
B35a
B33
GPL_A[0:5],
GPL_B[0:5]
Figure 15. External Bus Timing (UPM Controlled Signals)
MOTOROLA
MPC860 Hardware SpeciÞcations
23
Figure 16 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 16. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 17 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B[0:3]
GPL_A[0:5],
GPL_B[0:5]
Figure 17. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
24
MPC860 Hardware SpeciÞcations
MOTOROLA
Figure 18 provides the timing for the synchronous external master access controlled by the GPCM.
CLKOUT
B41
B40
B42
TS
A[0:31],
TSIZ[0:1],
R/W, BURST
B22
CSx
Figure 18. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 19 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 19. Asynchronous External Master Memory Access Timing (GPCM ControlledÑACS = 00)
Figure 20 provides the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Figure 20. Asynchronous External MasterÑControl Signals Negation Timing
MOTOROLA
MPC860 Hardware SpeciÞcations
25
Table 9 provides interrupt timing for the MPC860.
Table 9. Interrupt Timing
33 MHz
Min
50 MHz
Min
1
Num
Characteristic
Unit
Max
Max
I39
IRQx valid to CLKOUT rising edge
(set up time)
6.00
6.00
ns
I40
I41
I42
I43
IRQx hold time after CLKOUT
IRQx pulse width low
2.00
3.00
3.00
2.00
3.00
3.00
ns
ns
ns
Ñ
IRQx pulse width high
IRQx edge-to-edge time
4xT
4xT
CLOCKOUT
CLOCKOUT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being
deÞned as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or
negated with reference to the CLKOUT.
The timings I41, I42, and I43 are speciÞed to allow the correct function of the IRQ lines detection circuitry,
and has no direct relation with the total system interrupt latency that the MPC860 is able to support.
Figure 21 provides the interrupt detection timing for the external level-sensitive lines.
CLKOUT
I39
I40
IRQx
Figure 21. Interrupt Detection Timing for External Level Sensitive Lines
Figure 22 provides the interrupt detection timing for the external edge-sensitive lines.
CLKOUT
I39
I41
I42
IRQx
I43
I43
Figure 22. Interrupt Detection Timing for External Edge Sensitive Lines
26
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 10 shows the PCMCIA timing for the MPC860.
Table 10. PCMCIA Timing
33 MHz
Min Max
50 MHz
Min Max
Num
Characteristic
FFACTOR Unit
1
P44
P45
P46
P47
P48
P49
A(0:31), REG valid to PCMCIA Strobe asserted.
20.73
28.30
7.58
8.58
7.58
7.58
13.00
18.00
0.750
1.000
ns
ns
ns
ns
1
A(0:31), REG valid to ALE negation.
CLKOUT to REG valid
15.58 5.00
6.00
13.00 0.250
0.250
CLKOUT to REG Invalid.
CLKOUT to CE1, CE2 asserted.
CLKOUT to CE1, CE2 negated.
15.58 5.00
15.58 5.00
11.00
13.00 0.250
13.00 0.250
11.00
ns
ns
CLKOUT to PCOE, IORD, PCWE, IOWR assert
time.
P50
P51
CLKOUT to PCOE, IORD, PCWE, IOWR negate
time.
2.00
7.58
11.00 2.00
11.00
ns
P52
P53
P54
P55
CLKOUT to ALE assert time
CLKOUT to ALE negate time
15.58 5.00
15.58
13.00 0.250
13.00 0.250
0.250
ns
ns
ns
ns
ns
1
PCWE, IOWR negated to D(0:31) invalid.
5.58
8.00
2.00
3.00
1
WAITA and WAITB valid to CLKOUT rising edge.
8.00
CLKOUT rising edge to WAITA and WAITB
2.00
P56
1
invalid.
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings deÞne when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA
current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
PCMCIA Interface in the MPC860 PowerQUICC User s Manual.
MOTOROLA
MPC860 Hardware SpeciÞcations
27
Figure 23 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
REG
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
B19
D[0:31]
Figure 23. PCMCIA Access Cycles Timing External Bus Read
28
MPC860 Hardware SpeciÞcations
MOTOROLA
Figure 24 provides the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
B19
REG
CE1/CE2
PCOE, IOWR
ALE
P50
P53
B18
P54
P52
D[0:31]
Figure 24. PCMCIA Access Cycles Timing External Bus Write
Figure 25 provides the PCMCIA WAIT signals detection timing.
CLKOUT
P55
P56
WAITx
Figure 25. PCMCIA WAIT Signals Detection Timing
MOTOROLA
MPC860 Hardware SpeciÞcations
29
Table 11 shows the PCMCIA port timing for the MPC860.
Table 11. PCMCIA Port Timing
33 MHz
50 MHz
Num
P57
P58
P59
Characteristic
FFactor
Unit
ns
ns
ns
ns
Min
Max
19.00
Min
Max
19.00
CLKOUT to OPx Valid
HRESET negated to OPx drive
IP_Xx valid to CLKOUT rising edge
CLKOUT rising edge to IP_Xx invalid
1
25.73
5.00
1.00
18.00
5.00
1.00
0.75
P60
1
OP2 and OP3 only.
Figure 26 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 26. PCMCIA Output Port Timing
Figure 27 provides the PCMCIA output port timing for the MPC860.
CLKOUT
P59
P60
Input
Signals
Figure 27. PCMCIA Input Port Timing
30
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 12 shows the debug port timing for the MPC860.
Table 12. Debug Port Timing
33 MHz
Min
50 MHz
Min
Num
Characteristic
Unit
Max
Max
D61
DSCK cycle time
3xT
3xT
ns
CLOCKOUT
CLOCKOUT
D62
D63
D64
D65
D66
D67
DSCK clock pulse width
DSCK rise and fall times
DSDI input data setup time
DSDI data hold time
1.25xT
0.00
8.00
5.00
0.00
0.00
1.25xT
0.00
ns
ns
ns
ns
CLOCKOUT
CLOCKOUT
3.00
3.00
8.00
5.00
DSCK low to DSDO data valid
DSCK low to DSDO invalid
15.00 0.00
2.00 0.00
15.00 ns
2.00 ns
Figure 28 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
D63
Figure 28. Debug Port Clock Input Timing
Figure 29 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 29. Debug Port Timings
MPC860 Hardware SpeciÞcations
MOTOROLA
31
Table 13 shows the reset timing for the MPC860.
Table 13. Reset Timing
33 MHz
50 MHz
Num
Characteristic
FFACTOR Unit
Min
Max
Min
Max
R69
R70
R71
R72
CLKOUT to HRESET high impedance
CLKOUT to SRESET high impedance
RSTCONF pulse width
20.00
20.00
20.00
20.00
ns
ns
515.15
504.55
340.00
17.000
15.000
ns
ConÞguration data to HRESET rising edge set up
time
350.00
350.00
0.00
ns
ns
ns
R73
R74
R75
ConÞguration data to RSTCONF rising edge set up 350.00
time
ConÞguration data hold time after RSTCONF
negation
0.00
R76
R77
R78
ConÞguration data hold time after HRESET negation 0.00
HRESET and RSTCONF asserted to data out drive
RSTCONF negated to data out high impedance.
0.00
ns
ns
ns
ns
25.00
25.00
25.00
25.00
25.00
25.00
CLKOUT of last rising edge before chip three-states
HRESET to data out high impedance.
R79
R80
R81
DSDI, DSCK set up
90.91
0.00
60.00
0.00
3.000
8.000
ns
ns
ns
DSDI, DSCK hold time
SRESET negated to CLKOUT rising edge for DSDI 242.42
and DSCK sample
160.00
R82
Figure 30 shows the reset timing for the data bus conÞguration.
HRESET
R71
R76
RSTCONF
R73
R74
R75
D[0:31] (IN)
Figure 30. Reset TimingÑConfiguration from Data Bus
MPC860 Hardware SpeciÞcations
32
MOTOROLA
Figure 31 provides the reset timing for the data bus weak drive during conÞguration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 31. Reset TimingÑData Bus Weak Drive during Configuration
Figure 32 provides the reset timing for the debug port conÞguration.
CLKOUT
R70
R82
SRESET
R80
R80
R81
R81
DSCK, DSDI
Figure 32. Reset TimingÑDebug Port Configuration
1.7 IEEE 1149.1 Electrical SpeciÞcations
Table 14 provides the JTAG timings for the MPC860 shown in Figure 33 to Figure 36.
Table 14. JTAG Timing
33 MHz
Min Max
50 MHz
Num
J82
J83
J84
J85
J86
J87
J88
Characteristic
Unit
Min
Max
TCK cycle time
100.00
40.00
0.00
100.00
40.00
ns
ns
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO data invalid
10.00 0.00
5.00
10.00 ns
5.00
ns
ns
25.00
25.00
27.00
27.00 ns
ns
0.00
0.00
MOTOROLA
MPC860 Hardware SpeciÞcations
33
Table 14. JTAG Timing (Continued)
33 MHz
50 MHz
Num
J89
Characteristic
Unit
Min
Max
Min
Max
TCK low to TDO high impedance
20.00
20.00 ns
ns
J90
J91
J92
J93
J94
J95
J96
TRST assert time
100.00
40.00
100.00
40.00
TRST setup time to TCK low
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
ns
50.00
50.00
50.00
50.00 ns
50.00 ns
50.00 ns
ns
50.00
50.00
50.00
50.00
ns
TCK
J82
J83
J82
J83
J84
J84
Figure 33. JTAG Test Clock Input Timing
TCK
J85
J86
TMS, TDI
TDO
J87
J88
J89
Figure 34. JTAG Test Access Port Timing Diagram
TCK
J91
J90
TRST
Figure 35. JTAG TRST Timing Diagram
MPC860 Hardware SpeciÞcations
34
MOTOROLA
TCK
J92
J93
J94
Output
Signals
Output
Signals
J95
J96
Output
Signals
Figure 36. Boundary Scan (JTAG) Timing Diagram
1.8 CPM Electrical Characteristics
This section provides the AC and DC electrical speciÞcations for the communications processor module
(CPM) of the MPC860.
1.8.1 PIP/PIO AC Electrical SpeciÞcations
Table 15 provides the PIP/PIO AC timings as shown in Figure 37 to Figure 41.
Table 15. PIP/PIO Timing
All Frequencies
Num
21
Characteristic
Unit
ns
Min
Max
Data-in setup time to STBI low
Data-In hold time to STBI high
0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
2
Ñ
Ñ
Ñ
1
22
23
24
25
26
27
28
29
30
2.5 Ð t3
1.5
1 clk Ð 5ns
2
5
Ñ
2
15
7.5
Ñ
clk
clk
ns
clk
clk
clk
clk
ns
ns
ns
STBI pulse width
STBO pulse width
Data-out setup time to STBO low
Data-out hold time from STBO high
STBI low to STBO low (Rx interlock)
STBI low to STBO high (Tx interlock)
Data-in setup time to clock high
Data-in hold time from clock high
Clock low to data-out valid (CPU writes data, control, or direction)
31
25
1
t3 = SpeciÞcation 23
MOTOROLA
MPC860 Hardware SpeciÞcations
35
DATA-IN
STBI
21
22
23
27
24
STBO
Figure 37. PIP RX (Interlock Mode) Timing Diagram
DATA-OUT
25
26
24
STBO
(Output)
28
23
STBI
(Input)
Figure 38. PIP TX (Interlock Mode) Timing Diagram
DATA-IN
21
22
23
24
STBI
(Input)
STBO
(Output)
Figure 39. PIP RX (Pulse Mode) Timing Diagram
36
MPC860 Hardware SpeciÞcations
MOTOROLA
DATA-OUT
25
26
24
23
STBO
(Output)
STBI
(Input)
Figure 40. PIP TX (Pulse Mode) Timing Diagram
CLKO
DATA-IN
29
30
31
DATA-OUT
Figure 41. Parallel I/O Data-In/Data-Out Timing Diagram
1.8.2 IDMA Controller AC Electrical SpeciÞcations
Table 16 provides the IDMA controller timings as shown in Figure 42 to Figure 45.
Table 16. IDMA Controller Timing
All Frequencies
Min Max
Num
40
41
42
43
44
45
46
Characteristic
Unit
ns
ns
ns
ns
ns
ns
ns
DREQ setup time to clock high
DREQ hold time from clock high
SDACK assertion delay from clock high
SDACK negation delay from clock low
SDACK negation delay from TA low
7
3
Ñ
Ñ
12
12
20
15
Ñ
Ñ
Ñ
Ñ
Ñ
7
SDACK negation delay from clock high
TA assertion to falling edge of the clock setup time (applies to external TA)
MOTOROLA
MPC860 Hardware SpeciÞcations
37
CLKO
(Output)
41
40
DREQ
(Input)
Figure 42. IDMA External Requests Timing Diagram
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
43
DATA
46
TA
(Output)
SDACK
Figure 43. SDACK Timing DiagramÑPeripheral Write, TA Sampled Low at the Falling Edge
of the Clock
38
MPC860 Hardware SpeciÞcations
MOTOROLA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
44
DATA
TA
(Output)
SDACK
Figure 44. SDACK Timing DiagramÑPeripheral Write, TA Sampled High at the Falling Edge
of the Clock
CLKO
(Output)
TS
(Output)
R/W
(Output)
42
45
DATA
TA
(Output)
SDACK
Figure 45. SDACK Timing DiagramÑPeripheral Read
MPC860 Hardware SpeciÞcations
MOTOROLA
39
1.8.3 Baud Rate Generator AC Electrical SpeciÞcations
Table 17 provides the baud rate generator timings as shown in Figure 46.
Table 17. Baud Rate Generator Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
10
50
51
52
BRGO rise and fall time
BRGO duty cycle
BRGO cycle
Ñ
ns
40
40
60
Ñ
%
ns
50
50
BRGOX
51
51
52
Figure 46. Baud Rate Generator Timing Diagram
1.8.4 Timer AC Electrical SpeciÞcations
Table 18 provides the general-purpose timer timings as shown in Figure 47.
Table 18. Timer Timing
All Frequencies
Min Max
10
Num
Characteristic
Unit
61
62
63
64
65
TIN/TGATE rise and fall time
TIN/TGATE low time
Ñ
ns
clk
clk
clk
ns
1
2
3
3
Ñ
Ñ
Ñ
25
TIN/TGATE high time
TIN/TGATE cycle time
CLKO low to TOUT valid
40
MPC860 Hardware SpeciÞcations
MOTOROLA
CLKO
60
61
63
62
TIN/TGATE
(Input)
61
64
65
TOUT
(Output)
Figure 47. CPM General-Purpose Timers Timing Diagram
1.8.5 Serial Interface AC Electrical SpeciÞcations
Table 19 provides the serial interface timings as shown in Figure 48 to Figure 52.
Table 19. SI Timing
All Frequencies
Num
70
71
71a
72
Characteristic
Unit
MHz
ns
ns
ns
ns
Min
Max
1, 2
2
L1RCLK, L1TCLK frequency (DSC = 0)
L1RCLK, L1TCLK width low (DSC = 0)
SYNCCLK/2.5
P + 10
P + 10
3
L1RCLK, L1TCLK width high (DSC = 0)
L1TXD, L1ST(1Ð4), L1RQ, L1CLKO rise/fall time
L1RSYNC, L1TSYNC valid to L1CLK edge Edge
(SYNC setup time)
L1CLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
L1RSYNC, L1TSYNC rise/fall time
15.00
15.00
73
20.00
35.00
74
ns
75
76
77
78
78A
79
80
80A
81
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
L1RXD valid to L1CLK edge (L1RXD setup time)
17.00
L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00
4
L1CLK edge to L1ST(1Ð4) valid
L1SYNC valid to L1ST(1Ð4) valid
L1CLK edge to L1ST(1Ð4) invalid
L1CLK edge to L1TXD valid
10.00
10.00
10.00
10.00
10.00
0.00
45.00
45.00
45.00
55.00
55.00
42.00
4
L1TSYNC valid to L1TXD valid
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
16.00 or
SYNCCLK/2
83
83a
84
85
86
87
88
L1RCLK, L1TCLK width low (DSC =1)
L1RCLK, L1TCLK width high (DSC = 1)
P + 10
P + 10
ns
ns
ns
L1TCLK
ns
3
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC
30.00
0.00
4
1.00
42.00
42.00
2
L1GR setup time
L1GR hold time
L1CLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
ns
ns
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
MOTOROLA
MPC860 Hardware SpeciÞcations
41
2
3
4
These specs are valid for IDL mode only.
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
These strobes and TxD on the Þrst bit of the frame become valid after L1CLK edge or L1SYNC, whichever is
later.
L1RCLK
(FE=0, CE=0)
(Input)
71
70
71a
72
L1RCLK
(FE=1, CE=1)
(Input)
RFSD=1
75
74
L1RSYNC
(Input)
73
77
L1RxD
(Input)
BIT0
76
78
79
L1ST(1–4)
(Output)
Figure 48. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
42
MPC860 Hardware SpeciÞcations
MOTOROLA
72
83A
L1RCLK
(FE = 1)
(CE = 1)
(Input)
82
L1RCLK
(FE = 0)
(CE = 0)
(Input)
75
RFSD = 1
L1RSYNC
(INPUT)
73
74
77
76
L1RXD
(INPUT)
BIT0
78
79
L1ST (4-1)
(OUTPUT)
L1CLKO
(OUTPUT)
84
Figure 49. SI Receive Timing with Double-Speed Clocking (DSC = 1)
MOTOROLA
MPC860 Hardware SpeciÞcations
43
L1TCLK
(FE=0, CE=0)
(Input)
71
70
72
L1TCLK
(FE=1, CE=1)
(Input)
73
TFSD=0
75
74
L1TSYNC
(Input)
80a
81
L1TxD
(Output)
BIT0
80
79
78
L1ST(1–4)
(Output)
Figure 50. SI Transmit Timing Diagram (DSC = 0)
44
MPC860 Hardware SpeciÞcations
MOTOROLA
72
83A
L1TCLK
K
(FE = 0)
(CE = 0)
(Input)
82
L1TCLK
K
(FE = 1)
(CE = 1)
(Input)
75
L1TSYNC
(INPUT)
73
74
TFSD = 0
81
80A
L1TXD
BIT0
(OUTPUT)
80
78A
78
79
L1ST (1-4)
(OUTPUT)
L1CLKO
(OUTPUT)
84
Figure 51. SI Transmit Timing with Double Speed Clocking (DSC = 1)
MOTOROLA
MPC860 Hardware SpeciÞcations
45
Figure 52. IDL Timing
46
MPC860 Hardware SpeciÞcations
MOTOROLA
1.8.6 SCC in NMSI Mode Electrical SpeciÞcations
Table 20 provides the NMSI external clock timing.
Table 20. NMSI External Clock Timing
All Frequencies
Min
Num
Characteristic
Unit
Max
1
100
RCLK1 and TCLK1 width high
1/SYNCCLK
ns
ns
101
102
103
104
105
106
107
108
RCLK1 and TCLK1 width low
1/SYNCCLK +5
RCLK1 and TCLK1 rise/fall time
15.00 ns
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
0.00
0.00
5.00
5.00
5.00
5.00
50.00 ns
50.00 ns
ns
ns
ns
ns
2
RXD1 hold time from RCLK1 rising edge
CD1 setup Time to RCLK1 rising edge
1
2
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as an external sync signal.
Table 21 provides the NMSI internal clock timing.
Table 21. NMSI Internal Clock Timing
All Frequencies
Min Max
Num
100
102
103
104
105
106
107
Characteristic
Unit
1
RCLK1 and TCLK1 frequency
0.00
SYNCCLK/3 MHz
ns
RCLK1 and TCLK1 rise/fall time
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge
CD1 setup time to RCLK1 rising edge
0.00
0.00
30.00
30.00
ns
ns
ns
ns
ns
ns
40.00
40.00
0.00
2
108
40.00
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
Also applies to CD and CTS hold time when they are used as an external sync signals.
2
MOTOROLA
MPC860 Hardware SpeciÞcations
47
Figure 53 through Figure 55 show the NMSI timings.
RCLK1
102
102
101
106
100
RxD1
(Input)
107
108
CD1
(Input)
107
CD1
(SYNC Input)
Figure 53. SCC NMSI Receive Timing Diagram
TCLK1
102
102
101
100
TxD1
(Output)
103
105
RTS1
(Output)
104
104
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 54. SCC NMSI Transmit Timing Diagram
MPC860 Hardware SpeciÞcations
48
MOTOROLA
TCLK1
102
102
101
100
TxD1
(Output)
103
RTS1
(Output)
104
107
104
105
CTS1
(Echo Input)
Figure 55. HDLC Bus Timing Diagram
1.8.7 Ethernet Electrical SpeciÞcations
Table 22 provides the Ethernet timings as shown in Figure 56 to Figure 60.
Table 22. Ethernet Timing
All Frequencies
Num
120
Characteristic
Unit
ns
Min
Max
CLSN width high
RCLK1 rise/fall time
RCLK1 width low
RCLK1 clock period
RXD1 setup time
RXD1 hold time
40
Ñ
40
80
20
5
Ñ
15
Ñ
120
Ñ
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
ns
ns
1
Ñ
RENA active delay (from RCLK1 rising edge of the last data bit) 10
Ñ
RENA width low
100
Ñ
TCLK1 rise/fall time
TCLK1 width low
TCLK1 clock period
Ñ
40
99
10
10
10
10
10
10
1
15
Ñ
1
101
50
50
50
50
50
50
Ñ
TXD1 active delay (from TCLK1 rising edge)
TXD1 inactive delay (from TCLK1 rising edge)
TENA active delay (from TCLK1 rising edge)
TENA inactive delay (from TCLK1 rising edge)
RSTRT active delay (from TCLK1 falling edge)
RSTRT inactive delay (from TCLK1 falling edge)
REJECT width low
2
CLKO1 low to SDACK asserted
CLKO1 low to SDACK negated
Ñ
Ñ
20
20
2
139
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
MOTOROLA
MPC860 Hardware SpeciÞcations
49
CLSN(CTS1)
(Input)
120
Figure 56. Ethernet Collision Timing Diagram
RCLK1
121
121
124
123
Last Bit
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
Figure 57. Ethernet Receive Timing Diagram
TCLK1
128
128
129
131
121
TxD1
(Output)
132
133
134
TENA(RTS1)
(Input)
RENA(CD1)
(Input)
(NOTE 2)
NOTES:
1. Transmit clock invert (TCI) bit in GSMR is set.
2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 58. Ethernet Transmit Timing Diagram
50
MPC860 Hardware SpeciÞcations
MOTOROLA
RCLK1
RxD1
(Input)
0
1
1
BIT1
125
BIT2
136
Start Frame Delimiter
RSTRT
(Output)
Figure 59. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 60. CAM Interface REJECT Timing Diagram
1.8.8 SMC Transparent AC Electrical SpeciÞcations
Table 23 provides the SMC transparent timings as shown in Figure 61.
Table 23. SMC Transparent Timing
All Frequencies
Min Max
100
Num
150
151
151A
152
153
154
Characteristic
Unit
ns
ns
ns
ns
ns
ns
ns
1
SMCLK clock period
Ñ
Ñ
Ñ
SMCLK width low
SMCLK width high
50
50
Ñ
10
20
5
SMCLK rise/fall time
15
50
Ñ
Ñ
SMTXD active delay (from SMCLK falling edge)
SMRXD/SMSYNC setup time
RXD1/SMSYNC hold time
155
1
SyncCLK must be at least twice as fast as SMCLK.
MOTOROLA
MPC860 Hardware SpeciÞcations
51
SMCLK
152
152
151
151A
150
SMTXD
(Output)
NOTE 1
154
153
155
SMSYNC
154
155
SMRXD
(Input)
NOTE:
1. This delay is equal to an integer number of character-length clocks.
Figure 61. SMC Transparent Timing Diagram
1.8.9 SPI Master AC Electrical SpeciÞcations
Table 24 provides the SPI master timings as shown in Figure 62 and Figure 63.
Table 24. SPI Master Timing
All Frequencies
Min Max
1024
Num
160
Characteristic
Unit
MASTER cycle time
4
2
t
t
cyc
161
162
163
164
165
166
167
MASTER clock (SCK) high or low time
MASTER data setup time (inputs)
Master data hold time (inputs)
Master data valid (after SCK edge)
Master data hold time (outputs)
Rise time output
512
Ñ
Ñ
cyc
50
0
ns
ns
ns
ns
ns
ns
Ñ
0
20
Ñ
Ñ
Ñ
15
15
Fall time output
52
MPC860 Hardware SpeciÞcations
MOTOROLA
SPICLK
(CI=0)
(Output)
161
163
167
166
166
167
161
160
SPICLK
(CI=1)
(Output)
162
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 62. SPI Master (CP = 0) Timing Diagram
SPICLK
(CI=0)
(Output)
161
167
166
166
167
161
160
SPICLK
(CI=1)
(Output)
163
162
SPIMISO
(Input)
msb
167
Data
165
lsb
msb
164
166
SPIMOSI
(Output)
msb
Data
lsb
msb
Figure 63. SPI Master (CP = 1) Timing Diagram
MOTOROLA
MPC860 Hardware SpeciÞcations
53
1.8.10 SPI Slave AC Electrical SpeciÞcations
Table 25 provides the SPI slave timings as shown in Figure 64 and Figure 65.
Table 25. SPI Slave Timing
All Frequencies
Min Max
Num
170
Characteristic
Unit
Slave cycle time
Slave enable lead time
Slave enable lag time
2
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
t
cyc
ns
ns
171
172
173
174
175
176
177
15
15
1
Slave clock (SPICLK) high or low time
Slave sequential transfer delay (does not require deselect)
Slave data setup time (inputs)
t
t
cyc
1
cyc
20
20
Ñ
ns
ns
ns
Slave data hold time (inputs)
Slave access time
50
SPISEL
(Input)
172
171
174
SPICLK
(CI=0)
(Input)
173
182
181
182
173
170
SPICLK
(CI=1)
(Input)
177
181
180
178
SPIMISO
(Output)
msb
176
Data
lsb
Undef
msb
175
179
181 182
lsb
SPIMOSI
(Input)
msb
Data
msb
Figure 64. SPI Slave (CP = 0) Timing Diagram
54
MPC860 Hardware SpeciÞcations
MOTOROLA
SPISEL
(Input)
172
174
171
170
SPICLK
(CI=0)
(Input)
173
182
181
173
181
SPICLK
(CI=1)
(Input)
177
182
180
178
SPIMISO
(Output)
msb
msb
msb
Undef
175
Data
lsb
179
176
msb
181 182
Data
SPIMOSI
(Input)
lsb
Figure 65. SPI Slave (CP = 1) Timing Diagram
1.8.11 I2C AC Electrical SpeciÞcations
2
Table 26 provides the I C (SCL < 100 KHz) timings.
2
Table 26. I C Timing (SCL < 100 KHZ)
All Frequencies
Min Max
100
Num
200
Characteristic
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
Unit
KHz
0
1
200
202
203
204
205
206
207
208
209
210
1.5
4.7
4.7
4.0
4.7
4.0
0
100
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
1
KHz
ms
ms
ms
ms
ms
ms
ns
ms
ns
ms
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
250
Ñ
SDL/SCL fall time
Stop condition setup time
Ñ
300
Ñ
211
4.7
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
MOTOROLA
MPC860 Hardware SpeciÞcations
55
2
Table 27 provides the I C (SCL > 100 KHz) timings.
2
Table 27. I C Timing (SCL > 100 KHZ)
All Frequencies
Num
200
Characteristic
Expression
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
Min
Max
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
fSCL
fSCL
0
BRGCLK/48
1
200
202
203
204
205
206
207
208
209
210
BRGCLK/16512
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
0
BRGCLK/48
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
1/(40 * fSCL)
Ñ
Ñ
1/(10 * fSCL)
1/(33 * fSCL)
Ñ
SDL/SCL fall time
Stop condition setup time
Ñ
211
1/2(2.2 * fSCL)
s
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
2
Figure 66 shows the I C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
2
Figure 66. I C Bus Timing Diagram
56
MPC860 Hardware SpeciÞcations
MOTOROLA
1.9 Mechanical Data and Ordering Information
Table 28 provides information on the MPC860 revision C.1 derivative devices.
Table 28. MPC860 Revision C.1 Derivatives
Multi-Channel
HDLC Support
1
Device
Number of SCCs
Ethernet Support
ATM Support
2
MPC860DC
MPC860DE
MPC860DH
MPC860
Two
SCC1
Yes
N/A
N/A
Yes
N/A
N/A
Yes
Yes
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Four
N/A
Yes
MPC860EN
MPC860MH
MPC860SR
Yes
Yes
1
2
Serial communications controller (SCC)
50-MHz version supports 64 time slots on a time-division multiplexed line using one SCC
Table 29 provides information on the MPC860 revision D.3 derivative devices.
Table 29. MPC860 Revision D.3 Derivatives
Multi-Channel
HDLC Support
1
Device
Number of SCCs
Ethernet Support
ATM Support
MPC860DE
MPC860DT
MPC860DP
MPC860EN
MPC860SR
MPC860T
Two
10 Mbps
10/100 Mbps
10/100 Mbps
10 Mbps
N/A
Yes
Yes
N/A
Yes
Yes
Yes
N/A
Yes
Yes
N/A
Yes
Yes
Yes
Four
10 Mbps
10/100 Mbps
10/100 Mbps
MPC860P
1
Serial communications controller (SCC)
MOTOROLA
MPC860 Hardware SpeciÞcations
57
Table 30 identiÞes the packages and operating frequencies available for the MPC860 revision C.1.
Table 30. MPC860 Revision C.1 Package/Frequency Availability
Package Type
Frequency (MHz)
33
Temperature (Tj)
Order Number
Ball grid array
0¡C to 95¡C
XPC860ZP33C1
(ZP sufÞx)
XPC860ENZP33C1
XPC860MHZP33C1
XPC860DCZP33C1
XPC860DEZP33C1
XPC860DHZP33C1
XPC860SRZP33C1
50
66
33
50
0¡C to 95¡C
0¡C to 95¡C
-40¡C to 95¡C
XPC860ZP50C1
XPC860ENZP50C1
XPC860MHZP50C1
XPC860DCZP50C1
XPC860DEZP50C1
XPC860DHZP50C1
XPC860SRZP50C1
XPC860ZP66C1
XPC860ENZP66C1
XPC860MHZP66C1
XPC860DCZP66C1
XPC860DEZP66C1
XPC860DHZP66C1
XPC860SRZP66C1
Ball grid array
(CZP sufÞx)
XPC860CZP33C1
XPC860ENCZP33C1
XPC860MHCZP33C1
XPC860DCCZP33C1
XPC860DECZP33C1
XPC860DHCZP33C1
XPC860SRCZP33C1
XPC860CZP50C1
XPC860ENCZP50C1
XPC860MHCZP50C1
XPC860DCCZP50C1
XPC860DECZP50C1
XPC860DHCZP50C1
XPC860SRCZP50C1
58
MPC860 Hardware SpeciÞcations
MOTOROLA
Table 31 identiÞes the packages and operating frequencies available for the MPC860 revision D.3.
Table 31. MPC860 Revision D.3 Package/Frequency Availability
Package Type
Frequency (MHz)
50
Temperature (Tj)
Order Number
Ball grid array
(ZP sufÞx)
0¡C to 95¡C
XPC860DEZP50D3
XPC860DTZP50D3
XPC860ENZP50D3
XPC860SRZP50D3
XPC860TZP50D3
66
80
50
66
0¡C to 95¡C
0¡C to 95¡C
-40¡C to 95¡C
-40¡C to 95¡C
XPC860DEZP66D3
XPC860DTZP66D3
XPC860ENZP66D3
XPC860SRZP66D3
XPC860TZP66D3
XPC860DEZP80D3
XPC860DTZP80D3
XPC860ENZP80D3
XPC860SRZP80D3
XPC860TZP80D3
Ball grid array
(CZP sufÞx)
XPC860DECZP50D3
XPC860DTCZP50D3
XPC860ENCZP50D3
XPC860SRCZP50D3
XPC860TCZP50D3
XPC860DECZP66D3
XPC860DTCZP66D3
XPC860ENCZP66D3
XPC860SRCZP66D3
XPC860TCZP66D3
Table 32 identiÞes the packages and operating frequencies available for the MPC860P.
Table 32. MPC860P Package/Frequency Availability
Package Type
Frequency (MHz)
50
Temperature (Tj)
Order Number
Ball grid array
(ZP sufÞx)
0¡C to 95¡C
XPC860DPZP50D3
XPC860PZP50D3
66
80
50
66
0¡C to 95¡C
0¡C to 95¡C
-40¡C to 95¡C
-40¡C to 95¡C
XPC860DPZP66D3
XPC860PZP66D3
XPC860DPZP80D3
XPC860PZP80D3
Ball grid array
(CZP sufÞx)
XPC860DPCZP50D3
XPC860PCZP50D3
XPC860DPCZP66D3
XPC860PCZP66D3
MOTOROLA
MPC860 Hardware SpeciÞcations
59
1.9.1 Pin Assignments
Figure 67 shows the pinout of the PBGA package as viewed from the top surface.
W
V
pd[10] pd[8] pd[3]
d[0] d[4] d[1] d[2] d[3] d[5] VDDL d[6] d[7] d[29] dp2 clkout ipa3
irq7
d[10]
dp1
VSSsyn1
dp3 dp0 N/C
pd[14] pd[13] pd[9] pd[6] Spare3
pa[0] pb[14] pd[15] pd[4] pd[5]
d[13] d[27]
d[23]
d[14] d[18] d[20] d[24] d[28]
irq0
irq1
U
VSSsyn
d[8]
d[11] d[16] d[19] d[21] d[26] d[30] ipa5 ipa4 ipa2 N/C
T
VDDsyn
pa[1] pc[5] pc[4] pd[11] pd[7] vddh d[12] d[17] d[9] d[15] d[22] d[25] d[31] ipa6 ipa0 ipa1 ipa7 xfc
VDDH
R
P
kapwr
xtal
pc[6] pa[2] pb[15] pd[12]
pa[4] pb[17] pa[3] VDDH
pb[19] pa[5] pb[18] pb[16]
pa[7] pc[8] pa[6] pc[7]
pb[22] pc[9] pa[8] pb[20]
pc[10] pa[9] pb[23] pb[21]
VDDH
wait_bwait_aporeset
VDDH
rstconfsreset
GND
GND
N
M
texp extclk extal
hreset
modck2baddr28baddr29VDDL
L
modck1
irq4
op0
op1
as
K
J
baddr30ipb6 alea
GND
pc[11]
ipb5 ipb1 ipb2 aleb
pb[24] pa[10] pb[25]
VDDLSpare2 tdi tck
trst tms tdo pa[11]
H
G
Spare4
ipb0 ipb7
ipb4 ipb3
irq3 burst
irq2
irq6
ts
br
GND
GND
F
E
D
VDDH
pb[26] pc[12] pa[12] VDDH
pb[27] pc[13] pa[13] pb[29]
VDDH
VDDH
cs3
bi
bg
bb
pb[28] pc[14] pa[14] pc[15] a[8]
a[15] a[19] a[25] a[18]
N/C N/C
bsa0
N/C
gpla0
cs6
cs2 gpla5 bdip tea
C
B
A
pb[30] pa[15] pb[31] a[3]
a[0] a[1] a[4] a[6] a[10] a[13] a[17]
a[2] a[5] a[7]
18 17
a[12] a[16] a[20] a[24] a[26] tsiz1
a[9]
gpla3 cs7
cs0
ta
gpla4
bsa1 we0 gpla1
Spare1
a[21]
a[23] a[22] tsiz0
gpla2 cs5 ce1a wr gplb4
we3 cs4 ce2a cs1
bsa3
we2
a[11] a[14] a[27] a[29] a[30] a[28] a[31] VDDL
bsa2 we1
19
14
13
12
11
10
9
5
4
3
2
1
16
15
8
7
6
This shading denotes VDDH
This shading denotes GND
Figure 67. Pinout of the PBGA Package as Viewed from the Top Surface
1.9.2 Mechanical Dimensions of the PBGA
For more information on the printed circuit board layout of the PBGA package, including thermal via design
and suggested pad layout, please refer to Plastic Ball Grid Array Application Note (order number: AN1231/
D) available from your local Motorola sales ofÞce.
60
MPC860 Hardware SpeciÞcations
MOTOROLA
- T -
0.20 (0.008)
4X
0.20 (0.008) T
0.25 (0.010) T
A
- W -
0.35 (0.014) T
P
B
- L -
N
TOP VIEW
F
R
K
18X
G
E
C
W
V
U
T
SIDE VIEW
R
P
N
M
L
NOTES:
1. Dimensioning and tolerancing per ANSIY14.5M,
1982.
2. Dimensions in millimeters.
S
K
J
Millimeters
Min Max
Inches
Min Max
H
G
F
DIM
E
D
C
B
A
A
B
C
D
E
F
25.00 BSC
25.00 BSC
0.984 BSC
0.984 BSC
17 18 19
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
357X
D
Ñ
2.05
Ñ
0.081
BOTTOM VIEW
0.60
0.50
0.95
0.90
0.70
1.35
0.024
0.020
0.037
0.035
0.028
0.053
S
S
0.30 (0.012)
0.10 (0.004)
T
T
L
S
W
S
G
K
N
P
R
S
1.27 BSC
0.50 BSC
0.70
22.40
22.40
0.90
22.60
22.60
0.028
0.882
0.882
0.035
0.890
0.890
22.86 BSC
22.86 BSC
0.900 BSC
0.900 BSC
Figure 68. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MOTOROLA
MPC860 Hardware SpeciÞcations
61
1.10 Document Revision History
Table 33 lists signiÞcant changes between revisions of this document.
Table 33. Document Revision History
Document Revision
Substantive Changes
Rev 1
Added note to Table 4 about power supply ramp starting from 0.0 V.
Corrected note 6 of Table 8 to refer to B18 and B19 instead of B20 and B21.
Corrected characteristic of spec B29h in Table 8 to show ÔTRLX = 1Õ instead of ÔTRLX = 0.Õ
Corrected characteristic of spec 65 in Table 18 to show ÔCLKO lowÕ instead of ÔCLKO high.Õ
2
Changed section 1.8.8 to refer to SMC transparent speciÞcations instead of I C.
Changed co-planarity speciÞcation in Figure 68 to 0.20 instead of 0.15.
Corrected spec number 31 characteristic in Table 15.
Corrected the characteristic for spec numbers 29 and 30 in Table 15.
Made overbars for active-low signals consistent.
Rev 2
Rev 3
Rev 4
Added derivative and package/frequency availability information for revision C.1 and revision D.3
including the MPC860P. See Section 1.9, ÒMechanical Data and Ordering Information.Ó
62
MPC860 Hardware SpeciÞcations
MOTOROLA
MOTOROLA
MPC860 Hardware SpeciÞcations
63
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MPC860EC/D
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