HF500GS-15 [MPS]
Fixed Frequency Multi-Mode Flyback Regulator Integrated with Highly Rugged MOSFET;
| 型号： | HF500GS-15 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Fixed Frequency Multi-Mode Flyback Regulator Integrated with Highly Rugged MOSFET |
| 文件： | 总24页 (文件大小：1579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HF500-15
Fixed Frequency Multi-Mode
Flyback Regulator
Integrated with Highly Rugged MOSFET
DESCRIPTION
FEATURES
The HF500-15 is a fixed-frequency, current-
mode regulator with built-in slope compensation.
It combines a 700V MOSFET of high avalanche
ruggedness and a full-featured controller into
one chip for a low-power, offline, flyback,
switch-mode power supply.
700V/4.5 Integrated MOSFET with high
single pulse avalanche energy
Fixed-Frequency
Current-Mode-Control
Operation with Built-In Slope Compensation
Frequency Foldback Down to fOSC(min) at
Light Load
Burst Mode for Low Standby Power
Consumption
At medium and heavy loads, the regulator
works in a fixed frequency with frequency
jittering, which helps to spread energy out in a
conducted mode. During a light-load condition,
the regulator freezes the peak current and
reduces its switching frequency to fOSC(min) to
offer excellent efficiency at light load. At very
light loads, the regulator enters burst mode to
achieve low standby power consumption.
Frequency Jittering for a Reduced EMI
Signature
Over-Power Compensation
Internal High-Voltage Current Source
VCC Under-Voltage Lockout (UVLO) with
Hysteresis
Programmable Input B/O and OVP
Full protection features include thermal
shutdown, brown-in and brownout, VCC under-
voltage lockout (UVLO), overload protection
(OLP), short-circuit protection (SCP), input and
output over-voltage protection (OVP), and over-
temperature protection (OTP) .
Overload
Programmable Delay
Latch-Off Protection on TIMER
Thermal Shutdown (Auto-Restart with
Hysteresis)
Protection
(OLP)
with
a
Short-Circuit Protection (SCP)
Programmable Soft Start
The HF500-15 features timer-based fault
detection and over-power compensation to
ensure that the overload is independent of the
input voltage.
APPLICATIONS
Power Supplies for Home Appliances
Set-Top Boxes
Standby and Auxiliary Power
Adapters
The HF500-15 is available in a SOIC8-7B
package.
Maximum Output Power3
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
230Vac±15%
85Vac~265Vac
Open
Open
Adapter1
Adapter1
Frame2
Frame2
POUT
(W)
12
15
10
12
Notes:
1. Maximum continuous power in a non-ventilated enclosed adapter
measured at 50℃ ambient temperature.
2. Maximum continuous power in an open frame design at 50℃
ambient temperature.
3. The junction temperature can limit the maximum output power.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
1
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL APPLICATION
T1
Output
_
V BUS
Input
85 ~ 265 Vac
SOURCE
GND
4
5
6
7
DRAIN
B/O
VCC
2
FB
1
TIMER
8
HF500-15 Rev. 1.03
www.MonolithicPower.com
2
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
ORDERING INFORMATION
Part Number*
Package
Top Marking
HF500GS-15
SOIC8-7B
See Below
* For Tape & Reel, add suffix –Z (e.g. HF500GS-15–Z);
TOP MARKING
HF500-15: Part number
LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code
PACKAGE REFERENCE
SOIC8-7B
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
3
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
Thermal Resistance (6)
SOIC8-7B............................... 85...... 40... C/W
θJA θJC
ABSOLUTE MAXIMUM RATINGS (1)
Drain breakdown voltage ............ -0.3V to 700V
VCC to GND.................................... -0.3V to 30V
FB, TIMER, SOURCE, B/O to GND..-0.3V to 7V
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
Continuous power dissipation (TA = +25°C)
………………………………………………...1.5W
Junction temperature...............................150°C
Lead temperature ....................................260°C
Storage temperature ...............-60°C to +150°C
ESD capability human body model (all pins
except DRAIN) .........................................4.0kV
ESD capability machine model ..................200V
3) Pulse drain current is tested with Tp≤300μs, Dp≤2%, package
limited.
4) Single pulse avalanche energy is tested with Lm=10mH,
VDD=50V, IAS=3.16A.
(3)
Pulse Drain Current ............................. 2.38A
(4)
Single Pulse Avalanche Energy............50mJ
Lm
IAS
Recommended Operating Conditions (5)
Operating junction temp (TJ) ....-40°C to +125°C
Operating VCC range ................... 12.5V to 24V
VDD
Rg
VDS
Rgs
Vgs
UIS Test Circuit
5) The device is not guaranteed to function outside of its
operating conditions.
6) Measured on JESD51-7, 4-layer PCB.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
4
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
ELECTRICAL CHARACTERISTICS
For typical value, VCC=16V, TJ = -40°C to 125°C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Start-Up Current Source (DRAIN)
VCC = 0V,
IDrain_0
1.4
1.4
3.6
5
6.2
7.9
VDrain = 120V/400V
Supply current from DRAIN
Leakage current from DRAIN
mA
VCC = 11V,
VDrain = 120V/400V
IDrain_11
VCC = 10V,
VDrain = 400V
ILK
4.5
10.5
μA
Breakdown voltage
VBR
TJ = 25°C
700
V
Internal MOSFET (DRAIN)
VCC = 10.5V,
ID = 0.1A, TJ = 25°C
On-state resistance
RDS_ON
4.5
6.5
Ω
Supply Voltage Management (VCC)
VCC level (increasing) where the internal
regulator stops
VCCOFF
11
6
12
7
13
8
V
V
VCC level (decreasing) where the IC
shuts down and the internal regulator
turns on
VCCUVLO
VCCOFF
VCCUVLO
–
VCC UVLO hysteresis
4
4.8
5.3
2.5
V
V
V
VCC recharge level when protection
occurs
VCCPRO
4.7
5.9
VCC decreasing level where the latch-off
phase ends
VCCLATCH
Internal IC consumption
ICC
VFB = 3V, VCC = 12V
VCC = 12V, TJ = 25°C
0.9
1.2
mA
Internal IC consumption, latch-off phase
ICCLATCH
700
900
μA
Voltage on VCC (upper limit) where the
regulator latches off (OVP)
VOVP
TOVP
25
27
60
29
V
Blanking duration on the OVP
comparator
ms
Oscillator
VFB > 1.85V, TJ =
25°C
Oscillator frequency
fOSC
62
65
68
kHz
%
Frequency jittering amplitude in
percentage of fOSC
VFB > 1.85V, TJ =
25°C
Ajitter
5
6.5
8
Frequency jittering entry level
VFB_JITTER
Tjitter
1.95
V
Frequency jittering modulation period
CTIMER = 47nF
3.7
ms
HF500-15 Rev. 1.03
www.MonolithicPower.com
5
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
ELECTRICAL CHARACTERISTICS (continued)
For typical value, VCC=16V, TJ = -40°C to 125°C, unless otherwise noted.
Parameter
Symbol Conditions
Min
Typ Max
Unit
Protections (B/O)
Brown-in threshold voltage on B/O
Brownout threshold voltage on B/O
Brown-in/out hysteresis
VB/O_IN
VB/O_OUT
VB/O
VB/O increasing
VB/O decreasing
0.95
0.85
1
1.05
V
V
0.9 0.95
0.065 0.1 0.14
V
Timer duration for line cycle dropout
Input OVP threshold on B/O
Input OVP delay time
TB/O
CTIMER = 47nF
34
55
4.5
90
ms
V
OVPB/O
TOVPB/O
4.2
4.8
6.6
µs
V
Voltage on B/O to disable B/O and input
OVP function
VDIS
5.4
6
Clamp voltage on B/O
Input impedance
VB/O_Cla
RB/O
7
V
1.2
MΩ
Current Sense (SOURCE)
Current limit point
VILIM
VSCP
0.93
1.3
1
1.07
1.7
V
V
Short-circuit protection point
1.5
Current limitation during frequency
foldback
VFOLD
VFB = 1.85V
0.63 0.68 0.73
V
Current limitation when entering burst
Current limitation when exiting burst
Leading-edge blanking for VILIM
Leading-edge blanking for VSCP
Slope of the compensation ramp
Feedback (FB)
VIBURL
VIBURH
TLEB1
VFB = 0.7V
VFB = 0.8V
0.1
0.13
350
270
V
V
ns
TLEB2
ns
SRAMP
18
12
25
31
15
mV/μs
Internal pull-up resistor
RFB
VDD
TJ = 25°C
13.5
4.3
kΩ
Internal pull-up voltage
V
VFB to internal current-set point division
ratio
KFB1
KFB2
VFB = 2V
VFB = 3V
2.5
2.8
2.8
3.1
3.1
3.4
VFB to current-set point division ratio
FB level (decreasing) where the
regulator enters burst mode
VBURL
0.63
0.7 0.77
0.8 0.88
V
V
FB level (increasing) where the
regulator exits burst mode
VBURH
0.72
HF500-15 Rev. 1.03
www.MonolithicPower.com
6
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
ELECTRICAL CHARACTERISTICS (continued)
For typical value, VCC=16V, TJ = -40°C to 125°C, unless otherwise noted.
Parameter
Symbol Conditions
Min
Typ Max
Unit
Over-Load Protection (FB)
FB level where the regulator
enters OLP after a dedicated time
VOLP
3.7
V
Time duration before OLP when
FB reaches the protection point
TOLP
CTIMER = 47nF
32
ms
Over-Power Compensation (B/O)
VB/O = 1.1V, VFB=2.5V, TJ = 25°C
VB/O = 1.3V, VFB=2.5V, TJ = 25°C
VB/O = 2.9V, VFB=2.5V, TJ = 25°C
VB/O = 3.5V, VFB=2.5V, TJ = 25°C
VB/O > VDIS, TJ = 25°C
0
19
Compensation voltage
VOPC
153
205
200
270
0
247
335
mV
FB voltage (lower limit) when
compensation is removed
VOPC(OFF)
VOPC(ON)
0.55
V
V
FB voltage (upper limit) when
compensation is fully applied
2.5
30
Frequency Foldback
FB voltage (lower threshold) when
frequency foldback starts
VFB(FOLD)
fOSC(min)
1.8
25
1
V
kHz
V
Minimum switching frequency
TJ = 25°C
20.5
0.7
FB voltage (lower threshold) when
frequency foldback ends
VFB(FOLDE)
Latch-Off Input (Integration in TIMER)
Lower threshold when the
regulator is latched
VTIMER(LATCH)
1
1.2
V
Blanking duration on latch
detection
TLATCH
42
μs
Thermal Shutdown
Thermal shutdown threshold
Thermal shutdown hysteresis
TTSD
150
25
°C
°C
TTSD(HYS)
HF500-15 Rev. 1.03
www.MonolithicPower.com
7
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
PIN FUNCTIONS
Pin #
Name
Description
1
2
4
5
6
FB
Feedback. A pull-down optocoupler controls the output regulation.
VCC
Power supply of the IC. VCC enters OVP if the voltage on VCC rises above VOVP.
DRAIN Drain of the internal MOSFET. Input for the start-up, high-voltage current source.
SOURCE Source of the internal MOSFET. Input of the primary current sense signal.
GND
Ground.
Brown-in/out, input OVP, and over-power compensation detection. Brown-in/out, input
7
8
B/O
OVP and over-power compensation is achieved by detecting the voltage on B/O. All of the
functions are disabled when B/O is pulled higher than VDIS
.
TIMER combines the soft start, the frequency jittering, and the timer functions for OLP
TIMER and brownout protection. The IC is latched by pulling TIMER down. It allows for external
OVP and OTP detection.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
8
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL CHARACTERISTICS
HF500-15 Rev. 1.03
www.MonolithicPower.com
9
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL CHARACTERISTICS (continued)
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
10
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL CHARACTERISTICS (continued)
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
11
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL PERFORMANCE CHARACTERISIC
VIN = 230VAC, VOUT = 12V, IOUT = 1A, unless otherwise noted.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
12
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL PERFORMANCE CHARACTERISIC (continued)
VIN = 230VAC, VOUT = 12V, IOUT = 1A, unless otherwise noted.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
13
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
Power
Management
DRAIN
VCC
Start-Up Unit
OVP
OLP
Fault
Management
TIMER
Driving Signal
Management
Frequency
Foldback
Burst-Mode
Control
FB
Peak Current
Compression
Comparator
B/O
Slope
Compensation
Over-Power
Compensation
Input OVP
Brown Out
SOURCE
GND
Figure 1: Functional Block Diagram
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
14
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
Switching
Frequency
OPERATION
fOSC(1+|Ajitter|)
The HF500-15 is a fixed-frequency, current-
mode regulator with built-in slope compensation
that incorporates all of the necessary features
to build a reliable switch-mode power supply. In
light-load conditions, the regulator freezes the
peak current and reduces its switching
frequency to 25kHz to minimize switching loss.
fOSC
fOSC(1-|Ajitter|)
Time
T
jitter
When the output power falls below a given level,
the regulator enters burst mode. The HF500-15
uses frequency jittering to improve EMI
performance.
Figure 3: Frequency Jittering
Frequency Foldback
To achieve high efficiency during all load
conditions, the HF500-15 implements frequency
foldback during light-load conditions.
Fixed Frequency with Jittering
Frequency jittering reduces EMI by spreading
out the energy. Figure 2 shows the frequency
jitter circuit.
When the load decreases to a given level, the
regulator freezes the VFOLD peak current and
reduces the charging current, dropping its
switching frequency down to 25kHz and
reducing switching loss. If the load continues to
decrease, the peak current decreases with a
25kHz fixed frequency to avoid audible noise.
Figure 4 shows the frequency and peak current
vs. FB.
FB
14pF
VDD
10uA
Frequency
Peak
Frequency
Jittering
Timer
Current
S
R
Q
fOSC
VILIM
3.2V
2.8V
20uA
_
Q
VFOLD
Burst
Fixed
frequency
fOSC(min)
Fault
Frequency
foldback
VIBURL
/
Fixed
frequency
VIBURH
VFB
VBURL
VBURH
VFB(FOLDE) VFB(FOLD)
KFB2*VILIM
Figure 2: Frequency Jitter Circuit
Figure 4: Frequency and Peak Current vs. FB
An internal capacitor is charged with a
controlled current source, which is fixed when
FB > 2V, and its voltage is compared with the
TIMER voltage. The TIMER voltage is a
triangular wave between 2.8V and 3.2V with a
charging/discharging current (see Figure 3).
The switching frequency can be calculated
using Equation (1):
Current-Mode Operation with Slope
Compensation
The primary peak current is controlled by the
FB voltage. When the peak current reaches the
level determined by FB, the MOSFET turns off.
Also, the regulator operates in continuous
conduction mode (CCM) with a wide input
voltage range. Its internal synchronous slope
compensation (SRAMP) helps avoid subharmonic
oscillation when the duty cycle is larger than
50% at CCM.
1106
fs
Hz
(1)
5.28 VTIMER / V 0.2
Tjitter can be calculated using Equation (2):
High-Voltage Start-Up Current Source
8CTIMER /nF105s
(2)
Initially, the IC is self-supplied by the internal
high-voltage current source, which is drawn
from DRAIN. The IC turns off the current source
T
jitter
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
15
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
once the voltage on VCC reaches VCCOFF. If
the voltage on VCC falls below VCCUVLO, the
switching pulse stops, and the current source
turns on again. The auxiliary winding takes over
the power supply for the IC when the output
voltage rises normally to the set voltage. The
lower threshold of VCC UVLO is pulled down
from VCCUVLO to VCCPRO when a fault condition
occurs, such as OLP, SCP, brownout, OVP,
OTP, etc (see Figure 5).
Burst Operation
The HF500-15 uses burst-mode operation to
minimize the power dissipation in no-load or
light-load conditions. As the load decreases, the
FB voltage decreases. The IC stops the
switching cycle when the FB voltage drops
below the lower threshold (VBURL); the FB
increases again once the output voltage drops.
Switching resumes once the FB voltage
exceeds the threshold (VBURH). The FB voltage
then falls and rises repeatedly. Burst-mode
operation alternately enables and disables the
switching cycle of the MOSFET, thereby
reducing switching loss at no-load or light-load
conditions.
Auxiliary winding takes over
VCCOFF
Vcc
VCCUVLO
VCCPRO
ON
High-voltage
Current
Source
OFF
Over-Power Compensation
An offset voltage proportional to the B/O
voltage is added to the sensing voltage. The
B/O voltage is proportional to the input voltage.
Figure 7 shows the compensation in relation to
the voltage on FB and B/O. The VOPC can be
calculated using Equation (4):
Switch
Fault
Flag
Figure 5: VCC Power Supply Process
VOPC 0.094(VB/O 1.1V)
(4)
Soft Start (SS)
VOPC
To reduce the stress on the power components
and smoothly establish the output voltage, the
TIMER voltage increases from 1V to 1.75V with
a 1/4 charge current during normal operation at
every start-up. The TIMER voltage increases
the peak current from 0.25V to 1V gradually..
The switching frequency also increases
gradually. Figure 6 shows the typical waveform
of a soft start.
V
B/O
VOPC(OFF)
VOPC(ON)
FB
Figure 7: Compensation Current vs. FB and B/O
Voltage
TIMER
1.75V
ITIMER=10/4 mA
ITIMER=10mA
Timer Based Overload Protection (OLP)
1V
If the switching frequency is fixed in a flyback
converter, the maximum output power is limited
by the peak current. When the output
consumes more than the limited power, the
output voltage drops below the set value. The
current flowing through the primary and
secondary optocoupler is then reduced, and the
FB voltage is pulled high (see Figure 8).
Current
limit
1V
Ipri
0.25V
Soft start duration
Figure 6: Soft Start
FB
The start-up duration can be adjusted by the
capacitor connected to TIMER. The TIMER
capacitor determines the start-up duration,
shown in Equation (3):
OLP
3.7V
Timer
counter
16
TIMER
TSoftstart 0.3CTIMER /nF103s (3)
Figure 8: Overload Protection Block
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
16
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
FB rising higher than VOLP is considered an
error flag and causes the timer to start counting
the rising edge of VQ. When the error flag is
removed, the timer resets. When the timer
reaches completion after it has counted to 16, it
enters OLP. This timer duration does not trigger
the OLP function when the power supply is
starting up or during a load transition phase.
Figure 9 shows the OLP function.
VCC Over-Voltage Protection (OVP)
The HF500-15 enters a latched fault condition if
the VCC voltage rises above VOVP for TOVP. The
regulator remains fully latched until VCC drops
below VCCLATCH (e.g. the user unplugs the
power supply from the main input and plugs it
back in). Usually, this situation occurs when the
optocoupler fails, resulting in the loss of the
output voltage regulation.
TIMER Protection
TIMER
VQ
The HF500-15 is latched off by pulling TIMER
below VTIMER(LATCH) for TLATCH. This allows TIMER
to be used for external OVP and OTP functions
by adding an external compact circuit.
VFB
VOLP
Over load takes place here
Voltage regulation here
Leading-Edge Blanking (LEB)
OLP occurs here
An internal leading-edge blanking (LEB) unit
containing two LEB times is placed between
SOURCE and the current comparator input to
avoid premature switching pulse termination
due to parasitic capacitances. During the
blanking time, the current comparator is
disabled and cannot turn off the external
Figure 9: Overload Protection Function
Input Brownout and Input OVP
The input brownout and input OVP can be
realized by B/O. If the B/O voltage is higher
than VB/O_IN during the input voltage rising
period, the IC begins operating. If the B/O
voltage is lower than VB/O_OUT for TB/O (CTIMER
47nF), the IC stops operation. If the voltage on
B/O is higher than OVPB/O for TOVPB/O, the IC
stops operating, achieving the input OVP. If the
voltage on B/O is higher than VDIS, it disables
the input brownout and input OVP functions. To
simplify the external circuit, connect B/O to
VCC through a resistor if the input brownout,
over-power compensation, and the input OVP
functions are not desired.
MOSFET. Figure 10 shows the LEB waveform.
=
VLimit
TLEB2
TLEB1 for SCP
t
Short-Circuit Protection (SCP)
The HF500-15 features
a
short-circuit
Figure 10: Leading-Edge Blanking
protection that senses the SOURCE voltage
and stops switching if VSOURCE reaches VSCP
after a reduced leading-edge blanking time
(TLEB2). Once the fault disappears, the power
supply resumes operation.
Thermal Shutdown
The HF500-15 uses thermal shutdown to turn
off the switching cycle when the inner
temperature exceeds TOTP. As soon as the inner
temperature drops below TOTP(HYS), the power
supply resumes operation. During thermal
shutdown, the VCC UVLO lower threshold is
pulled down from VCCUVLO to VCCPRO
.
HF500-15 Rev. 1.03
www.MonolithicPower.com
17
1/10/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
APPLICATION INFORMATION
For CCM at a minimum input, calculate the
converter duty cycle with Equation (7):
VCC Capacitor Selection
When the input voltage is applied, the VCC
capacitor is charged up by the IC internal high-
voltage current source. Set the output voltage
(VO VF )N
D
(7)
(VO VF )N V
in(min)
before the VCC voltage drops below VCCUVLO
.
Where VF is the secondary diode’s forward
voltage, N is the transformer turn ratio, and
VIN(MIN) is the minimum voltage on the bulk
capacitor.
Otherwise, VCC charges and discharges
repeatedly, and the output voltage cannot be set
normally. For most applications, choose a VCC
capacitor value between 10µF and 47µF . The
value for the VCC capacitor can be estimated
with Equation (5):
The MOSFET turn-on time is calculated with
Equation (8):
ICC * T
T DT
(8)
rise
on
s
CVCC
(5)
VCCOFF VCCUVLO
Where Ts is the frequency jitter’s dominant
1
Where ICC is the internal consumption and Trise is
the output voltage rise period.
switching period, and
fs 65kHz
.
T
s
The average value of the primary current can be
calculated with Equation (9):
Primary-Side Inductor Design (Lm)
The HF500-15 uses an internal slope
compensation to support CCM when the duty
cycle exceeds 50%. Set a ratio (KP) of the
primary inductor’s ripple current amplitude vs. the
peak current value to 0 < KP 1, where KP = 1 for
DCM. Figure 11 shows the relevant waveforms.
A larger inductor leads to a smaller KP, which
reduces the RMS current, but increases
transformer size. An optimal KP value is between
0.7 and 0.8 for the universal input range and
CrCM or DCM for the 230VAC input range.
P
in
Iav
(9)
V
in(min)
The peak value of the primary current can be
calculated with Equation (10):
Iav
(10)
Ipeak
K
(1 P )D
2
The ripple value of the primary current can be
calculated with Equation (11):
KP=Iripple/Ipeak
Iripple
Iripple KP Ipeak
(11)
Ipeak
The valley value of the primary current can be
calculated with Equation (12):
Iav
Ivalley (1KP )Ipeak
(12)
Figure 11: Typical Primary Current Waveform
Lm can be calculated with Equation (13):
The input power (Pin) at the minimum input can
be estimated with Equation (6):
V
in(min) T
on
Lm
(13)
Iripple
VO IO
P
(6)
in
Current-Sense Resistor
Figure 12 shows the peak current comparator
logic and the subsequent waveform. When the
sum of the sensing resistor voltage and the slope
compensator reaches Vpeak, the comparator goes
high to reset the RS flip-flop, and the MOSFET is
turned off.
Where VO is the output voltage, IO is the rated
output current, and is the estimated efficiency,
typically between 0.75 and 0.85 depending on
the input range and output voltage.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
18
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
30MHz), the spectrum analyzer receives less
noise energy.
DRAIN
Q
DRV
LEB
S
R
The capacitor on TIMER determines the period of
-
FB
the frequency jitter. A 10µA current source
charges the capacitor when the TIMER voltage
reaches 3.2V, and another 10µA current source
discharges the capacitor to 2.8V. This charging
and discharging cycle repeats.
+
Vlimit
SOURCE
Slope
compensation
a) Peak Current Comparator
Circuit
Equation (2) describes the jitter period in theory.
A smaller fjitter is more effective for EMI reduction.
However, the measurement bandwidth requires
fjitter to be large compared to the spectrum
analyzer RBW for effective EMI reduction. Also,
fjitter should be less than the control loop gain
crossover frequency to avoid disturbing the
output voltage regulation.
Vpeak
Sramp*Ton
Ipeak*Rsense
The TIMER capacitor must be selected carefully.
A capacitor that is too large may cause the start-
up to fail at full load because of the long, soft
start-up duration, shown in Equation (3).
However, a TIMER capacitor that is too small
causes the timer period to decrease, which
overloads the timer count capability and may
cause logic problems. For most applications, a
fjitter between 200Hz and 400Hz is recommended.
b) Typical Waveform
Figure 12: Peak Current Comparator
The maximum current limit is VILIM. The ramp of
the slope compensator is Sramp. Given a certain
margin, use 0.95 x VILIM as Vpeak at full load.
Calculate the voltage on the sensing resistor
with Equation (14):
Ramp Compensation
Vsense 95% VILIM Sramp T
(14)
In peak current control, subharmonic oscillation
occurs when D > 0.5 in CCM. The HF500-15
solves this problem with internal ramp
compensation. Calculate α with Equation (17).
For stable operation, α must be less than 1:
on
The value of the sense resistor is then calculated
with Equation (15):
Vsense
Rsense
(15)
Dmax V
Ipeak
in(min)
Rsense -ma
(1-Dmax )Lm
Select
a
current-sense resistor with an
appropriate power rating. Estimate the sense
resistor power loss with Equation (16):
(17)
=
V
in(min) Rsense +ma
Lm
2
Where ma = 20mV/µs is the minimum internal
slope value of the compensation ramp, and
I
I
2
1
(16)
peak
valley
P
I
Ivalley
DRsense
peak
2
12
V
Dmax V
in(min)
in(min)
and
are the
Rsense
Rsense
Jitter Period
Lm
(1Dmax )Lm
Frequency jitter is used as an effective method
for reducing EMI by dissipating energy. The nth-
slew rates of the primary-side and equivalent
secondary-side voltages sensed by the current-
sensing resistor respectively.
order
harmonic
noise
bandwidth
is
BTn n(2f fjitter
)
, where f is the frequency
jitter amplitude. If BTn exceeds the resolution
bandwidth (RBW) of the spectrum analyzer
(200Hz for noise frequency less than 150kHz,
9kHz for noise frequency between 150kHz and
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
19
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
PCB Layout Guidelines
Design Example
Efficient PCB layout is critical for stable operation,
good EMI performance, and good thermal
performance. For best results refer to Figure 13
and follow the guidelines below:
Table 1 below is a design example of the HF500-
15 for power adapter applications.
Table 1: Design Specification
1. Minimize the power stage loop area for better
EMI performance. This includes the input
loop (C4 - T1 - U1 - R2/R4 - C4), the auxiliary
winding loop (T1 - D7 - R12 - C7 - T1), the
output loop (T1 - D8 - C10 - T1), and the
RCD snubber loop (T1 - R9 - D6 - R10/C6 -
T1).
VIN
VOUT
IOUT
85 to 265VAC
12V
1A
2. Keep the input loop GND and the control
circuit GND separate and only connect them
at C4. Otherwise, the IC operation may be
influenced by noise.
3. Place the control circuit capacitors (such as
those for FB, B/O, and VCC) close to the IC
to decouple noise effectively.
4. Place a larger source area around the IC to
improve thermal performance, if needed.
a) Top
b) Bottom
Figure 13: Recommended PCB Layout
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
20
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
TYPICAL APPLICATION CIRCUIT
C9 470pF
R13 100
L1 1.0mH
D8
F1
L2
9
5
CN1
100V/3A
Magnetic Bead
D2
IN4007
D4
IN4007
1
2
R22 10K
R21
NC
C6
R10
150K
R6
5.1M
C12
1uF
Np
Ns
C10
680uF
2.2nF
L
3
7
R7
5.1M
D6
FR107
C2
10uF
C4
22uF
RV1
CX1
275Vac Varistor
100nF
N
T1
EE19
2
B/O
D7
R9
51
R8
R12
10
D3
IN4007
D5
IN4007
N_Aux
R18
10
91K
Magnetic Bead
L3
C7 47uF
1
R14
1K
C8 100nF
U1
U2
PC817A
R19
38.3K
5
4
Source
Drain
R16
2K
6
7
8
GND
HFC500-15
VCC
R11
NC
C13
1nF
RT2
NC
R3
NC
2
1
B/O
Vcc
FB
B/O
VCC
C11 22nF
100K
R15
TIMER
R1
NC
D1
C5
1nF
U3
TL431
2.5V
NC
CY1 2.2nF
Q1
NC
R4
3.3
R5
3.3
R17
10K
R20
NC
C3
47nF
R2
NC
C1
NC
Figure 14: Example of a Typical Application
NC
N1
5
Np2: 0.20mm×1P?80Ts
4
5
4
9
7
Ns: 0.45mm?1P?24Ts TIW
9
N5
N2
1
2
Naux: 0.10mm×2P?27Ts
Np1: 0.2mm×1P?110Ts
Primary
Secondary
N4
4
3
3
7
Ncp: 0.2mm×2P?19Ts
5
2
1
Secondary side
Primary side
N3
Note:
Start Winding Point
Tape
Note:
One tape between each winding
: Start Point
Cut 4th, 8th Pin after Winding
a) Connection Diagram
b) Winding Diagram
Figure 15: Transformer Structure
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
21
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
Table 2: Winding Order
Tape (T)
Winding
Start-End Wire Size (φ) Turns (T)
Tube
0
1
1
1
1
N1
N2
N3
N4
N5
5 NC
3 4
2 1
9 7
4 5
0.20mm*2
0.20mm*1
0.10mm*2
19
110
27
No
Matching with wire
Matching with wire
0.45mm*1
TIW
24
No
Matching with wire
0.20mm*1
80
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
22
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
FLOW CHART
Start
Y
Internal High
Voltage
Current
Vcc Decrease
to 5.3V
N
Vcc<3V?
Source On
Shut Off the
Switching
Pulse
Latch Off the
Switching Pulse
Y
Y
Y
OTP=
Logic High
N
N
SCP=
Logic High
Shut Down
Internal High Voltage
?
?
N
Y
Vcc 12V
>
Current Source
Y
Y
N
N
VTIMER
<1V
N
Vcc<7.0V
VCC>24V
Thermal
Monitor
Vs>1.5V
in LEB2
Y
Monitor VTIMER after
VTIMER>1.0V
Monitor Vcc
Monitor VB/O
Soft Start
Y
Y
N
Timer Recharge
16
Times and
Fault=Logic High
Monitor V
FB
Continuous
Fault Monitor
VFB<0.7V
0.7V<VFB<3.0V
VFB>3.7V
Y
Y
Y
Normal
Operation
Switch Off
OLP= Logic High
Fault= Logic High
Brown-Out
= Logic High
Disable Input B/O
OPC, Input OVP
Y
N
VFB>0.8V
Y
Y
N
N
N
VB/O<VB/O_IN
VB/O>VDIS
VB/O>OVPB/O
, and latch
UVLO, brown-out, OTP & OLPare auto restart; OVPon VCC -off on TIMER are latch mode.
To release from the latch condition, unplug from the main input.
Figure 16: Control Flow Chart
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
23
HF500-15 – FULL-FEATURED FLYBACK REGULATOR
PACKAGE INFORMATION
SOIC8-7B
0.189(4.80)
0.197(5.00)
0.050(1.27)
0.024(0.61)
0.063(1.60)
8
5
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.213(5.40)
PIN 1 ID
1
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
0.0075(0.19)
0.0098(0.25)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
GAUGE PLANE
0.010(0.25) BSC
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
0.016(0.41)
0.050(1.27)
0o-8o
5) JEDEC REFERENCE IS MS-012.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
HF500-15 Rev. 1.03
1/10/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
24
相关型号：
©2020 ICPDF网 联系我们和版权申明